1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
58 #include "record-full.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data
*arm_objfile_data_key
;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
92 DEF_VEC_O(arm_mapping_symbol_s
);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s
) **section_maps
;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element
*setarmcmdlist
= NULL
;
101 static struct cmd_list_element
*showarmcmdlist
= NULL
;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings
[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
117 static const char *current_fp_model
= "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
130 static const char *arm_abi_string
= "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode
= -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options
;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases
[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names
[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles
;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style
;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element
*);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat
*, const void *,
228 static void convert_to_extended (const struct floatformat
*, void *,
231 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
232 struct regcache
*regcache
,
233 int regnum
, gdb_byte
*buf
);
234 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, const gdb_byte
*buf
);
238 static int thumb_insn_size (unsigned short inst1
);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg
*saved_regs
;
260 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
261 CORE_ADDR prologue_start
,
262 CORE_ADDR prologue_end
,
263 struct arm_prologue_cache
*cache
);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
285 if (gdbarch_tdep (gdbarch
)->is_m
)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info
*frame
)
297 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
312 const struct arm_mapping_symbol
*rhs
)
314 return lhs
->value
< rhs
->value
;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
324 struct obj_section
*sec
;
326 /* If there are mapping symbols, consult them. */
327 sec
= find_pc_section (memaddr
);
330 struct arm_per_objfile
*data
;
331 VEC(arm_mapping_symbol_s
) *map
;
332 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
336 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
339 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
340 if (!VEC_empty (arm_mapping_symbol_s
, map
))
342 struct arm_mapping_symbol
*map_sym
;
344 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
345 arm_compare_mapping_symbols
);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
353 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
354 if (map_sym
->value
== map_key
.value
)
357 *start
= map_sym
->value
+ obj_section_addr (sec
);
358 return map_sym
->type
;
364 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
366 *start
= map_sym
->value
+ obj_section_addr (sec
);
367 return map_sym
->type
;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
383 struct bound_minimal_symbol sym
;
385 struct displaced_step_closure
* dsc
386 = get_displaced_step_closure_by_addr(memaddr
);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog
,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc
->insn_addr
,
396 (unsigned long) memaddr
);
397 memaddr
= dsc
->insn_addr
;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr
))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode
!= -1)
406 return arm_override_mode
;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string
, "arm") == 0)
411 if (strcmp (arm_force_mode_string
, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch
)->is_m
)
418 /* If there are mapping symbols, consult them. */
419 type
= arm_find_mapping_symbol (memaddr
, NULL
);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym
= lookup_minimal_symbol_by_pc (memaddr
);
426 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers
)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* On M-profile devices, do not strip the low bit from EXC_RETURN
451 (the magic exception return address). */
452 if (gdbarch_tdep (gdbarch
)->is_m
453 && (val
& 0xfffffff0) == 0xfffffff0)
457 return UNMAKE_THUMB_ADDR (val
);
459 return (val
& 0x03fffffc);
462 /* Return 1 if PC is the start of a compiler helper function which
463 can be safely ignored during prologue skipping. IS_THUMB is true
464 if the function is known to be a Thumb function due to the way it
467 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
469 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
470 struct bound_minimal_symbol msym
;
472 msym
= lookup_minimal_symbol_by_pc (pc
);
473 if (msym
.minsym
!= NULL
474 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
475 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
477 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
479 /* The GNU linker's Thumb call stub to foo is named
481 if (strstr (name
, "_from_thumb") != NULL
)
484 /* On soft-float targets, __truncdfsf2 is called to convert promoted
485 arguments to their argument types in non-prototyped
487 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
489 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
492 /* Internal functions related to thread-local storage. */
493 if (strncmp (name
, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
495 if (strncmp (name
, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
500 /* If we run against a stripped glibc, we may be unable to identify
501 special functions by name. Check for one important case,
502 __aeabi_read_tp, by comparing the *code* against the default
503 implementation (this is hand-written ARM assembler in glibc). */
506 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
507 == 0xe3e00a0f /* mov r0, #0xffff0fff */
508 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
509 == 0xe240f01f) /* sub pc, r0, #31 */
516 /* Support routines for instruction parsing. */
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
525 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
526 the first 16-bit of instruction, and INSN2 is the second 16-bit of
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
534 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
535 the 32-bit instruction. */
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
540 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
543 thumb_expand_immediate (unsigned int imm
)
545 unsigned int count
= imm
>> 7;
553 return (imm
& 0xff) | ((imm
& 0xff) << 16);
555 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
557 return (imm
& 0xff) | ((imm
& 0xff) << 8)
558 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
561 return (0x80 | (imm
& 0x7f)) << (32 - count
);
564 /* Return 1 if the 16-bit Thumb instruction INST might change
565 control flow, 0 otherwise. */
568 thumb_instruction_changes_pc (unsigned short inst
)
570 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
573 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
576 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
579 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
582 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
585 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
591 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
592 might change control flow, 0 otherwise. */
595 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
597 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
599 /* Branches and miscellaneous control instructions. */
601 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
606 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
608 /* SUBS PC, LR, #imm8. */
611 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
613 /* Conditional branch. */
620 if ((inst1
& 0xfe50) == 0xe810)
622 /* Load multiple or RFE. */
624 if (bit (inst1
, 7) && !bit (inst1
, 8))
630 else if (!bit (inst1
, 7) && bit (inst1
, 8))
636 else if (bit (inst1
, 7) && bit (inst1
, 8))
641 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
650 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
652 /* MOV PC or MOVS PC. */
656 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
659 if (bits (inst1
, 0, 3) == 15)
665 if ((inst2
& 0x0fc0) == 0x0000)
671 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
677 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
686 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
687 epilogue, 0 otherwise. */
690 thumb_instruction_restores_sp (unsigned short insn
)
692 return (insn
== 0x46bd /* mov sp, r7 */
693 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
694 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
697 /* Analyze a Thumb prologue, looking for a recognizable stack frame
698 and frame pointer. Scan until we encounter a store that could
699 clobber the stack frame unexpectedly, or an unknown instruction.
700 Return the last address which is definitely safe to skip for an
701 initial breakpoint. */
704 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
705 CORE_ADDR start
, CORE_ADDR limit
,
706 struct arm_prologue_cache
*cache
)
708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
709 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
712 struct pv_area
*stack
;
713 struct cleanup
*back_to
;
715 CORE_ADDR unrecognized_pc
= 0;
717 for (i
= 0; i
< 16; i
++)
718 regs
[i
] = pv_register (i
, 0);
719 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
720 back_to
= make_cleanup_free_pv_area (stack
);
722 while (start
< limit
)
726 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
728 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
733 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
736 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
737 whether to save LR (R14). */
738 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
740 /* Calculate offsets of saved R0-R7 and LR. */
741 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
742 if (mask
& (1 << regno
))
744 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
746 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
749 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
751 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
752 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
755 else if (thumb_instruction_restores_sp (insn
))
757 /* Don't scan past the epilogue. */
760 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
761 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
763 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
764 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
765 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
767 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
768 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
769 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
771 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
772 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
773 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
774 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
775 regs
[bits (insn
, 6, 8)]);
776 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
777 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
779 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
780 int rm
= bits (insn
, 3, 6);
781 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
783 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
785 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
786 int src_reg
= (insn
& 0x78) >> 3;
787 regs
[dst_reg
] = regs
[src_reg
];
789 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
791 /* Handle stores to the stack. Normally pushes are used,
792 but with GCC -mtpcs-frame, there may be other stores
793 in the prologue to create the frame. */
794 int regno
= (insn
>> 8) & 0x7;
797 offset
= (insn
& 0xff) << 2;
798 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
800 if (pv_area_store_would_trash (stack
, addr
))
803 pv_area_store (stack
, addr
, 4, regs
[regno
]);
805 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
807 int rd
= bits (insn
, 0, 2);
808 int rn
= bits (insn
, 3, 5);
811 offset
= bits (insn
, 6, 10) << 2;
812 addr
= pv_add_constant (regs
[rn
], offset
);
814 if (pv_area_store_would_trash (stack
, addr
))
817 pv_area_store (stack
, addr
, 4, regs
[rd
]);
819 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
820 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
821 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
822 /* Ignore stores of argument registers to the stack. */
824 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
825 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
826 /* Ignore block loads from the stack, potentially copying
827 parameters from memory. */
829 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
830 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
831 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
832 /* Similarly ignore single loads from the stack. */
834 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
835 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
836 /* Skip register copies, i.e. saves to another register
837 instead of the stack. */
839 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
840 /* Recognize constant loads; even with small stacks these are necessary
842 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
843 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
845 /* Constant pool loads, for the same reason. */
846 unsigned int constant
;
849 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
850 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
851 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
853 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
855 unsigned short inst2
;
857 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
858 byte_order_for_code
);
860 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
862 /* BL, BLX. Allow some special function calls when
863 skipping the prologue; GCC generates these before
864 storing arguments to the stack. */
866 int j1
, j2
, imm1
, imm2
;
868 imm1
= sbits (insn
, 0, 10);
869 imm2
= bits (inst2
, 0, 10);
870 j1
= bit (inst2
, 13);
871 j2
= bit (inst2
, 11);
873 offset
= ((imm1
<< 12) + (imm2
<< 1));
874 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
876 nextpc
= start
+ 4 + offset
;
877 /* For BLX make sure to clear the low bits. */
878 if (bit (inst2
, 12) == 0)
879 nextpc
= nextpc
& 0xfffffffc;
881 if (!skip_prologue_function (gdbarch
, nextpc
,
882 bit (inst2
, 12) != 0))
886 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
888 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
890 pv_t addr
= regs
[bits (insn
, 0, 3)];
893 if (pv_area_store_would_trash (stack
, addr
))
896 /* Calculate offsets of saved registers. */
897 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
898 if (inst2
& (1 << regno
))
900 addr
= pv_add_constant (addr
, -4);
901 pv_area_store (stack
, addr
, 4, regs
[regno
]);
905 regs
[bits (insn
, 0, 3)] = addr
;
908 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
910 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
912 int regno1
= bits (inst2
, 12, 15);
913 int regno2
= bits (inst2
, 8, 11);
914 pv_t addr
= regs
[bits (insn
, 0, 3)];
916 offset
= inst2
& 0xff;
918 addr
= pv_add_constant (addr
, offset
);
920 addr
= pv_add_constant (addr
, -offset
);
922 if (pv_area_store_would_trash (stack
, addr
))
925 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
926 pv_area_store (stack
, pv_add_constant (addr
, 4),
930 regs
[bits (insn
, 0, 3)] = addr
;
933 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
934 && (inst2
& 0x0c00) == 0x0c00
935 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
937 int regno
= bits (inst2
, 12, 15);
938 pv_t addr
= regs
[bits (insn
, 0, 3)];
940 offset
= inst2
& 0xff;
942 addr
= pv_add_constant (addr
, offset
);
944 addr
= pv_add_constant (addr
, -offset
);
946 if (pv_area_store_would_trash (stack
, addr
))
949 pv_area_store (stack
, addr
, 4, regs
[regno
]);
952 regs
[bits (insn
, 0, 3)] = addr
;
955 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
956 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
958 int regno
= bits (inst2
, 12, 15);
961 offset
= inst2
& 0xfff;
962 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
964 if (pv_area_store_would_trash (stack
, addr
))
967 pv_area_store (stack
, addr
, 4, regs
[regno
]);
970 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
971 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
972 /* Ignore stores of argument registers to the stack. */
975 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
976 && (inst2
& 0x0d00) == 0x0c00
977 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
978 /* Ignore stores of argument registers to the stack. */
981 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
983 && (inst2
& 0x8000) == 0x0000
984 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
985 /* Ignore block loads from the stack, potentially copying
986 parameters from memory. */
989 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
991 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
992 /* Similarly ignore dual loads from the stack. */
995 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
996 && (inst2
& 0x0d00) == 0x0c00
997 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
998 /* Similarly ignore single loads from the stack. */
1001 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1002 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1003 /* Similarly ignore single loads from the stack. */
1006 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1007 && (inst2
& 0x8000) == 0x0000)
1009 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1010 | (bits (inst2
, 12, 14) << 8)
1011 | bits (inst2
, 0, 7));
1013 regs
[bits (inst2
, 8, 11)]
1014 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1015 thumb_expand_immediate (imm
));
1018 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1019 && (inst2
& 0x8000) == 0x0000)
1021 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1022 | (bits (inst2
, 12, 14) << 8)
1023 | bits (inst2
, 0, 7));
1025 regs
[bits (inst2
, 8, 11)]
1026 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1029 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1030 && (inst2
& 0x8000) == 0x0000)
1032 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1033 | (bits (inst2
, 12, 14) << 8)
1034 | bits (inst2
, 0, 7));
1036 regs
[bits (inst2
, 8, 11)]
1037 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1038 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1041 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1042 && (inst2
& 0x8000) == 0x0000)
1044 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1045 | (bits (inst2
, 12, 14) << 8)
1046 | bits (inst2
, 0, 7));
1048 regs
[bits (inst2
, 8, 11)]
1049 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1052 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1054 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1055 | (bits (inst2
, 12, 14) << 8)
1056 | bits (inst2
, 0, 7));
1058 regs
[bits (inst2
, 8, 11)]
1059 = pv_constant (thumb_expand_immediate (imm
));
1062 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1065 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1067 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1070 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1071 && (inst2
& 0xf0f0) == 0)
1073 int dst_reg
= (inst2
& 0x0f00) >> 8;
1074 int src_reg
= inst2
& 0xf;
1075 regs
[dst_reg
] = regs
[src_reg
];
1078 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1080 /* Constant pool loads. */
1081 unsigned int constant
;
1084 offset
= bits (inst2
, 0, 11);
1086 loc
= start
+ 4 + offset
;
1088 loc
= start
+ 4 - offset
;
1090 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1091 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1094 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1096 /* Constant pool loads. */
1097 unsigned int constant
;
1100 offset
= bits (inst2
, 0, 7) << 2;
1102 loc
= start
+ 4 + offset
;
1104 loc
= start
+ 4 - offset
;
1106 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1107 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1109 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1110 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1113 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1115 /* Don't scan past anything that might change control flow. */
1120 /* The optimizer might shove anything into the prologue,
1121 so we just skip what we don't recognize. */
1122 unrecognized_pc
= start
;
1127 else if (thumb_instruction_changes_pc (insn
))
1129 /* Don't scan past anything that might change control flow. */
1134 /* The optimizer might shove anything into the prologue,
1135 so we just skip what we don't recognize. */
1136 unrecognized_pc
= start
;
1143 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1144 paddress (gdbarch
, start
));
1146 if (unrecognized_pc
== 0)
1147 unrecognized_pc
= start
;
1151 do_cleanups (back_to
);
1152 return unrecognized_pc
;
1155 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1157 /* Frame pointer is fp. Frame size is constant. */
1158 cache
->framereg
= ARM_FP_REGNUM
;
1159 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1161 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1163 /* Frame pointer is r7. Frame size is constant. */
1164 cache
->framereg
= THUMB_FP_REGNUM
;
1165 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1169 /* Try the stack pointer... this is a bit desperate. */
1170 cache
->framereg
= ARM_SP_REGNUM
;
1171 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1174 for (i
= 0; i
< 16; i
++)
1175 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1176 cache
->saved_regs
[i
].addr
= offset
;
1178 do_cleanups (back_to
);
1179 return unrecognized_pc
;
1183 /* Try to analyze the instructions starting from PC, which load symbol
1184 __stack_chk_guard. Return the address of instruction after loading this
1185 symbol, set the dest register number to *BASEREG, and set the size of
1186 instructions for loading symbol in OFFSET. Return 0 if instructions are
1190 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1191 unsigned int *destreg
, int *offset
)
1193 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1195 unsigned int low
, high
, address
;
1200 unsigned short insn1
1201 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1203 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1205 *destreg
= bits (insn1
, 8, 10);
1207 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1208 address
= read_memory_unsigned_integer (address
, 4,
1209 byte_order_for_code
);
1211 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1213 unsigned short insn2
1214 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1216 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1219 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1221 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1223 /* movt Rd, #const */
1224 if ((insn1
& 0xfbc0) == 0xf2c0)
1226 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1227 *destreg
= bits (insn2
, 8, 11);
1229 address
= (high
<< 16 | low
);
1236 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1238 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1240 address
= bits (insn
, 0, 11) + pc
+ 8;
1241 address
= read_memory_unsigned_integer (address
, 4,
1242 byte_order_for_code
);
1244 *destreg
= bits (insn
, 12, 15);
1247 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1249 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1252 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1254 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1256 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1257 *destreg
= bits (insn
, 12, 15);
1259 address
= (high
<< 16 | low
);
1267 /* Try to skip a sequence of instructions used for stack protector. If PC
1268 points to the first instruction of this sequence, return the address of
1269 first instruction after this sequence, otherwise, return original PC.
1271 On arm, this sequence of instructions is composed of mainly three steps,
1272 Step 1: load symbol __stack_chk_guard,
1273 Step 2: load from address of __stack_chk_guard,
1274 Step 3: store it to somewhere else.
1276 Usually, instructions on step 2 and step 3 are the same on various ARM
1277 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1278 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1279 instructions in step 1 vary from different ARM architectures. On ARMv7,
1282 movw Rn, #:lower16:__stack_chk_guard
1283 movt Rn, #:upper16:__stack_chk_guard
1290 .word __stack_chk_guard
1292 Since ldr/str is a very popular instruction, we can't use them as
1293 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1294 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1295 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1298 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1300 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1301 unsigned int basereg
;
1302 struct bound_minimal_symbol stack_chk_guard
;
1304 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1307 /* Try to parse the instructions in Step 1. */
1308 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1313 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1314 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1315 Otherwise, this sequence cannot be for stack protector. */
1316 if (stack_chk_guard
.minsym
== NULL
1317 || strncmp (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
),
1318 "__stack_chk_guard",
1319 strlen ("__stack_chk_guard")) != 0)
1324 unsigned int destreg
;
1326 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1328 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1329 if ((insn
& 0xf800) != 0x6800)
1331 if (bits (insn
, 3, 5) != basereg
)
1333 destreg
= bits (insn
, 0, 2);
1335 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1336 byte_order_for_code
);
1337 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1338 if ((insn
& 0xf800) != 0x6000)
1340 if (destreg
!= bits (insn
, 0, 2))
1345 unsigned int destreg
;
1347 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1349 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1350 if ((insn
& 0x0e500000) != 0x04100000)
1352 if (bits (insn
, 16, 19) != basereg
)
1354 destreg
= bits (insn
, 12, 15);
1355 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1356 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1357 4, byte_order_for_code
);
1358 if ((insn
& 0x0e500000) != 0x04000000)
1360 if (bits (insn
, 12, 15) != destreg
)
1363 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1366 return pc
+ offset
+ 4;
1368 return pc
+ offset
+ 8;
1371 /* Advance the PC across any function entry prologue instructions to
1372 reach some "real" code.
1374 The APCS (ARM Procedure Call Standard) defines the following
1378 [stmfd sp!, {a1,a2,a3,a4}]
1379 stmfd sp!, {...,fp,ip,lr,pc}
1380 [stfe f7, [sp, #-12]!]
1381 [stfe f6, [sp, #-12]!]
1382 [stfe f5, [sp, #-12]!]
1383 [stfe f4, [sp, #-12]!]
1384 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1387 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1389 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1392 CORE_ADDR func_addr
, limit_pc
;
1394 /* See if we can determine the end of the prologue via the symbol table.
1395 If so, then return either PC, or the PC after the prologue, whichever
1397 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1399 CORE_ADDR post_prologue_pc
1400 = skip_prologue_using_sal (gdbarch
, func_addr
);
1401 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1403 if (post_prologue_pc
)
1405 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1408 /* GCC always emits a line note before the prologue and another
1409 one after, even if the two are at the same address or on the
1410 same line. Take advantage of this so that we do not need to
1411 know every instruction that might appear in the prologue. We
1412 will have producer information for most binaries; if it is
1413 missing (e.g. for -gstabs), assuming the GNU tools. */
1414 if (post_prologue_pc
1416 || COMPUNIT_PRODUCER (cust
) == NULL
1417 || strncmp (COMPUNIT_PRODUCER (cust
), "GNU ",
1418 sizeof ("GNU ") - 1) == 0
1419 || strncmp (COMPUNIT_PRODUCER (cust
), "clang ",
1420 sizeof ("clang ") - 1) == 0))
1421 return post_prologue_pc
;
1423 if (post_prologue_pc
!= 0)
1425 CORE_ADDR analyzed_limit
;
1427 /* For non-GCC compilers, make sure the entire line is an
1428 acceptable prologue; GDB will round this function's
1429 return value up to the end of the following line so we
1430 can not skip just part of a line (and we do not want to).
1432 RealView does not treat the prologue specially, but does
1433 associate prologue code with the opening brace; so this
1434 lets us skip the first line if we think it is the opening
1436 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1437 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1438 post_prologue_pc
, NULL
);
1440 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1441 post_prologue_pc
, NULL
);
1443 if (analyzed_limit
!= post_prologue_pc
)
1446 return post_prologue_pc
;
1450 /* Can't determine prologue from the symbol table, need to examine
1453 /* Find an upper limit on the function prologue using the debug
1454 information. If the debug information could not be used to provide
1455 that bound, then use an arbitrary large number as the upper bound. */
1456 /* Like arm_scan_prologue, stop no later than pc + 64. */
1457 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1459 limit_pc
= pc
+ 64; /* Magic. */
1462 /* Check if this is Thumb code. */
1463 if (arm_pc_is_thumb (gdbarch
, pc
))
1464 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1466 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
1468 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
1470 /* "mov ip, sp" is no longer a required part of the prologue. */
1471 if (inst
== 0xe1a0c00d) /* mov ip, sp */
1474 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1477 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1480 /* Some prologues begin with "str lr, [sp, #-4]!". */
1481 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
1484 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1487 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1490 /* Any insns after this point may float into the code, if it makes
1491 for better instruction scheduling, so we skip them only if we
1492 find them, but still consider the function to be frame-ful. */
1494 /* We may have either one sfmfd instruction here, or several stfe
1495 insns, depending on the version of floating point code we
1497 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1500 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1503 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1506 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1509 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1510 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1511 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1514 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1515 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1516 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1519 /* Un-recognized instruction; stop scanning. */
1523 return skip_pc
; /* End of prologue. */
1527 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1528 This function decodes a Thumb function prologue to determine:
1529 1) the size of the stack frame
1530 2) which registers are saved on it
1531 3) the offsets of saved regs
1532 4) the offset from the stack pointer to the frame pointer
1534 A typical Thumb function prologue would create this stack frame
1535 (offsets relative to FP)
1536 old SP -> 24 stack parameters
1539 R7 -> 0 local variables (16 bytes)
1540 SP -> -12 additional stack space (12 bytes)
1541 The frame size would thus be 36 bytes, and the frame offset would be
1542 12 bytes. The frame register is R7.
1544 The comments for thumb_skip_prolog() describe the algorithm we use
1545 to detect the end of the prolog. */
1549 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1550 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1552 CORE_ADDR prologue_start
;
1553 CORE_ADDR prologue_end
;
1555 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1558 /* See comment in arm_scan_prologue for an explanation of
1560 if (prologue_end
> prologue_start
+ 64)
1562 prologue_end
= prologue_start
+ 64;
1566 /* We're in the boondocks: we have no idea where the start of the
1570 prologue_end
= min (prologue_end
, prev_pc
);
1572 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1575 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1578 arm_instruction_changes_pc (uint32_t this_instr
)
1580 if (bits (this_instr
, 28, 31) == INST_NV
)
1581 /* Unconditional instructions. */
1582 switch (bits (this_instr
, 24, 27))
1586 /* Branch with Link and change to Thumb. */
1591 /* Coprocessor register transfer. */
1592 if (bits (this_instr
, 12, 15) == 15)
1593 error (_("Invalid update to pc in instruction"));
1599 switch (bits (this_instr
, 25, 27))
1602 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1604 /* Multiplies and extra load/stores. */
1605 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1606 /* Neither multiplies nor extension load/stores are allowed
1610 /* Otherwise, miscellaneous instructions. */
1612 /* BX <reg>, BXJ <reg>, BLX <reg> */
1613 if (bits (this_instr
, 4, 27) == 0x12fff1
1614 || bits (this_instr
, 4, 27) == 0x12fff2
1615 || bits (this_instr
, 4, 27) == 0x12fff3)
1618 /* Other miscellaneous instructions are unpredictable if they
1622 /* Data processing instruction. Fall through. */
1625 if (bits (this_instr
, 12, 15) == 15)
1632 /* Media instructions and architecturally undefined instructions. */
1633 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1637 if (bit (this_instr
, 20) == 0)
1641 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1647 /* Load/store multiple. */
1648 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1654 /* Branch and branch with link. */
1659 /* Coprocessor transfers or SWIs can not affect PC. */
1663 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1667 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1668 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1669 fill it in. Return the first address not recognized as a prologue
1672 We recognize all the instructions typically found in ARM prologues,
1673 plus harmless instructions which can be skipped (either for analysis
1674 purposes, or a more restrictive set that can be skipped when finding
1675 the end of the prologue). */
1678 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1679 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1680 struct arm_prologue_cache
*cache
)
1682 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1683 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1685 CORE_ADDR offset
, current_pc
;
1686 pv_t regs
[ARM_FPS_REGNUM
];
1687 struct pv_area
*stack
;
1688 struct cleanup
*back_to
;
1689 int framereg
, framesize
;
1690 CORE_ADDR unrecognized_pc
= 0;
1692 /* Search the prologue looking for instructions that set up the
1693 frame pointer, adjust the stack pointer, and save registers.
1695 Be careful, however, and if it doesn't look like a prologue,
1696 don't try to scan it. If, for instance, a frameless function
1697 begins with stmfd sp!, then we will tell ourselves there is
1698 a frame, which will confuse stack traceback, as well as "finish"
1699 and other operations that rely on a knowledge of the stack
1702 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1703 regs
[regno
] = pv_register (regno
, 0);
1704 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1705 back_to
= make_cleanup_free_pv_area (stack
);
1707 for (current_pc
= prologue_start
;
1708 current_pc
< prologue_end
;
1712 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1714 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1716 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1719 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1720 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1722 unsigned imm
= insn
& 0xff; /* immediate value */
1723 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1724 int rd
= bits (insn
, 12, 15);
1725 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1726 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1729 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1730 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1732 unsigned imm
= insn
& 0xff; /* immediate value */
1733 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1734 int rd
= bits (insn
, 12, 15);
1735 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1736 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1739 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1742 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1744 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1745 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1746 regs
[bits (insn
, 12, 15)]);
1749 else if ((insn
& 0xffff0000) == 0xe92d0000)
1750 /* stmfd sp!, {..., fp, ip, lr, pc}
1752 stmfd sp!, {a1, a2, a3, a4} */
1754 int mask
= insn
& 0xffff;
1756 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1759 /* Calculate offsets of saved registers. */
1760 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1761 if (mask
& (1 << regno
))
1764 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1765 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1768 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1769 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1770 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1772 /* No need to add this to saved_regs -- it's just an arg reg. */
1775 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1776 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1777 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1779 /* No need to add this to saved_regs -- it's just an arg reg. */
1782 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1784 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1786 /* No need to add this to saved_regs -- it's just arg regs. */
1789 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1791 unsigned imm
= insn
& 0xff; /* immediate value */
1792 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1793 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1794 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1796 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1798 unsigned imm
= insn
& 0xff; /* immediate value */
1799 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1800 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1801 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1803 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1805 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1807 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1810 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1811 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1812 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1814 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1816 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1818 int n_saved_fp_regs
;
1819 unsigned int fp_start_reg
, fp_bound_reg
;
1821 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1824 if ((insn
& 0x800) == 0x800) /* N0 is set */
1826 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1827 n_saved_fp_regs
= 3;
1829 n_saved_fp_regs
= 1;
1833 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1834 n_saved_fp_regs
= 2;
1836 n_saved_fp_regs
= 4;
1839 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1840 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1841 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1843 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1844 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1845 regs
[fp_start_reg
++]);
1848 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1850 /* Allow some special function calls when skipping the
1851 prologue; GCC generates these before storing arguments to
1853 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1855 if (skip_prologue_function (gdbarch
, dest
, 0))
1860 else if ((insn
& 0xf0000000) != 0xe0000000)
1861 break; /* Condition not true, exit early. */
1862 else if (arm_instruction_changes_pc (insn
))
1863 /* Don't scan past anything that might change control flow. */
1865 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1866 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1867 /* Ignore block loads from the stack, potentially copying
1868 parameters from memory. */
1870 else if ((insn
& 0xfc500000) == 0xe4100000
1871 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1872 /* Similarly ignore single loads from the stack. */
1874 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1875 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1876 register instead of the stack. */
1880 /* The optimizer might shove anything into the prologue,
1881 so we just skip what we don't recognize. */
1882 unrecognized_pc
= current_pc
;
1887 if (unrecognized_pc
== 0)
1888 unrecognized_pc
= current_pc
;
1890 /* The frame size is just the distance from the frame register
1891 to the original stack pointer. */
1892 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1894 /* Frame pointer is fp. */
1895 framereg
= ARM_FP_REGNUM
;
1896 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1900 /* Try the stack pointer... this is a bit desperate. */
1901 framereg
= ARM_SP_REGNUM
;
1902 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1907 cache
->framereg
= framereg
;
1908 cache
->framesize
= framesize
;
1910 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1911 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1912 cache
->saved_regs
[regno
].addr
= offset
;
1916 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1917 paddress (gdbarch
, unrecognized_pc
));
1919 do_cleanups (back_to
);
1920 return unrecognized_pc
;
1924 arm_scan_prologue (struct frame_info
*this_frame
,
1925 struct arm_prologue_cache
*cache
)
1927 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1928 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1930 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1931 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1932 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1933 pv_t regs
[ARM_FPS_REGNUM
];
1934 struct pv_area
*stack
;
1935 struct cleanup
*back_to
;
1938 /* Assume there is no frame until proven otherwise. */
1939 cache
->framereg
= ARM_SP_REGNUM
;
1940 cache
->framesize
= 0;
1942 /* Check for Thumb prologue. */
1943 if (arm_frame_is_thumb (this_frame
))
1945 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1949 /* Find the function prologue. If we can't find the function in
1950 the symbol table, peek in the stack frame to find the PC. */
1951 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1954 /* One way to find the end of the prologue (which works well
1955 for unoptimized code) is to do the following:
1957 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1960 prologue_end = prev_pc;
1961 else if (sal.end < prologue_end)
1962 prologue_end = sal.end;
1964 This mechanism is very accurate so long as the optimizer
1965 doesn't move any instructions from the function body into the
1966 prologue. If this happens, sal.end will be the last
1967 instruction in the first hunk of prologue code just before
1968 the first instruction that the scheduler has moved from
1969 the body to the prologue.
1971 In order to make sure that we scan all of the prologue
1972 instructions, we use a slightly less accurate mechanism which
1973 may scan more than necessary. To help compensate for this
1974 lack of accuracy, the prologue scanning loop below contains
1975 several clauses which'll cause the loop to terminate early if
1976 an implausible prologue instruction is encountered.
1982 is a suitable endpoint since it accounts for the largest
1983 possible prologue plus up to five instructions inserted by
1986 if (prologue_end
> prologue_start
+ 64)
1988 prologue_end
= prologue_start
+ 64; /* See above. */
1993 /* We have no symbol information. Our only option is to assume this
1994 function has a standard stack frame and the normal frame register.
1995 Then, we can find the value of our frame pointer on entrance to
1996 the callee (or at the present moment if this is the innermost frame).
1997 The value stored there should be the address of the stmfd + 8. */
1998 CORE_ADDR frame_loc
;
1999 LONGEST return_value
;
2001 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
2002 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
2006 prologue_start
= gdbarch_addr_bits_remove
2007 (gdbarch
, return_value
) - 8;
2008 prologue_end
= prologue_start
+ 64; /* See above. */
2012 if (prev_pc
< prologue_end
)
2013 prologue_end
= prev_pc
;
2015 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
2018 static struct arm_prologue_cache
*
2019 arm_make_prologue_cache (struct frame_info
*this_frame
)
2022 struct arm_prologue_cache
*cache
;
2023 CORE_ADDR unwound_fp
;
2025 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2026 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2028 arm_scan_prologue (this_frame
, cache
);
2030 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2031 if (unwound_fp
== 0)
2034 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2036 /* Calculate actual addresses of saved registers using offsets
2037 determined by arm_scan_prologue. */
2038 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2039 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2040 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2045 /* Our frame ID for a normal frame is the current function's starting PC
2046 and the caller's SP when we were called. */
2049 arm_prologue_this_id (struct frame_info
*this_frame
,
2051 struct frame_id
*this_id
)
2053 struct arm_prologue_cache
*cache
;
2057 if (*this_cache
== NULL
)
2058 *this_cache
= arm_make_prologue_cache (this_frame
);
2059 cache
= *this_cache
;
2061 /* This is meant to halt the backtrace at "_start". */
2062 pc
= get_frame_pc (this_frame
);
2063 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2066 /* If we've hit a wall, stop. */
2067 if (cache
->prev_sp
== 0)
2070 /* Use function start address as part of the frame ID. If we cannot
2071 identify the start address (due to missing symbol information),
2072 fall back to just using the current PC. */
2073 func
= get_frame_func (this_frame
);
2077 id
= frame_id_build (cache
->prev_sp
, func
);
2081 static struct value
*
2082 arm_prologue_prev_register (struct frame_info
*this_frame
,
2086 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2087 struct arm_prologue_cache
*cache
;
2089 if (*this_cache
== NULL
)
2090 *this_cache
= arm_make_prologue_cache (this_frame
);
2091 cache
= *this_cache
;
2093 /* If we are asked to unwind the PC, then we need to return the LR
2094 instead. The prologue may save PC, but it will point into this
2095 frame's prologue, not the next frame's resume location. Also
2096 strip the saved T bit. A valid LR may have the low bit set, but
2097 a valid PC never does. */
2098 if (prev_regnum
== ARM_PC_REGNUM
)
2102 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2103 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2104 arm_addr_bits_remove (gdbarch
, lr
));
2107 /* SP is generally not saved to the stack, but this frame is
2108 identified by the next frame's stack pointer at the time of the call.
2109 The value was already reconstructed into PREV_SP. */
2110 if (prev_regnum
== ARM_SP_REGNUM
)
2111 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2113 /* The CPSR may have been changed by the call instruction and by the
2114 called function. The only bit we can reconstruct is the T bit,
2115 by checking the low bit of LR as of the call. This is a reliable
2116 indicator of Thumb-ness except for some ARM v4T pre-interworking
2117 Thumb code, which could get away with a clear low bit as long as
2118 the called function did not use bx. Guess that all other
2119 bits are unchanged; the condition flags are presumably lost,
2120 but the processor status is likely valid. */
2121 if (prev_regnum
== ARM_PS_REGNUM
)
2124 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2126 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2127 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2128 if (IS_THUMB_ADDR (lr
))
2132 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2135 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2139 struct frame_unwind arm_prologue_unwind
= {
2141 default_frame_unwind_stop_reason
,
2142 arm_prologue_this_id
,
2143 arm_prologue_prev_register
,
2145 default_frame_sniffer
2148 /* Maintain a list of ARM exception table entries per objfile, similar to the
2149 list of mapping symbols. We only cache entries for standard ARM-defined
2150 personality routines; the cache will contain only the frame unwinding
2151 instructions associated with the entry (not the descriptors). */
2153 static const struct objfile_data
*arm_exidx_data_key
;
2155 struct arm_exidx_entry
2160 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2161 DEF_VEC_O(arm_exidx_entry_s
);
2163 struct arm_exidx_data
2165 VEC(arm_exidx_entry_s
) **section_maps
;
2169 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2171 struct arm_exidx_data
*data
= arg
;
2174 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2175 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2179 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2180 const struct arm_exidx_entry
*rhs
)
2182 return lhs
->addr
< rhs
->addr
;
2185 static struct obj_section
*
2186 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2188 struct obj_section
*osect
;
2190 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2191 if (bfd_get_section_flags (objfile
->obfd
,
2192 osect
->the_bfd_section
) & SEC_ALLOC
)
2194 bfd_vma start
, size
;
2195 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2196 size
= bfd_get_section_size (osect
->the_bfd_section
);
2198 if (start
<= vma
&& vma
< start
+ size
)
2205 /* Parse contents of exception table and exception index sections
2206 of OBJFILE, and fill in the exception table entry cache.
2208 For each entry that refers to a standard ARM-defined personality
2209 routine, extract the frame unwinding instructions (from either
2210 the index or the table section). The unwinding instructions
2212 - extracting them from the rest of the table data
2213 - converting to host endianness
2214 - appending the implicit 0xb0 ("Finish") code
2216 The extracted and normalized instructions are stored for later
2217 retrieval by the arm_find_exidx_entry routine. */
2220 arm_exidx_new_objfile (struct objfile
*objfile
)
2222 struct cleanup
*cleanups
;
2223 struct arm_exidx_data
*data
;
2224 asection
*exidx
, *extab
;
2225 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2226 bfd_size_type exidx_size
= 0, extab_size
= 0;
2227 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2230 /* If we've already touched this file, do nothing. */
2231 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2233 cleanups
= make_cleanup (null_cleanup
, NULL
);
2235 /* Read contents of exception table and index. */
2236 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2239 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2240 exidx_size
= bfd_get_section_size (exidx
);
2241 exidx_data
= xmalloc (exidx_size
);
2242 make_cleanup (xfree
, exidx_data
);
2244 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2245 exidx_data
, 0, exidx_size
))
2247 do_cleanups (cleanups
);
2252 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2255 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2256 extab_size
= bfd_get_section_size (extab
);
2257 extab_data
= xmalloc (extab_size
);
2258 make_cleanup (xfree
, extab_data
);
2260 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2261 extab_data
, 0, extab_size
))
2263 do_cleanups (cleanups
);
2268 /* Allocate exception table data structure. */
2269 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2270 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2271 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2272 objfile
->obfd
->section_count
,
2273 VEC(arm_exidx_entry_s
) *);
2275 /* Fill in exception table. */
2276 for (i
= 0; i
< exidx_size
/ 8; i
++)
2278 struct arm_exidx_entry new_exidx_entry
;
2279 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2280 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2281 bfd_vma addr
= 0, word
= 0;
2282 int n_bytes
= 0, n_words
= 0;
2283 struct obj_section
*sec
;
2284 gdb_byte
*entry
= NULL
;
2286 /* Extract address of start of function. */
2287 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2288 idx
+= exidx_vma
+ i
* 8;
2290 /* Find section containing function and compute section offset. */
2291 sec
= arm_obj_section_from_vma (objfile
, idx
);
2294 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2296 /* Determine address of exception table entry. */
2299 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2301 else if ((val
& 0xff000000) == 0x80000000)
2303 /* Exception table entry embedded in .ARM.exidx
2304 -- must be short form. */
2308 else if (!(val
& 0x80000000))
2310 /* Exception table entry in .ARM.extab. */
2311 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2312 addr
+= exidx_vma
+ i
* 8 + 4;
2314 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2316 word
= bfd_h_get_32 (objfile
->obfd
,
2317 extab_data
+ addr
- extab_vma
);
2320 if ((word
& 0xff000000) == 0x80000000)
2325 else if ((word
& 0xff000000) == 0x81000000
2326 || (word
& 0xff000000) == 0x82000000)
2330 n_words
= ((word
>> 16) & 0xff);
2332 else if (!(word
& 0x80000000))
2335 struct obj_section
*pers_sec
;
2336 int gnu_personality
= 0;
2338 /* Custom personality routine. */
2339 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2340 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2342 /* Check whether we've got one of the variants of the
2343 GNU personality routines. */
2344 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2347 static const char *personality
[] =
2349 "__gcc_personality_v0",
2350 "__gxx_personality_v0",
2351 "__gcj_personality_v0",
2352 "__gnu_objc_personality_v0",
2356 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2359 for (k
= 0; personality
[k
]; k
++)
2360 if (lookup_minimal_symbol_by_pc_name
2361 (pc
, personality
[k
], objfile
))
2363 gnu_personality
= 1;
2368 /* If so, the next word contains a word count in the high
2369 byte, followed by the same unwind instructions as the
2370 pre-defined forms. */
2372 && addr
+ 4 <= extab_vma
+ extab_size
)
2374 word
= bfd_h_get_32 (objfile
->obfd
,
2375 extab_data
+ addr
- extab_vma
);
2378 n_words
= ((word
>> 24) & 0xff);
2384 /* Sanity check address. */
2386 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2387 n_words
= n_bytes
= 0;
2389 /* The unwind instructions reside in WORD (only the N_BYTES least
2390 significant bytes are valid), followed by N_WORDS words in the
2391 extab section starting at ADDR. */
2392 if (n_bytes
|| n_words
)
2394 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2395 n_bytes
+ n_words
* 4 + 1);
2398 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2402 word
= bfd_h_get_32 (objfile
->obfd
,
2403 extab_data
+ addr
- extab_vma
);
2406 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2407 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2408 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2409 *p
++ = (gdb_byte
) (word
& 0xff);
2412 /* Implied "Finish" to terminate the list. */
2416 /* Push entry onto vector. They are guaranteed to always
2417 appear in order of increasing addresses. */
2418 new_exidx_entry
.addr
= idx
;
2419 new_exidx_entry
.entry
= entry
;
2420 VEC_safe_push (arm_exidx_entry_s
,
2421 data
->section_maps
[sec
->the_bfd_section
->index
],
2425 do_cleanups (cleanups
);
2428 /* Search for the exception table entry covering MEMADDR. If one is found,
2429 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2430 set *START to the start of the region covered by this entry. */
2433 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2435 struct obj_section
*sec
;
2437 sec
= find_pc_section (memaddr
);
2440 struct arm_exidx_data
*data
;
2441 VEC(arm_exidx_entry_s
) *map
;
2442 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2445 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2448 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2449 if (!VEC_empty (arm_exidx_entry_s
, map
))
2451 struct arm_exidx_entry
*map_sym
;
2453 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2454 arm_compare_exidx_entries
);
2456 /* VEC_lower_bound finds the earliest ordered insertion
2457 point. If the following symbol starts at this exact
2458 address, we use that; otherwise, the preceding
2459 exception table entry covers this address. */
2460 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2462 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2463 if (map_sym
->addr
== map_key
.addr
)
2466 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2467 return map_sym
->entry
;
2473 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2475 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2476 return map_sym
->entry
;
2485 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2486 instruction list from the ARM exception table entry ENTRY, allocate and
2487 return a prologue cache structure describing how to unwind this frame.
2489 Return NULL if the unwinding instruction list contains a "spare",
2490 "reserved" or "refuse to unwind" instruction as defined in section
2491 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2492 for the ARM Architecture" document. */
2494 static struct arm_prologue_cache
*
2495 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2500 struct arm_prologue_cache
*cache
;
2501 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2502 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2508 /* Whenever we reload SP, we actually have to retrieve its
2509 actual value in the current frame. */
2512 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2514 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2515 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2519 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2520 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2526 /* Decode next unwind instruction. */
2529 if ((insn
& 0xc0) == 0)
2531 int offset
= insn
& 0x3f;
2532 vsp
+= (offset
<< 2) + 4;
2534 else if ((insn
& 0xc0) == 0x40)
2536 int offset
= insn
& 0x3f;
2537 vsp
-= (offset
<< 2) + 4;
2539 else if ((insn
& 0xf0) == 0x80)
2541 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2544 /* The special case of an all-zero mask identifies
2545 "Refuse to unwind". We return NULL to fall back
2546 to the prologue analyzer. */
2550 /* Pop registers r4..r15 under mask. */
2551 for (i
= 0; i
< 12; i
++)
2552 if (mask
& (1 << i
))
2554 cache
->saved_regs
[4 + i
].addr
= vsp
;
2558 /* Special-case popping SP -- we need to reload vsp. */
2559 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2562 else if ((insn
& 0xf0) == 0x90)
2564 int reg
= insn
& 0xf;
2566 /* Reserved cases. */
2567 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2570 /* Set SP from another register and mark VSP for reload. */
2571 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2574 else if ((insn
& 0xf0) == 0xa0)
2576 int count
= insn
& 0x7;
2577 int pop_lr
= (insn
& 0x8) != 0;
2580 /* Pop r4..r[4+count]. */
2581 for (i
= 0; i
<= count
; i
++)
2583 cache
->saved_regs
[4 + i
].addr
= vsp
;
2587 /* If indicated by flag, pop LR as well. */
2590 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2594 else if (insn
== 0xb0)
2596 /* We could only have updated PC by popping into it; if so, it
2597 will show up as address. Otherwise, copy LR into PC. */
2598 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2599 cache
->saved_regs
[ARM_PC_REGNUM
]
2600 = cache
->saved_regs
[ARM_LR_REGNUM
];
2605 else if (insn
== 0xb1)
2607 int mask
= *entry
++;
2610 /* All-zero mask and mask >= 16 is "spare". */
2611 if (mask
== 0 || mask
>= 16)
2614 /* Pop r0..r3 under mask. */
2615 for (i
= 0; i
< 4; i
++)
2616 if (mask
& (1 << i
))
2618 cache
->saved_regs
[i
].addr
= vsp
;
2622 else if (insn
== 0xb2)
2624 ULONGEST offset
= 0;
2629 offset
|= (*entry
& 0x7f) << shift
;
2632 while (*entry
++ & 0x80);
2634 vsp
+= 0x204 + (offset
<< 2);
2636 else if (insn
== 0xb3)
2638 int start
= *entry
>> 4;
2639 int count
= (*entry
++) & 0xf;
2642 /* Only registers D0..D15 are valid here. */
2643 if (start
+ count
>= 16)
2646 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2647 for (i
= 0; i
<= count
; i
++)
2649 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2653 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2656 else if ((insn
& 0xf8) == 0xb8)
2658 int count
= insn
& 0x7;
2661 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2662 for (i
= 0; i
<= count
; i
++)
2664 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2668 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2671 else if (insn
== 0xc6)
2673 int start
= *entry
>> 4;
2674 int count
= (*entry
++) & 0xf;
2677 /* Only registers WR0..WR15 are valid. */
2678 if (start
+ count
>= 16)
2681 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2682 for (i
= 0; i
<= count
; i
++)
2684 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2688 else if (insn
== 0xc7)
2690 int mask
= *entry
++;
2693 /* All-zero mask and mask >= 16 is "spare". */
2694 if (mask
== 0 || mask
>= 16)
2697 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2698 for (i
= 0; i
< 4; i
++)
2699 if (mask
& (1 << i
))
2701 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2705 else if ((insn
& 0xf8) == 0xc0)
2707 int count
= insn
& 0x7;
2710 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2711 for (i
= 0; i
<= count
; i
++)
2713 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2717 else if (insn
== 0xc8)
2719 int start
= *entry
>> 4;
2720 int count
= (*entry
++) & 0xf;
2723 /* Only registers D0..D31 are valid. */
2724 if (start
+ count
>= 16)
2727 /* Pop VFP double-precision registers
2728 D[16+start]..D[16+start+count]. */
2729 for (i
= 0; i
<= count
; i
++)
2731 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2735 else if (insn
== 0xc9)
2737 int start
= *entry
>> 4;
2738 int count
= (*entry
++) & 0xf;
2741 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2742 for (i
= 0; i
<= count
; i
++)
2744 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2748 else if ((insn
& 0xf8) == 0xd0)
2750 int count
= insn
& 0x7;
2753 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2754 for (i
= 0; i
<= count
; i
++)
2756 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2762 /* Everything else is "spare". */
2767 /* If we restore SP from a register, assume this was the frame register.
2768 Otherwise just fall back to SP as frame register. */
2769 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2770 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2772 cache
->framereg
= ARM_SP_REGNUM
;
2774 /* Determine offset to previous frame. */
2776 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2778 /* We already got the previous SP. */
2779 cache
->prev_sp
= vsp
;
2784 /* Unwinding via ARM exception table entries. Note that the sniffer
2785 already computes a filled-in prologue cache, which is then used
2786 with the same arm_prologue_this_id and arm_prologue_prev_register
2787 routines also used for prologue-parsing based unwinding. */
2790 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2791 struct frame_info
*this_frame
,
2792 void **this_prologue_cache
)
2794 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2795 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2796 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2797 struct arm_prologue_cache
*cache
;
2800 /* See if we have an ARM exception table entry covering this address. */
2801 addr_in_block
= get_frame_address_in_block (this_frame
);
2802 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2806 /* The ARM exception table does not describe unwind information
2807 for arbitrary PC values, but is guaranteed to be correct only
2808 at call sites. We have to decide here whether we want to use
2809 ARM exception table information for this frame, or fall back
2810 to using prologue parsing. (Note that if we have DWARF CFI,
2811 this sniffer isn't even called -- CFI is always preferred.)
2813 Before we make this decision, however, we check whether we
2814 actually have *symbol* information for the current frame.
2815 If not, prologue parsing would not work anyway, so we might
2816 as well use the exception table and hope for the best. */
2817 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2821 /* If the next frame is "normal", we are at a call site in this
2822 frame, so exception information is guaranteed to be valid. */
2823 if (get_next_frame (this_frame
)
2824 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2827 /* We also assume exception information is valid if we're currently
2828 blocked in a system call. The system library is supposed to
2829 ensure this, so that e.g. pthread cancellation works. */
2830 if (arm_frame_is_thumb (this_frame
))
2834 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2835 byte_order_for_code
, &insn
)
2836 && (insn
& 0xff00) == 0xdf00 /* svc */)
2843 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2844 byte_order_for_code
, &insn
)
2845 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2849 /* Bail out if we don't know that exception information is valid. */
2853 /* The ARM exception index does not mark the *end* of the region
2854 covered by the entry, and some functions will not have any entry.
2855 To correctly recognize the end of the covered region, the linker
2856 should have inserted dummy records with a CANTUNWIND marker.
2858 Unfortunately, current versions of GNU ld do not reliably do
2859 this, and thus we may have found an incorrect entry above.
2860 As a (temporary) sanity check, we only use the entry if it
2861 lies *within* the bounds of the function. Note that this check
2862 might reject perfectly valid entries that just happen to cover
2863 multiple functions; therefore this check ought to be removed
2864 once the linker is fixed. */
2865 if (func_start
> exidx_region
)
2869 /* Decode the list of unwinding instructions into a prologue cache.
2870 Note that this may fail due to e.g. a "refuse to unwind" code. */
2871 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2875 *this_prologue_cache
= cache
;
2879 struct frame_unwind arm_exidx_unwind
= {
2881 default_frame_unwind_stop_reason
,
2882 arm_prologue_this_id
,
2883 arm_prologue_prev_register
,
2885 arm_exidx_unwind_sniffer
2888 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2889 trampoline, return the target PC. Otherwise return 0.
2891 void call0a (char c, short s, int i, long l) {}
2895 (*pointer_to_call0a) (c, s, i, l);
2898 Instead of calling a stub library function _call_via_xx (xx is
2899 the register name), GCC may inline the trampoline in the object
2900 file as below (register r2 has the address of call0a).
2903 .type main, %function
2912 The trampoline 'bx r2' doesn't belong to main. */
2915 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2917 /* The heuristics of recognizing such trampoline is that FRAME is
2918 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2919 if (arm_frame_is_thumb (frame
))
2923 if (target_read_memory (pc
, buf
, 2) == 0)
2925 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2926 enum bfd_endian byte_order_for_code
2927 = gdbarch_byte_order_for_code (gdbarch
);
2929 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2931 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2934 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2936 /* Clear the LSB so that gdb core sets step-resume
2937 breakpoint at the right address. */
2938 return UNMAKE_THUMB_ADDR (dest
);
2946 static struct arm_prologue_cache
*
2947 arm_make_stub_cache (struct frame_info
*this_frame
)
2949 struct arm_prologue_cache
*cache
;
2951 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2952 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2954 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2959 /* Our frame ID for a stub frame is the current SP and LR. */
2962 arm_stub_this_id (struct frame_info
*this_frame
,
2964 struct frame_id
*this_id
)
2966 struct arm_prologue_cache
*cache
;
2968 if (*this_cache
== NULL
)
2969 *this_cache
= arm_make_stub_cache (this_frame
);
2970 cache
= *this_cache
;
2972 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2976 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2977 struct frame_info
*this_frame
,
2978 void **this_prologue_cache
)
2980 CORE_ADDR addr_in_block
;
2982 CORE_ADDR pc
, start_addr
;
2985 addr_in_block
= get_frame_address_in_block (this_frame
);
2986 pc
= get_frame_pc (this_frame
);
2987 if (in_plt_section (addr_in_block
)
2988 /* We also use the stub winder if the target memory is unreadable
2989 to avoid having the prologue unwinder trying to read it. */
2990 || target_read_memory (pc
, dummy
, 4) != 0)
2993 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2994 && arm_skip_bx_reg (this_frame
, pc
) != 0)
3000 struct frame_unwind arm_stub_unwind
= {
3002 default_frame_unwind_stop_reason
,
3004 arm_prologue_prev_register
,
3006 arm_stub_unwind_sniffer
3009 /* Put here the code to store, into CACHE->saved_regs, the addresses
3010 of the saved registers of frame described by THIS_FRAME. CACHE is
3013 static struct arm_prologue_cache
*
3014 arm_m_exception_cache (struct frame_info
*this_frame
)
3016 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3017 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3018 struct arm_prologue_cache
*cache
;
3019 CORE_ADDR unwound_sp
;
3022 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3023 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3025 unwound_sp
= get_frame_register_unsigned (this_frame
,
3028 /* The hardware saves eight 32-bit words, comprising xPSR,
3029 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3030 "B1.5.6 Exception entry behavior" in
3031 "ARMv7-M Architecture Reference Manual". */
3032 cache
->saved_regs
[0].addr
= unwound_sp
;
3033 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
3034 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
3035 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
3036 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
3037 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
3038 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
3039 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
3041 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3042 aligner between the top of the 32-byte stack frame and the
3043 previous context's stack pointer. */
3044 cache
->prev_sp
= unwound_sp
+ 32;
3045 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
3046 && (xpsr
& (1 << 9)) != 0)
3047 cache
->prev_sp
+= 4;
3052 /* Implementation of function hook 'this_id' in
3053 'struct frame_uwnind'. */
3056 arm_m_exception_this_id (struct frame_info
*this_frame
,
3058 struct frame_id
*this_id
)
3060 struct arm_prologue_cache
*cache
;
3062 if (*this_cache
== NULL
)
3063 *this_cache
= arm_m_exception_cache (this_frame
);
3064 cache
= *this_cache
;
3066 /* Our frame ID for a stub frame is the current SP and LR. */
3067 *this_id
= frame_id_build (cache
->prev_sp
,
3068 get_frame_pc (this_frame
));
3071 /* Implementation of function hook 'prev_register' in
3072 'struct frame_uwnind'. */
3074 static struct value
*
3075 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3079 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3080 struct arm_prologue_cache
*cache
;
3082 if (*this_cache
== NULL
)
3083 *this_cache
= arm_m_exception_cache (this_frame
);
3084 cache
= *this_cache
;
3086 /* The value was already reconstructed into PREV_SP. */
3087 if (prev_regnum
== ARM_SP_REGNUM
)
3088 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3091 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3095 /* Implementation of function hook 'sniffer' in
3096 'struct frame_uwnind'. */
3099 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3100 struct frame_info
*this_frame
,
3101 void **this_prologue_cache
)
3103 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3105 /* No need to check is_m; this sniffer is only registered for
3106 M-profile architectures. */
3108 /* Exception frames return to one of these magic PCs. Other values
3109 are not defined as of v7-M. See details in "B1.5.8 Exception
3110 return behavior" in "ARMv7-M Architecture Reference Manual". */
3111 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3112 || this_pc
== 0xfffffffd)
3118 /* Frame unwinder for M-profile exceptions. */
3120 struct frame_unwind arm_m_exception_unwind
=
3123 default_frame_unwind_stop_reason
,
3124 arm_m_exception_this_id
,
3125 arm_m_exception_prev_register
,
3127 arm_m_exception_unwind_sniffer
3131 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3133 struct arm_prologue_cache
*cache
;
3135 if (*this_cache
== NULL
)
3136 *this_cache
= arm_make_prologue_cache (this_frame
);
3137 cache
= *this_cache
;
3139 return cache
->prev_sp
- cache
->framesize
;
3142 struct frame_base arm_normal_base
= {
3143 &arm_prologue_unwind
,
3144 arm_normal_frame_base
,
3145 arm_normal_frame_base
,
3146 arm_normal_frame_base
3149 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3150 dummy frame. The frame ID's base needs to match the TOS value
3151 saved by save_dummy_frame_tos() and returned from
3152 arm_push_dummy_call, and the PC needs to match the dummy frame's
3155 static struct frame_id
3156 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3158 return frame_id_build (get_frame_register_unsigned (this_frame
,
3160 get_frame_pc (this_frame
));
3163 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3164 be used to construct the previous frame's ID, after looking up the
3165 containing function). */
3168 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3171 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3172 return arm_addr_bits_remove (gdbarch
, pc
);
3176 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3178 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3181 static struct value
*
3182 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3185 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3187 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3192 /* The PC is normally copied from the return column, which
3193 describes saves of LR. However, that version may have an
3194 extra bit set to indicate Thumb state. The bit is not
3196 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3197 return frame_unwind_got_constant (this_frame
, regnum
,
3198 arm_addr_bits_remove (gdbarch
, lr
));
3201 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3202 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3203 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3204 if (IS_THUMB_ADDR (lr
))
3208 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3211 internal_error (__FILE__
, __LINE__
,
3212 _("Unexpected register %d"), regnum
);
3217 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3218 struct dwarf2_frame_state_reg
*reg
,
3219 struct frame_info
*this_frame
)
3225 reg
->how
= DWARF2_FRAME_REG_FN
;
3226 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3229 reg
->how
= DWARF2_FRAME_REG_CFA
;
3234 /* Return true if we are in the function's epilogue, i.e. after the
3235 instruction that destroyed the function's stack frame. */
3238 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3240 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3241 unsigned int insn
, insn2
;
3242 int found_return
= 0, found_stack_adjust
= 0;
3243 CORE_ADDR func_start
, func_end
;
3247 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3250 /* The epilogue is a sequence of instructions along the following lines:
3252 - add stack frame size to SP or FP
3253 - [if frame pointer used] restore SP from FP
3254 - restore registers from SP [may include PC]
3255 - a return-type instruction [if PC wasn't already restored]
3257 In a first pass, we scan forward from the current PC and verify the
3258 instructions we find as compatible with this sequence, ending in a
3261 However, this is not sufficient to distinguish indirect function calls
3262 within a function from indirect tail calls in the epilogue in some cases.
3263 Therefore, if we didn't already find any SP-changing instruction during
3264 forward scan, we add a backward scanning heuristic to ensure we actually
3265 are in the epilogue. */
3268 while (scan_pc
< func_end
&& !found_return
)
3270 if (target_read_memory (scan_pc
, buf
, 2))
3274 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3276 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3278 else if (insn
== 0x46f7) /* mov pc, lr */
3280 else if (thumb_instruction_restores_sp (insn
))
3282 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3285 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3287 if (target_read_memory (scan_pc
, buf
, 2))
3291 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3293 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3295 if (insn2
& 0x8000) /* <registers> include PC. */
3298 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3299 && (insn2
& 0x0fff) == 0x0b04)
3301 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3304 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3305 && (insn2
& 0x0e00) == 0x0a00)
3317 /* Since any instruction in the epilogue sequence, with the possible
3318 exception of return itself, updates the stack pointer, we need to
3319 scan backwards for at most one instruction. Try either a 16-bit or
3320 a 32-bit instruction. This is just a heuristic, so we do not worry
3321 too much about false positives. */
3323 if (pc
- 4 < func_start
)
3325 if (target_read_memory (pc
- 4, buf
, 4))
3328 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3329 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3331 if (thumb_instruction_restores_sp (insn2
))
3332 found_stack_adjust
= 1;
3333 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3334 found_stack_adjust
= 1;
3335 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3336 && (insn2
& 0x0fff) == 0x0b04)
3337 found_stack_adjust
= 1;
3338 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3339 && (insn2
& 0x0e00) == 0x0a00)
3340 found_stack_adjust
= 1;
3342 return found_stack_adjust
;
3345 /* Return true if we are in the function's epilogue, i.e. after the
3346 instruction that destroyed the function's stack frame. */
3349 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3351 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3353 int found_return
, found_stack_adjust
;
3354 CORE_ADDR func_start
, func_end
;
3356 if (arm_pc_is_thumb (gdbarch
, pc
))
3357 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3359 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3362 /* We are in the epilogue if the previous instruction was a stack
3363 adjustment and the next instruction is a possible return (bx, mov
3364 pc, or pop). We could have to scan backwards to find the stack
3365 adjustment, or forwards to find the return, but this is a decent
3366 approximation. First scan forwards. */
3369 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3370 if (bits (insn
, 28, 31) != INST_NV
)
3372 if ((insn
& 0x0ffffff0) == 0x012fff10)
3375 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3378 else if ((insn
& 0x0fff0000) == 0x08bd0000
3379 && (insn
& 0x0000c000) != 0)
3380 /* POP (LDMIA), including PC or LR. */
3387 /* Scan backwards. This is just a heuristic, so do not worry about
3388 false positives from mode changes. */
3390 if (pc
< func_start
+ 4)
3393 found_stack_adjust
= 0;
3394 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3395 if (bits (insn
, 28, 31) != INST_NV
)
3397 if ((insn
& 0x0df0f000) == 0x0080d000)
3398 /* ADD SP (register or immediate). */
3399 found_stack_adjust
= 1;
3400 else if ((insn
& 0x0df0f000) == 0x0040d000)
3401 /* SUB SP (register or immediate). */
3402 found_stack_adjust
= 1;
3403 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
3405 found_stack_adjust
= 1;
3406 else if ((insn
& 0x0fff0000) == 0x08bd0000)
3408 found_stack_adjust
= 1;
3409 else if ((insn
& 0x0fff0000) == 0x049d0000)
3410 /* POP of a single register. */
3411 found_stack_adjust
= 1;
3414 if (found_stack_adjust
)
3421 /* When arguments must be pushed onto the stack, they go on in reverse
3422 order. The code below implements a FILO (stack) to do this. */
3427 struct stack_item
*prev
;
3431 static struct stack_item
*
3432 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3434 struct stack_item
*si
;
3435 si
= xmalloc (sizeof (struct stack_item
));
3436 si
->data
= xmalloc (len
);
3439 memcpy (si
->data
, contents
, len
);
3443 static struct stack_item
*
3444 pop_stack_item (struct stack_item
*si
)
3446 struct stack_item
*dead
= si
;
3454 /* Return the alignment (in bytes) of the given type. */
3457 arm_type_align (struct type
*t
)
3463 t
= check_typedef (t
);
3464 switch (TYPE_CODE (t
))
3467 /* Should never happen. */
3468 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3472 case TYPE_CODE_ENUM
:
3476 case TYPE_CODE_RANGE
:
3478 case TYPE_CODE_CHAR
:
3479 case TYPE_CODE_BOOL
:
3480 return TYPE_LENGTH (t
);
3482 case TYPE_CODE_ARRAY
:
3483 case TYPE_CODE_COMPLEX
:
3484 /* TODO: What about vector types? */
3485 return arm_type_align (TYPE_TARGET_TYPE (t
));
3487 case TYPE_CODE_STRUCT
:
3488 case TYPE_CODE_UNION
:
3490 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3492 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3500 /* Possible base types for a candidate for passing and returning in
3503 enum arm_vfp_cprc_base_type
3512 /* The length of one element of base type B. */
3515 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3519 case VFP_CPRC_SINGLE
:
3521 case VFP_CPRC_DOUBLE
:
3523 case VFP_CPRC_VEC64
:
3525 case VFP_CPRC_VEC128
:
3528 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3533 /* The character ('s', 'd' or 'q') for the type of VFP register used
3534 for passing base type B. */
3537 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3541 case VFP_CPRC_SINGLE
:
3543 case VFP_CPRC_DOUBLE
:
3545 case VFP_CPRC_VEC64
:
3547 case VFP_CPRC_VEC128
:
3550 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3555 /* Determine whether T may be part of a candidate for passing and
3556 returning in VFP registers, ignoring the limit on the total number
3557 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3558 classification of the first valid component found; if it is not
3559 VFP_CPRC_UNKNOWN, all components must have the same classification
3560 as *BASE_TYPE. If it is found that T contains a type not permitted
3561 for passing and returning in VFP registers, a type differently
3562 classified from *BASE_TYPE, or two types differently classified
3563 from each other, return -1, otherwise return the total number of
3564 base-type elements found (possibly 0 in an empty structure or
3565 array). Vector types are not currently supported, matching the
3566 generic AAPCS support. */
3569 arm_vfp_cprc_sub_candidate (struct type
*t
,
3570 enum arm_vfp_cprc_base_type
*base_type
)
3572 t
= check_typedef (t
);
3573 switch (TYPE_CODE (t
))
3576 switch (TYPE_LENGTH (t
))
3579 if (*base_type
== VFP_CPRC_UNKNOWN
)
3580 *base_type
= VFP_CPRC_SINGLE
;
3581 else if (*base_type
!= VFP_CPRC_SINGLE
)
3586 if (*base_type
== VFP_CPRC_UNKNOWN
)
3587 *base_type
= VFP_CPRC_DOUBLE
;
3588 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3597 case TYPE_CODE_COMPLEX
:
3598 /* Arguments of complex T where T is one of the types float or
3599 double get treated as if they are implemented as:
3608 switch (TYPE_LENGTH (t
))
3611 if (*base_type
== VFP_CPRC_UNKNOWN
)
3612 *base_type
= VFP_CPRC_SINGLE
;
3613 else if (*base_type
!= VFP_CPRC_SINGLE
)
3618 if (*base_type
== VFP_CPRC_UNKNOWN
)
3619 *base_type
= VFP_CPRC_DOUBLE
;
3620 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3629 case TYPE_CODE_ARRAY
:
3633 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3636 if (TYPE_LENGTH (t
) == 0)
3638 gdb_assert (count
== 0);
3641 else if (count
== 0)
3643 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3644 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3645 return TYPE_LENGTH (t
) / unitlen
;
3649 case TYPE_CODE_STRUCT
:
3654 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3656 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3658 if (sub_count
== -1)
3662 if (TYPE_LENGTH (t
) == 0)
3664 gdb_assert (count
== 0);
3667 else if (count
== 0)
3669 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3670 if (TYPE_LENGTH (t
) != unitlen
* count
)
3675 case TYPE_CODE_UNION
:
3680 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3682 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3684 if (sub_count
== -1)
3686 count
= (count
> sub_count
? count
: sub_count
);
3688 if (TYPE_LENGTH (t
) == 0)
3690 gdb_assert (count
== 0);
3693 else if (count
== 0)
3695 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3696 if (TYPE_LENGTH (t
) != unitlen
* count
)
3708 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3709 if passed to or returned from a non-variadic function with the VFP
3710 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3711 *BASE_TYPE to the base type for T and *COUNT to the number of
3712 elements of that base type before returning. */
3715 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3718 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3719 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3720 if (c
<= 0 || c
> 4)
3727 /* Return 1 if the VFP ABI should be used for passing arguments to and
3728 returning values from a function of type FUNC_TYPE, 0
3732 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3735 /* Variadic functions always use the base ABI. Assume that functions
3736 without debug info are not variadic. */
3737 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3739 /* The VFP ABI is only supported as a variant of AAPCS. */
3740 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3742 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3745 /* We currently only support passing parameters in integer registers, which
3746 conforms with GCC's default model, and VFP argument passing following
3747 the VFP variant of AAPCS. Several other variants exist and
3748 we should probably support some of them based on the selected ABI. */
3751 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3752 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3753 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3754 CORE_ADDR struct_addr
)
3756 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3760 struct stack_item
*si
= NULL
;
3763 unsigned vfp_regs_free
= (1 << 16) - 1;
3765 /* Determine the type of this function and whether the VFP ABI
3767 ftype
= check_typedef (value_type (function
));
3768 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3769 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3770 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3772 /* Set the return address. For the ARM, the return breakpoint is
3773 always at BP_ADDR. */
3774 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3776 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3778 /* Walk through the list of args and determine how large a temporary
3779 stack is required. Need to take care here as structs may be
3780 passed on the stack, and we have to push them. */
3783 argreg
= ARM_A1_REGNUM
;
3786 /* The struct_return pointer occupies the first parameter
3787 passing register. */
3791 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3792 gdbarch_register_name (gdbarch
, argreg
),
3793 paddress (gdbarch
, struct_addr
));
3794 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3798 for (argnum
= 0; argnum
< nargs
; argnum
++)
3801 struct type
*arg_type
;
3802 struct type
*target_type
;
3803 enum type_code typecode
;
3804 const bfd_byte
*val
;
3806 enum arm_vfp_cprc_base_type vfp_base_type
;
3808 int may_use_core_reg
= 1;
3810 arg_type
= check_typedef (value_type (args
[argnum
]));
3811 len
= TYPE_LENGTH (arg_type
);
3812 target_type
= TYPE_TARGET_TYPE (arg_type
);
3813 typecode
= TYPE_CODE (arg_type
);
3814 val
= value_contents (args
[argnum
]);
3816 align
= arm_type_align (arg_type
);
3817 /* Round alignment up to a whole number of words. */
3818 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3819 /* Different ABIs have different maximum alignments. */
3820 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3822 /* The APCS ABI only requires word alignment. */
3823 align
= INT_REGISTER_SIZE
;
3827 /* The AAPCS requires at most doubleword alignment. */
3828 if (align
> INT_REGISTER_SIZE
* 2)
3829 align
= INT_REGISTER_SIZE
* 2;
3833 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3841 /* Because this is a CPRC it cannot go in a core register or
3842 cause a core register to be skipped for alignment.
3843 Either it goes in VFP registers and the rest of this loop
3844 iteration is skipped for this argument, or it goes on the
3845 stack (and the stack alignment code is correct for this
3847 may_use_core_reg
= 0;
3849 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3850 shift
= unit_length
/ 4;
3851 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3852 for (regno
= 0; regno
< 16; regno
+= shift
)
3853 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3862 vfp_regs_free
&= ~(mask
<< regno
);
3863 reg_scaled
= regno
/ shift
;
3864 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3865 for (i
= 0; i
< vfp_base_count
; i
++)
3869 if (reg_char
== 'q')
3870 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3871 val
+ i
* unit_length
);
3874 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3875 reg_char
, reg_scaled
+ i
);
3876 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3878 regcache_cooked_write (regcache
, regnum
,
3879 val
+ i
* unit_length
);
3886 /* This CPRC could not go in VFP registers, so all VFP
3887 registers are now marked as used. */
3892 /* Push stack padding for dowubleword alignment. */
3893 if (nstack
& (align
- 1))
3895 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3896 nstack
+= INT_REGISTER_SIZE
;
3899 /* Doubleword aligned quantities must go in even register pairs. */
3900 if (may_use_core_reg
3901 && argreg
<= ARM_LAST_ARG_REGNUM
3902 && align
> INT_REGISTER_SIZE
3906 /* If the argument is a pointer to a function, and it is a
3907 Thumb function, create a LOCAL copy of the value and set
3908 the THUMB bit in it. */
3909 if (TYPE_CODE_PTR
== typecode
3910 && target_type
!= NULL
3911 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3913 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3914 if (arm_pc_is_thumb (gdbarch
, regval
))
3916 bfd_byte
*copy
= alloca (len
);
3917 store_unsigned_integer (copy
, len
, byte_order
,
3918 MAKE_THUMB_ADDR (regval
));
3923 /* Copy the argument to general registers or the stack in
3924 register-sized pieces. Large arguments are split between
3925 registers and stack. */
3928 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3930 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3932 /* The argument is being passed in a general purpose
3935 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3936 if (byte_order
== BFD_ENDIAN_BIG
)
3937 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3939 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3941 gdbarch_register_name
3943 phex (regval
, INT_REGISTER_SIZE
));
3944 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3949 /* Push the arguments onto the stack. */
3951 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3953 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3954 nstack
+= INT_REGISTER_SIZE
;
3961 /* If we have an odd number of words to push, then decrement the stack
3962 by one word now, so first stack argument will be dword aligned. */
3969 write_memory (sp
, si
->data
, si
->len
);
3970 si
= pop_stack_item (si
);
3973 /* Finally, update teh SP register. */
3974 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3980 /* Always align the frame to an 8-byte boundary. This is required on
3981 some platforms and harmless on the rest. */
3984 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3986 /* Align the stack to eight bytes. */
3987 return sp
& ~ (CORE_ADDR
) 7;
3991 print_fpu_flags (struct ui_file
*file
, int flags
)
3993 if (flags
& (1 << 0))
3994 fputs_filtered ("IVO ", file
);
3995 if (flags
& (1 << 1))
3996 fputs_filtered ("DVZ ", file
);
3997 if (flags
& (1 << 2))
3998 fputs_filtered ("OFL ", file
);
3999 if (flags
& (1 << 3))
4000 fputs_filtered ("UFL ", file
);
4001 if (flags
& (1 << 4))
4002 fputs_filtered ("INX ", file
);
4003 fputc_filtered ('\n', file
);
4006 /* Print interesting information about the floating point processor
4007 (if present) or emulator. */
4009 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4010 struct frame_info
*frame
, const char *args
)
4012 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
4015 type
= (status
>> 24) & 127;
4016 if (status
& (1 << 31))
4017 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
4019 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
4020 /* i18n: [floating point unit] mask */
4021 fputs_filtered (_("mask: "), file
);
4022 print_fpu_flags (file
, status
>> 16);
4023 /* i18n: [floating point unit] flags */
4024 fputs_filtered (_("flags: "), file
);
4025 print_fpu_flags (file
, status
);
4028 /* Construct the ARM extended floating point type. */
4029 static struct type
*
4030 arm_ext_type (struct gdbarch
*gdbarch
)
4032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4034 if (!tdep
->arm_ext_type
)
4036 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
4037 floatformats_arm_ext
);
4039 return tdep
->arm_ext_type
;
4042 static struct type
*
4043 arm_neon_double_type (struct gdbarch
*gdbarch
)
4045 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4047 if (tdep
->neon_double_type
== NULL
)
4049 struct type
*t
, *elem
;
4051 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4053 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4054 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4055 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4056 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4057 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4058 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4059 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4060 append_composite_type_field (t
, "u64", elem
);
4061 elem
= builtin_type (gdbarch
)->builtin_float
;
4062 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4063 elem
= builtin_type (gdbarch
)->builtin_double
;
4064 append_composite_type_field (t
, "f64", elem
);
4066 TYPE_VECTOR (t
) = 1;
4067 TYPE_NAME (t
) = "neon_d";
4068 tdep
->neon_double_type
= t
;
4071 return tdep
->neon_double_type
;
4074 /* FIXME: The vector types are not correctly ordered on big-endian
4075 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4076 bits of d0 - regardless of what unit size is being held in d0. So
4077 the offset of the first uint8 in d0 is 7, but the offset of the
4078 first float is 4. This code works as-is for little-endian
4081 static struct type
*
4082 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4084 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4086 if (tdep
->neon_quad_type
== NULL
)
4088 struct type
*t
, *elem
;
4090 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4092 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4093 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4094 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4095 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4096 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4097 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4098 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4099 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4100 elem
= builtin_type (gdbarch
)->builtin_float
;
4101 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4102 elem
= builtin_type (gdbarch
)->builtin_double
;
4103 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4105 TYPE_VECTOR (t
) = 1;
4106 TYPE_NAME (t
) = "neon_q";
4107 tdep
->neon_quad_type
= t
;
4110 return tdep
->neon_quad_type
;
4113 /* Return the GDB type object for the "standard" data type of data in
4116 static struct type
*
4117 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4119 int num_regs
= gdbarch_num_regs (gdbarch
);
4121 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4122 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4123 return builtin_type (gdbarch
)->builtin_float
;
4125 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4126 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4127 return arm_neon_quad_type (gdbarch
);
4129 /* If the target description has register information, we are only
4130 in this function so that we can override the types of
4131 double-precision registers for NEON. */
4132 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4134 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4136 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4137 && TYPE_CODE (t
) == TYPE_CODE_FLT
4138 && gdbarch_tdep (gdbarch
)->have_neon
)
4139 return arm_neon_double_type (gdbarch
);
4144 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4146 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4147 return builtin_type (gdbarch
)->builtin_void
;
4149 return arm_ext_type (gdbarch
);
4151 else if (regnum
== ARM_SP_REGNUM
)
4152 return builtin_type (gdbarch
)->builtin_data_ptr
;
4153 else if (regnum
== ARM_PC_REGNUM
)
4154 return builtin_type (gdbarch
)->builtin_func_ptr
;
4155 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4156 /* These registers are only supported on targets which supply
4157 an XML description. */
4158 return builtin_type (gdbarch
)->builtin_int0
;
4160 return builtin_type (gdbarch
)->builtin_uint32
;
4163 /* Map a DWARF register REGNUM onto the appropriate GDB register
4167 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4169 /* Core integer regs. */
4170 if (reg
>= 0 && reg
<= 15)
4173 /* Legacy FPA encoding. These were once used in a way which
4174 overlapped with VFP register numbering, so their use is
4175 discouraged, but GDB doesn't support the ARM toolchain
4176 which used them for VFP. */
4177 if (reg
>= 16 && reg
<= 23)
4178 return ARM_F0_REGNUM
+ reg
- 16;
4180 /* New assignments for the FPA registers. */
4181 if (reg
>= 96 && reg
<= 103)
4182 return ARM_F0_REGNUM
+ reg
- 96;
4184 /* WMMX register assignments. */
4185 if (reg
>= 104 && reg
<= 111)
4186 return ARM_WCGR0_REGNUM
+ reg
- 104;
4188 if (reg
>= 112 && reg
<= 127)
4189 return ARM_WR0_REGNUM
+ reg
- 112;
4191 if (reg
>= 192 && reg
<= 199)
4192 return ARM_WC0_REGNUM
+ reg
- 192;
4194 /* VFP v2 registers. A double precision value is actually
4195 in d1 rather than s2, but the ABI only defines numbering
4196 for the single precision registers. This will "just work"
4197 in GDB for little endian targets (we'll read eight bytes,
4198 starting in s0 and then progressing to s1), but will be
4199 reversed on big endian targets with VFP. This won't
4200 be a problem for the new Neon quad registers; you're supposed
4201 to use DW_OP_piece for those. */
4202 if (reg
>= 64 && reg
<= 95)
4206 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4207 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4211 /* VFP v3 / Neon registers. This range is also used for VFP v2
4212 registers, except that it now describes d0 instead of s0. */
4213 if (reg
>= 256 && reg
<= 287)
4217 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4218 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4225 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4227 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4230 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4232 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4233 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4235 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4236 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4238 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4239 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4241 if (reg
< NUM_GREGS
)
4242 return SIM_ARM_R0_REGNUM
+ reg
;
4245 if (reg
< NUM_FREGS
)
4246 return SIM_ARM_FP0_REGNUM
+ reg
;
4249 if (reg
< NUM_SREGS
)
4250 return SIM_ARM_FPS_REGNUM
+ reg
;
4253 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4256 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4257 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4258 It is thought that this is is the floating-point register format on
4259 little-endian systems. */
4262 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4263 void *dbl
, int endianess
)
4267 if (endianess
== BFD_ENDIAN_BIG
)
4268 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4270 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4272 floatformat_from_doublest (fmt
, &d
, dbl
);
4276 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4281 floatformat_to_doublest (fmt
, ptr
, &d
);
4282 if (endianess
== BFD_ENDIAN_BIG
)
4283 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4285 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4290 condition_true (unsigned long cond
, unsigned long status_reg
)
4292 if (cond
== INST_AL
|| cond
== INST_NV
)
4298 return ((status_reg
& FLAG_Z
) != 0);
4300 return ((status_reg
& FLAG_Z
) == 0);
4302 return ((status_reg
& FLAG_C
) != 0);
4304 return ((status_reg
& FLAG_C
) == 0);
4306 return ((status_reg
& FLAG_N
) != 0);
4308 return ((status_reg
& FLAG_N
) == 0);
4310 return ((status_reg
& FLAG_V
) != 0);
4312 return ((status_reg
& FLAG_V
) == 0);
4314 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4316 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4318 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4320 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4322 return (((status_reg
& FLAG_Z
) == 0)
4323 && (((status_reg
& FLAG_N
) == 0)
4324 == ((status_reg
& FLAG_V
) == 0)));
4326 return (((status_reg
& FLAG_Z
) != 0)
4327 || (((status_reg
& FLAG_N
) == 0)
4328 != ((status_reg
& FLAG_V
) == 0)));
4333 static unsigned long
4334 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4335 unsigned long pc_val
, unsigned long status_reg
)
4337 unsigned long res
, shift
;
4338 int rm
= bits (inst
, 0, 3);
4339 unsigned long shifttype
= bits (inst
, 5, 6);
4343 int rs
= bits (inst
, 8, 11);
4344 shift
= (rs
== 15 ? pc_val
+ 8
4345 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4348 shift
= bits (inst
, 7, 11);
4350 res
= (rm
== ARM_PC_REGNUM
4351 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4352 : get_frame_register_unsigned (frame
, rm
));
4357 res
= shift
>= 32 ? 0 : res
<< shift
;
4361 res
= shift
>= 32 ? 0 : res
>> shift
;
4367 res
= ((res
& 0x80000000L
)
4368 ? ~((~res
) >> shift
) : res
>> shift
);
4371 case 3: /* ROR/RRX */
4374 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4376 res
= (res
>> shift
) | (res
<< (32 - shift
));
4380 return res
& 0xffffffff;
4383 /* Return number of 1-bits in VAL. */
4386 bitcount (unsigned long val
)
4389 for (nbits
= 0; val
!= 0; nbits
++)
4390 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4394 /* Return the size in bytes of the complete Thumb instruction whose
4395 first halfword is INST1. */
4398 thumb_insn_size (unsigned short inst1
)
4400 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4407 thumb_advance_itstate (unsigned int itstate
)
4409 /* Preserve IT[7:5], the first three bits of the condition. Shift
4410 the upcoming condition flags left by one bit. */
4411 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4413 /* If we have finished the IT block, clear the state. */
4414 if ((itstate
& 0x0f) == 0)
4420 /* Find the next PC after the current instruction executes. In some
4421 cases we can not statically determine the answer (see the IT state
4422 handling in this function); in that case, a breakpoint may be
4423 inserted in addition to the returned PC, which will be used to set
4424 another breakpoint by our caller. */
4427 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4429 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4430 struct address_space
*aspace
= get_frame_address_space (frame
);
4431 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4432 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4433 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4434 unsigned short inst1
;
4435 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4436 unsigned long offset
;
4437 ULONGEST status
, itstate
;
4439 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4440 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4442 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4444 /* Thumb-2 conditional execution support. There are eight bits in
4445 the CPSR which describe conditional execution state. Once
4446 reconstructed (they're in a funny order), the low five bits
4447 describe the low bit of the condition for each instruction and
4448 how many instructions remain. The high three bits describe the
4449 base condition. One of the low four bits will be set if an IT
4450 block is active. These bits read as zero on earlier
4452 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4453 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4455 /* If-Then handling. On GNU/Linux, where this routine is used, we
4456 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4457 can disable execution of the undefined instruction. So we might
4458 miss the breakpoint if we set it on a skipped conditional
4459 instruction. Because conditional instructions can change the
4460 flags, affecting the execution of further instructions, we may
4461 need to set two breakpoints. */
4463 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4465 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4467 /* An IT instruction. Because this instruction does not
4468 modify the flags, we can accurately predict the next
4469 executed instruction. */
4470 itstate
= inst1
& 0x00ff;
4471 pc
+= thumb_insn_size (inst1
);
4473 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4475 inst1
= read_memory_unsigned_integer (pc
, 2,
4476 byte_order_for_code
);
4477 pc
+= thumb_insn_size (inst1
);
4478 itstate
= thumb_advance_itstate (itstate
);
4481 return MAKE_THUMB_ADDR (pc
);
4483 else if (itstate
!= 0)
4485 /* We are in a conditional block. Check the condition. */
4486 if (! condition_true (itstate
>> 4, status
))
4488 /* Advance to the next executed instruction. */
4489 pc
+= thumb_insn_size (inst1
);
4490 itstate
= thumb_advance_itstate (itstate
);
4492 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4494 inst1
= read_memory_unsigned_integer (pc
, 2,
4495 byte_order_for_code
);
4496 pc
+= thumb_insn_size (inst1
);
4497 itstate
= thumb_advance_itstate (itstate
);
4500 return MAKE_THUMB_ADDR (pc
);
4502 else if ((itstate
& 0x0f) == 0x08)
4504 /* This is the last instruction of the conditional
4505 block, and it is executed. We can handle it normally
4506 because the following instruction is not conditional,
4507 and we must handle it normally because it is
4508 permitted to branch. Fall through. */
4514 /* There are conditional instructions after this one.
4515 If this instruction modifies the flags, then we can
4516 not predict what the next executed instruction will
4517 be. Fortunately, this instruction is architecturally
4518 forbidden to branch; we know it will fall through.
4519 Start by skipping past it. */
4520 pc
+= thumb_insn_size (inst1
);
4521 itstate
= thumb_advance_itstate (itstate
);
4523 /* Set a breakpoint on the following instruction. */
4524 gdb_assert ((itstate
& 0x0f) != 0);
4525 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4526 MAKE_THUMB_ADDR (pc
));
4527 cond_negated
= (itstate
>> 4) & 1;
4529 /* Skip all following instructions with the same
4530 condition. If there is a later instruction in the IT
4531 block with the opposite condition, set the other
4532 breakpoint there. If not, then set a breakpoint on
4533 the instruction after the IT block. */
4536 inst1
= read_memory_unsigned_integer (pc
, 2,
4537 byte_order_for_code
);
4538 pc
+= thumb_insn_size (inst1
);
4539 itstate
= thumb_advance_itstate (itstate
);
4541 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4543 return MAKE_THUMB_ADDR (pc
);
4547 else if (itstate
& 0x0f)
4549 /* We are in a conditional block. Check the condition. */
4550 int cond
= itstate
>> 4;
4552 if (! condition_true (cond
, status
))
4553 /* Advance to the next instruction. All the 32-bit
4554 instructions share a common prefix. */
4555 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4557 /* Otherwise, handle the instruction normally. */
4560 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4564 /* Fetch the saved PC from the stack. It's stored above
4565 all of the other registers. */
4566 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4567 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4568 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4570 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4572 unsigned long cond
= bits (inst1
, 8, 11);
4573 if (cond
== 0x0f) /* 0x0f = SWI */
4575 struct gdbarch_tdep
*tdep
;
4576 tdep
= gdbarch_tdep (gdbarch
);
4578 if (tdep
->syscall_next_pc
!= NULL
)
4579 nextpc
= tdep
->syscall_next_pc (frame
);
4582 else if (cond
!= 0x0f && condition_true (cond
, status
))
4583 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4585 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4587 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4589 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4591 unsigned short inst2
;
4592 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4594 /* Default to the next instruction. */
4596 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4598 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4600 /* Branches and miscellaneous control instructions. */
4602 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4605 int j1
, j2
, imm1
, imm2
;
4607 imm1
= sbits (inst1
, 0, 10);
4608 imm2
= bits (inst2
, 0, 10);
4609 j1
= bit (inst2
, 13);
4610 j2
= bit (inst2
, 11);
4612 offset
= ((imm1
<< 12) + (imm2
<< 1));
4613 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4615 nextpc
= pc_val
+ offset
;
4616 /* For BLX make sure to clear the low bits. */
4617 if (bit (inst2
, 12) == 0)
4618 nextpc
= nextpc
& 0xfffffffc;
4620 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4622 /* SUBS PC, LR, #imm8. */
4623 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4624 nextpc
-= inst2
& 0x00ff;
4626 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4628 /* Conditional branch. */
4629 if (condition_true (bits (inst1
, 6, 9), status
))
4631 int sign
, j1
, j2
, imm1
, imm2
;
4633 sign
= sbits (inst1
, 10, 10);
4634 imm1
= bits (inst1
, 0, 5);
4635 imm2
= bits (inst2
, 0, 10);
4636 j1
= bit (inst2
, 13);
4637 j2
= bit (inst2
, 11);
4639 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4640 offset
+= (imm1
<< 12) + (imm2
<< 1);
4642 nextpc
= pc_val
+ offset
;
4646 else if ((inst1
& 0xfe50) == 0xe810)
4648 /* Load multiple or RFE. */
4649 int rn
, offset
, load_pc
= 1;
4651 rn
= bits (inst1
, 0, 3);
4652 if (bit (inst1
, 7) && !bit (inst1
, 8))
4655 if (!bit (inst2
, 15))
4657 offset
= bitcount (inst2
) * 4 - 4;
4659 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4662 if (!bit (inst2
, 15))
4666 else if (bit (inst1
, 7) && bit (inst1
, 8))
4671 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4681 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4682 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4685 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4687 /* MOV PC or MOVS PC. */
4688 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4689 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4691 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4695 int rn
, load_pc
= 1;
4697 rn
= bits (inst1
, 0, 3);
4698 base
= get_frame_register_unsigned (frame
, rn
);
4699 if (rn
== ARM_PC_REGNUM
)
4701 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4703 base
+= bits (inst2
, 0, 11);
4705 base
-= bits (inst2
, 0, 11);
4707 else if (bit (inst1
, 7))
4708 base
+= bits (inst2
, 0, 11);
4709 else if (bit (inst2
, 11))
4711 if (bit (inst2
, 10))
4714 base
+= bits (inst2
, 0, 7);
4716 base
-= bits (inst2
, 0, 7);
4719 else if ((inst2
& 0x0fc0) == 0x0000)
4721 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4722 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4729 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4731 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4734 CORE_ADDR tbl_reg
, table
, offset
, length
;
4736 tbl_reg
= bits (inst1
, 0, 3);
4737 if (tbl_reg
== 0x0f)
4738 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4740 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4742 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4743 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4744 nextpc
= pc_val
+ length
;
4746 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4749 CORE_ADDR tbl_reg
, table
, offset
, length
;
4751 tbl_reg
= bits (inst1
, 0, 3);
4752 if (tbl_reg
== 0x0f)
4753 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4755 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4757 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4758 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4759 nextpc
= pc_val
+ length
;
4762 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4764 if (bits (inst1
, 3, 6) == 0x0f)
4765 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4767 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4769 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4771 if (bits (inst1
, 3, 6) == 0x0f)
4774 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4776 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4778 else if ((inst1
& 0xf500) == 0xb100)
4781 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4782 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4784 if (bit (inst1
, 11) && reg
!= 0)
4785 nextpc
= pc_val
+ imm
;
4786 else if (!bit (inst1
, 11) && reg
== 0)
4787 nextpc
= pc_val
+ imm
;
4792 /* Get the raw next address. PC is the current program counter, in
4793 FRAME, which is assumed to be executing in ARM mode.
4795 The value returned has the execution state of the next instruction
4796 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4797 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4801 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4803 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4804 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4805 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4806 unsigned long pc_val
;
4807 unsigned long this_instr
;
4808 unsigned long status
;
4811 pc_val
= (unsigned long) pc
;
4812 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4814 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4815 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4817 if (bits (this_instr
, 28, 31) == INST_NV
)
4818 switch (bits (this_instr
, 24, 27))
4823 /* Branch with Link and change to Thumb. */
4824 nextpc
= BranchDest (pc
, this_instr
);
4825 nextpc
|= bit (this_instr
, 24) << 1;
4826 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4832 /* Coprocessor register transfer. */
4833 if (bits (this_instr
, 12, 15) == 15)
4834 error (_("Invalid update to pc in instruction"));
4837 else if (condition_true (bits (this_instr
, 28, 31), status
))
4839 switch (bits (this_instr
, 24, 27))
4842 case 0x1: /* data processing */
4846 unsigned long operand1
, operand2
, result
= 0;
4850 if (bits (this_instr
, 12, 15) != 15)
4853 if (bits (this_instr
, 22, 25) == 0
4854 && bits (this_instr
, 4, 7) == 9) /* multiply */
4855 error (_("Invalid update to pc in instruction"));
4857 /* BX <reg>, BLX <reg> */
4858 if (bits (this_instr
, 4, 27) == 0x12fff1
4859 || bits (this_instr
, 4, 27) == 0x12fff3)
4861 rn
= bits (this_instr
, 0, 3);
4862 nextpc
= ((rn
== ARM_PC_REGNUM
)
4864 : get_frame_register_unsigned (frame
, rn
));
4869 /* Multiply into PC. */
4870 c
= (status
& FLAG_C
) ? 1 : 0;
4871 rn
= bits (this_instr
, 16, 19);
4872 operand1
= ((rn
== ARM_PC_REGNUM
)
4874 : get_frame_register_unsigned (frame
, rn
));
4876 if (bit (this_instr
, 25))
4878 unsigned long immval
= bits (this_instr
, 0, 7);
4879 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4880 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4883 else /* operand 2 is a shifted register. */
4884 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4887 switch (bits (this_instr
, 21, 24))
4890 result
= operand1
& operand2
;
4894 result
= operand1
^ operand2
;
4898 result
= operand1
- operand2
;
4902 result
= operand2
- operand1
;
4906 result
= operand1
+ operand2
;
4910 result
= operand1
+ operand2
+ c
;
4914 result
= operand1
- operand2
+ c
;
4918 result
= operand2
- operand1
+ c
;
4924 case 0xb: /* tst, teq, cmp, cmn */
4925 result
= (unsigned long) nextpc
;
4929 result
= operand1
| operand2
;
4933 /* Always step into a function. */
4938 result
= operand1
& ~operand2
;
4946 /* In 26-bit APCS the bottom two bits of the result are
4947 ignored, and we always end up in ARM state. */
4949 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4957 case 0x5: /* data transfer */
4960 if (bit (this_instr
, 20))
4963 if (bits (this_instr
, 12, 15) == 15)
4969 if (bit (this_instr
, 22))
4970 error (_("Invalid update to pc in instruction"));
4972 /* byte write to PC */
4973 rn
= bits (this_instr
, 16, 19);
4974 base
= ((rn
== ARM_PC_REGNUM
)
4976 : get_frame_register_unsigned (frame
, rn
));
4978 if (bit (this_instr
, 24))
4981 int c
= (status
& FLAG_C
) ? 1 : 0;
4982 unsigned long offset
=
4983 (bit (this_instr
, 25)
4984 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4985 : bits (this_instr
, 0, 11));
4987 if (bit (this_instr
, 23))
4993 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
5000 case 0x9: /* block transfer */
5001 if (bit (this_instr
, 20))
5004 if (bit (this_instr
, 15))
5008 unsigned long rn_val
5009 = get_frame_register_unsigned (frame
,
5010 bits (this_instr
, 16, 19));
5012 if (bit (this_instr
, 23))
5015 unsigned long reglist
= bits (this_instr
, 0, 14);
5016 offset
= bitcount (reglist
) * 4;
5017 if (bit (this_instr
, 24)) /* pre */
5020 else if (bit (this_instr
, 24))
5024 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
5031 case 0xb: /* branch & link */
5032 case 0xa: /* branch */
5034 nextpc
= BranchDest (pc
, this_instr
);
5040 case 0xe: /* coproc ops */
5044 struct gdbarch_tdep
*tdep
;
5045 tdep
= gdbarch_tdep (gdbarch
);
5047 if (tdep
->syscall_next_pc
!= NULL
)
5048 nextpc
= tdep
->syscall_next_pc (frame
);
5054 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
5062 /* Determine next PC after current instruction executes. Will call either
5063 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5064 loop is detected. */
5067 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5071 if (arm_frame_is_thumb (frame
))
5072 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
5074 nextpc
= arm_get_next_pc_raw (frame
, pc
);
5079 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5080 of the appropriate mode (as encoded in the PC value), even if this
5081 differs from what would be expected according to the symbol tables. */
5084 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
5085 struct address_space
*aspace
,
5088 struct cleanup
*old_chain
5089 = make_cleanup_restore_integer (&arm_override_mode
);
5091 arm_override_mode
= IS_THUMB_ADDR (pc
);
5092 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
5094 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
5096 do_cleanups (old_chain
);
5099 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5100 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5101 is found, attempt to step through it. A breakpoint is placed at the end of
5105 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5107 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5108 struct address_space
*aspace
= get_frame_address_space (frame
);
5109 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5110 CORE_ADDR pc
= get_frame_pc (frame
);
5111 CORE_ADDR breaks
[2] = {-1, -1};
5113 unsigned short insn1
, insn2
;
5116 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5117 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5118 ULONGEST status
, itstate
;
5120 /* We currently do not support atomic sequences within an IT block. */
5121 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
5122 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
5126 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5127 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5129 if (thumb_insn_size (insn1
) != 4)
5132 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5134 if (!((insn1
& 0xfff0) == 0xe850
5135 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
5138 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5140 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5142 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5145 if (thumb_insn_size (insn1
) != 4)
5147 /* Assume that there is at most one conditional branch in the
5148 atomic sequence. If a conditional branch is found, put a
5149 breakpoint in its destination address. */
5150 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
5152 if (last_breakpoint
> 0)
5153 return 0; /* More than one conditional branch found,
5154 fallback to the standard code. */
5156 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
5160 /* We do not support atomic sequences that use any *other*
5161 instructions but conditional branches to change the PC.
5162 Fall back to standard code to avoid losing control of
5164 else if (thumb_instruction_changes_pc (insn1
))
5169 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5172 /* Assume that there is at most one conditional branch in the
5173 atomic sequence. If a conditional branch is found, put a
5174 breakpoint in its destination address. */
5175 if ((insn1
& 0xf800) == 0xf000
5176 && (insn2
& 0xd000) == 0x8000
5177 && (insn1
& 0x0380) != 0x0380)
5179 int sign
, j1
, j2
, imm1
, imm2
;
5180 unsigned int offset
;
5182 sign
= sbits (insn1
, 10, 10);
5183 imm1
= bits (insn1
, 0, 5);
5184 imm2
= bits (insn2
, 0, 10);
5185 j1
= bit (insn2
, 13);
5186 j2
= bit (insn2
, 11);
5188 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
5189 offset
+= (imm1
<< 12) + (imm2
<< 1);
5191 if (last_breakpoint
> 0)
5192 return 0; /* More than one conditional branch found,
5193 fallback to the standard code. */
5195 breaks
[1] = loc
+ offset
;
5199 /* We do not support atomic sequences that use any *other*
5200 instructions but conditional branches to change the PC.
5201 Fall back to standard code to avoid losing control of
5203 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
5206 /* If we find a strex{,b,h,d}, we're done. */
5207 if ((insn1
& 0xfff0) == 0xe840
5208 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5213 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5214 if (insn_count
== atomic_sequence_length
)
5217 /* Insert a breakpoint right after the end of the atomic sequence. */
5220 /* Check for duplicated breakpoints. Check also for a breakpoint
5221 placed (branch instruction's destination) anywhere in sequence. */
5223 && (breaks
[1] == breaks
[0]
5224 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5225 last_breakpoint
= 0;
5227 /* Effectively inserts the breakpoints. */
5228 for (index
= 0; index
<= last_breakpoint
; index
++)
5229 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5230 MAKE_THUMB_ADDR (breaks
[index
]));
5236 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5238 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5239 struct address_space
*aspace
= get_frame_address_space (frame
);
5240 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5241 CORE_ADDR pc
= get_frame_pc (frame
);
5242 CORE_ADDR breaks
[2] = {-1, -1};
5247 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5248 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5250 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5251 Note that we do not currently support conditionally executed atomic
5253 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5255 if ((insn
& 0xff9000f0) != 0xe1900090)
5258 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5260 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5262 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5265 /* Assume that there is at most one conditional branch in the atomic
5266 sequence. If a conditional branch is found, put a breakpoint in
5267 its destination address. */
5268 if (bits (insn
, 24, 27) == 0xa)
5270 if (last_breakpoint
> 0)
5271 return 0; /* More than one conditional branch found, fallback
5272 to the standard single-step code. */
5274 breaks
[1] = BranchDest (loc
- 4, insn
);
5278 /* We do not support atomic sequences that use any *other* instructions
5279 but conditional branches to change the PC. Fall back to standard
5280 code to avoid losing control of execution. */
5281 else if (arm_instruction_changes_pc (insn
))
5284 /* If we find a strex{,b,h,d}, we're done. */
5285 if ((insn
& 0xff9000f0) == 0xe1800090)
5289 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5290 if (insn_count
== atomic_sequence_length
)
5293 /* Insert a breakpoint right after the end of the atomic sequence. */
5296 /* Check for duplicated breakpoints. Check also for a breakpoint
5297 placed (branch instruction's destination) anywhere in sequence. */
5299 && (breaks
[1] == breaks
[0]
5300 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5301 last_breakpoint
= 0;
5303 /* Effectively inserts the breakpoints. */
5304 for (index
= 0; index
<= last_breakpoint
; index
++)
5305 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5311 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5313 if (arm_frame_is_thumb (frame
))
5314 return thumb_deal_with_atomic_sequence_raw (frame
);
5316 return arm_deal_with_atomic_sequence_raw (frame
);
5319 /* single_step() is called just before we want to resume the inferior,
5320 if we want to single-step it but there is no hardware or kernel
5321 single-step support. We find the target of the coming instruction
5322 and breakpoint it. */
5325 arm_software_single_step (struct frame_info
*frame
)
5327 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5328 struct address_space
*aspace
= get_frame_address_space (frame
);
5331 if (arm_deal_with_atomic_sequence (frame
))
5334 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5335 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5340 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5341 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5342 NULL if an error occurs. BUF is freed. */
5345 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5346 int old_len
, int new_len
)
5349 int bytes_to_read
= new_len
- old_len
;
5351 new_buf
= xmalloc (new_len
);
5352 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5354 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5362 /* An IT block is at most the 2-byte IT instruction followed by
5363 four 4-byte instructions. The furthest back we must search to
5364 find an IT block that affects the current instruction is thus
5365 2 + 3 * 4 == 14 bytes. */
5366 #define MAX_IT_BLOCK_PREFIX 14
5368 /* Use a quick scan if there are more than this many bytes of
5370 #define IT_SCAN_THRESHOLD 32
5372 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5373 A breakpoint in an IT block may not be hit, depending on the
5376 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5380 CORE_ADDR boundary
, func_start
;
5382 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5383 int i
, any
, last_it
, last_it_count
;
5385 /* If we are using BKPT breakpoints, none of this is necessary. */
5386 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5389 /* ARM mode does not have this problem. */
5390 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5393 /* We are setting a breakpoint in Thumb code that could potentially
5394 contain an IT block. The first step is to find how much Thumb
5395 code there is; we do not need to read outside of known Thumb
5397 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5399 /* Thumb-2 code must have mapping symbols to have a chance. */
5402 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5404 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5405 && func_start
> boundary
)
5406 boundary
= func_start
;
5408 /* Search for a candidate IT instruction. We have to do some fancy
5409 footwork to distinguish a real IT instruction from the second
5410 half of a 32-bit instruction, but there is no need for that if
5411 there's no candidate. */
5412 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5414 /* No room for an IT instruction. */
5417 buf
= xmalloc (buf_len
);
5418 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5421 for (i
= 0; i
< buf_len
; i
+= 2)
5423 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5424 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5436 /* OK, the code bytes before this instruction contain at least one
5437 halfword which resembles an IT instruction. We know that it's
5438 Thumb code, but there are still two possibilities. Either the
5439 halfword really is an IT instruction, or it is the second half of
5440 a 32-bit Thumb instruction. The only way we can tell is to
5441 scan forwards from a known instruction boundary. */
5442 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5446 /* There's a lot of code before this instruction. Start with an
5447 optimistic search; it's easy to recognize halfwords that can
5448 not be the start of a 32-bit instruction, and use that to
5449 lock on to the instruction boundaries. */
5450 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5453 buf_len
= IT_SCAN_THRESHOLD
;
5456 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5458 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5459 if (thumb_insn_size (inst1
) == 2)
5466 /* At this point, if DEFINITE, BUF[I] is the first place we
5467 are sure that we know the instruction boundaries, and it is far
5468 enough from BPADDR that we could not miss an IT instruction
5469 affecting BPADDR. If ! DEFINITE, give up - start from a
5473 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5477 buf_len
= bpaddr
- boundary
;
5483 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5486 buf_len
= bpaddr
- boundary
;
5490 /* Scan forwards. Find the last IT instruction before BPADDR. */
5495 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5497 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5502 else if (inst1
& 0x0002)
5504 else if (inst1
& 0x0004)
5509 i
+= thumb_insn_size (inst1
);
5515 /* There wasn't really an IT instruction after all. */
5518 if (last_it_count
< 1)
5519 /* It was too far away. */
5522 /* This really is a trouble spot. Move the breakpoint to the IT
5524 return bpaddr
- buf_len
+ last_it
;
5527 /* ARM displaced stepping support.
5529 Generally ARM displaced stepping works as follows:
5531 1. When an instruction is to be single-stepped, it is first decoded by
5532 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5533 Depending on the type of instruction, it is then copied to a scratch
5534 location, possibly in a modified form. The copy_* set of functions
5535 performs such modification, as necessary. A breakpoint is placed after
5536 the modified instruction in the scratch space to return control to GDB.
5537 Note in particular that instructions which modify the PC will no longer
5538 do so after modification.
5540 2. The instruction is single-stepped, by setting the PC to the scratch
5541 location address, and resuming. Control returns to GDB when the
5544 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5545 function used for the current instruction. This function's job is to
5546 put the CPU/memory state back to what it would have been if the
5547 instruction had been executed unmodified in its original location. */
5549 /* NOP instruction (mov r0, r0). */
5550 #define ARM_NOP 0xe1a00000
5551 #define THUMB_NOP 0x4600
5553 /* Helper for register reads for displaced stepping. In particular, this
5554 returns the PC as it would be seen by the instruction at its original
5558 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5562 CORE_ADDR from
= dsc
->insn_addr
;
5564 if (regno
== ARM_PC_REGNUM
)
5566 /* Compute pipeline offset:
5567 - When executing an ARM instruction, PC reads as the address of the
5568 current instruction plus 8.
5569 - When executing a Thumb instruction, PC reads as the address of the
5570 current instruction plus 4. */
5577 if (debug_displaced
)
5578 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5579 (unsigned long) from
);
5580 return (ULONGEST
) from
;
5584 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5585 if (debug_displaced
)
5586 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5587 regno
, (unsigned long) ret
);
5593 displaced_in_arm_mode (struct regcache
*regs
)
5596 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5598 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5600 return (ps
& t_bit
) == 0;
5603 /* Write to the PC as from a branch instruction. */
5606 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5610 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5611 architecture versions < 6. */
5612 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5613 val
& ~(ULONGEST
) 0x3);
5615 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5616 val
& ~(ULONGEST
) 0x1);
5619 /* Write to the PC as from a branch-exchange instruction. */
5622 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5625 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5627 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5631 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5632 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5634 else if ((val
& 2) == 0)
5636 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5637 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5641 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5642 mode, align dest to 4 bytes). */
5643 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5644 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5645 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5649 /* Write to the PC as if from a load instruction. */
5652 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5655 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5656 bx_write_pc (regs
, val
);
5658 branch_write_pc (regs
, dsc
, val
);
5661 /* Write to the PC as if from an ALU instruction. */
5664 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5667 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5668 bx_write_pc (regs
, val
);
5670 branch_write_pc (regs
, dsc
, val
);
5673 /* Helper for writing to registers for displaced stepping. Writing to the PC
5674 has a varying effects depending on the instruction which does the write:
5675 this is controlled by the WRITE_PC argument. */
5678 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5679 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5681 if (regno
== ARM_PC_REGNUM
)
5683 if (debug_displaced
)
5684 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5685 (unsigned long) val
);
5688 case BRANCH_WRITE_PC
:
5689 branch_write_pc (regs
, dsc
, val
);
5693 bx_write_pc (regs
, val
);
5697 load_write_pc (regs
, dsc
, val
);
5701 alu_write_pc (regs
, dsc
, val
);
5704 case CANNOT_WRITE_PC
:
5705 warning (_("Instruction wrote to PC in an unexpected way when "
5706 "single-stepping"));
5710 internal_error (__FILE__
, __LINE__
,
5711 _("Invalid argument to displaced_write_reg"));
5714 dsc
->wrote_to_pc
= 1;
5718 if (debug_displaced
)
5719 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5720 regno
, (unsigned long) val
);
5721 regcache_cooked_write_unsigned (regs
, regno
, val
);
5725 /* This function is used to concisely determine if an instruction INSN
5726 references PC. Register fields of interest in INSN should have the
5727 corresponding fields of BITMASK set to 0b1111. The function
5728 returns return 1 if any of these fields in INSN reference the PC
5729 (also 0b1111, r15), else it returns 0. */
5732 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5734 uint32_t lowbit
= 1;
5736 while (bitmask
!= 0)
5740 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5746 mask
= lowbit
* 0xf;
5748 if ((insn
& mask
) == mask
)
5757 /* The simplest copy function. Many instructions have the same effect no
5758 matter what address they are executed at: in those cases, use this. */
5761 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5762 const char *iname
, struct displaced_step_closure
*dsc
)
5764 if (debug_displaced
)
5765 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5766 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5769 dsc
->modinsn
[0] = insn
;
5775 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5776 uint16_t insn2
, const char *iname
,
5777 struct displaced_step_closure
*dsc
)
5779 if (debug_displaced
)
5780 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5781 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5784 dsc
->modinsn
[0] = insn1
;
5785 dsc
->modinsn
[1] = insn2
;
5791 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5794 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5796 struct displaced_step_closure
*dsc
)
5798 if (debug_displaced
)
5799 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5800 "opcode/class '%s' unmodified\n", insn
,
5803 dsc
->modinsn
[0] = insn
;
5808 /* Preload instructions with immediate offset. */
5811 cleanup_preload (struct gdbarch
*gdbarch
,
5812 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5814 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5815 if (!dsc
->u
.preload
.immed
)
5816 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5820 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5821 struct displaced_step_closure
*dsc
, unsigned int rn
)
5824 /* Preload instructions:
5826 {pli/pld} [rn, #+/-imm]
5828 {pli/pld} [r0, #+/-imm]. */
5830 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5831 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5832 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5833 dsc
->u
.preload
.immed
= 1;
5835 dsc
->cleanup
= &cleanup_preload
;
5839 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5840 struct displaced_step_closure
*dsc
)
5842 unsigned int rn
= bits (insn
, 16, 19);
5844 if (!insn_references_pc (insn
, 0x000f0000ul
))
5845 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5847 if (debug_displaced
)
5848 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5849 (unsigned long) insn
);
5851 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5853 install_preload (gdbarch
, regs
, dsc
, rn
);
5859 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5860 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5862 unsigned int rn
= bits (insn1
, 0, 3);
5863 unsigned int u_bit
= bit (insn1
, 7);
5864 int imm12
= bits (insn2
, 0, 11);
5867 if (rn
!= ARM_PC_REGNUM
)
5868 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5870 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5871 PLD (literal) Encoding T1. */
5872 if (debug_displaced
)
5873 fprintf_unfiltered (gdb_stdlog
,
5874 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5875 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5881 /* Rewrite instruction {pli/pld} PC imm12 into:
5882 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5886 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5888 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5889 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5891 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5893 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5894 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5895 dsc
->u
.preload
.immed
= 0;
5897 /* {pli/pld} [r0, r1] */
5898 dsc
->modinsn
[0] = insn1
& 0xfff0;
5899 dsc
->modinsn
[1] = 0xf001;
5902 dsc
->cleanup
= &cleanup_preload
;
5906 /* Preload instructions with register offset. */
5909 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5910 struct displaced_step_closure
*dsc
, unsigned int rn
,
5913 ULONGEST rn_val
, rm_val
;
5915 /* Preload register-offset instructions:
5917 {pli/pld} [rn, rm {, shift}]
5919 {pli/pld} [r0, r1 {, shift}]. */
5921 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5922 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5923 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5924 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5925 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5926 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5927 dsc
->u
.preload
.immed
= 0;
5929 dsc
->cleanup
= &cleanup_preload
;
5933 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5934 struct regcache
*regs
,
5935 struct displaced_step_closure
*dsc
)
5937 unsigned int rn
= bits (insn
, 16, 19);
5938 unsigned int rm
= bits (insn
, 0, 3);
5941 if (!insn_references_pc (insn
, 0x000f000ful
))
5942 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5944 if (debug_displaced
)
5945 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5946 (unsigned long) insn
);
5948 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5950 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5954 /* Copy/cleanup coprocessor load and store instructions. */
5957 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5958 struct regcache
*regs
,
5959 struct displaced_step_closure
*dsc
)
5961 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5963 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5965 if (dsc
->u
.ldst
.writeback
)
5966 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5970 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5971 struct displaced_step_closure
*dsc
,
5972 int writeback
, unsigned int rn
)
5976 /* Coprocessor load/store instructions:
5978 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5980 {stc/stc2} [r0, #+/-imm].
5982 ldc/ldc2 are handled identically. */
5984 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5985 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5986 /* PC should be 4-byte aligned. */
5987 rn_val
= rn_val
& 0xfffffffc;
5988 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5990 dsc
->u
.ldst
.writeback
= writeback
;
5991 dsc
->u
.ldst
.rn
= rn
;
5993 dsc
->cleanup
= &cleanup_copro_load_store
;
5997 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5998 struct regcache
*regs
,
5999 struct displaced_step_closure
*dsc
)
6001 unsigned int rn
= bits (insn
, 16, 19);
6003 if (!insn_references_pc (insn
, 0x000f0000ul
))
6004 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
6006 if (debug_displaced
)
6007 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
6008 "load/store insn %.8lx\n", (unsigned long) insn
);
6010 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
6012 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
6018 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
6019 uint16_t insn2
, struct regcache
*regs
,
6020 struct displaced_step_closure
*dsc
)
6022 unsigned int rn
= bits (insn1
, 0, 3);
6024 if (rn
!= ARM_PC_REGNUM
)
6025 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6026 "copro load/store", dsc
);
6028 if (debug_displaced
)
6029 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
6030 "load/store insn %.4x%.4x\n", insn1
, insn2
);
6032 dsc
->modinsn
[0] = insn1
& 0xfff0;
6033 dsc
->modinsn
[1] = insn2
;
6036 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6037 doesn't support writeback, so pass 0. */
6038 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
6043 /* Clean up branch instructions (actually perform the branch, by setting
6047 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6048 struct displaced_step_closure
*dsc
)
6050 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6051 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
6052 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
6053 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
6058 if (dsc
->u
.branch
.link
)
6060 /* The value of LR should be the next insn of current one. In order
6061 not to confuse logic hanlding later insn `bx lr', if current insn mode
6062 is Thumb, the bit 0 of LR value should be set to 1. */
6063 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6066 next_insn_addr
|= 0x1;
6068 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
6072 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
6075 /* Copy B/BL/BLX instructions with immediate destinations. */
6078 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6079 struct displaced_step_closure
*dsc
,
6080 unsigned int cond
, int exchange
, int link
, long offset
)
6082 /* Implement "BL<cond> <label>" as:
6084 Preparation: cond <- instruction condition
6085 Insn: mov r0, r0 (nop)
6086 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6088 B<cond> similar, but don't set r14 in cleanup. */
6090 dsc
->u
.branch
.cond
= cond
;
6091 dsc
->u
.branch
.link
= link
;
6092 dsc
->u
.branch
.exchange
= exchange
;
6094 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
6095 if (link
&& exchange
)
6096 /* For BLX, offset is computed from the Align (PC, 4). */
6097 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
6100 dsc
->u
.branch
.dest
+= 4 + offset
;
6102 dsc
->u
.branch
.dest
+= 8 + offset
;
6104 dsc
->cleanup
= &cleanup_branch
;
6107 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
6108 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6110 unsigned int cond
= bits (insn
, 28, 31);
6111 int exchange
= (cond
== 0xf);
6112 int link
= exchange
|| bit (insn
, 24);
6115 if (debug_displaced
)
6116 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
6117 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
6118 (unsigned long) insn
);
6120 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6121 then arrange the switch into Thumb mode. */
6122 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
6124 offset
= bits (insn
, 0, 23) << 2;
6126 if (bit (offset
, 25))
6127 offset
= offset
| ~0x3ffffff;
6129 dsc
->modinsn
[0] = ARM_NOP
;
6131 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6136 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
6137 uint16_t insn2
, struct regcache
*regs
,
6138 struct displaced_step_closure
*dsc
)
6140 int link
= bit (insn2
, 14);
6141 int exchange
= link
&& !bit (insn2
, 12);
6144 int j1
= bit (insn2
, 13);
6145 int j2
= bit (insn2
, 11);
6146 int s
= sbits (insn1
, 10, 10);
6147 int i1
= !(j1
^ bit (insn1
, 10));
6148 int i2
= !(j2
^ bit (insn1
, 10));
6150 if (!link
&& !exchange
) /* B */
6152 offset
= (bits (insn2
, 0, 10) << 1);
6153 if (bit (insn2
, 12)) /* Encoding T4 */
6155 offset
|= (bits (insn1
, 0, 9) << 12)
6161 else /* Encoding T3 */
6163 offset
|= (bits (insn1
, 0, 5) << 12)
6167 cond
= bits (insn1
, 6, 9);
6172 offset
= (bits (insn1
, 0, 9) << 12);
6173 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
6174 offset
|= exchange
?
6175 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
6178 if (debug_displaced
)
6179 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
6180 "%.4x %.4x with offset %.8lx\n",
6181 link
? (exchange
) ? "blx" : "bl" : "b",
6182 insn1
, insn2
, offset
);
6184 dsc
->modinsn
[0] = THUMB_NOP
;
6186 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6190 /* Copy B Thumb instructions. */
6192 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
6193 struct displaced_step_closure
*dsc
)
6195 unsigned int cond
= 0;
6197 unsigned short bit_12_15
= bits (insn
, 12, 15);
6198 CORE_ADDR from
= dsc
->insn_addr
;
6200 if (bit_12_15
== 0xd)
6202 /* offset = SignExtend (imm8:0, 32) */
6203 offset
= sbits ((insn
<< 1), 0, 8);
6204 cond
= bits (insn
, 8, 11);
6206 else if (bit_12_15
== 0xe) /* Encoding T2 */
6208 offset
= sbits ((insn
<< 1), 0, 11);
6212 if (debug_displaced
)
6213 fprintf_unfiltered (gdb_stdlog
,
6214 "displaced: copying b immediate insn %.4x "
6215 "with offset %d\n", insn
, offset
);
6217 dsc
->u
.branch
.cond
= cond
;
6218 dsc
->u
.branch
.link
= 0;
6219 dsc
->u
.branch
.exchange
= 0;
6220 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6222 dsc
->modinsn
[0] = THUMB_NOP
;
6224 dsc
->cleanup
= &cleanup_branch
;
6229 /* Copy BX/BLX with register-specified destinations. */
6232 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6233 struct displaced_step_closure
*dsc
, int link
,
6234 unsigned int cond
, unsigned int rm
)
6236 /* Implement {BX,BLX}<cond> <reg>" as:
6238 Preparation: cond <- instruction condition
6239 Insn: mov r0, r0 (nop)
6240 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6242 Don't set r14 in cleanup for BX. */
6244 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6246 dsc
->u
.branch
.cond
= cond
;
6247 dsc
->u
.branch
.link
= link
;
6249 dsc
->u
.branch
.exchange
= 1;
6251 dsc
->cleanup
= &cleanup_branch
;
6255 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6256 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6258 unsigned int cond
= bits (insn
, 28, 31);
6261 int link
= bit (insn
, 5);
6262 unsigned int rm
= bits (insn
, 0, 3);
6264 if (debug_displaced
)
6265 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6266 (unsigned long) insn
);
6268 dsc
->modinsn
[0] = ARM_NOP
;
6270 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6275 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6276 struct regcache
*regs
,
6277 struct displaced_step_closure
*dsc
)
6279 int link
= bit (insn
, 7);
6280 unsigned int rm
= bits (insn
, 3, 6);
6282 if (debug_displaced
)
6283 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6284 (unsigned short) insn
);
6286 dsc
->modinsn
[0] = THUMB_NOP
;
6288 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6294 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6297 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6298 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6300 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6301 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6302 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6303 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6307 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6308 struct displaced_step_closure
*dsc
)
6310 unsigned int rn
= bits (insn
, 16, 19);
6311 unsigned int rd
= bits (insn
, 12, 15);
6312 unsigned int op
= bits (insn
, 21, 24);
6313 int is_mov
= (op
== 0xd);
6314 ULONGEST rd_val
, rn_val
;
6316 if (!insn_references_pc (insn
, 0x000ff000ul
))
6317 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6319 if (debug_displaced
)
6320 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6321 "%.8lx\n", is_mov
? "move" : "ALU",
6322 (unsigned long) insn
);
6324 /* Instruction is of form:
6326 <op><cond> rd, [rn,] #imm
6330 Preparation: tmp1, tmp2 <- r0, r1;
6332 Insn: <op><cond> r0, r1, #imm
6333 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6336 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6337 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6338 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6339 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6340 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6341 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6345 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6347 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6349 dsc
->cleanup
= &cleanup_alu_imm
;
6355 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6356 uint16_t insn2
, struct regcache
*regs
,
6357 struct displaced_step_closure
*dsc
)
6359 unsigned int op
= bits (insn1
, 5, 8);
6360 unsigned int rn
, rm
, rd
;
6361 ULONGEST rd_val
, rn_val
;
6363 rn
= bits (insn1
, 0, 3); /* Rn */
6364 rm
= bits (insn2
, 0, 3); /* Rm */
6365 rd
= bits (insn2
, 8, 11); /* Rd */
6367 /* This routine is only called for instruction MOV. */
6368 gdb_assert (op
== 0x2 && rn
== 0xf);
6370 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6371 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6373 if (debug_displaced
)
6374 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6375 "ALU", insn1
, insn2
);
6377 /* Instruction is of form:
6379 <op><cond> rd, [rn,] #imm
6383 Preparation: tmp1, tmp2 <- r0, r1;
6385 Insn: <op><cond> r0, r1, #imm
6386 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6389 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6390 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6391 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6392 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6393 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6394 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6397 dsc
->modinsn
[0] = insn1
;
6398 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6401 dsc
->cleanup
= &cleanup_alu_imm
;
6406 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6409 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6410 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6415 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6417 for (i
= 0; i
< 3; i
++)
6418 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6420 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6424 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6425 struct displaced_step_closure
*dsc
,
6426 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6428 ULONGEST rd_val
, rn_val
, rm_val
;
6430 /* Instruction is of form:
6432 <op><cond> rd, [rn,] rm [, <shift>]
6436 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6437 r0, r1, r2 <- rd, rn, rm
6438 Insn: <op><cond> r0, r1, r2 [, <shift>]
6439 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6442 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6443 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6444 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6445 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6446 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6447 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6448 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6449 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6450 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6453 dsc
->cleanup
= &cleanup_alu_reg
;
6457 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6458 struct displaced_step_closure
*dsc
)
6460 unsigned int op
= bits (insn
, 21, 24);
6461 int is_mov
= (op
== 0xd);
6463 if (!insn_references_pc (insn
, 0x000ff00ful
))
6464 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6466 if (debug_displaced
)
6467 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6468 is_mov
? "move" : "ALU", (unsigned long) insn
);
6471 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6473 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6475 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6481 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6482 struct regcache
*regs
,
6483 struct displaced_step_closure
*dsc
)
6485 unsigned rn
, rm
, rd
;
6487 rd
= bits (insn
, 3, 6);
6488 rn
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6491 if (rd
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6492 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6494 if (debug_displaced
)
6495 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x\n",
6496 "ALU", (unsigned short) insn
);
6498 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x08);
6500 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
);
6505 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6508 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6509 struct regcache
*regs
,
6510 struct displaced_step_closure
*dsc
)
6512 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6515 for (i
= 0; i
< 4; i
++)
6516 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6518 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6522 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6523 struct displaced_step_closure
*dsc
,
6524 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6528 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6530 /* Instruction is of form:
6532 <op><cond> rd, [rn,] rm, <shift> rs
6536 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6537 r0, r1, r2, r3 <- rd, rn, rm, rs
6538 Insn: <op><cond> r0, r1, r2, <shift> r3
6540 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6544 for (i
= 0; i
< 4; i
++)
6545 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6547 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6548 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6549 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6550 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6551 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6552 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6553 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6554 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6556 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6560 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6561 struct regcache
*regs
,
6562 struct displaced_step_closure
*dsc
)
6564 unsigned int op
= bits (insn
, 21, 24);
6565 int is_mov
= (op
== 0xd);
6566 unsigned int rd
, rn
, rm
, rs
;
6568 if (!insn_references_pc (insn
, 0x000fff0ful
))
6569 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6571 if (debug_displaced
)
6572 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6573 "%.8lx\n", is_mov
? "move" : "ALU",
6574 (unsigned long) insn
);
6576 rn
= bits (insn
, 16, 19);
6577 rm
= bits (insn
, 0, 3);
6578 rs
= bits (insn
, 8, 11);
6579 rd
= bits (insn
, 12, 15);
6582 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6584 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6586 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6591 /* Clean up load instructions. */
6594 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6595 struct displaced_step_closure
*dsc
)
6597 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6599 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6600 if (dsc
->u
.ldst
.xfersize
== 8)
6601 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6602 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6604 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6605 if (dsc
->u
.ldst
.xfersize
> 4)
6606 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6607 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6608 if (!dsc
->u
.ldst
.immed
)
6609 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6611 /* Handle register writeback. */
6612 if (dsc
->u
.ldst
.writeback
)
6613 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6614 /* Put result in right place. */
6615 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6616 if (dsc
->u
.ldst
.xfersize
== 8)
6617 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6620 /* Clean up store instructions. */
6623 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6624 struct displaced_step_closure
*dsc
)
6626 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6628 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6629 if (dsc
->u
.ldst
.xfersize
> 4)
6630 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6631 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6632 if (!dsc
->u
.ldst
.immed
)
6633 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6634 if (!dsc
->u
.ldst
.restore_r4
)
6635 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6638 if (dsc
->u
.ldst
.writeback
)
6639 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6642 /* Copy "extra" load/store instructions. These are halfword/doubleword
6643 transfers, which have a different encoding to byte/word transfers. */
6646 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6647 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6649 unsigned int op1
= bits (insn
, 20, 24);
6650 unsigned int op2
= bits (insn
, 5, 6);
6651 unsigned int rt
= bits (insn
, 12, 15);
6652 unsigned int rn
= bits (insn
, 16, 19);
6653 unsigned int rm
= bits (insn
, 0, 3);
6654 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6655 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6656 int immed
= (op1
& 0x4) != 0;
6658 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6660 if (!insn_references_pc (insn
, 0x000ff00ful
))
6661 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6663 if (debug_displaced
)
6664 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6665 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6666 (unsigned long) insn
);
6668 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6671 internal_error (__FILE__
, __LINE__
,
6672 _("copy_extra_ld_st: instruction decode error"));
6674 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6675 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6676 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6678 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6680 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6681 if (bytesize
[opcode
] == 8)
6682 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6683 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6685 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6687 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6688 if (bytesize
[opcode
] == 8)
6689 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6690 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6692 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6695 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6696 dsc
->u
.ldst
.rn
= rn
;
6697 dsc
->u
.ldst
.immed
= immed
;
6698 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6699 dsc
->u
.ldst
.restore_r4
= 0;
6702 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6704 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6705 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6707 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6709 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6710 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6712 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6717 /* Copy byte/half word/word loads and stores. */
6720 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6721 struct displaced_step_closure
*dsc
, int load
,
6722 int immed
, int writeback
, int size
, int usermode
,
6723 int rt
, int rm
, int rn
)
6725 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6727 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6728 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6730 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6732 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6734 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6735 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6737 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6739 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6740 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6742 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6744 dsc
->u
.ldst
.xfersize
= size
;
6745 dsc
->u
.ldst
.rn
= rn
;
6746 dsc
->u
.ldst
.immed
= immed
;
6747 dsc
->u
.ldst
.writeback
= writeback
;
6749 /* To write PC we can do:
6751 Before this sequence of instructions:
6752 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6753 r2 is the Rn value got from dispalced_read_reg.
6755 Insn1: push {pc} Write address of STR instruction + offset on stack
6756 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6757 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6758 = addr(Insn1) + offset - addr(Insn3) - 8
6760 Insn4: add r4, r4, #8 r4 = offset - 8
6761 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6763 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6765 Otherwise we don't know what value to write for PC, since the offset is
6766 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6767 of this can be found in Section "Saving from r15" in
6768 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6770 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6775 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6776 uint16_t insn2
, struct regcache
*regs
,
6777 struct displaced_step_closure
*dsc
, int size
)
6779 unsigned int u_bit
= bit (insn1
, 7);
6780 unsigned int rt
= bits (insn2
, 12, 15);
6781 int imm12
= bits (insn2
, 0, 11);
6784 if (debug_displaced
)
6785 fprintf_unfiltered (gdb_stdlog
,
6786 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6787 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6793 /* Rewrite instruction LDR Rt imm12 into:
6795 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6799 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6802 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6803 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6804 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6806 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6808 pc_val
= pc_val
& 0xfffffffc;
6810 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6811 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6815 dsc
->u
.ldst
.xfersize
= size
;
6816 dsc
->u
.ldst
.immed
= 0;
6817 dsc
->u
.ldst
.writeback
= 0;
6818 dsc
->u
.ldst
.restore_r4
= 0;
6820 /* LDR R0, R2, R3 */
6821 dsc
->modinsn
[0] = 0xf852;
6822 dsc
->modinsn
[1] = 0x3;
6825 dsc
->cleanup
= &cleanup_load
;
6831 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6832 uint16_t insn2
, struct regcache
*regs
,
6833 struct displaced_step_closure
*dsc
,
6834 int writeback
, int immed
)
6836 unsigned int rt
= bits (insn2
, 12, 15);
6837 unsigned int rn
= bits (insn1
, 0, 3);
6838 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6839 /* In LDR (register), there is also a register Rm, which is not allowed to
6840 be PC, so we don't have to check it. */
6842 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6843 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6846 if (debug_displaced
)
6847 fprintf_unfiltered (gdb_stdlog
,
6848 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6849 rt
, rn
, insn1
, insn2
);
6851 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6854 dsc
->u
.ldst
.restore_r4
= 0;
6857 /* ldr[b]<cond> rt, [rn, #imm], etc.
6859 ldr[b]<cond> r0, [r2, #imm]. */
6861 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6862 dsc
->modinsn
[1] = insn2
& 0x0fff;
6865 /* ldr[b]<cond> rt, [rn, rm], etc.
6867 ldr[b]<cond> r0, [r2, r3]. */
6869 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6870 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6880 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6881 struct regcache
*regs
,
6882 struct displaced_step_closure
*dsc
,
6883 int load
, int size
, int usermode
)
6885 int immed
= !bit (insn
, 25);
6886 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6887 unsigned int rt
= bits (insn
, 12, 15);
6888 unsigned int rn
= bits (insn
, 16, 19);
6889 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6891 if (!insn_references_pc (insn
, 0x000ff00ful
))
6892 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6894 if (debug_displaced
)
6895 fprintf_unfiltered (gdb_stdlog
,
6896 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6897 load
? (size
== 1 ? "ldrb" : "ldr")
6898 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6900 (unsigned long) insn
);
6902 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6903 usermode
, rt
, rm
, rn
);
6905 if (load
|| rt
!= ARM_PC_REGNUM
)
6907 dsc
->u
.ldst
.restore_r4
= 0;
6910 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6912 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6913 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6915 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6917 {ldr,str}[b]<cond> r0, [r2, r3]. */
6918 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6922 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6923 dsc
->u
.ldst
.restore_r4
= 1;
6924 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6925 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6926 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6927 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6928 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6932 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6934 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6939 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6944 /* Cleanup LDM instructions with fully-populated register list. This is an
6945 unfortunate corner case: it's impossible to implement correctly by modifying
6946 the instruction. The issue is as follows: we have an instruction,
6950 which we must rewrite to avoid loading PC. A possible solution would be to
6951 do the load in two halves, something like (with suitable cleanup
6955 ldm[id][ab] r8!, {r0-r7}
6957 ldm[id][ab] r8, {r7-r14}
6960 but at present there's no suitable place for <temp>, since the scratch space
6961 is overwritten before the cleanup routine is called. For now, we simply
6962 emulate the instruction. */
6965 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6966 struct displaced_step_closure
*dsc
)
6968 int inc
= dsc
->u
.block
.increment
;
6969 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6970 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6971 uint32_t regmask
= dsc
->u
.block
.regmask
;
6972 int regno
= inc
? 0 : 15;
6973 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6974 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6975 && (regmask
& 0x8000) != 0;
6976 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6977 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6978 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6983 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6984 sensible we can do here. Complain loudly. */
6985 if (exception_return
)
6986 error (_("Cannot single-step exception return"));
6988 /* We don't handle any stores here for now. */
6989 gdb_assert (dsc
->u
.block
.load
!= 0);
6991 if (debug_displaced
)
6992 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6993 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6994 dsc
->u
.block
.increment
? "inc" : "dec",
6995 dsc
->u
.block
.before
? "before" : "after");
7002 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
7005 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
7008 xfer_addr
+= bump_before
;
7010 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
7011 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
7013 xfer_addr
+= bump_after
;
7015 regmask
&= ~(1 << regno
);
7018 if (dsc
->u
.block
.writeback
)
7019 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
7023 /* Clean up an STM which included the PC in the register list. */
7026 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7027 struct displaced_step_closure
*dsc
)
7029 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7030 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7031 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
7032 CORE_ADDR stm_insn_addr
;
7035 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7037 /* If condition code fails, there's nothing else to do. */
7038 if (!store_executed
)
7041 if (dsc
->u
.block
.increment
)
7043 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
7045 if (dsc
->u
.block
.before
)
7050 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
7052 if (dsc
->u
.block
.before
)
7056 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
7057 stm_insn_addr
= dsc
->scratch_base
;
7058 offset
= pc_val
- stm_insn_addr
;
7060 if (debug_displaced
)
7061 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
7062 "STM instruction\n", offset
);
7064 /* Rewrite the stored PC to the proper value for the non-displaced original
7066 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
7067 dsc
->insn_addr
+ offset
);
7070 /* Clean up an LDM which includes the PC in the register list. We clumped all
7071 the registers in the transferred list into a contiguous range r0...rX (to
7072 avoid loading PC directly and losing control of the debugged program), so we
7073 must undo that here. */
7076 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
7077 struct regcache
*regs
,
7078 struct displaced_step_closure
*dsc
)
7080 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7081 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7082 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
7083 unsigned int regs_loaded
= bitcount (mask
);
7084 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
7086 /* The method employed here will fail if the register list is fully populated
7087 (we need to avoid loading PC directly). */
7088 gdb_assert (num_to_shuffle
< 16);
7093 clobbered
= (1 << num_to_shuffle
) - 1;
7095 while (num_to_shuffle
> 0)
7097 if ((mask
& (1 << write_reg
)) != 0)
7099 unsigned int read_reg
= num_to_shuffle
- 1;
7101 if (read_reg
!= write_reg
)
7103 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
7104 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
7105 if (debug_displaced
)
7106 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
7107 "loaded register r%d to r%d\n"), read_reg
,
7110 else if (debug_displaced
)
7111 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
7112 "r%d already in the right place\n"),
7115 clobbered
&= ~(1 << write_reg
);
7123 /* Restore any registers we scribbled over. */
7124 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
7126 if ((clobbered
& (1 << write_reg
)) != 0)
7128 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
7130 if (debug_displaced
)
7131 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
7132 "clobbered register r%d\n"), write_reg
);
7133 clobbered
&= ~(1 << write_reg
);
7137 /* Perform register writeback manually. */
7138 if (dsc
->u
.block
.writeback
)
7140 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
7142 if (dsc
->u
.block
.increment
)
7143 new_rn_val
+= regs_loaded
* 4;
7145 new_rn_val
-= regs_loaded
* 4;
7147 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
7152 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7153 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7156 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
7157 struct regcache
*regs
,
7158 struct displaced_step_closure
*dsc
)
7160 int load
= bit (insn
, 20);
7161 int user
= bit (insn
, 22);
7162 int increment
= bit (insn
, 23);
7163 int before
= bit (insn
, 24);
7164 int writeback
= bit (insn
, 21);
7165 int rn
= bits (insn
, 16, 19);
7167 /* Block transfers which don't mention PC can be run directly
7169 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
7170 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
7172 if (rn
== ARM_PC_REGNUM
)
7174 warning (_("displaced: Unpredictable LDM or STM with "
7175 "base register r15"));
7176 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
7179 if (debug_displaced
)
7180 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7181 "%.8lx\n", (unsigned long) insn
);
7183 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7184 dsc
->u
.block
.rn
= rn
;
7186 dsc
->u
.block
.load
= load
;
7187 dsc
->u
.block
.user
= user
;
7188 dsc
->u
.block
.increment
= increment
;
7189 dsc
->u
.block
.before
= before
;
7190 dsc
->u
.block
.writeback
= writeback
;
7191 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
7193 dsc
->u
.block
.regmask
= insn
& 0xffff;
7197 if ((insn
& 0xffff) == 0xffff)
7199 /* LDM with a fully-populated register list. This case is
7200 particularly tricky. Implement for now by fully emulating the
7201 instruction (which might not behave perfectly in all cases, but
7202 these instructions should be rare enough for that not to matter
7204 dsc
->modinsn
[0] = ARM_NOP
;
7206 dsc
->cleanup
= &cleanup_block_load_all
;
7210 /* LDM of a list of registers which includes PC. Implement by
7211 rewriting the list of registers to be transferred into a
7212 contiguous chunk r0...rX before doing the transfer, then shuffling
7213 registers into the correct places in the cleanup routine. */
7214 unsigned int regmask
= insn
& 0xffff;
7215 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7216 unsigned int to
= 0, from
= 0, i
, new_rn
;
7218 for (i
= 0; i
< num_in_list
; i
++)
7219 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7221 /* Writeback makes things complicated. We need to avoid clobbering
7222 the base register with one of the registers in our modified
7223 register list, but just using a different register can't work in
7226 ldm r14!, {r0-r13,pc}
7228 which would need to be rewritten as:
7232 but that can't work, because there's no free register for N.
7234 Solve this by turning off the writeback bit, and emulating
7235 writeback manually in the cleanup routine. */
7240 new_regmask
= (1 << num_in_list
) - 1;
7242 if (debug_displaced
)
7243 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7244 "{..., pc}: original reg list %.4x, modified "
7245 "list %.4x\n"), rn
, writeback
? "!" : "",
7246 (int) insn
& 0xffff, new_regmask
);
7248 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7250 dsc
->cleanup
= &cleanup_block_load_pc
;
7255 /* STM of a list of registers which includes PC. Run the instruction
7256 as-is, but out of line: this will store the wrong value for the PC,
7257 so we must manually fix up the memory in the cleanup routine.
7258 Doing things this way has the advantage that we can auto-detect
7259 the offset of the PC write (which is architecture-dependent) in
7260 the cleanup routine. */
7261 dsc
->modinsn
[0] = insn
;
7263 dsc
->cleanup
= &cleanup_block_store_pc
;
7270 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7271 struct regcache
*regs
,
7272 struct displaced_step_closure
*dsc
)
7274 int rn
= bits (insn1
, 0, 3);
7275 int load
= bit (insn1
, 4);
7276 int writeback
= bit (insn1
, 5);
7278 /* Block transfers which don't mention PC can be run directly
7280 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7281 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7283 if (rn
== ARM_PC_REGNUM
)
7285 warning (_("displaced: Unpredictable LDM or STM with "
7286 "base register r15"));
7287 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7288 "unpredictable ldm/stm", dsc
);
7291 if (debug_displaced
)
7292 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7293 "%.4x%.4x\n", insn1
, insn2
);
7295 /* Clear bit 13, since it should be always zero. */
7296 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7297 dsc
->u
.block
.rn
= rn
;
7299 dsc
->u
.block
.load
= load
;
7300 dsc
->u
.block
.user
= 0;
7301 dsc
->u
.block
.increment
= bit (insn1
, 7);
7302 dsc
->u
.block
.before
= bit (insn1
, 8);
7303 dsc
->u
.block
.writeback
= writeback
;
7304 dsc
->u
.block
.cond
= INST_AL
;
7305 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7309 if (dsc
->u
.block
.regmask
== 0xffff)
7311 /* This branch is impossible to happen. */
7316 unsigned int regmask
= dsc
->u
.block
.regmask
;
7317 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7318 unsigned int to
= 0, from
= 0, i
, new_rn
;
7320 for (i
= 0; i
< num_in_list
; i
++)
7321 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7326 new_regmask
= (1 << num_in_list
) - 1;
7328 if (debug_displaced
)
7329 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7330 "{..., pc}: original reg list %.4x, modified "
7331 "list %.4x\n"), rn
, writeback
? "!" : "",
7332 (int) dsc
->u
.block
.regmask
, new_regmask
);
7334 dsc
->modinsn
[0] = insn1
;
7335 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7338 dsc
->cleanup
= &cleanup_block_load_pc
;
7343 dsc
->modinsn
[0] = insn1
;
7344 dsc
->modinsn
[1] = insn2
;
7346 dsc
->cleanup
= &cleanup_block_store_pc
;
7351 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7352 for Linux, where some SVC instructions must be treated specially. */
7355 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7356 struct displaced_step_closure
*dsc
)
7358 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7360 if (debug_displaced
)
7361 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7362 "%.8lx\n", (unsigned long) resume_addr
);
7364 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7368 /* Common copy routine for svc instruciton. */
7371 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7372 struct displaced_step_closure
*dsc
)
7374 /* Preparation: none.
7375 Insn: unmodified svc.
7376 Cleanup: pc <- insn_addr + insn_size. */
7378 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7380 dsc
->wrote_to_pc
= 1;
7382 /* Allow OS-specific code to override SVC handling. */
7383 if (dsc
->u
.svc
.copy_svc_os
)
7384 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7387 dsc
->cleanup
= &cleanup_svc
;
7393 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7394 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7397 if (debug_displaced
)
7398 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7399 (unsigned long) insn
);
7401 dsc
->modinsn
[0] = insn
;
7403 return install_svc (gdbarch
, regs
, dsc
);
7407 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7408 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7411 if (debug_displaced
)
7412 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7415 dsc
->modinsn
[0] = insn
;
7417 return install_svc (gdbarch
, regs
, dsc
);
7420 /* Copy undefined instructions. */
7423 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7424 struct displaced_step_closure
*dsc
)
7426 if (debug_displaced
)
7427 fprintf_unfiltered (gdb_stdlog
,
7428 "displaced: copying undefined insn %.8lx\n",
7429 (unsigned long) insn
);
7431 dsc
->modinsn
[0] = insn
;
7437 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7438 struct displaced_step_closure
*dsc
)
7441 if (debug_displaced
)
7442 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7443 "%.4x %.4x\n", (unsigned short) insn1
,
7444 (unsigned short) insn2
);
7446 dsc
->modinsn
[0] = insn1
;
7447 dsc
->modinsn
[1] = insn2
;
7453 /* Copy unpredictable instructions. */
7456 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7457 struct displaced_step_closure
*dsc
)
7459 if (debug_displaced
)
7460 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7461 "%.8lx\n", (unsigned long) insn
);
7463 dsc
->modinsn
[0] = insn
;
7468 /* The decode_* functions are instruction decoding helpers. They mostly follow
7469 the presentation in the ARM ARM. */
7472 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7473 struct regcache
*regs
,
7474 struct displaced_step_closure
*dsc
)
7476 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7477 unsigned int rn
= bits (insn
, 16, 19);
7479 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7480 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7481 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7482 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7483 else if ((op1
& 0x60) == 0x20)
7484 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7485 else if ((op1
& 0x71) == 0x40)
7486 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7488 else if ((op1
& 0x77) == 0x41)
7489 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7490 else if ((op1
& 0x77) == 0x45)
7491 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7492 else if ((op1
& 0x77) == 0x51)
7495 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7497 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7499 else if ((op1
& 0x77) == 0x55)
7500 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7501 else if (op1
== 0x57)
7504 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7505 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7506 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7507 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7508 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7510 else if ((op1
& 0x63) == 0x43)
7511 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7512 else if ((op2
& 0x1) == 0x0)
7513 switch (op1
& ~0x80)
7516 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7518 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7519 case 0x71: case 0x75:
7521 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7522 case 0x63: case 0x67: case 0x73: case 0x77:
7523 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7525 return arm_copy_undef (gdbarch
, insn
, dsc
);
7528 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7532 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7533 struct regcache
*regs
,
7534 struct displaced_step_closure
*dsc
)
7536 if (bit (insn
, 27) == 0)
7537 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7538 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7539 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7542 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7545 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7547 case 0x4: case 0x5: case 0x6: case 0x7:
7548 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7551 switch ((insn
& 0xe00000) >> 21)
7553 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7555 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7558 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7561 return arm_copy_undef (gdbarch
, insn
, dsc
);
7566 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7567 switch ((insn
& 0xe00000) >> 21)
7570 /* ldc/ldc2 imm (undefined for rn == pc). */
7571 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7572 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7575 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7577 case 0x4: case 0x5: case 0x6: case 0x7:
7578 /* ldc/ldc2 lit (undefined for rn != pc). */
7579 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7580 : arm_copy_undef (gdbarch
, insn
, dsc
);
7583 return arm_copy_undef (gdbarch
, insn
, dsc
);
7588 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7591 if (bits (insn
, 16, 19) == 0xf)
7593 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7595 return arm_copy_undef (gdbarch
, insn
, dsc
);
7599 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7601 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7605 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7607 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7610 return arm_copy_undef (gdbarch
, insn
, dsc
);
7614 /* Decode miscellaneous instructions in dp/misc encoding space. */
7617 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7618 struct regcache
*regs
,
7619 struct displaced_step_closure
*dsc
)
7621 unsigned int op2
= bits (insn
, 4, 6);
7622 unsigned int op
= bits (insn
, 21, 22);
7623 unsigned int op1
= bits (insn
, 16, 19);
7628 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7631 if (op
== 0x1) /* bx. */
7632 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7634 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7636 return arm_copy_undef (gdbarch
, insn
, dsc
);
7640 /* Not really supported. */
7641 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7643 return arm_copy_undef (gdbarch
, insn
, dsc
);
7647 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7648 regs
, dsc
); /* blx register. */
7650 return arm_copy_undef (gdbarch
, insn
, dsc
);
7653 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7657 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7659 /* Not really supported. */
7660 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7663 return arm_copy_undef (gdbarch
, insn
, dsc
);
7668 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7669 struct regcache
*regs
,
7670 struct displaced_step_closure
*dsc
)
7673 switch (bits (insn
, 20, 24))
7676 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7679 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7681 case 0x12: case 0x16:
7682 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7685 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7689 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7691 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7692 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7693 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7694 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7695 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7696 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7697 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7698 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7699 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7700 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7701 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7702 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7703 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7704 /* 2nd arg means "unpriveleged". */
7705 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7709 /* Should be unreachable. */
7714 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7715 struct regcache
*regs
,
7716 struct displaced_step_closure
*dsc
)
7718 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7719 uint32_t op1
= bits (insn
, 20, 24);
7720 int rn_f
= bits (insn
, 16, 19) == 0xf;
7722 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7723 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7724 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7725 else if ((!a
&& (op1
& 0x17) == 0x02)
7726 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7727 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7728 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7729 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7730 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7731 else if ((!a
&& (op1
& 0x17) == 0x03)
7732 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7733 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7734 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7735 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7736 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7737 else if ((!a
&& (op1
& 0x17) == 0x06)
7738 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7739 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7740 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7741 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7742 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7743 else if ((!a
&& (op1
& 0x17) == 0x07)
7744 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7745 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7747 /* Should be unreachable. */
7752 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7753 struct displaced_step_closure
*dsc
)
7755 switch (bits (insn
, 20, 24))
7757 case 0x00: case 0x01: case 0x02: case 0x03:
7758 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7760 case 0x04: case 0x05: case 0x06: case 0x07:
7761 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7763 case 0x08: case 0x09: case 0x0a: case 0x0b:
7764 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7765 return arm_copy_unmodified (gdbarch
, insn
,
7766 "decode/pack/unpack/saturate/reverse", dsc
);
7769 if (bits (insn
, 5, 7) == 0) /* op2. */
7771 if (bits (insn
, 12, 15) == 0xf)
7772 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7774 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7777 return arm_copy_undef (gdbarch
, insn
, dsc
);
7779 case 0x1a: case 0x1b:
7780 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7781 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7783 return arm_copy_undef (gdbarch
, insn
, dsc
);
7785 case 0x1c: case 0x1d:
7786 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7788 if (bits (insn
, 0, 3) == 0xf)
7789 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7791 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7794 return arm_copy_undef (gdbarch
, insn
, dsc
);
7796 case 0x1e: case 0x1f:
7797 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7798 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7800 return arm_copy_undef (gdbarch
, insn
, dsc
);
7803 /* Should be unreachable. */
7808 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7809 struct regcache
*regs
,
7810 struct displaced_step_closure
*dsc
)
7813 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7815 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7819 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7820 struct regcache
*regs
,
7821 struct displaced_step_closure
*dsc
)
7823 unsigned int opcode
= bits (insn
, 20, 24);
7827 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7828 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7830 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7831 case 0x12: case 0x16:
7832 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7834 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7835 case 0x13: case 0x17:
7836 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7838 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7839 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7840 /* Note: no writeback for these instructions. Bit 25 will always be
7841 zero though (via caller), so the following works OK. */
7842 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7845 /* Should be unreachable. */
7849 /* Decode shifted register instructions. */
7852 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7853 uint16_t insn2
, struct regcache
*regs
,
7854 struct displaced_step_closure
*dsc
)
7856 /* PC is only allowed to be used in instruction MOV. */
7858 unsigned int op
= bits (insn1
, 5, 8);
7859 unsigned int rn
= bits (insn1
, 0, 3);
7861 if (op
== 0x2 && rn
== 0xf) /* MOV */
7862 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7864 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7865 "dp (shift reg)", dsc
);
7869 /* Decode extension register load/store. Exactly the same as
7870 arm_decode_ext_reg_ld_st. */
7873 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7874 uint16_t insn2
, struct regcache
*regs
,
7875 struct displaced_step_closure
*dsc
)
7877 unsigned int opcode
= bits (insn1
, 4, 8);
7881 case 0x04: case 0x05:
7882 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7883 "vfp/neon vmov", dsc
);
7885 case 0x08: case 0x0c: /* 01x00 */
7886 case 0x0a: case 0x0e: /* 01x10 */
7887 case 0x12: case 0x16: /* 10x10 */
7888 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7889 "vfp/neon vstm/vpush", dsc
);
7891 case 0x09: case 0x0d: /* 01x01 */
7892 case 0x0b: case 0x0f: /* 01x11 */
7893 case 0x13: case 0x17: /* 10x11 */
7894 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7895 "vfp/neon vldm/vpop", dsc
);
7897 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7898 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7900 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7901 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7904 /* Should be unreachable. */
7909 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7910 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7912 unsigned int op1
= bits (insn
, 20, 25);
7913 int op
= bit (insn
, 4);
7914 unsigned int coproc
= bits (insn
, 8, 11);
7915 unsigned int rn
= bits (insn
, 16, 19);
7917 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7918 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7919 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7920 && (coproc
& 0xe) != 0xa)
7922 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7923 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7924 && (coproc
& 0xe) != 0xa)
7925 /* ldc/ldc2 imm/lit. */
7926 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7927 else if ((op1
& 0x3e) == 0x00)
7928 return arm_copy_undef (gdbarch
, insn
, dsc
);
7929 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7930 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7931 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7932 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7933 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7934 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7935 else if ((op1
& 0x30) == 0x20 && !op
)
7937 if ((coproc
& 0xe) == 0xa)
7938 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7940 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7942 else if ((op1
& 0x30) == 0x20 && op
)
7943 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7944 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7945 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7946 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7947 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7948 else if ((op1
& 0x30) == 0x30)
7949 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7951 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7955 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7956 uint16_t insn2
, struct regcache
*regs
,
7957 struct displaced_step_closure
*dsc
)
7959 unsigned int coproc
= bits (insn2
, 8, 11);
7960 unsigned int op1
= bits (insn1
, 4, 9);
7961 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7962 unsigned int bit_9
= bit (insn1
, 9);
7963 unsigned int bit_4
= bit (insn1
, 4);
7964 unsigned int rn
= bits (insn1
, 0, 3);
7969 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7970 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7972 else if (bit_5_8
== 0) /* UNDEFINED. */
7973 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7976 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7977 if ((coproc
& 0xe) == 0xa)
7978 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7980 else /* coproc is not 101x. */
7982 if (bit_4
== 0) /* STC/STC2. */
7983 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7985 else /* LDC/LDC2 {literal, immeidate}. */
7986 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7992 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7998 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7999 struct displaced_step_closure
*dsc
, int rd
)
8005 Preparation: Rd <- PC
8011 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8012 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
8016 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8017 struct displaced_step_closure
*dsc
,
8018 int rd
, unsigned int imm
)
8021 /* Encoding T2: ADDS Rd, #imm */
8022 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
8024 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8030 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
8031 struct regcache
*regs
,
8032 struct displaced_step_closure
*dsc
)
8034 unsigned int rd
= bits (insn
, 8, 10);
8035 unsigned int imm8
= bits (insn
, 0, 7);
8037 if (debug_displaced
)
8038 fprintf_unfiltered (gdb_stdlog
,
8039 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8042 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
8046 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
8047 uint16_t insn2
, struct regcache
*regs
,
8048 struct displaced_step_closure
*dsc
)
8050 unsigned int rd
= bits (insn2
, 8, 11);
8051 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8052 extract raw immediate encoding rather than computing immediate. When
8053 generating ADD or SUB instruction, we can simply perform OR operation to
8054 set immediate into ADD. */
8055 unsigned int imm_3_8
= insn2
& 0x70ff;
8056 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
8058 if (debug_displaced
)
8059 fprintf_unfiltered (gdb_stdlog
,
8060 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8061 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
8063 if (bit (insn1
, 7)) /* Encoding T2 */
8065 /* Encoding T3: SUB Rd, Rd, #imm */
8066 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
8067 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8069 else /* Encoding T3 */
8071 /* Encoding T3: ADD Rd, Rd, #imm */
8072 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
8073 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8077 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8083 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
8084 struct regcache
*regs
,
8085 struct displaced_step_closure
*dsc
)
8087 unsigned int rt
= bits (insn1
, 8, 10);
8089 int imm8
= (bits (insn1
, 0, 7) << 2);
8090 CORE_ADDR from
= dsc
->insn_addr
;
8096 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8098 Insn: LDR R0, [R2, R3];
8099 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8101 if (debug_displaced
)
8102 fprintf_unfiltered (gdb_stdlog
,
8103 "displaced: copying thumb ldr r%d [pc #%d]\n"
8106 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
8107 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
8108 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
8109 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8110 /* The assembler calculates the required value of the offset from the
8111 Align(PC,4) value of this instruction to the label. */
8112 pc
= pc
& 0xfffffffc;
8114 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
8115 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
8118 dsc
->u
.ldst
.xfersize
= 4;
8120 dsc
->u
.ldst
.immed
= 0;
8121 dsc
->u
.ldst
.writeback
= 0;
8122 dsc
->u
.ldst
.restore_r4
= 0;
8124 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8126 dsc
->cleanup
= &cleanup_load
;
8131 /* Copy Thumb cbnz/cbz insruction. */
8134 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
8135 struct regcache
*regs
,
8136 struct displaced_step_closure
*dsc
)
8138 int non_zero
= bit (insn1
, 11);
8139 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
8140 CORE_ADDR from
= dsc
->insn_addr
;
8141 int rn
= bits (insn1
, 0, 2);
8142 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
8144 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
8145 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8146 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8147 condition is false, let it be, cleanup_branch will do nothing. */
8148 if (dsc
->u
.branch
.cond
)
8150 dsc
->u
.branch
.cond
= INST_AL
;
8151 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
8154 dsc
->u
.branch
.dest
= from
+ 2;
8156 dsc
->u
.branch
.link
= 0;
8157 dsc
->u
.branch
.exchange
= 0;
8159 if (debug_displaced
)
8160 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
8161 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
8162 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
8164 dsc
->modinsn
[0] = THUMB_NOP
;
8166 dsc
->cleanup
= &cleanup_branch
;
8170 /* Copy Table Branch Byte/Halfword */
8172 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
8173 uint16_t insn2
, struct regcache
*regs
,
8174 struct displaced_step_closure
*dsc
)
8176 ULONGEST rn_val
, rm_val
;
8177 int is_tbh
= bit (insn2
, 4);
8178 CORE_ADDR halfwords
= 0;
8179 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8181 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
8182 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
8188 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
8189 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
8195 target_read_memory (rn_val
+ rm_val
, buf
, 1);
8196 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
8199 if (debug_displaced
)
8200 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
8201 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
8202 (unsigned int) rn_val
, (unsigned int) rm_val
,
8203 (unsigned int) halfwords
);
8205 dsc
->u
.branch
.cond
= INST_AL
;
8206 dsc
->u
.branch
.link
= 0;
8207 dsc
->u
.branch
.exchange
= 0;
8208 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
8210 dsc
->cleanup
= &cleanup_branch
;
8216 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8217 struct displaced_step_closure
*dsc
)
8220 int val
= displaced_read_reg (regs
, dsc
, 7);
8221 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8224 val
= displaced_read_reg (regs
, dsc
, 8);
8225 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8228 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8233 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8234 struct regcache
*regs
,
8235 struct displaced_step_closure
*dsc
)
8237 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8239 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8242 (1) register list is full, that is, r0-r7 are used.
8243 Prepare: tmp[0] <- r8
8245 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8246 MOV r8, r7; Move value of r7 to r8;
8247 POP {r7}; Store PC value into r7.
8249 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8251 (2) register list is not full, supposing there are N registers in
8252 register list (except PC, 0 <= N <= 7).
8253 Prepare: for each i, 0 - N, tmp[i] <- ri.
8255 POP {r0, r1, ...., rN};
8257 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8258 from tmp[] properly.
8260 if (debug_displaced
)
8261 fprintf_unfiltered (gdb_stdlog
,
8262 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8263 dsc
->u
.block
.regmask
, insn1
);
8265 if (dsc
->u
.block
.regmask
== 0xff)
8267 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8269 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8270 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8271 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8274 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8278 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8279 unsigned int new_regmask
, bit
= 1;
8280 unsigned int to
= 0, from
= 0, i
, new_rn
;
8282 for (i
= 0; i
< num_in_list
+ 1; i
++)
8283 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8285 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8287 if (debug_displaced
)
8288 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8289 "{..., pc}: original reg list %.4x,"
8290 " modified list %.4x\n"),
8291 (int) dsc
->u
.block
.regmask
, new_regmask
);
8293 dsc
->u
.block
.regmask
|= 0x8000;
8294 dsc
->u
.block
.writeback
= 0;
8295 dsc
->u
.block
.cond
= INST_AL
;
8297 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8299 dsc
->cleanup
= &cleanup_block_load_pc
;
8306 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8307 struct regcache
*regs
,
8308 struct displaced_step_closure
*dsc
)
8310 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8311 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8314 /* 16-bit thumb instructions. */
8315 switch (op_bit_12_15
)
8317 /* Shift (imme), add, subtract, move and compare. */
8318 case 0: case 1: case 2: case 3:
8319 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8320 "shift/add/sub/mov/cmp",
8324 switch (op_bit_10_11
)
8326 case 0: /* Data-processing */
8327 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8331 case 1: /* Special data instructions and branch and exchange. */
8333 unsigned short op
= bits (insn1
, 7, 9);
8334 if (op
== 6 || op
== 7) /* BX or BLX */
8335 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8336 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8337 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8339 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8343 default: /* LDR (literal) */
8344 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8347 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8348 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8351 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8352 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8353 else /* Generate SP-relative address */
8354 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8356 case 11: /* Misc 16-bit instructions */
8358 switch (bits (insn1
, 8, 11))
8360 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8361 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8363 case 12: case 13: /* POP */
8364 if (bit (insn1
, 8)) /* PC is in register list. */
8365 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8367 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8369 case 15: /* If-Then, and hints */
8370 if (bits (insn1
, 0, 3))
8371 /* If-Then makes up to four following instructions conditional.
8372 IT instruction itself is not conditional, so handle it as a
8373 common unmodified instruction. */
8374 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8377 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8380 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8385 if (op_bit_10_11
< 2) /* Store multiple registers */
8386 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8387 else /* Load multiple registers */
8388 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8390 case 13: /* Conditional branch and supervisor call */
8391 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8392 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8394 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8396 case 14: /* Unconditional branch */
8397 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8404 internal_error (__FILE__
, __LINE__
,
8405 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8409 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8410 uint16_t insn1
, uint16_t insn2
,
8411 struct regcache
*regs
,
8412 struct displaced_step_closure
*dsc
)
8414 int rt
= bits (insn2
, 12, 15);
8415 int rn
= bits (insn1
, 0, 3);
8416 int op1
= bits (insn1
, 7, 8);
8419 switch (bits (insn1
, 5, 6))
8421 case 0: /* Load byte and memory hints */
8422 if (rt
== 0xf) /* PLD/PLI */
8425 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8426 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8428 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8433 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8434 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8437 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8438 "ldrb{reg, immediate}/ldrbt",
8443 case 1: /* Load halfword and memory hints. */
8444 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8445 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8446 "pld/unalloc memhint", dsc
);
8450 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8453 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8457 case 2: /* Load word */
8459 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8462 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8463 else if (op1
== 0x1) /* Encoding T3 */
8464 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8466 else /* op1 == 0x0 */
8468 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8469 /* LDR (immediate) */
8470 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8471 dsc
, bit (insn2
, 8), 1);
8472 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8473 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8476 /* LDR (register) */
8477 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8483 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8490 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8491 uint16_t insn2
, struct regcache
*regs
,
8492 struct displaced_step_closure
*dsc
)
8495 unsigned short op
= bit (insn2
, 15);
8496 unsigned int op1
= bits (insn1
, 11, 12);
8502 switch (bits (insn1
, 9, 10))
8507 /* Load/store {dual, execlusive}, table branch. */
8508 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8509 && bits (insn2
, 5, 7) == 0)
8510 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8513 /* PC is not allowed to use in load/store {dual, exclusive}
8515 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8516 "load/store dual/ex", dsc
);
8518 else /* load/store multiple */
8520 switch (bits (insn1
, 7, 8))
8522 case 0: case 3: /* SRS, RFE */
8523 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8526 case 1: case 2: /* LDM/STM/PUSH/POP */
8527 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8534 /* Data-processing (shift register). */
8535 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8538 default: /* Coprocessor instructions. */
8539 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8544 case 2: /* op1 = 2 */
8545 if (op
) /* Branch and misc control. */
8547 if (bit (insn2
, 14) /* BLX/BL */
8548 || bit (insn2
, 12) /* Unconditional branch */
8549 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8550 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8552 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8557 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8559 int op
= bits (insn1
, 4, 8);
8560 int rn
= bits (insn1
, 0, 3);
8561 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8562 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8565 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8568 else /* Data processing (modified immeidate) */
8569 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8573 case 3: /* op1 = 3 */
8574 switch (bits (insn1
, 9, 10))
8578 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8580 else /* NEON Load/Store and Store single data item */
8581 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8582 "neon elt/struct load/store",
8585 case 1: /* op1 = 3, bits (9, 10) == 1 */
8586 switch (bits (insn1
, 7, 8))
8588 case 0: case 1: /* Data processing (register) */
8589 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8592 case 2: /* Multiply and absolute difference */
8593 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8594 "mul/mua/diff", dsc
);
8596 case 3: /* Long multiply and divide */
8597 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8602 default: /* Coprocessor instructions */
8603 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8612 internal_error (__FILE__
, __LINE__
,
8613 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8618 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8619 CORE_ADDR to
, struct regcache
*regs
,
8620 struct displaced_step_closure
*dsc
)
8622 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8624 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8626 if (debug_displaced
)
8627 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8628 "at %.8lx\n", insn1
, (unsigned long) from
);
8631 dsc
->insn_size
= thumb_insn_size (insn1
);
8632 if (thumb_insn_size (insn1
) == 4)
8635 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8636 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8639 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8643 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8644 CORE_ADDR to
, struct regcache
*regs
,
8645 struct displaced_step_closure
*dsc
)
8648 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8651 /* Most displaced instructions use a 1-instruction scratch space, so set this
8652 here and override below if/when necessary. */
8654 dsc
->insn_addr
= from
;
8655 dsc
->scratch_base
= to
;
8656 dsc
->cleanup
= NULL
;
8657 dsc
->wrote_to_pc
= 0;
8659 if (!displaced_in_arm_mode (regs
))
8660 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8664 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8665 if (debug_displaced
)
8666 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8667 "at %.8lx\n", (unsigned long) insn
,
8668 (unsigned long) from
);
8670 if ((insn
& 0xf0000000) == 0xf0000000)
8671 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8672 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8674 case 0x0: case 0x1: case 0x2: case 0x3:
8675 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8678 case 0x4: case 0x5: case 0x6:
8679 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8683 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8686 case 0x8: case 0x9: case 0xa: case 0xb:
8687 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8690 case 0xc: case 0xd: case 0xe: case 0xf:
8691 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8696 internal_error (__FILE__
, __LINE__
,
8697 _("arm_process_displaced_insn: Instruction decode error"));
8700 /* Actually set up the scratch space for a displaced instruction. */
8703 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8704 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8706 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8707 unsigned int i
, len
, offset
;
8708 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8709 int size
= dsc
->is_thumb
? 2 : 4;
8710 const gdb_byte
*bkp_insn
;
8713 /* Poke modified instruction(s). */
8714 for (i
= 0; i
< dsc
->numinsns
; i
++)
8716 if (debug_displaced
)
8718 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8720 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8723 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8724 (unsigned short)dsc
->modinsn
[i
]);
8726 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8727 (unsigned long) to
+ offset
);
8730 write_memory_unsigned_integer (to
+ offset
, size
,
8731 byte_order_for_code
,
8736 /* Choose the correct breakpoint instruction. */
8739 bkp_insn
= tdep
->thumb_breakpoint
;
8740 len
= tdep
->thumb_breakpoint_size
;
8744 bkp_insn
= tdep
->arm_breakpoint
;
8745 len
= tdep
->arm_breakpoint_size
;
8748 /* Put breakpoint afterwards. */
8749 write_memory (to
+ offset
, bkp_insn
, len
);
8751 if (debug_displaced
)
8752 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8753 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8756 /* Entry point for copying an instruction into scratch space for displaced
8759 struct displaced_step_closure
*
8760 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8761 CORE_ADDR from
, CORE_ADDR to
,
8762 struct regcache
*regs
)
8764 struct displaced_step_closure
*dsc
8765 = xmalloc (sizeof (struct displaced_step_closure
));
8766 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8767 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8772 /* Entry point for cleaning things up after a displaced instruction has been
8776 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8777 struct displaced_step_closure
*dsc
,
8778 CORE_ADDR from
, CORE_ADDR to
,
8779 struct regcache
*regs
)
8782 dsc
->cleanup (gdbarch
, regs
, dsc
);
8784 if (!dsc
->wrote_to_pc
)
8785 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8786 dsc
->insn_addr
+ dsc
->insn_size
);
8790 #include "bfd-in2.h"
8791 #include "libcoff.h"
8794 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8796 struct gdbarch
*gdbarch
= info
->application_data
;
8798 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8800 static asymbol
*asym
;
8801 static combined_entry_type ce
;
8802 static struct coff_symbol_struct csym
;
8803 static struct bfd fake_bfd
;
8804 static bfd_target fake_target
;
8806 if (csym
.native
== NULL
)
8808 /* Create a fake symbol vector containing a Thumb symbol.
8809 This is solely so that the code in print_insn_little_arm()
8810 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8811 the presence of a Thumb symbol and switch to decoding
8812 Thumb instructions. */
8814 fake_target
.flavour
= bfd_target_coff_flavour
;
8815 fake_bfd
.xvec
= &fake_target
;
8816 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8818 csym
.symbol
.the_bfd
= &fake_bfd
;
8819 csym
.symbol
.name
= "fake";
8820 asym
= (asymbol
*) & csym
;
8823 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8824 info
->symbols
= &asym
;
8827 info
->symbols
= NULL
;
8829 if (info
->endian
== BFD_ENDIAN_BIG
)
8830 return print_insn_big_arm (memaddr
, info
);
8832 return print_insn_little_arm (memaddr
, info
);
8835 /* The following define instruction sequences that will cause ARM
8836 cpu's to take an undefined instruction trap. These are used to
8837 signal a breakpoint to GDB.
8839 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8840 modes. A different instruction is required for each mode. The ARM
8841 cpu's can also be big or little endian. Thus four different
8842 instructions are needed to support all cases.
8844 Note: ARMv4 defines several new instructions that will take the
8845 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8846 not in fact add the new instructions. The new undefined
8847 instructions in ARMv4 are all instructions that had no defined
8848 behaviour in earlier chips. There is no guarantee that they will
8849 raise an exception, but may be treated as NOP's. In practice, it
8850 may only safe to rely on instructions matching:
8852 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8853 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8854 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8856 Even this may only true if the condition predicate is true. The
8857 following use a condition predicate of ALWAYS so it is always TRUE.
8859 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8860 and NetBSD all use a software interrupt rather than an undefined
8861 instruction to force a trap. This can be handled by by the
8862 abi-specific code during establishment of the gdbarch vector. */
8864 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8865 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8866 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8867 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8869 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8870 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8871 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8872 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8874 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8875 the program counter value to determine whether a 16-bit or 32-bit
8876 breakpoint should be used. It returns a pointer to a string of
8877 bytes that encode a breakpoint instruction, stores the length of
8878 the string to *lenptr, and adjusts the program counter (if
8879 necessary) to point to the actual memory location where the
8880 breakpoint should be inserted. */
8882 static const unsigned char *
8883 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8885 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8886 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8888 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8890 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8892 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8893 check whether we are replacing a 32-bit instruction. */
8894 if (tdep
->thumb2_breakpoint
!= NULL
)
8897 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8899 unsigned short inst1
;
8900 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8901 if (thumb_insn_size (inst1
) == 4)
8903 *lenptr
= tdep
->thumb2_breakpoint_size
;
8904 return tdep
->thumb2_breakpoint
;
8909 *lenptr
= tdep
->thumb_breakpoint_size
;
8910 return tdep
->thumb_breakpoint
;
8914 *lenptr
= tdep
->arm_breakpoint_size
;
8915 return tdep
->arm_breakpoint
;
8920 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8923 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8925 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8926 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8927 that this is not confused with a 32-bit ARM breakpoint. */
8931 /* Extract from an array REGBUF containing the (raw) register state a
8932 function return value of type TYPE, and copy that, in virtual
8933 format, into VALBUF. */
8936 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8939 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8940 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8942 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8944 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8948 /* The value is in register F0 in internal format. We need to
8949 extract the raw value and then convert it to the desired
8951 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8953 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8954 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8955 valbuf
, gdbarch_byte_order (gdbarch
));
8959 case ARM_FLOAT_SOFT_FPA
:
8960 case ARM_FLOAT_SOFT_VFP
:
8961 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8962 not using the VFP ABI code. */
8964 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8965 if (TYPE_LENGTH (type
) > 4)
8966 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8967 valbuf
+ INT_REGISTER_SIZE
);
8971 internal_error (__FILE__
, __LINE__
,
8972 _("arm_extract_return_value: "
8973 "Floating point model not supported"));
8977 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8978 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8979 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8980 || TYPE_CODE (type
) == TYPE_CODE_PTR
8981 || TYPE_CODE (type
) == TYPE_CODE_REF
8982 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8984 /* If the type is a plain integer, then the access is
8985 straight-forward. Otherwise we have to play around a bit
8987 int len
= TYPE_LENGTH (type
);
8988 int regno
= ARM_A1_REGNUM
;
8993 /* By using store_unsigned_integer we avoid having to do
8994 anything special for small big-endian values. */
8995 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8996 store_unsigned_integer (valbuf
,
8997 (len
> INT_REGISTER_SIZE
8998 ? INT_REGISTER_SIZE
: len
),
9000 len
-= INT_REGISTER_SIZE
;
9001 valbuf
+= INT_REGISTER_SIZE
;
9006 /* For a structure or union the behaviour is as if the value had
9007 been stored to word-aligned memory and then loaded into
9008 registers with 32-bit load instruction(s). */
9009 int len
= TYPE_LENGTH (type
);
9010 int regno
= ARM_A1_REGNUM
;
9011 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9015 regcache_cooked_read (regs
, regno
++, tmpbuf
);
9016 memcpy (valbuf
, tmpbuf
,
9017 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9018 len
-= INT_REGISTER_SIZE
;
9019 valbuf
+= INT_REGISTER_SIZE
;
9025 /* Will a function return an aggregate type in memory or in a
9026 register? Return 0 if an aggregate type can be returned in a
9027 register, 1 if it must be returned in memory. */
9030 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
9033 enum type_code code
;
9035 CHECK_TYPEDEF (type
);
9037 /* In the ARM ABI, "integer" like aggregate types are returned in
9038 registers. For an aggregate type to be integer like, its size
9039 must be less than or equal to INT_REGISTER_SIZE and the
9040 offset of each addressable subfield must be zero. Note that bit
9041 fields are not addressable, and all addressable subfields of
9042 unions always start at offset zero.
9044 This function is based on the behaviour of GCC 2.95.1.
9045 See: gcc/arm.c: arm_return_in_memory() for details.
9047 Note: All versions of GCC before GCC 2.95.2 do not set up the
9048 parameters correctly for a function returning the following
9049 structure: struct { float f;}; This should be returned in memory,
9050 not a register. Richard Earnshaw sent me a patch, but I do not
9051 know of any way to detect if a function like the above has been
9052 compiled with the correct calling convention. */
9054 /* All aggregate types that won't fit in a register must be returned
9056 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
9061 /* The AAPCS says all aggregates not larger than a word are returned
9063 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
9066 /* The only aggregate types that can be returned in a register are
9067 structs and unions. Arrays must be returned in memory. */
9068 code
= TYPE_CODE (type
);
9069 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
9074 /* Assume all other aggregate types can be returned in a register.
9075 Run a check for structures, unions and arrays. */
9078 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
9081 /* Need to check if this struct/union is "integer" like. For
9082 this to be true, its size must be less than or equal to
9083 INT_REGISTER_SIZE and the offset of each addressable
9084 subfield must be zero. Note that bit fields are not
9085 addressable, and unions always start at offset zero. If any
9086 of the subfields is a floating point type, the struct/union
9087 cannot be an integer type. */
9089 /* For each field in the object, check:
9090 1) Is it FP? --> yes, nRc = 1;
9091 2) Is it addressable (bitpos != 0) and
9092 not packed (bitsize == 0)?
9096 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
9098 enum type_code field_type_code
;
9099 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
9102 /* Is it a floating point type field? */
9103 if (field_type_code
== TYPE_CODE_FLT
)
9109 /* If bitpos != 0, then we have to care about it. */
9110 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
9112 /* Bitfields are not addressable. If the field bitsize is
9113 zero, then the field is not packed. Hence it cannot be
9114 a bitfield or any other packed type. */
9115 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
9127 /* Write into appropriate registers a function return value of type
9128 TYPE, given in virtual format. */
9131 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
9132 const gdb_byte
*valbuf
)
9134 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
9135 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9137 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
9139 gdb_byte buf
[MAX_REGISTER_SIZE
];
9141 switch (gdbarch_tdep (gdbarch
)->fp_model
)
9145 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
9146 gdbarch_byte_order (gdbarch
));
9147 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
9150 case ARM_FLOAT_SOFT_FPA
:
9151 case ARM_FLOAT_SOFT_VFP
:
9152 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9153 not using the VFP ABI code. */
9155 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
9156 if (TYPE_LENGTH (type
) > 4)
9157 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
9158 valbuf
+ INT_REGISTER_SIZE
);
9162 internal_error (__FILE__
, __LINE__
,
9163 _("arm_store_return_value: Floating "
9164 "point model not supported"));
9168 else if (TYPE_CODE (type
) == TYPE_CODE_INT
9169 || TYPE_CODE (type
) == TYPE_CODE_CHAR
9170 || TYPE_CODE (type
) == TYPE_CODE_BOOL
9171 || TYPE_CODE (type
) == TYPE_CODE_PTR
9172 || TYPE_CODE (type
) == TYPE_CODE_REF
9173 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
9175 if (TYPE_LENGTH (type
) <= 4)
9177 /* Values of one word or less are zero/sign-extended and
9179 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9180 LONGEST val
= unpack_long (type
, valbuf
);
9182 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
9183 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
9187 /* Integral values greater than one word are stored in consecutive
9188 registers starting with r0. This will always be a multiple of
9189 the regiser size. */
9190 int len
= TYPE_LENGTH (type
);
9191 int regno
= ARM_A1_REGNUM
;
9195 regcache_cooked_write (regs
, regno
++, valbuf
);
9196 len
-= INT_REGISTER_SIZE
;
9197 valbuf
+= INT_REGISTER_SIZE
;
9203 /* For a structure or union the behaviour is as if the value had
9204 been stored to word-aligned memory and then loaded into
9205 registers with 32-bit load instruction(s). */
9206 int len
= TYPE_LENGTH (type
);
9207 int regno
= ARM_A1_REGNUM
;
9208 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9212 memcpy (tmpbuf
, valbuf
,
9213 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9214 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9215 len
-= INT_REGISTER_SIZE
;
9216 valbuf
+= INT_REGISTER_SIZE
;
9222 /* Handle function return values. */
9224 static enum return_value_convention
9225 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9226 struct type
*valtype
, struct regcache
*regcache
,
9227 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9229 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9230 struct type
*func_type
= function
? value_type (function
) : NULL
;
9231 enum arm_vfp_cprc_base_type vfp_base_type
;
9234 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9235 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9237 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9238 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9240 for (i
= 0; i
< vfp_base_count
; i
++)
9242 if (reg_char
== 'q')
9245 arm_neon_quad_write (gdbarch
, regcache
, i
,
9246 writebuf
+ i
* unit_length
);
9249 arm_neon_quad_read (gdbarch
, regcache
, i
,
9250 readbuf
+ i
* unit_length
);
9257 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
9258 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9261 regcache_cooked_write (regcache
, regnum
,
9262 writebuf
+ i
* unit_length
);
9264 regcache_cooked_read (regcache
, regnum
,
9265 readbuf
+ i
* unit_length
);
9268 return RETURN_VALUE_REGISTER_CONVENTION
;
9271 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9272 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9273 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9275 if (tdep
->struct_return
== pcc_struct_return
9276 || arm_return_in_memory (gdbarch
, valtype
))
9277 return RETURN_VALUE_STRUCT_CONVENTION
;
9280 /* AAPCS returns complex types longer than a register in memory. */
9281 if (tdep
->arm_abi
!= ARM_ABI_APCS
9282 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9283 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9284 return RETURN_VALUE_STRUCT_CONVENTION
;
9287 arm_store_return_value (valtype
, regcache
, writebuf
);
9290 arm_extract_return_value (valtype
, regcache
, readbuf
);
9292 return RETURN_VALUE_REGISTER_CONVENTION
;
9297 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9299 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9300 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9301 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9303 gdb_byte buf
[INT_REGISTER_SIZE
];
9305 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9307 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9311 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9315 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9316 return the target PC. Otherwise return 0. */
9319 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9323 CORE_ADDR start_addr
;
9325 /* Find the starting address and name of the function containing the PC. */
9326 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9328 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9330 start_addr
= arm_skip_bx_reg (frame
, pc
);
9331 if (start_addr
!= 0)
9337 /* If PC is in a Thumb call or return stub, return the address of the
9338 target PC, which is in a register. The thunk functions are called
9339 _call_via_xx, where x is the register name. The possible names
9340 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9341 functions, named __ARM_call_via_r[0-7]. */
9342 if (strncmp (name
, "_call_via_", 10) == 0
9343 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9345 /* Use the name suffix to determine which register contains the
9347 static char *table
[15] =
9348 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9349 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9352 int offset
= strlen (name
) - 2;
9354 for (regno
= 0; regno
<= 14; regno
++)
9355 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9356 return get_frame_register_unsigned (frame
, regno
);
9359 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9360 non-interworking calls to foo. We could decode the stubs
9361 to find the target but it's easier to use the symbol table. */
9362 namelen
= strlen (name
);
9363 if (name
[0] == '_' && name
[1] == '_'
9364 && ((namelen
> 2 + strlen ("_from_thumb")
9365 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
9366 strlen ("_from_thumb")) == 0)
9367 || (namelen
> 2 + strlen ("_from_arm")
9368 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
9369 strlen ("_from_arm")) == 0)))
9372 int target_len
= namelen
- 2;
9373 struct bound_minimal_symbol minsym
;
9374 struct objfile
*objfile
;
9375 struct obj_section
*sec
;
9377 if (name
[namelen
- 1] == 'b')
9378 target_len
-= strlen ("_from_thumb");
9380 target_len
-= strlen ("_from_arm");
9382 target_name
= alloca (target_len
+ 1);
9383 memcpy (target_name
, name
+ 2, target_len
);
9384 target_name
[target_len
] = '\0';
9386 sec
= find_pc_section (pc
);
9387 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9388 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9389 if (minsym
.minsym
!= NULL
)
9390 return BMSYMBOL_VALUE_ADDRESS (minsym
);
9395 return 0; /* not a stub */
9399 set_arm_command (char *args
, int from_tty
)
9401 printf_unfiltered (_("\
9402 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9403 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9407 show_arm_command (char *args
, int from_tty
)
9409 cmd_show_list (showarmcmdlist
, from_tty
, "");
9413 arm_update_current_architecture (void)
9415 struct gdbarch_info info
;
9417 /* If the current architecture is not ARM, we have nothing to do. */
9418 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9421 /* Update the architecture. */
9422 gdbarch_info_init (&info
);
9424 if (!gdbarch_update_p (info
))
9425 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9429 set_fp_model_sfunc (char *args
, int from_tty
,
9430 struct cmd_list_element
*c
)
9432 enum arm_float_model fp_model
;
9434 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9435 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9437 arm_fp_model
= fp_model
;
9441 if (fp_model
== ARM_FLOAT_LAST
)
9442 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9445 arm_update_current_architecture ();
9449 show_fp_model (struct ui_file
*file
, int from_tty
,
9450 struct cmd_list_element
*c
, const char *value
)
9452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9454 if (arm_fp_model
== ARM_FLOAT_AUTO
9455 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9456 fprintf_filtered (file
, _("\
9457 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9458 fp_model_strings
[tdep
->fp_model
]);
9460 fprintf_filtered (file
, _("\
9461 The current ARM floating point model is \"%s\".\n"),
9462 fp_model_strings
[arm_fp_model
]);
9466 arm_set_abi (char *args
, int from_tty
,
9467 struct cmd_list_element
*c
)
9469 enum arm_abi_kind arm_abi
;
9471 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9472 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9474 arm_abi_global
= arm_abi
;
9478 if (arm_abi
== ARM_ABI_LAST
)
9479 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9482 arm_update_current_architecture ();
9486 arm_show_abi (struct ui_file
*file
, int from_tty
,
9487 struct cmd_list_element
*c
, const char *value
)
9489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9491 if (arm_abi_global
== ARM_ABI_AUTO
9492 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9493 fprintf_filtered (file
, _("\
9494 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9495 arm_abi_strings
[tdep
->arm_abi
]);
9497 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9502 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9503 struct cmd_list_element
*c
, const char *value
)
9505 fprintf_filtered (file
,
9506 _("The current execution mode assumed "
9507 "(when symbols are unavailable) is \"%s\".\n"),
9508 arm_fallback_mode_string
);
9512 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9513 struct cmd_list_element
*c
, const char *value
)
9515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9517 fprintf_filtered (file
,
9518 _("The current execution mode assumed "
9519 "(even when symbols are available) is \"%s\".\n"),
9520 arm_force_mode_string
);
9523 /* If the user changes the register disassembly style used for info
9524 register and other commands, we have to also switch the style used
9525 in opcodes for disassembly output. This function is run in the "set
9526 arm disassembly" command, and does that. */
9529 set_disassembly_style_sfunc (char *args
, int from_tty
,
9530 struct cmd_list_element
*c
)
9532 set_disassembly_style ();
9535 /* Return the ARM register name corresponding to register I. */
9537 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9539 const int num_regs
= gdbarch_num_regs (gdbarch
);
9541 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9542 && i
>= num_regs
&& i
< num_regs
+ 32)
9544 static const char *const vfp_pseudo_names
[] = {
9545 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9546 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9547 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9548 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9551 return vfp_pseudo_names
[i
- num_regs
];
9554 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9555 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9557 static const char *const neon_pseudo_names
[] = {
9558 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9559 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9562 return neon_pseudo_names
[i
- num_regs
- 32];
9565 if (i
>= ARRAY_SIZE (arm_register_names
))
9566 /* These registers are only supported on targets which supply
9567 an XML description. */
9570 return arm_register_names
[i
];
9574 set_disassembly_style (void)
9578 /* Find the style that the user wants. */
9579 for (current
= 0; current
< num_disassembly_options
; current
++)
9580 if (disassembly_style
== valid_disassembly_styles
[current
])
9582 gdb_assert (current
< num_disassembly_options
);
9584 /* Synchronize the disassembler. */
9585 set_arm_regname_option (current
);
9588 /* Test whether the coff symbol specific value corresponds to a Thumb
9592 coff_sym_is_thumb (int val
)
9594 return (val
== C_THUMBEXT
9595 || val
== C_THUMBSTAT
9596 || val
== C_THUMBEXTFUNC
9597 || val
== C_THUMBSTATFUNC
9598 || val
== C_THUMBLABEL
);
9601 /* arm_coff_make_msymbol_special()
9602 arm_elf_make_msymbol_special()
9604 These functions test whether the COFF or ELF symbol corresponds to
9605 an address in thumb code, and set a "special" bit in a minimal
9606 symbol to indicate that it does. */
9609 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9611 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9612 == ST_BRANCH_TO_THUMB
)
9613 MSYMBOL_SET_SPECIAL (msym
);
9617 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9619 if (coff_sym_is_thumb (val
))
9620 MSYMBOL_SET_SPECIAL (msym
);
9624 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9626 struct arm_per_objfile
*data
= arg
;
9629 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9630 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9634 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9637 const char *name
= bfd_asymbol_name (sym
);
9638 struct arm_per_objfile
*data
;
9639 VEC(arm_mapping_symbol_s
) **map_p
;
9640 struct arm_mapping_symbol new_map_sym
;
9642 gdb_assert (name
[0] == '$');
9643 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9646 data
= objfile_data (objfile
, arm_objfile_data_key
);
9649 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9650 struct arm_per_objfile
);
9651 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9652 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9653 objfile
->obfd
->section_count
,
9654 VEC(arm_mapping_symbol_s
) *);
9656 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9658 new_map_sym
.value
= sym
->value
;
9659 new_map_sym
.type
= name
[1];
9661 /* Assume that most mapping symbols appear in order of increasing
9662 value. If they were randomly distributed, it would be faster to
9663 always push here and then sort at first use. */
9664 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9666 struct arm_mapping_symbol
*prev_map_sym
;
9668 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9669 if (prev_map_sym
->value
>= sym
->value
)
9672 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9673 arm_compare_mapping_symbols
);
9674 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9679 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9683 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9685 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9686 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9688 /* If necessary, set the T bit. */
9691 ULONGEST val
, t_bit
;
9692 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9693 t_bit
= arm_psr_thumb_bit (gdbarch
);
9694 if (arm_pc_is_thumb (gdbarch
, pc
))
9695 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9698 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9703 /* Read the contents of a NEON quad register, by reading from two
9704 double registers. This is used to implement the quad pseudo
9705 registers, and for argument passing in case the quad registers are
9706 missing; vectors are passed in quad registers when using the VFP
9707 ABI, even if a NEON unit is not present. REGNUM is the index of
9708 the quad register, in [0, 15]. */
9710 static enum register_status
9711 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9712 int regnum
, gdb_byte
*buf
)
9715 gdb_byte reg_buf
[8];
9716 int offset
, double_regnum
;
9717 enum register_status status
;
9719 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9720 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9723 /* d0 is always the least significant half of q0. */
9724 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9729 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9730 if (status
!= REG_VALID
)
9732 memcpy (buf
+ offset
, reg_buf
, 8);
9734 offset
= 8 - offset
;
9735 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9736 if (status
!= REG_VALID
)
9738 memcpy (buf
+ offset
, reg_buf
, 8);
9743 static enum register_status
9744 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9745 int regnum
, gdb_byte
*buf
)
9747 const int num_regs
= gdbarch_num_regs (gdbarch
);
9749 gdb_byte reg_buf
[8];
9750 int offset
, double_regnum
;
9752 gdb_assert (regnum
>= num_regs
);
9755 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9756 /* Quad-precision register. */
9757 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9760 enum register_status status
;
9762 /* Single-precision register. */
9763 gdb_assert (regnum
< 32);
9765 /* s0 is always the least significant half of d0. */
9766 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9767 offset
= (regnum
& 1) ? 0 : 4;
9769 offset
= (regnum
& 1) ? 4 : 0;
9771 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9772 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9775 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9776 if (status
== REG_VALID
)
9777 memcpy (buf
, reg_buf
+ offset
, 4);
9782 /* Store the contents of BUF to a NEON quad register, by writing to
9783 two double registers. This is used to implement the quad pseudo
9784 registers, and for argument passing in case the quad registers are
9785 missing; vectors are passed in quad registers when using the VFP
9786 ABI, even if a NEON unit is not present. REGNUM is the index
9787 of the quad register, in [0, 15]. */
9790 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9791 int regnum
, const gdb_byte
*buf
)
9794 int offset
, double_regnum
;
9796 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9797 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9800 /* d0 is always the least significant half of q0. */
9801 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9806 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9807 offset
= 8 - offset
;
9808 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9812 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9813 int regnum
, const gdb_byte
*buf
)
9815 const int num_regs
= gdbarch_num_regs (gdbarch
);
9817 gdb_byte reg_buf
[8];
9818 int offset
, double_regnum
;
9820 gdb_assert (regnum
>= num_regs
);
9823 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9824 /* Quad-precision register. */
9825 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9828 /* Single-precision register. */
9829 gdb_assert (regnum
< 32);
9831 /* s0 is always the least significant half of d0. */
9832 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9833 offset
= (regnum
& 1) ? 0 : 4;
9835 offset
= (regnum
& 1) ? 4 : 0;
9837 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9838 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9841 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9842 memcpy (reg_buf
+ offset
, buf
, 4);
9843 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9847 static struct value
*
9848 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9850 const int *reg_p
= baton
;
9851 return value_of_register (*reg_p
, frame
);
9854 static enum gdb_osabi
9855 arm_elf_osabi_sniffer (bfd
*abfd
)
9857 unsigned int elfosabi
;
9858 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9860 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9862 if (elfosabi
== ELFOSABI_ARM
)
9863 /* GNU tools use this value. Check note sections in this case,
9865 bfd_map_over_sections (abfd
,
9866 generic_elf_osabi_sniff_abi_tag_sections
,
9869 /* Anything else will be handled by the generic ELF sniffer. */
9874 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9875 struct reggroup
*group
)
9877 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9878 this, FPS register belongs to save_regroup, restore_reggroup, and
9879 all_reggroup, of course. */
9880 if (regnum
== ARM_FPS_REGNUM
)
9881 return (group
== float_reggroup
9882 || group
== save_reggroup
9883 || group
== restore_reggroup
9884 || group
== all_reggroup
);
9886 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9890 /* For backward-compatibility we allow two 'g' packet lengths with
9891 the remote protocol depending on whether FPA registers are
9892 supplied. M-profile targets do not have FPA registers, but some
9893 stubs already exist in the wild which use a 'g' packet which
9894 supplies them albeit with dummy values. The packet format which
9895 includes FPA registers should be considered deprecated for
9896 M-profile targets. */
9899 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9901 if (gdbarch_tdep (gdbarch
)->is_m
)
9903 /* If we know from the executable this is an M-profile target,
9904 cater for remote targets whose register set layout is the
9905 same as the FPA layout. */
9906 register_remote_g_packet_guess (gdbarch
,
9907 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9908 (16 * INT_REGISTER_SIZE
)
9909 + (8 * FP_REGISTER_SIZE
)
9910 + (2 * INT_REGISTER_SIZE
),
9911 tdesc_arm_with_m_fpa_layout
);
9913 /* The regular M-profile layout. */
9914 register_remote_g_packet_guess (gdbarch
,
9915 /* r0-r12,sp,lr,pc; xpsr */
9916 (16 * INT_REGISTER_SIZE
)
9917 + INT_REGISTER_SIZE
,
9920 /* M-profile plus M4F VFP. */
9921 register_remote_g_packet_guess (gdbarch
,
9922 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9923 (16 * INT_REGISTER_SIZE
)
9924 + (16 * VFP_REGISTER_SIZE
)
9925 + (2 * INT_REGISTER_SIZE
),
9926 tdesc_arm_with_m_vfp_d16
);
9929 /* Otherwise we don't have a useful guess. */
9933 /* Initialize the current architecture based on INFO. If possible,
9934 re-use an architecture from ARCHES, which is a list of
9935 architectures already created during this debugging session.
9937 Called e.g. at program startup, when reading a core file, and when
9938 reading a binary file. */
9940 static struct gdbarch
*
9941 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9943 struct gdbarch_tdep
*tdep
;
9944 struct gdbarch
*gdbarch
;
9945 struct gdbarch_list
*best_arch
;
9946 enum arm_abi_kind arm_abi
= arm_abi_global
;
9947 enum arm_float_model fp_model
= arm_fp_model
;
9948 struct tdesc_arch_data
*tdesc_data
= NULL
;
9950 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9952 int have_fpa_registers
= 1;
9953 const struct target_desc
*tdesc
= info
.target_desc
;
9955 /* If we have an object to base this architecture on, try to determine
9958 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9960 int ei_osabi
, e_flags
;
9962 switch (bfd_get_flavour (info
.abfd
))
9964 case bfd_target_aout_flavour
:
9965 /* Assume it's an old APCS-style ABI. */
9966 arm_abi
= ARM_ABI_APCS
;
9969 case bfd_target_coff_flavour
:
9970 /* Assume it's an old APCS-style ABI. */
9972 arm_abi
= ARM_ABI_APCS
;
9975 case bfd_target_elf_flavour
:
9976 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9977 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9979 if (ei_osabi
== ELFOSABI_ARM
)
9981 /* GNU tools used to use this value, but do not for EABI
9982 objects. There's nowhere to tag an EABI version
9983 anyway, so assume APCS. */
9984 arm_abi
= ARM_ABI_APCS
;
9986 else if (ei_osabi
== ELFOSABI_NONE
)
9988 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9989 int attr_arch
, attr_profile
;
9993 case EF_ARM_EABI_UNKNOWN
:
9994 /* Assume GNU tools. */
9995 arm_abi
= ARM_ABI_APCS
;
9998 case EF_ARM_EABI_VER4
:
9999 case EF_ARM_EABI_VER5
:
10000 arm_abi
= ARM_ABI_AAPCS
;
10001 /* EABI binaries default to VFP float ordering.
10002 They may also contain build attributes that can
10003 be used to identify if the VFP argument-passing
10005 if (fp_model
== ARM_FLOAT_AUTO
)
10008 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
10013 /* "The user intended FP parameter/result
10014 passing to conform to AAPCS, base
10016 fp_model
= ARM_FLOAT_SOFT_VFP
;
10019 /* "The user intended FP parameter/result
10020 passing to conform to AAPCS, VFP
10022 fp_model
= ARM_FLOAT_VFP
;
10025 /* "The user intended FP parameter/result
10026 passing to conform to tool chain-specific
10027 conventions" - we don't know any such
10028 conventions, so leave it as "auto". */
10031 /* Attribute value not mentioned in the
10032 October 2008 ABI, so leave it as
10037 fp_model
= ARM_FLOAT_SOFT_VFP
;
10043 /* Leave it as "auto". */
10044 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
10049 /* Detect M-profile programs. This only works if the
10050 executable file includes build attributes; GCC does
10051 copy them to the executable, but e.g. RealView does
10053 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
10055 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
10057 Tag_CPU_arch_profile
);
10058 /* GCC specifies the profile for v6-M; RealView only
10059 specifies the profile for architectures starting with
10060 V7 (as opposed to architectures with a tag
10061 numerically greater than TAG_CPU_ARCH_V7). */
10062 if (!tdesc_has_registers (tdesc
)
10063 && (attr_arch
== TAG_CPU_ARCH_V6_M
10064 || attr_arch
== TAG_CPU_ARCH_V6S_M
10065 || attr_profile
== 'M'))
10070 if (fp_model
== ARM_FLOAT_AUTO
)
10072 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
10074 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
10077 /* Leave it as "auto". Strictly speaking this case
10078 means FPA, but almost nobody uses that now, and
10079 many toolchains fail to set the appropriate bits
10080 for the floating-point model they use. */
10082 case EF_ARM_SOFT_FLOAT
:
10083 fp_model
= ARM_FLOAT_SOFT_FPA
;
10085 case EF_ARM_VFP_FLOAT
:
10086 fp_model
= ARM_FLOAT_VFP
;
10088 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
10089 fp_model
= ARM_FLOAT_SOFT_VFP
;
10094 if (e_flags
& EF_ARM_BE8
)
10095 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
10100 /* Leave it as "auto". */
10105 /* Check any target description for validity. */
10106 if (tdesc_has_registers (tdesc
))
10108 /* For most registers we require GDB's default names; but also allow
10109 the numeric names for sp / lr / pc, as a convenience. */
10110 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
10111 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
10112 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
10114 const struct tdesc_feature
*feature
;
10117 feature
= tdesc_find_feature (tdesc
,
10118 "org.gnu.gdb.arm.core");
10119 if (feature
== NULL
)
10121 feature
= tdesc_find_feature (tdesc
,
10122 "org.gnu.gdb.arm.m-profile");
10123 if (feature
== NULL
)
10129 tdesc_data
= tdesc_data_alloc ();
10132 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
10133 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10134 arm_register_names
[i
]);
10135 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10138 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10141 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10145 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10146 ARM_PS_REGNUM
, "xpsr");
10148 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10149 ARM_PS_REGNUM
, "cpsr");
10153 tdesc_data_cleanup (tdesc_data
);
10157 feature
= tdesc_find_feature (tdesc
,
10158 "org.gnu.gdb.arm.fpa");
10159 if (feature
!= NULL
)
10162 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
10163 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10164 arm_register_names
[i
]);
10167 tdesc_data_cleanup (tdesc_data
);
10172 have_fpa_registers
= 0;
10174 feature
= tdesc_find_feature (tdesc
,
10175 "org.gnu.gdb.xscale.iwmmxt");
10176 if (feature
!= NULL
)
10178 static const char *const iwmmxt_names
[] = {
10179 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10180 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10181 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10182 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10186 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
10188 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10189 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10191 /* Check for the control registers, but do not fail if they
10193 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
10194 tdesc_numbered_register (feature
, tdesc_data
, i
,
10195 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10197 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
10199 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10200 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10204 tdesc_data_cleanup (tdesc_data
);
10209 /* If we have a VFP unit, check whether the single precision registers
10210 are present. If not, then we will synthesize them as pseudo
10212 feature
= tdesc_find_feature (tdesc
,
10213 "org.gnu.gdb.arm.vfp");
10214 if (feature
!= NULL
)
10216 static const char *const vfp_double_names
[] = {
10217 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10218 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10219 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10220 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10223 /* Require the double precision registers. There must be either
10226 for (i
= 0; i
< 32; i
++)
10228 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10230 vfp_double_names
[i
]);
10234 if (!valid_p
&& i
== 16)
10237 /* Also require FPSCR. */
10238 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10239 ARM_FPSCR_REGNUM
, "fpscr");
10242 tdesc_data_cleanup (tdesc_data
);
10246 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10247 have_vfp_pseudos
= 1;
10249 have_vfp_registers
= 1;
10251 /* If we have VFP, also check for NEON. The architecture allows
10252 NEON without VFP (integer vector operations only), but GDB
10253 does not support that. */
10254 feature
= tdesc_find_feature (tdesc
,
10255 "org.gnu.gdb.arm.neon");
10256 if (feature
!= NULL
)
10258 /* NEON requires 32 double-precision registers. */
10261 tdesc_data_cleanup (tdesc_data
);
10265 /* If there are quad registers defined by the stub, use
10266 their type; otherwise (normally) provide them with
10267 the default type. */
10268 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10269 have_neon_pseudos
= 1;
10276 /* If there is already a candidate, use it. */
10277 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10279 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10281 if (arm_abi
!= ARM_ABI_AUTO
10282 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10285 if (fp_model
!= ARM_FLOAT_AUTO
10286 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10289 /* There are various other properties in tdep that we do not
10290 need to check here: those derived from a target description,
10291 since gdbarches with a different target description are
10292 automatically disqualified. */
10294 /* Do check is_m, though, since it might come from the binary. */
10295 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10298 /* Found a match. */
10302 if (best_arch
!= NULL
)
10304 if (tdesc_data
!= NULL
)
10305 tdesc_data_cleanup (tdesc_data
);
10306 return best_arch
->gdbarch
;
10309 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
10310 gdbarch
= gdbarch_alloc (&info
, tdep
);
10312 /* Record additional information about the architecture we are defining.
10313 These are gdbarch discriminators, like the OSABI. */
10314 tdep
->arm_abi
= arm_abi
;
10315 tdep
->fp_model
= fp_model
;
10317 tdep
->have_fpa_registers
= have_fpa_registers
;
10318 tdep
->have_vfp_registers
= have_vfp_registers
;
10319 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10320 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10321 tdep
->have_neon
= have_neon
;
10323 arm_register_g_packet_guesses (gdbarch
);
10326 switch (info
.byte_order_for_code
)
10328 case BFD_ENDIAN_BIG
:
10329 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10330 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10331 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10332 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10336 case BFD_ENDIAN_LITTLE
:
10337 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10338 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10339 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10340 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10345 internal_error (__FILE__
, __LINE__
,
10346 _("arm_gdbarch_init: bad byte order for float format"));
10349 /* On ARM targets char defaults to unsigned. */
10350 set_gdbarch_char_signed (gdbarch
, 0);
10352 /* Note: for displaced stepping, this includes the breakpoint, and one word
10353 of additional scratch space. This setting isn't used for anything beside
10354 displaced stepping at present. */
10355 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10357 /* This should be low enough for everything. */
10358 tdep
->lowest_pc
= 0x20;
10359 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10361 /* The default, for both APCS and AAPCS, is to return small
10362 structures in registers. */
10363 tdep
->struct_return
= reg_struct_return
;
10365 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10366 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10368 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10370 /* Frame handling. */
10371 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10372 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10373 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10375 frame_base_set_default (gdbarch
, &arm_normal_base
);
10377 /* Address manipulation. */
10378 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10380 /* Advance PC across function entry code. */
10381 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10383 /* Detect whether PC is in function epilogue. */
10384 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
10386 /* Skip trampolines. */
10387 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10389 /* The stack grows downward. */
10390 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10392 /* Breakpoint manipulation. */
10393 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10394 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10395 arm_remote_breakpoint_from_pc
);
10397 /* Information about registers, etc. */
10398 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10399 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10400 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10401 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10402 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10404 /* This "info float" is FPA-specific. Use the generic version if we
10405 do not have FPA. */
10406 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10407 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10409 /* Internal <-> external register number maps. */
10410 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10411 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10413 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10415 /* Returning results. */
10416 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10419 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10421 /* Minsymbol frobbing. */
10422 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10423 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10424 arm_coff_make_msymbol_special
);
10425 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10427 /* Thumb-2 IT block support. */
10428 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10429 arm_adjust_breakpoint_address
);
10431 /* Virtual tables. */
10432 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10434 /* Hook in the ABI-specific overrides, if they have been registered. */
10435 gdbarch_init_osabi (info
, gdbarch
);
10437 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10439 /* Add some default predicates. */
10441 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10442 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10443 dwarf2_append_unwinders (gdbarch
);
10444 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10445 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10447 /* Now we have tuned the configuration, set a few final things,
10448 based on what the OS ABI has told us. */
10450 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10451 binaries are always marked. */
10452 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10453 tdep
->arm_abi
= ARM_ABI_APCS
;
10455 /* Watchpoints are not steppable. */
10456 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10458 /* We used to default to FPA for generic ARM, but almost nobody
10459 uses that now, and we now provide a way for the user to force
10460 the model. So default to the most useful variant. */
10461 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10462 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10464 if (tdep
->jb_pc
>= 0)
10465 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10467 /* Floating point sizes and format. */
10468 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10469 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10471 set_gdbarch_double_format
10472 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10473 set_gdbarch_long_double_format
10474 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10478 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10479 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10482 if (have_vfp_pseudos
)
10484 /* NOTE: These are the only pseudo registers used by
10485 the ARM target at the moment. If more are added, a
10486 little more care in numbering will be needed. */
10488 int num_pseudos
= 32;
10489 if (have_neon_pseudos
)
10491 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10492 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10493 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10498 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10500 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10502 /* Override tdesc_register_type to adjust the types of VFP
10503 registers for NEON. */
10504 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10507 /* Add standard register aliases. We add aliases even for those
10508 nanes which are used by the current architecture - it's simpler,
10509 and does no harm, since nothing ever lists user registers. */
10510 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10511 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10512 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10518 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10520 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10525 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10526 (unsigned long) tdep
->lowest_pc
);
10529 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10532 _initialize_arm_tdep (void)
10534 struct ui_file
*stb
;
10536 struct cmd_list_element
*new_set
, *new_show
;
10537 const char *setname
;
10538 const char *setdesc
;
10539 const char *const *regnames
;
10541 static char *helptext
;
10542 char regdesc
[1024], *rdptr
= regdesc
;
10543 size_t rest
= sizeof (regdesc
);
10545 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10547 arm_objfile_data_key
10548 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10550 /* Add ourselves to objfile event chain. */
10551 observer_attach_new_objfile (arm_exidx_new_objfile
);
10553 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10555 /* Register an ELF OS ABI sniffer for ARM binaries. */
10556 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10557 bfd_target_elf_flavour
,
10558 arm_elf_osabi_sniffer
);
10560 /* Initialize the standard target descriptions. */
10561 initialize_tdesc_arm_with_m ();
10562 initialize_tdesc_arm_with_m_fpa_layout ();
10563 initialize_tdesc_arm_with_m_vfp_d16 ();
10564 initialize_tdesc_arm_with_iwmmxt ();
10565 initialize_tdesc_arm_with_vfpv2 ();
10566 initialize_tdesc_arm_with_vfpv3 ();
10567 initialize_tdesc_arm_with_neon ();
10569 /* Get the number of possible sets of register names defined in opcodes. */
10570 num_disassembly_options
= get_arm_regname_num_options ();
10572 /* Add root prefix command for all "set arm"/"show arm" commands. */
10573 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10574 _("Various ARM-specific commands."),
10575 &setarmcmdlist
, "set arm ", 0, &setlist
);
10577 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10578 _("Various ARM-specific commands."),
10579 &showarmcmdlist
, "show arm ", 0, &showlist
);
10581 /* Sync the opcode insn printer with our register viewer. */
10582 parse_arm_disassembler_option ("reg-names-std");
10584 /* Initialize the array that will be passed to
10585 add_setshow_enum_cmd(). */
10586 valid_disassembly_styles
10587 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
10588 for (i
= 0; i
< num_disassembly_options
; i
++)
10590 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10591 valid_disassembly_styles
[i
] = setname
;
10592 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10595 /* When we find the default names, tell the disassembler to use
10597 if (!strcmp (setname
, "std"))
10599 disassembly_style
= setname
;
10600 set_arm_regname_option (i
);
10603 /* Mark the end of valid options. */
10604 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10606 /* Create the help text. */
10607 stb
= mem_fileopen ();
10608 fprintf_unfiltered (stb
, "%s%s%s",
10609 _("The valid values are:\n"),
10611 _("The default is \"std\"."));
10612 helptext
= ui_file_xstrdup (stb
, NULL
);
10613 ui_file_delete (stb
);
10615 add_setshow_enum_cmd("disassembler", no_class
,
10616 valid_disassembly_styles
, &disassembly_style
,
10617 _("Set the disassembly style."),
10618 _("Show the disassembly style."),
10620 set_disassembly_style_sfunc
,
10621 NULL
, /* FIXME: i18n: The disassembly style is
10623 &setarmcmdlist
, &showarmcmdlist
);
10625 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10626 _("Set usage of ARM 32-bit mode."),
10627 _("Show usage of ARM 32-bit mode."),
10628 _("When off, a 26-bit PC will be used."),
10630 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10632 &setarmcmdlist
, &showarmcmdlist
);
10634 /* Add a command to allow the user to force the FPU model. */
10635 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10636 _("Set the floating point type."),
10637 _("Show the floating point type."),
10638 _("auto - Determine the FP typefrom the OS-ABI.\n\
10639 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10640 fpa - FPA co-processor (GCC compiled).\n\
10641 softvfp - Software FP with pure-endian doubles.\n\
10642 vfp - VFP co-processor."),
10643 set_fp_model_sfunc
, show_fp_model
,
10644 &setarmcmdlist
, &showarmcmdlist
);
10646 /* Add a command to allow the user to force the ABI. */
10647 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10649 _("Show the ABI."),
10650 NULL
, arm_set_abi
, arm_show_abi
,
10651 &setarmcmdlist
, &showarmcmdlist
);
10653 /* Add two commands to allow the user to force the assumed
10655 add_setshow_enum_cmd ("fallback-mode", class_support
,
10656 arm_mode_strings
, &arm_fallback_mode_string
,
10657 _("Set the mode assumed when symbols are unavailable."),
10658 _("Show the mode assumed when symbols are unavailable."),
10659 NULL
, NULL
, arm_show_fallback_mode
,
10660 &setarmcmdlist
, &showarmcmdlist
);
10661 add_setshow_enum_cmd ("force-mode", class_support
,
10662 arm_mode_strings
, &arm_force_mode_string
,
10663 _("Set the mode assumed even when symbols are available."),
10664 _("Show the mode assumed even when symbols are available."),
10665 NULL
, NULL
, arm_show_force_mode
,
10666 &setarmcmdlist
, &showarmcmdlist
);
10668 /* Debugging flag. */
10669 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10670 _("Set ARM debugging."),
10671 _("Show ARM debugging."),
10672 _("When on, arm-specific debugging is enabled."),
10674 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10675 &setdebuglist
, &showdebuglist
);
10678 /* ARM-reversible process record data structures. */
10680 #define ARM_INSN_SIZE_BYTES 4
10681 #define THUMB_INSN_SIZE_BYTES 2
10682 #define THUMB2_INSN_SIZE_BYTES 4
10685 /* Position of the bit within a 32-bit ARM instruction
10686 that defines whether the instruction is a load or store. */
10687 #define INSN_S_L_BIT_NUM 20
10689 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10692 unsigned int reg_len = LENGTH; \
10695 REGS = XNEWVEC (uint32_t, reg_len); \
10696 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10701 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10704 unsigned int mem_len = LENGTH; \
10707 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10708 memcpy(&MEMS->len, &RECORD_BUF[0], \
10709 sizeof(struct arm_mem_r) * LENGTH); \
10714 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10715 #define INSN_RECORDED(ARM_RECORD) \
10716 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10718 /* ARM memory record structure. */
10721 uint32_t len
; /* Record length. */
10722 uint32_t addr
; /* Memory address. */
10725 /* ARM instruction record contains opcode of current insn
10726 and execution state (before entry to decode_insn()),
10727 contains list of to-be-modified registers and
10728 memory blocks (on return from decode_insn()). */
10730 typedef struct insn_decode_record_t
10732 struct gdbarch
*gdbarch
;
10733 struct regcache
*regcache
;
10734 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10735 uint32_t arm_insn
; /* Should accommodate thumb. */
10736 uint32_t cond
; /* Condition code. */
10737 uint32_t opcode
; /* Insn opcode. */
10738 uint32_t decode
; /* Insn decode bits. */
10739 uint32_t mem_rec_count
; /* No of mem records. */
10740 uint32_t reg_rec_count
; /* No of reg records. */
10741 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10742 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10743 } insn_decode_record
;
10746 /* Checks ARM SBZ and SBO mandatory fields. */
10749 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10751 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10770 enum arm_record_result
10772 ARM_RECORD_SUCCESS
= 0,
10773 ARM_RECORD_FAILURE
= 1
10780 } arm_record_strx_t
;
10791 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10792 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10795 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10796 ULONGEST u_regval
[2]= {0};
10798 uint32_t reg_src1
= 0, reg_src2
= 0;
10799 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10800 uint32_t opcode1
= 0;
10802 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10803 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10804 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10807 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10809 /* 1) Handle misc store, immediate offset. */
10810 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10811 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10812 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10813 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10815 if (ARM_PC_REGNUM
== reg_src1
)
10817 /* If R15 was used as Rn, hence current PC+8. */
10818 u_regval
[0] = u_regval
[0] + 8;
10820 offset_8
= (immed_high
<< 4) | immed_low
;
10821 /* Calculate target store address. */
10822 if (14 == arm_insn_r
->opcode
)
10824 tgt_mem_addr
= u_regval
[0] + offset_8
;
10828 tgt_mem_addr
= u_regval
[0] - offset_8
;
10830 if (ARM_RECORD_STRH
== str_type
)
10832 record_buf_mem
[0] = 2;
10833 record_buf_mem
[1] = tgt_mem_addr
;
10834 arm_insn_r
->mem_rec_count
= 1;
10836 else if (ARM_RECORD_STRD
== str_type
)
10838 record_buf_mem
[0] = 4;
10839 record_buf_mem
[1] = tgt_mem_addr
;
10840 record_buf_mem
[2] = 4;
10841 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10842 arm_insn_r
->mem_rec_count
= 2;
10845 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10847 /* 2) Store, register offset. */
10849 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10851 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10852 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10853 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10854 if (15 == reg_src2
)
10856 /* If R15 was used as Rn, hence current PC+8. */
10857 u_regval
[0] = u_regval
[0] + 8;
10859 /* Calculate target store address, Rn +/- Rm, register offset. */
10860 if (12 == arm_insn_r
->opcode
)
10862 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10866 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10868 if (ARM_RECORD_STRH
== str_type
)
10870 record_buf_mem
[0] = 2;
10871 record_buf_mem
[1] = tgt_mem_addr
;
10872 arm_insn_r
->mem_rec_count
= 1;
10874 else if (ARM_RECORD_STRD
== str_type
)
10876 record_buf_mem
[0] = 4;
10877 record_buf_mem
[1] = tgt_mem_addr
;
10878 record_buf_mem
[2] = 4;
10879 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10880 arm_insn_r
->mem_rec_count
= 2;
10883 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10884 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10886 /* 3) Store, immediate pre-indexed. */
10887 /* 5) Store, immediate post-indexed. */
10888 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10889 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10890 offset_8
= (immed_high
<< 4) | immed_low
;
10891 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10892 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10893 /* Calculate target store address, Rn +/- Rm, register offset. */
10894 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10896 tgt_mem_addr
= u_regval
[0] + offset_8
;
10900 tgt_mem_addr
= u_regval
[0] - offset_8
;
10902 if (ARM_RECORD_STRH
== str_type
)
10904 record_buf_mem
[0] = 2;
10905 record_buf_mem
[1] = tgt_mem_addr
;
10906 arm_insn_r
->mem_rec_count
= 1;
10908 else if (ARM_RECORD_STRD
== str_type
)
10910 record_buf_mem
[0] = 4;
10911 record_buf_mem
[1] = tgt_mem_addr
;
10912 record_buf_mem
[2] = 4;
10913 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10914 arm_insn_r
->mem_rec_count
= 2;
10916 /* Record Rn also as it changes. */
10917 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10918 arm_insn_r
->reg_rec_count
= 1;
10920 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10921 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10923 /* 4) Store, register pre-indexed. */
10924 /* 6) Store, register post -indexed. */
10925 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10926 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10927 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10928 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10929 /* Calculate target store address, Rn +/- Rm, register offset. */
10930 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10932 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10936 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10938 if (ARM_RECORD_STRH
== str_type
)
10940 record_buf_mem
[0] = 2;
10941 record_buf_mem
[1] = tgt_mem_addr
;
10942 arm_insn_r
->mem_rec_count
= 1;
10944 else if (ARM_RECORD_STRD
== str_type
)
10946 record_buf_mem
[0] = 4;
10947 record_buf_mem
[1] = tgt_mem_addr
;
10948 record_buf_mem
[2] = 4;
10949 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10950 arm_insn_r
->mem_rec_count
= 2;
10952 /* Record Rn also as it changes. */
10953 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10954 arm_insn_r
->reg_rec_count
= 1;
10959 /* Handling ARM extension space insns. */
10962 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10964 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10965 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10966 uint32_t record_buf
[8], record_buf_mem
[8];
10967 uint32_t reg_src1
= 0;
10968 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10969 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10970 ULONGEST u_regval
= 0;
10972 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10973 /* Handle unconditional insn extension space. */
10975 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10976 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10977 if (arm_insn_r
->cond
)
10979 /* PLD has no affect on architectural state, it just affects
10981 if (5 == ((opcode1
& 0xE0) >> 5))
10984 record_buf
[0] = ARM_PS_REGNUM
;
10985 record_buf
[1] = ARM_LR_REGNUM
;
10986 arm_insn_r
->reg_rec_count
= 2;
10988 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10992 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10993 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10996 /* Undefined instruction on ARM V5; need to handle if later
10997 versions define it. */
11000 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
11001 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
11002 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11004 /* Handle arithmetic insn extension space. */
11005 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
11006 && !INSN_RECORDED(arm_insn_r
))
11008 /* Handle MLA(S) and MUL(S). */
11009 if (0 <= insn_op1
&& 3 >= insn_op1
)
11011 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11012 record_buf
[1] = ARM_PS_REGNUM
;
11013 arm_insn_r
->reg_rec_count
= 2;
11015 else if (4 <= insn_op1
&& 15 >= insn_op1
)
11017 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
11018 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11019 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11020 record_buf
[2] = ARM_PS_REGNUM
;
11021 arm_insn_r
->reg_rec_count
= 3;
11025 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
11026 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
11027 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
11029 /* Handle control insn extension space. */
11031 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
11032 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
11034 if (!bit (arm_insn_r
->arm_insn
,25))
11036 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
11038 if ((0 == insn_op1
) || (2 == insn_op1
))
11041 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11042 arm_insn_r
->reg_rec_count
= 1;
11044 else if (1 == insn_op1
)
11046 /* CSPR is going to be changed. */
11047 record_buf
[0] = ARM_PS_REGNUM
;
11048 arm_insn_r
->reg_rec_count
= 1;
11050 else if (3 == insn_op1
)
11052 /* SPSR is going to be changed. */
11053 /* We need to get SPSR value, which is yet to be done. */
11054 printf_unfiltered (_("Process record does not support "
11055 "instruction 0x%0x at address %s.\n"),
11056 arm_insn_r
->arm_insn
,
11057 paddress (arm_insn_r
->gdbarch
,
11058 arm_insn_r
->this_addr
));
11062 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
11067 record_buf
[0] = ARM_PS_REGNUM
;
11068 arm_insn_r
->reg_rec_count
= 1;
11070 else if (3 == insn_op1
)
11073 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11074 arm_insn_r
->reg_rec_count
= 1;
11077 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
11080 record_buf
[0] = ARM_PS_REGNUM
;
11081 record_buf
[1] = ARM_LR_REGNUM
;
11082 arm_insn_r
->reg_rec_count
= 2;
11084 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
11086 /* QADD, QSUB, QDADD, QDSUB */
11087 record_buf
[0] = ARM_PS_REGNUM
;
11088 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11089 arm_insn_r
->reg_rec_count
= 2;
11091 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
11094 record_buf
[0] = ARM_PS_REGNUM
;
11095 record_buf
[1] = ARM_LR_REGNUM
;
11096 arm_insn_r
->reg_rec_count
= 2;
11098 /* Save SPSR also;how? */
11099 printf_unfiltered (_("Process record does not support "
11100 "instruction 0x%0x at address %s.\n"),
11101 arm_insn_r
->arm_insn
,
11102 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11105 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
11106 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
11107 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
11108 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11111 if (0 == insn_op1
|| 1 == insn_op1
)
11113 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11114 /* We dont do optimization for SMULW<y> where we
11116 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11117 record_buf
[1] = ARM_PS_REGNUM
;
11118 arm_insn_r
->reg_rec_count
= 2;
11120 else if (2 == insn_op1
)
11123 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11124 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11125 arm_insn_r
->reg_rec_count
= 2;
11127 else if (3 == insn_op1
)
11130 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11131 arm_insn_r
->reg_rec_count
= 1;
11137 /* MSR : immediate form. */
11140 /* CSPR is going to be changed. */
11141 record_buf
[0] = ARM_PS_REGNUM
;
11142 arm_insn_r
->reg_rec_count
= 1;
11144 else if (3 == insn_op1
)
11146 /* SPSR is going to be changed. */
11147 /* we need to get SPSR value, which is yet to be done */
11148 printf_unfiltered (_("Process record does not support "
11149 "instruction 0x%0x at address %s.\n"),
11150 arm_insn_r
->arm_insn
,
11151 paddress (arm_insn_r
->gdbarch
,
11152 arm_insn_r
->this_addr
));
11158 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11159 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11160 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11162 /* Handle load/store insn extension space. */
11164 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11165 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11166 && !INSN_RECORDED(arm_insn_r
))
11171 /* These insn, changes register and memory as well. */
11172 /* SWP or SWPB insn. */
11173 /* Get memory address given by Rn. */
11174 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11175 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11176 /* SWP insn ?, swaps word. */
11177 if (8 == arm_insn_r
->opcode
)
11179 record_buf_mem
[0] = 4;
11183 /* SWPB insn, swaps only byte. */
11184 record_buf_mem
[0] = 1;
11186 record_buf_mem
[1] = u_regval
;
11187 arm_insn_r
->mem_rec_count
= 1;
11188 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11189 arm_insn_r
->reg_rec_count
= 1;
11191 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11194 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11197 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11200 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11201 record_buf
[1] = record_buf
[0] + 1;
11202 arm_insn_r
->reg_rec_count
= 2;
11204 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11207 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11210 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11212 /* LDRH, LDRSB, LDRSH. */
11213 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11214 arm_insn_r
->reg_rec_count
= 1;
11219 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11220 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11221 && !INSN_RECORDED(arm_insn_r
))
11224 /* Handle coprocessor insn extension space. */
11227 /* To be done for ARMv5 and later; as of now we return -1. */
11229 printf_unfiltered (_("Process record does not support instruction x%0x "
11230 "at address %s.\n"),arm_insn_r
->arm_insn
,
11231 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11234 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11235 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11240 /* Handling opcode 000 insns. */
11243 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11245 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11246 uint32_t record_buf
[8], record_buf_mem
[8];
11247 ULONGEST u_regval
[2] = {0};
11249 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11250 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11251 uint32_t opcode1
= 0;
11253 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11254 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11255 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11257 /* Data processing insn /multiply insn. */
11258 if (9 == arm_insn_r
->decode
11259 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11260 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11262 /* Handle multiply instructions. */
11263 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11264 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11266 /* Handle MLA and MUL. */
11267 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11268 record_buf
[1] = ARM_PS_REGNUM
;
11269 arm_insn_r
->reg_rec_count
= 2;
11271 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11273 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11274 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11275 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11276 record_buf
[2] = ARM_PS_REGNUM
;
11277 arm_insn_r
->reg_rec_count
= 3;
11280 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11281 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11283 /* Handle misc load insns, as 20th bit (L = 1). */
11284 /* LDR insn has a capability to do branching, if
11285 MOV LR, PC is precceded by LDR insn having Rn as R15
11286 in that case, it emulates branch and link insn, and hence we
11287 need to save CSPR and PC as well. I am not sure this is right
11288 place; as opcode = 010 LDR insn make this happen, if R15 was
11290 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11291 if (15 != reg_dest
)
11293 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11294 arm_insn_r
->reg_rec_count
= 1;
11298 record_buf
[0] = reg_dest
;
11299 record_buf
[1] = ARM_PS_REGNUM
;
11300 arm_insn_r
->reg_rec_count
= 2;
11303 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11304 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11305 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11306 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11308 /* Handle MSR insn. */
11309 if (9 == arm_insn_r
->opcode
)
11311 /* CSPR is going to be changed. */
11312 record_buf
[0] = ARM_PS_REGNUM
;
11313 arm_insn_r
->reg_rec_count
= 1;
11317 /* SPSR is going to be changed. */
11318 /* How to read SPSR value? */
11319 printf_unfiltered (_("Process record does not support instruction "
11320 "0x%0x at address %s.\n"),
11321 arm_insn_r
->arm_insn
,
11322 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11326 else if (9 == arm_insn_r
->decode
11327 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11328 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11330 /* Handling SWP, SWPB. */
11331 /* These insn, changes register and memory as well. */
11332 /* SWP or SWPB insn. */
11334 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11335 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11336 /* SWP insn ?, swaps word. */
11337 if (8 == arm_insn_r
->opcode
)
11339 record_buf_mem
[0] = 4;
11343 /* SWPB insn, swaps only byte. */
11344 record_buf_mem
[0] = 1;
11346 record_buf_mem
[1] = u_regval
[0];
11347 arm_insn_r
->mem_rec_count
= 1;
11348 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11349 arm_insn_r
->reg_rec_count
= 1;
11351 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11352 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11354 /* Handle BLX, branch and link/exchange. */
11355 if (9 == arm_insn_r
->opcode
)
11357 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11358 and R14 stores the return address. */
11359 record_buf
[0] = ARM_PS_REGNUM
;
11360 record_buf
[1] = ARM_LR_REGNUM
;
11361 arm_insn_r
->reg_rec_count
= 2;
11364 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11366 /* Handle enhanced software breakpoint insn, BKPT. */
11367 /* CPSR is changed to be executed in ARM state, disabling normal
11368 interrupts, entering abort mode. */
11369 /* According to high vector configuration PC is set. */
11370 /* user hit breakpoint and type reverse, in
11371 that case, we need to go back with previous CPSR and
11372 Program Counter. */
11373 record_buf
[0] = ARM_PS_REGNUM
;
11374 record_buf
[1] = ARM_LR_REGNUM
;
11375 arm_insn_r
->reg_rec_count
= 2;
11377 /* Save SPSR also; how? */
11378 printf_unfiltered (_("Process record does not support instruction "
11379 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11380 paddress (arm_insn_r
->gdbarch
,
11381 arm_insn_r
->this_addr
));
11384 else if (11 == arm_insn_r
->decode
11385 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11387 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11389 /* Handle str(x) insn */
11390 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11393 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11394 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11396 /* Handle BX, branch and link/exchange. */
11397 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11398 record_buf
[0] = ARM_PS_REGNUM
;
11399 arm_insn_r
->reg_rec_count
= 1;
11401 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11402 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11403 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11405 /* Count leading zeros: CLZ. */
11406 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11407 arm_insn_r
->reg_rec_count
= 1;
11409 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11410 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11411 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11412 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11415 /* Handle MRS insn. */
11416 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11417 arm_insn_r
->reg_rec_count
= 1;
11419 else if (arm_insn_r
->opcode
<= 15)
11421 /* Normal data processing insns. */
11422 /* Out of 11 shifter operands mode, all the insn modifies destination
11423 register, which is specified by 13-16 decode. */
11424 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11425 record_buf
[1] = ARM_PS_REGNUM
;
11426 arm_insn_r
->reg_rec_count
= 2;
11433 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11434 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11438 /* Handling opcode 001 insns. */
11441 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11443 uint32_t record_buf
[8], record_buf_mem
[8];
11445 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11446 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11448 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11449 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11450 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11453 /* Handle MSR insn. */
11454 if (9 == arm_insn_r
->opcode
)
11456 /* CSPR is going to be changed. */
11457 record_buf
[0] = ARM_PS_REGNUM
;
11458 arm_insn_r
->reg_rec_count
= 1;
11462 /* SPSR is going to be changed. */
11465 else if (arm_insn_r
->opcode
<= 15)
11467 /* Normal data processing insns. */
11468 /* Out of 11 shifter operands mode, all the insn modifies destination
11469 register, which is specified by 13-16 decode. */
11470 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11471 record_buf
[1] = ARM_PS_REGNUM
;
11472 arm_insn_r
->reg_rec_count
= 2;
11479 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11480 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11484 /* Handle ARM mode instructions with opcode 010. */
11487 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11489 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11491 uint32_t reg_base
, reg_dest
;
11492 uint32_t offset_12
, tgt_mem_addr
;
11493 uint32_t record_buf
[8], record_buf_mem
[8];
11494 unsigned char wback
;
11497 /* Calculate wback. */
11498 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
11499 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
11501 arm_insn_r
->reg_rec_count
= 0;
11502 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11504 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11506 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11509 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11510 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
11512 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11513 preceeds a LDR instruction having R15 as reg_base, it
11514 emulates a branch and link instruction, and hence we need to save
11515 CPSR and PC as well. */
11516 if (ARM_PC_REGNUM
== reg_dest
)
11517 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11519 /* If wback is true, also save the base register, which is going to be
11522 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11526 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11528 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11529 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11531 /* Handle bit U. */
11532 if (bit (arm_insn_r
->arm_insn
, 23))
11534 /* U == 1: Add the offset. */
11535 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
11539 /* U == 0: subtract the offset. */
11540 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
11543 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11545 if (bit (arm_insn_r
->arm_insn
, 22))
11547 /* STRB and STRBT: 1 byte. */
11548 record_buf_mem
[0] = 1;
11552 /* STR and STRT: 4 bytes. */
11553 record_buf_mem
[0] = 4;
11556 /* Handle bit P. */
11557 if (bit (arm_insn_r
->arm_insn
, 24))
11558 record_buf_mem
[1] = tgt_mem_addr
;
11560 record_buf_mem
[1] = (uint32_t) u_regval
;
11562 arm_insn_r
->mem_rec_count
= 1;
11564 /* If wback is true, also save the base register, which is going to be
11567 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11570 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11571 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11575 /* Handling opcode 011 insns. */
11578 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11580 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11582 uint32_t shift_imm
= 0;
11583 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11584 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11585 uint32_t record_buf
[8], record_buf_mem
[8];
11588 ULONGEST u_regval
[2];
11590 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11591 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11593 /* Handle enhanced store insns and LDRD DSP insn,
11594 order begins according to addressing modes for store insns
11598 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11600 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11601 /* LDR insn has a capability to do branching, if
11602 MOV LR, PC is precedded by LDR insn having Rn as R15
11603 in that case, it emulates branch and link insn, and hence we
11604 need to save CSPR and PC as well. */
11605 if (15 != reg_dest
)
11607 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11608 arm_insn_r
->reg_rec_count
= 1;
11612 record_buf
[0] = reg_dest
;
11613 record_buf
[1] = ARM_PS_REGNUM
;
11614 arm_insn_r
->reg_rec_count
= 2;
11619 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11621 /* Store insn, register offset and register pre-indexed,
11622 register post-indexed. */
11624 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11626 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11627 regcache_raw_read_unsigned (reg_cache
, reg_src1
11629 regcache_raw_read_unsigned (reg_cache
, reg_src2
11631 if (15 == reg_src2
)
11633 /* If R15 was used as Rn, hence current PC+8. */
11634 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11635 u_regval
[0] = u_regval
[0] + 8;
11637 /* Calculate target store address, Rn +/- Rm, register offset. */
11639 if (bit (arm_insn_r
->arm_insn
, 23))
11641 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11645 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11648 switch (arm_insn_r
->opcode
)
11662 record_buf_mem
[0] = 4;
11677 record_buf_mem
[0] = 1;
11681 gdb_assert_not_reached ("no decoding pattern found");
11684 record_buf_mem
[1] = tgt_mem_addr
;
11685 arm_insn_r
->mem_rec_count
= 1;
11687 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11688 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11689 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11690 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11691 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11692 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11695 /* Rn is going to be changed in pre-indexed mode and
11696 post-indexed mode as well. */
11697 record_buf
[0] = reg_src2
;
11698 arm_insn_r
->reg_rec_count
= 1;
11703 /* Store insn, scaled register offset; scaled pre-indexed. */
11704 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11706 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11708 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11709 /* Get shift_imm. */
11710 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11711 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11712 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11713 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11714 /* Offset_12 used as shift. */
11718 /* Offset_12 used as index. */
11719 offset_12
= u_regval
[0] << shift_imm
;
11723 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11729 if (bit (u_regval
[0], 31))
11731 offset_12
= 0xFFFFFFFF;
11740 /* This is arithmetic shift. */
11741 offset_12
= s_word
>> shift_imm
;
11748 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11750 /* Get C flag value and shift it by 31. */
11751 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11752 | (u_regval
[0]) >> 1);
11756 offset_12
= (u_regval
[0] >> shift_imm
) \
11758 (sizeof(uint32_t) - shift_imm
));
11763 gdb_assert_not_reached ("no decoding pattern found");
11767 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11769 if (bit (arm_insn_r
->arm_insn
, 23))
11771 tgt_mem_addr
= u_regval
[1] + offset_12
;
11775 tgt_mem_addr
= u_regval
[1] - offset_12
;
11778 switch (arm_insn_r
->opcode
)
11792 record_buf_mem
[0] = 4;
11807 record_buf_mem
[0] = 1;
11811 gdb_assert_not_reached ("no decoding pattern found");
11814 record_buf_mem
[1] = tgt_mem_addr
;
11815 arm_insn_r
->mem_rec_count
= 1;
11817 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11818 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11819 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11820 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11821 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11822 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11825 /* Rn is going to be changed in register scaled pre-indexed
11826 mode,and scaled post indexed mode. */
11827 record_buf
[0] = reg_src2
;
11828 arm_insn_r
->reg_rec_count
= 1;
11833 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11834 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11838 /* Handle ARM mode instructions with opcode 100. */
11841 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11843 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11844 uint32_t register_count
= 0, register_bits
;
11845 uint32_t reg_base
, addr_mode
;
11846 uint32_t record_buf
[24], record_buf_mem
[48];
11850 /* Fetch the list of registers. */
11851 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11852 arm_insn_r
->reg_rec_count
= 0;
11854 /* Fetch the base register that contains the address we are loading data
11856 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11858 /* Calculate wback. */
11859 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11861 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11863 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11865 /* Find out which registers are going to be loaded from memory. */
11866 while (register_bits
)
11868 if (register_bits
& 0x00000001)
11869 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11870 register_bits
= register_bits
>> 1;
11875 /* If wback is true, also save the base register, which is going to be
11878 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11880 /* Save the CPSR register. */
11881 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11885 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11887 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11889 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11891 /* Find out how many registers are going to be stored to memory. */
11892 while (register_bits
)
11894 if (register_bits
& 0x00000001)
11896 register_bits
= register_bits
>> 1;
11901 /* STMDA (STMED): Decrement after. */
11903 record_buf_mem
[1] = (uint32_t) u_regval
11904 - register_count
* INT_REGISTER_SIZE
+ 4;
11906 /* STM (STMIA, STMEA): Increment after. */
11908 record_buf_mem
[1] = (uint32_t) u_regval
;
11910 /* STMDB (STMFD): Decrement before. */
11912 record_buf_mem
[1] = (uint32_t) u_regval
11913 - register_count
* INT_REGISTER_SIZE
;
11915 /* STMIB (STMFA): Increment before. */
11917 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11920 gdb_assert_not_reached ("no decoding pattern found");
11924 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11925 arm_insn_r
->mem_rec_count
= 1;
11927 /* If wback is true, also save the base register, which is going to be
11930 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11933 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11934 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11938 /* Handling opcode 101 insns. */
11941 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11943 uint32_t record_buf
[8];
11945 /* Handle B, BL, BLX(1) insns. */
11946 /* B simply branches so we do nothing here. */
11947 /* Note: BLX(1) doesnt fall here but instead it falls into
11948 extension space. */
11949 if (bit (arm_insn_r
->arm_insn
, 24))
11951 record_buf
[0] = ARM_LR_REGNUM
;
11952 arm_insn_r
->reg_rec_count
= 1;
11955 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11960 /* Handling opcode 110 insns. */
11963 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11965 printf_unfiltered (_("Process record does not support instruction "
11966 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11967 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11972 /* Record handler for vector data transfer instructions. */
11975 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11977 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11978 uint32_t record_buf
[4];
11980 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11981 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11982 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11983 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11984 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11985 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11987 /* Handle VMOV instruction. */
11988 if (bit_l
&& bit_c
)
11990 record_buf
[0] = reg_t
;
11991 arm_insn_r
->reg_rec_count
= 1;
11993 else if (bit_l
&& !bit_c
)
11995 /* Handle VMOV instruction. */
11996 if (bits_a
== 0x00)
11998 if (bit (arm_insn_r
->arm_insn
, 20))
11999 record_buf
[0] = reg_t
;
12001 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12004 arm_insn_r
->reg_rec_count
= 1;
12006 /* Handle VMRS instruction. */
12007 else if (bits_a
== 0x07)
12010 reg_t
= ARM_PS_REGNUM
;
12012 record_buf
[0] = reg_t
;
12013 arm_insn_r
->reg_rec_count
= 1;
12016 else if (!bit_l
&& !bit_c
)
12018 /* Handle VMOV instruction. */
12019 if (bits_a
== 0x00)
12021 if (bit (arm_insn_r
->arm_insn
, 20))
12022 record_buf
[0] = reg_t
;
12024 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12027 arm_insn_r
->reg_rec_count
= 1;
12029 /* Handle VMSR instruction. */
12030 else if (bits_a
== 0x07)
12032 record_buf
[0] = ARM_FPSCR_REGNUM
;
12033 arm_insn_r
->reg_rec_count
= 1;
12036 else if (!bit_l
&& bit_c
)
12038 /* Handle VMOV instruction. */
12039 if (!(bits_a
& 0x04))
12041 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
12043 arm_insn_r
->reg_rec_count
= 1;
12045 /* Handle VDUP instruction. */
12048 if (bit (arm_insn_r
->arm_insn
, 21))
12050 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12051 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12052 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
12053 arm_insn_r
->reg_rec_count
= 2;
12057 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12058 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12059 arm_insn_r
->reg_rec_count
= 1;
12064 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12068 /* Record handler for extension register load/store instructions. */
12071 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
12073 uint32_t opcode
, single_reg
;
12074 uint8_t op_vldm_vstm
;
12075 uint32_t record_buf
[8], record_buf_mem
[128];
12076 ULONGEST u_regval
= 0;
12078 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12079 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
12081 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
12082 single_reg
= bit (arm_insn_r
->arm_insn
, 8);
12083 op_vldm_vstm
= opcode
& 0x1b;
12085 /* Handle VMOV instructions. */
12086 if ((opcode
& 0x1e) == 0x04)
12088 if (bit (arm_insn_r
->arm_insn
, 4))
12090 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12091 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12092 arm_insn_r
->reg_rec_count
= 2;
12096 uint8_t reg_m
= (bits (arm_insn_r
->arm_insn
, 0, 3) << 1)
12097 | bit (arm_insn_r
->arm_insn
, 5);
12101 record_buf
[0] = num_regs
+ reg_m
;
12102 record_buf
[1] = num_regs
+ reg_m
+ 1;
12103 arm_insn_r
->reg_rec_count
= 2;
12107 record_buf
[0] = reg_m
+ ARM_D0_REGNUM
;
12108 arm_insn_r
->reg_rec_count
= 1;
12112 /* Handle VSTM and VPUSH instructions. */
12113 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
12114 || op_vldm_vstm
== 0x12)
12116 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12117 uint32_t memory_index
= 0;
12119 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12120 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12121 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12122 imm_off32
= imm_off8
<< 24;
12123 memory_count
= imm_off8
;
12125 if (bit (arm_insn_r
->arm_insn
, 23))
12126 start_address
= u_regval
;
12128 start_address
= u_regval
- imm_off32
;
12130 if (bit (arm_insn_r
->arm_insn
, 21))
12132 record_buf
[0] = reg_rn
;
12133 arm_insn_r
->reg_rec_count
= 1;
12136 while (memory_count
> 0)
12140 record_buf_mem
[memory_index
] = start_address
;
12141 record_buf_mem
[memory_index
+ 1] = 4;
12142 start_address
= start_address
+ 4;
12143 memory_index
= memory_index
+ 2;
12147 record_buf_mem
[memory_index
] = start_address
;
12148 record_buf_mem
[memory_index
+ 1] = 4;
12149 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12150 record_buf_mem
[memory_index
+ 3] = 4;
12151 start_address
= start_address
+ 8;
12152 memory_index
= memory_index
+ 4;
12156 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
12158 /* Handle VLDM instructions. */
12159 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
12160 || op_vldm_vstm
== 0x13)
12162 uint32_t reg_count
, reg_vd
;
12163 uint32_t reg_index
= 0;
12165 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12166 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
12169 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12171 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12173 if (bit (arm_insn_r
->arm_insn
, 21))
12174 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
12176 while (reg_count
> 0)
12179 record_buf
[reg_index
++] = num_regs
+ reg_vd
+ reg_count
- 1;
12181 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
12185 arm_insn_r
->reg_rec_count
= reg_index
;
12187 /* VSTR Vector store register. */
12188 else if ((opcode
& 0x13) == 0x10)
12190 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12191 uint32_t memory_index
= 0;
12193 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12194 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12195 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12196 imm_off32
= imm_off8
<< 24;
12197 memory_count
= imm_off8
;
12199 if (bit (arm_insn_r
->arm_insn
, 23))
12200 start_address
= u_regval
+ imm_off32
;
12202 start_address
= u_regval
- imm_off32
;
12206 record_buf_mem
[memory_index
] = start_address
;
12207 record_buf_mem
[memory_index
+ 1] = 4;
12208 arm_insn_r
->mem_rec_count
= 1;
12212 record_buf_mem
[memory_index
] = start_address
;
12213 record_buf_mem
[memory_index
+ 1] = 4;
12214 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12215 record_buf_mem
[memory_index
+ 3] = 4;
12216 arm_insn_r
->mem_rec_count
= 2;
12219 /* VLDR Vector load register. */
12220 else if ((opcode
& 0x13) == 0x11)
12222 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12226 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12227 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
12231 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12232 record_buf
[0] = num_regs
+ reg_vd
;
12234 arm_insn_r
->reg_rec_count
= 1;
12237 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12238 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12242 /* Record handler for arm/thumb mode VFP data processing instructions. */
12245 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
12247 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
12248 uint32_t record_buf
[4];
12249 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
12250 enum insn_types curr_insn_type
= INSN_INV
;
12252 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12253 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
12254 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
12255 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
12256 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
12257 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12258 opc1
= opc1
& 0x04;
12260 /* Handle VMLA, VMLS. */
12263 if (bit (arm_insn_r
->arm_insn
, 10))
12265 if (bit (arm_insn_r
->arm_insn
, 6))
12266 curr_insn_type
= INSN_T0
;
12268 curr_insn_type
= INSN_T1
;
12273 curr_insn_type
= INSN_T1
;
12275 curr_insn_type
= INSN_T2
;
12278 /* Handle VNMLA, VNMLS, VNMUL. */
12279 else if (opc1
== 0x01)
12282 curr_insn_type
= INSN_T1
;
12284 curr_insn_type
= INSN_T2
;
12287 else if (opc1
== 0x02 && !(opc3
& 0x01))
12289 if (bit (arm_insn_r
->arm_insn
, 10))
12291 if (bit (arm_insn_r
->arm_insn
, 6))
12292 curr_insn_type
= INSN_T0
;
12294 curr_insn_type
= INSN_T1
;
12299 curr_insn_type
= INSN_T1
;
12301 curr_insn_type
= INSN_T2
;
12304 /* Handle VADD, VSUB. */
12305 else if (opc1
== 0x03)
12307 if (!bit (arm_insn_r
->arm_insn
, 9))
12309 if (bit (arm_insn_r
->arm_insn
, 6))
12310 curr_insn_type
= INSN_T0
;
12312 curr_insn_type
= INSN_T1
;
12317 curr_insn_type
= INSN_T1
;
12319 curr_insn_type
= INSN_T2
;
12323 else if (opc1
== 0x0b)
12326 curr_insn_type
= INSN_T1
;
12328 curr_insn_type
= INSN_T2
;
12330 /* Handle all other vfp data processing instructions. */
12331 else if (opc1
== 0x0b)
12334 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
12336 if (bit (arm_insn_r
->arm_insn
, 4))
12338 if (bit (arm_insn_r
->arm_insn
, 6))
12339 curr_insn_type
= INSN_T0
;
12341 curr_insn_type
= INSN_T1
;
12346 curr_insn_type
= INSN_T1
;
12348 curr_insn_type
= INSN_T2
;
12351 /* Handle VNEG and VABS. */
12352 else if ((opc2
== 0x01 && opc3
== 0x01)
12353 || (opc2
== 0x00 && opc3
== 0x03))
12355 if (!bit (arm_insn_r
->arm_insn
, 11))
12357 if (bit (arm_insn_r
->arm_insn
, 6))
12358 curr_insn_type
= INSN_T0
;
12360 curr_insn_type
= INSN_T1
;
12365 curr_insn_type
= INSN_T1
;
12367 curr_insn_type
= INSN_T2
;
12370 /* Handle VSQRT. */
12371 else if (opc2
== 0x01 && opc3
== 0x03)
12374 curr_insn_type
= INSN_T1
;
12376 curr_insn_type
= INSN_T2
;
12379 else if (opc2
== 0x07 && opc3
== 0x03)
12382 curr_insn_type
= INSN_T1
;
12384 curr_insn_type
= INSN_T2
;
12386 else if (opc3
& 0x01)
12389 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
12391 if (!bit (arm_insn_r
->arm_insn
, 18))
12392 curr_insn_type
= INSN_T2
;
12396 curr_insn_type
= INSN_T1
;
12398 curr_insn_type
= INSN_T2
;
12402 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
12405 curr_insn_type
= INSN_T1
;
12407 curr_insn_type
= INSN_T2
;
12409 /* Handle VCVTB, VCVTT. */
12410 else if ((opc2
& 0x0e) == 0x02)
12411 curr_insn_type
= INSN_T2
;
12412 /* Handle VCMP, VCMPE. */
12413 else if ((opc2
& 0x0e) == 0x04)
12414 curr_insn_type
= INSN_T3
;
12418 switch (curr_insn_type
)
12421 reg_vd
= reg_vd
| (bit_d
<< 4);
12422 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12423 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
12424 arm_insn_r
->reg_rec_count
= 2;
12428 reg_vd
= reg_vd
| (bit_d
<< 4);
12429 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12430 arm_insn_r
->reg_rec_count
= 1;
12434 reg_vd
= (reg_vd
<< 1) | bit_d
;
12435 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12436 arm_insn_r
->reg_rec_count
= 1;
12440 record_buf
[0] = ARM_FPSCR_REGNUM
;
12441 arm_insn_r
->reg_rec_count
= 1;
12445 gdb_assert_not_reached ("no decoding pattern found");
12449 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12453 /* Handling opcode 110 insns. */
12456 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
12458 uint32_t op
, op1
, op1_sbit
, op1_ebit
, coproc
;
12460 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12461 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12462 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12464 if ((coproc
& 0x0e) == 0x0a)
12466 /* Handle extension register ld/st instructions. */
12468 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12470 /* 64-bit transfers between arm core and extension registers. */
12471 if ((op1
& 0x3e) == 0x04)
12472 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12476 /* Handle coprocessor ld/st instructions. */
12481 return arm_record_unsupported_insn (arm_insn_r
);
12484 return arm_record_unsupported_insn (arm_insn_r
);
12487 /* Move to coprocessor from two arm core registers. */
12489 return arm_record_unsupported_insn (arm_insn_r
);
12491 /* Move to two arm core registers from coprocessor. */
12496 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12497 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12498 arm_insn_r
->reg_rec_count
= 2;
12500 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
12504 return arm_record_unsupported_insn (arm_insn_r
);
12507 /* Handling opcode 111 insns. */
12510 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
12512 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
12513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
12514 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12515 ULONGEST u_regval
= 0;
12517 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
12518 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12519 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
12520 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12521 op
= bit (arm_insn_r
->arm_insn
, 4);
12523 /* Handle arm SWI/SVC system call instructions. */
12526 if (tdep
->arm_syscall_record
!= NULL
)
12528 ULONGEST svc_operand
, svc_number
;
12530 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
12532 if (svc_operand
) /* OABI. */
12533 svc_number
= svc_operand
- 0x900000;
12535 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
12537 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
12541 printf_unfiltered (_("no syscall record support\n"));
12546 if ((coproc
& 0x0e) == 0x0a)
12548 /* VFP data-processing instructions. */
12549 if (!op1_sbit
&& !op
)
12550 return arm_record_vfp_data_proc_insn (arm_insn_r
);
12552 /* Advanced SIMD, VFP instructions. */
12553 if (!op1_sbit
&& op
)
12554 return arm_record_vdata_transfer_insn (arm_insn_r
);
12558 /* Coprocessor data operations. */
12559 if (!op1_sbit
&& !op
)
12560 return arm_record_unsupported_insn (arm_insn_r
);
12562 /* Move to Coprocessor from ARM core register. */
12563 if (!op1_sbit
&& !op1_ebit
&& op
)
12564 return arm_record_unsupported_insn (arm_insn_r
);
12566 /* Move to arm core register from coprocessor. */
12567 if (!op1_sbit
&& op1_ebit
&& op
)
12569 uint32_t record_buf
[1];
12571 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12572 if (record_buf
[0] == 15)
12573 record_buf
[0] = ARM_PS_REGNUM
;
12575 arm_insn_r
->reg_rec_count
= 1;
12576 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
12582 return arm_record_unsupported_insn (arm_insn_r
);
12585 /* Handling opcode 000 insns. */
12588 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
12590 uint32_t record_buf
[8];
12591 uint32_t reg_src1
= 0;
12593 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12595 record_buf
[0] = ARM_PS_REGNUM
;
12596 record_buf
[1] = reg_src1
;
12597 thumb_insn_r
->reg_rec_count
= 2;
12599 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12605 /* Handling opcode 001 insns. */
12608 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
12610 uint32_t record_buf
[8];
12611 uint32_t reg_src1
= 0;
12613 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12615 record_buf
[0] = ARM_PS_REGNUM
;
12616 record_buf
[1] = reg_src1
;
12617 thumb_insn_r
->reg_rec_count
= 2;
12619 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12624 /* Handling opcode 010 insns. */
12627 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12629 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12630 uint32_t record_buf
[8], record_buf_mem
[8];
12632 uint32_t reg_src1
= 0, reg_src2
= 0;
12633 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12635 ULONGEST u_regval
[2] = {0};
12637 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12639 if (bit (thumb_insn_r
->arm_insn
, 12))
12641 /* Handle load/store register offset. */
12642 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
12643 if (opcode2
>= 12 && opcode2
<= 15)
12645 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12646 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12647 record_buf
[0] = reg_src1
;
12648 thumb_insn_r
->reg_rec_count
= 1;
12650 else if (opcode2
>= 8 && opcode2
<= 10)
12652 /* STR(2), STRB(2), STRH(2) . */
12653 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12654 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12655 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12656 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12658 record_buf_mem
[0] = 4; /* STR (2). */
12659 else if (10 == opcode2
)
12660 record_buf_mem
[0] = 1; /* STRB (2). */
12661 else if (9 == opcode2
)
12662 record_buf_mem
[0] = 2; /* STRH (2). */
12663 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12664 thumb_insn_r
->mem_rec_count
= 1;
12667 else if (bit (thumb_insn_r
->arm_insn
, 11))
12669 /* Handle load from literal pool. */
12671 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12672 record_buf
[0] = reg_src1
;
12673 thumb_insn_r
->reg_rec_count
= 1;
12677 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12678 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12679 if ((3 == opcode2
) && (!opcode3
))
12681 /* Branch with exchange. */
12682 record_buf
[0] = ARM_PS_REGNUM
;
12683 thumb_insn_r
->reg_rec_count
= 1;
12687 /* Format 8; special data processing insns. */
12688 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12689 record_buf
[0] = ARM_PS_REGNUM
;
12690 record_buf
[1] = reg_src1
;
12691 thumb_insn_r
->reg_rec_count
= 2;
12696 /* Format 5; data processing insns. */
12697 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12698 if (bit (thumb_insn_r
->arm_insn
, 7))
12700 reg_src1
= reg_src1
+ 8;
12702 record_buf
[0] = ARM_PS_REGNUM
;
12703 record_buf
[1] = reg_src1
;
12704 thumb_insn_r
->reg_rec_count
= 2;
12707 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12708 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12714 /* Handling opcode 001 insns. */
12717 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12719 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12720 uint32_t record_buf
[8], record_buf_mem
[8];
12722 uint32_t reg_src1
= 0;
12723 uint32_t opcode
= 0, immed_5
= 0;
12725 ULONGEST u_regval
= 0;
12727 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12732 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12733 record_buf
[0] = reg_src1
;
12734 thumb_insn_r
->reg_rec_count
= 1;
12739 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12740 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12741 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12742 record_buf_mem
[0] = 4;
12743 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12744 thumb_insn_r
->mem_rec_count
= 1;
12747 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12748 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12754 /* Handling opcode 100 insns. */
12757 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12759 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12760 uint32_t record_buf
[8], record_buf_mem
[8];
12762 uint32_t reg_src1
= 0;
12763 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12765 ULONGEST u_regval
= 0;
12767 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12772 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12773 record_buf
[0] = reg_src1
;
12774 thumb_insn_r
->reg_rec_count
= 1;
12776 else if (1 == opcode
)
12779 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12780 record_buf
[0] = reg_src1
;
12781 thumb_insn_r
->reg_rec_count
= 1;
12783 else if (2 == opcode
)
12786 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12787 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12788 record_buf_mem
[0] = 4;
12789 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12790 thumb_insn_r
->mem_rec_count
= 1;
12792 else if (0 == opcode
)
12795 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12796 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12797 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12798 record_buf_mem
[0] = 2;
12799 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12800 thumb_insn_r
->mem_rec_count
= 1;
12803 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12804 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12810 /* Handling opcode 101 insns. */
12813 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12815 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12817 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12818 uint32_t register_bits
= 0, register_count
= 0;
12819 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12820 uint32_t record_buf
[24], record_buf_mem
[48];
12823 ULONGEST u_regval
= 0;
12825 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12826 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12827 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12832 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12833 while (register_bits
)
12835 if (register_bits
& 0x00000001)
12836 record_buf
[index
++] = register_count
;
12837 register_bits
= register_bits
>> 1;
12840 record_buf
[index
++] = ARM_PS_REGNUM
;
12841 record_buf
[index
++] = ARM_SP_REGNUM
;
12842 thumb_insn_r
->reg_rec_count
= index
;
12844 else if (10 == opcode2
)
12847 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12848 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12849 while (register_bits
)
12851 if (register_bits
& 0x00000001)
12853 register_bits
= register_bits
>> 1;
12855 start_address
= u_regval
- \
12856 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12857 thumb_insn_r
->mem_rec_count
= register_count
;
12858 while (register_count
)
12860 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12861 record_buf_mem
[(register_count
* 2) - 2] = 4;
12862 start_address
= start_address
+ 4;
12865 record_buf
[0] = ARM_SP_REGNUM
;
12866 thumb_insn_r
->reg_rec_count
= 1;
12868 else if (0x1E == opcode1
)
12871 /* Handle enhanced software breakpoint insn, BKPT. */
12872 /* CPSR is changed to be executed in ARM state, disabling normal
12873 interrupts, entering abort mode. */
12874 /* According to high vector configuration PC is set. */
12875 /* User hits breakpoint and type reverse, in that case, we need to go back with
12876 previous CPSR and Program Counter. */
12877 record_buf
[0] = ARM_PS_REGNUM
;
12878 record_buf
[1] = ARM_LR_REGNUM
;
12879 thumb_insn_r
->reg_rec_count
= 2;
12880 /* We need to save SPSR value, which is not yet done. */
12881 printf_unfiltered (_("Process record does not support instruction "
12882 "0x%0x at address %s.\n"),
12883 thumb_insn_r
->arm_insn
,
12884 paddress (thumb_insn_r
->gdbarch
,
12885 thumb_insn_r
->this_addr
));
12888 else if ((0 == opcode
) || (1 == opcode
))
12890 /* ADD(5), ADD(6). */
12891 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12892 record_buf
[0] = reg_src1
;
12893 thumb_insn_r
->reg_rec_count
= 1;
12895 else if (2 == opcode
)
12897 /* ADD(7), SUB(4). */
12898 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12899 record_buf
[0] = ARM_SP_REGNUM
;
12900 thumb_insn_r
->reg_rec_count
= 1;
12903 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12904 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12910 /* Handling opcode 110 insns. */
12913 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12915 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12916 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12918 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12919 uint32_t reg_src1
= 0;
12920 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12921 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12922 uint32_t record_buf
[24], record_buf_mem
[48];
12924 ULONGEST u_regval
= 0;
12926 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12927 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12933 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12935 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12936 while (register_bits
)
12938 if (register_bits
& 0x00000001)
12939 record_buf
[index
++] = register_count
;
12940 register_bits
= register_bits
>> 1;
12943 record_buf
[index
++] = reg_src1
;
12944 thumb_insn_r
->reg_rec_count
= index
;
12946 else if (0 == opcode2
)
12948 /* It handles both STMIA. */
12949 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12951 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12952 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12953 while (register_bits
)
12955 if (register_bits
& 0x00000001)
12957 register_bits
= register_bits
>> 1;
12959 start_address
= u_regval
;
12960 thumb_insn_r
->mem_rec_count
= register_count
;
12961 while (register_count
)
12963 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12964 record_buf_mem
[(register_count
* 2) - 2] = 4;
12965 start_address
= start_address
+ 4;
12969 else if (0x1F == opcode1
)
12971 /* Handle arm syscall insn. */
12972 if (tdep
->arm_syscall_record
!= NULL
)
12974 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12975 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12979 printf_unfiltered (_("no syscall record support\n"));
12984 /* B (1), conditional branch is automatically taken care in process_record,
12985 as PC is saved there. */
12987 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12988 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12994 /* Handling opcode 111 insns. */
12997 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12999 uint32_t record_buf
[8];
13000 uint32_t bits_h
= 0;
13002 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
13004 if (2 == bits_h
|| 3 == bits_h
)
13007 record_buf
[0] = ARM_LR_REGNUM
;
13008 thumb_insn_r
->reg_rec_count
= 1;
13010 else if (1 == bits_h
)
13013 record_buf
[0] = ARM_PS_REGNUM
;
13014 record_buf
[1] = ARM_LR_REGNUM
;
13015 thumb_insn_r
->reg_rec_count
= 2;
13018 /* B(2) is automatically taken care in process_record, as PC is
13021 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13026 /* Handler for thumb2 load/store multiple instructions. */
13029 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
13031 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13033 uint32_t reg_rn
, op
;
13034 uint32_t register_bits
= 0, register_count
= 0;
13035 uint32_t index
= 0, start_address
= 0;
13036 uint32_t record_buf
[24], record_buf_mem
[48];
13038 ULONGEST u_regval
= 0;
13040 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13041 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13043 if (0 == op
|| 3 == op
)
13045 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13047 /* Handle RFE instruction. */
13048 record_buf
[0] = ARM_PS_REGNUM
;
13049 thumb2_insn_r
->reg_rec_count
= 1;
13053 /* Handle SRS instruction after reading banked SP. */
13054 return arm_record_unsupported_insn (thumb2_insn_r
);
13057 else if (1 == op
|| 2 == op
)
13059 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13061 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13062 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13063 while (register_bits
)
13065 if (register_bits
& 0x00000001)
13066 record_buf
[index
++] = register_count
;
13069 register_bits
= register_bits
>> 1;
13071 record_buf
[index
++] = reg_rn
;
13072 record_buf
[index
++] = ARM_PS_REGNUM
;
13073 thumb2_insn_r
->reg_rec_count
= index
;
13077 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13078 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13079 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13080 while (register_bits
)
13082 if (register_bits
& 0x00000001)
13085 register_bits
= register_bits
>> 1;
13090 /* Start address calculation for LDMDB/LDMEA. */
13091 start_address
= u_regval
;
13095 /* Start address calculation for LDMDB/LDMEA. */
13096 start_address
= u_regval
- register_count
* 4;
13099 thumb2_insn_r
->mem_rec_count
= register_count
;
13100 while (register_count
)
13102 record_buf_mem
[register_count
* 2 - 1] = start_address
;
13103 record_buf_mem
[register_count
* 2 - 2] = 4;
13104 start_address
= start_address
+ 4;
13107 record_buf
[0] = reg_rn
;
13108 record_buf
[1] = ARM_PS_REGNUM
;
13109 thumb2_insn_r
->reg_rec_count
= 2;
13113 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13115 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13117 return ARM_RECORD_SUCCESS
;
13120 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13124 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
13126 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13128 uint32_t reg_rd
, reg_rn
, offset_imm
;
13129 uint32_t reg_dest1
, reg_dest2
;
13130 uint32_t address
, offset_addr
;
13131 uint32_t record_buf
[8], record_buf_mem
[8];
13132 uint32_t op1
, op2
, op3
;
13135 ULONGEST u_regval
[2];
13137 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13138 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
13139 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13141 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13143 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
13145 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13146 record_buf
[0] = reg_dest1
;
13147 record_buf
[1] = ARM_PS_REGNUM
;
13148 thumb2_insn_r
->reg_rec_count
= 2;
13151 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
13153 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13154 record_buf
[2] = reg_dest2
;
13155 thumb2_insn_r
->reg_rec_count
= 3;
13160 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13161 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13163 if (0 == op1
&& 0 == op2
)
13165 /* Handle STREX. */
13166 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13167 address
= u_regval
[0] + (offset_imm
* 4);
13168 record_buf_mem
[0] = 4;
13169 record_buf_mem
[1] = address
;
13170 thumb2_insn_r
->mem_rec_count
= 1;
13171 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13172 record_buf
[0] = reg_rd
;
13173 thumb2_insn_r
->reg_rec_count
= 1;
13175 else if (1 == op1
&& 0 == op2
)
13177 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13178 record_buf
[0] = reg_rd
;
13179 thumb2_insn_r
->reg_rec_count
= 1;
13180 address
= u_regval
[0];
13181 record_buf_mem
[1] = address
;
13185 /* Handle STREXB. */
13186 record_buf_mem
[0] = 1;
13187 thumb2_insn_r
->mem_rec_count
= 1;
13191 /* Handle STREXH. */
13192 record_buf_mem
[0] = 2 ;
13193 thumb2_insn_r
->mem_rec_count
= 1;
13197 /* Handle STREXD. */
13198 address
= u_regval
[0];
13199 record_buf_mem
[0] = 4;
13200 record_buf_mem
[2] = 4;
13201 record_buf_mem
[3] = address
+ 4;
13202 thumb2_insn_r
->mem_rec_count
= 2;
13207 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13209 if (bit (thumb2_insn_r
->arm_insn
, 24))
13211 if (bit (thumb2_insn_r
->arm_insn
, 23))
13212 offset_addr
= u_regval
[0] + (offset_imm
* 4);
13214 offset_addr
= u_regval
[0] - (offset_imm
* 4);
13216 address
= offset_addr
;
13219 address
= u_regval
[0];
13221 record_buf_mem
[0] = 4;
13222 record_buf_mem
[1] = address
;
13223 record_buf_mem
[2] = 4;
13224 record_buf_mem
[3] = address
+ 4;
13225 thumb2_insn_r
->mem_rec_count
= 2;
13226 record_buf
[0] = reg_rn
;
13227 thumb2_insn_r
->reg_rec_count
= 1;
13231 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13233 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13235 return ARM_RECORD_SUCCESS
;
13238 /* Handler for thumb2 data processing (shift register and modified immediate)
13242 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
13244 uint32_t reg_rd
, op
;
13245 uint32_t record_buf
[8];
13247 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
13248 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13250 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
13252 record_buf
[0] = ARM_PS_REGNUM
;
13253 thumb2_insn_r
->reg_rec_count
= 1;
13257 record_buf
[0] = reg_rd
;
13258 record_buf
[1] = ARM_PS_REGNUM
;
13259 thumb2_insn_r
->reg_rec_count
= 2;
13262 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13264 return ARM_RECORD_SUCCESS
;
13267 /* Generic handler for thumb2 instructions which effect destination and PS
13271 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
13274 uint32_t record_buf
[8];
13276 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13278 record_buf
[0] = reg_rd
;
13279 record_buf
[1] = ARM_PS_REGNUM
;
13280 thumb2_insn_r
->reg_rec_count
= 2;
13282 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13284 return ARM_RECORD_SUCCESS
;
13287 /* Handler for thumb2 branch and miscellaneous control instructions. */
13290 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
13292 uint32_t op
, op1
, op2
;
13293 uint32_t record_buf
[8];
13295 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13296 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
13297 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13299 /* Handle MSR insn. */
13300 if (!(op1
& 0x2) && 0x38 == op
)
13304 /* CPSR is going to be changed. */
13305 record_buf
[0] = ARM_PS_REGNUM
;
13306 thumb2_insn_r
->reg_rec_count
= 1;
13310 arm_record_unsupported_insn(thumb2_insn_r
);
13314 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
13317 record_buf
[0] = ARM_PS_REGNUM
;
13318 record_buf
[1] = ARM_LR_REGNUM
;
13319 thumb2_insn_r
->reg_rec_count
= 2;
13322 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13324 return ARM_RECORD_SUCCESS
;
13327 /* Handler for thumb2 store single data item instructions. */
13330 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
13332 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13334 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
13335 uint32_t address
, offset_addr
;
13336 uint32_t record_buf
[8], record_buf_mem
[8];
13339 ULONGEST u_regval
[2];
13341 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
13342 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
13343 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13344 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13346 if (bit (thumb2_insn_r
->arm_insn
, 23))
13349 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
13350 offset_addr
= u_regval
[0] + offset_imm
;
13351 address
= offset_addr
;
13356 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
13358 /* Handle STRB (register). */
13359 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13360 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
13361 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
13362 offset_addr
= u_regval
[1] << shift_imm
;
13363 address
= u_regval
[0] + offset_addr
;
13367 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13368 if (bit (thumb2_insn_r
->arm_insn
, 10))
13370 if (bit (thumb2_insn_r
->arm_insn
, 9))
13371 offset_addr
= u_regval
[0] + offset_imm
;
13373 offset_addr
= u_regval
[0] - offset_imm
;
13375 address
= offset_addr
;
13378 address
= u_regval
[0];
13384 /* Store byte instructions. */
13387 record_buf_mem
[0] = 1;
13389 /* Store half word instructions. */
13392 record_buf_mem
[0] = 2;
13394 /* Store word instructions. */
13397 record_buf_mem
[0] = 4;
13401 gdb_assert_not_reached ("no decoding pattern found");
13405 record_buf_mem
[1] = address
;
13406 thumb2_insn_r
->mem_rec_count
= 1;
13407 record_buf
[0] = reg_rn
;
13408 thumb2_insn_r
->reg_rec_count
= 1;
13410 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13412 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13414 return ARM_RECORD_SUCCESS
;
13417 /* Handler for thumb2 load memory hints instructions. */
13420 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
13422 uint32_t record_buf
[8];
13423 uint32_t reg_rt
, reg_rn
;
13425 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13426 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13428 if (ARM_PC_REGNUM
!= reg_rt
)
13430 record_buf
[0] = reg_rt
;
13431 record_buf
[1] = reg_rn
;
13432 record_buf
[2] = ARM_PS_REGNUM
;
13433 thumb2_insn_r
->reg_rec_count
= 3;
13435 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13437 return ARM_RECORD_SUCCESS
;
13440 return ARM_RECORD_FAILURE
;
13443 /* Handler for thumb2 load word instructions. */
13446 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
13448 uint32_t opcode1
= 0, opcode2
= 0;
13449 uint32_t record_buf
[8];
13451 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13452 record_buf
[1] = ARM_PS_REGNUM
;
13453 thumb2_insn_r
->reg_rec_count
= 2;
13455 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13457 return ARM_RECORD_SUCCESS
;
13460 /* Handler for thumb2 long multiply, long multiply accumulate, and
13461 divide instructions. */
13464 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
13466 uint32_t opcode1
= 0, opcode2
= 0;
13467 uint32_t record_buf
[8];
13468 uint32_t reg_src1
= 0;
13470 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
13471 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13473 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
13475 /* Handle SMULL, UMULL, SMULAL. */
13476 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13477 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13478 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13479 record_buf
[2] = ARM_PS_REGNUM
;
13480 thumb2_insn_r
->reg_rec_count
= 3;
13482 else if (1 == opcode1
|| 3 == opcode2
)
13484 /* Handle SDIV and UDIV. */
13485 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13486 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13487 record_buf
[2] = ARM_PS_REGNUM
;
13488 thumb2_insn_r
->reg_rec_count
= 3;
13491 return ARM_RECORD_FAILURE
;
13493 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13495 return ARM_RECORD_SUCCESS
;
13498 /* Record handler for thumb32 coprocessor instructions. */
13501 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
13503 if (bit (thumb2_insn_r
->arm_insn
, 25))
13504 return arm_record_coproc_data_proc (thumb2_insn_r
);
13506 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
13509 /* Record handler for advance SIMD structure load/store instructions. */
13512 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
13514 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13515 uint32_t l_bit
, a_bit
, b_bits
;
13516 uint32_t record_buf
[128], record_buf_mem
[128];
13517 uint32_t reg_rn
, reg_vd
, address
, f_esize
, f_elem
;
13518 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
13521 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
13522 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
13523 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13524 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13525 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13526 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
13527 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
13528 f_esize
= 8 * f_ebytes
;
13529 f_elem
= 8 / f_ebytes
;
13533 ULONGEST u_regval
= 0;
13534 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13535 address
= u_regval
;
13540 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13542 if (b_bits
== 0x07)
13544 else if (b_bits
== 0x0a)
13546 else if (b_bits
== 0x06)
13548 else if (b_bits
== 0x02)
13553 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13555 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13557 record_buf_mem
[index_m
++] = f_ebytes
;
13558 record_buf_mem
[index_m
++] = address
;
13559 address
= address
+ f_ebytes
;
13560 thumb2_insn_r
->mem_rec_count
+= 1;
13565 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13567 if (b_bits
== 0x09 || b_bits
== 0x08)
13569 else if (b_bits
== 0x03)
13574 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13575 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13577 for (loop_t
= 0; loop_t
< 2; loop_t
++)
13579 record_buf_mem
[index_m
++] = f_ebytes
;
13580 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13581 thumb2_insn_r
->mem_rec_count
+= 1;
13583 address
= address
+ (2 * f_ebytes
);
13587 else if ((b_bits
& 0x0e) == 0x04)
13589 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13591 for (loop_t
= 0; loop_t
< 3; loop_t
++)
13593 record_buf_mem
[index_m
++] = f_ebytes
;
13594 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13595 thumb2_insn_r
->mem_rec_count
+= 1;
13597 address
= address
+ (3 * f_ebytes
);
13601 else if (!(b_bits
& 0x0e))
13603 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13605 for (loop_t
= 0; loop_t
< 4; loop_t
++)
13607 record_buf_mem
[index_m
++] = f_ebytes
;
13608 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13609 thumb2_insn_r
->mem_rec_count
+= 1;
13611 address
= address
+ (4 * f_ebytes
);
13617 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
13619 if (bft_size
== 0x00)
13621 else if (bft_size
== 0x01)
13623 else if (bft_size
== 0x02)
13629 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
13630 thumb2_insn_r
->mem_rec_count
= 1;
13632 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
13633 thumb2_insn_r
->mem_rec_count
= 2;
13635 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
13636 thumb2_insn_r
->mem_rec_count
= 3;
13638 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
13639 thumb2_insn_r
->mem_rec_count
= 4;
13641 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
13643 record_buf_mem
[index_m
] = f_ebytes
;
13644 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
13653 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13654 thumb2_insn_r
->reg_rec_count
= 1;
13656 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13657 thumb2_insn_r
->reg_rec_count
= 2;
13659 else if ((b_bits
& 0x0e) == 0x04)
13660 thumb2_insn_r
->reg_rec_count
= 3;
13662 else if (!(b_bits
& 0x0e))
13663 thumb2_insn_r
->reg_rec_count
= 4;
13668 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
13669 thumb2_insn_r
->reg_rec_count
= 1;
13671 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
13672 thumb2_insn_r
->reg_rec_count
= 2;
13674 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
13675 thumb2_insn_r
->reg_rec_count
= 3;
13677 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
13678 thumb2_insn_r
->reg_rec_count
= 4;
13680 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
13681 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
13685 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
13687 record_buf
[index_r
] = reg_rn
;
13688 thumb2_insn_r
->reg_rec_count
+= 1;
13691 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13693 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13698 /* Decodes thumb2 instruction type and invokes its record handler. */
13700 static unsigned int
13701 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
13703 uint32_t op
, op1
, op2
;
13705 op
= bit (thumb2_insn_r
->arm_insn
, 15);
13706 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
13707 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13711 if (!(op2
& 0x64 ))
13713 /* Load/store multiple instruction. */
13714 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
13716 else if (!((op2
& 0x64) ^ 0x04))
13718 /* Load/store (dual/exclusive) and table branch instruction. */
13719 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
13721 else if (!((op2
& 0x20) ^ 0x20))
13723 /* Data-processing (shifted register). */
13724 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13726 else if (op2
& 0x40)
13728 /* Co-processor instructions. */
13729 return thumb2_record_coproc_insn (thumb2_insn_r
);
13732 else if (op1
== 0x02)
13736 /* Branches and miscellaneous control instructions. */
13737 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
13739 else if (op2
& 0x20)
13741 /* Data-processing (plain binary immediate) instruction. */
13742 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13746 /* Data-processing (modified immediate). */
13747 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13750 else if (op1
== 0x03)
13752 if (!(op2
& 0x71 ))
13754 /* Store single data item. */
13755 return thumb2_record_str_single_data (thumb2_insn_r
);
13757 else if (!((op2
& 0x71) ^ 0x10))
13759 /* Advanced SIMD or structure load/store instructions. */
13760 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13762 else if (!((op2
& 0x67) ^ 0x01))
13764 /* Load byte, memory hints instruction. */
13765 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13767 else if (!((op2
& 0x67) ^ 0x03))
13769 /* Load halfword, memory hints instruction. */
13770 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13772 else if (!((op2
& 0x67) ^ 0x05))
13774 /* Load word instruction. */
13775 return thumb2_record_ld_word (thumb2_insn_r
);
13777 else if (!((op2
& 0x70) ^ 0x20))
13779 /* Data-processing (register) instruction. */
13780 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13782 else if (!((op2
& 0x78) ^ 0x30))
13784 /* Multiply, multiply accumulate, abs diff instruction. */
13785 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13787 else if (!((op2
& 0x78) ^ 0x38))
13789 /* Long multiply, long multiply accumulate, and divide. */
13790 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13792 else if (op2
& 0x40)
13794 /* Co-processor instructions. */
13795 return thumb2_record_coproc_insn (thumb2_insn_r
);
13802 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13803 and positive val on fauilure. */
13806 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
13808 gdb_byte buf
[insn_size
];
13810 memset (&buf
[0], 0, insn_size
);
13812 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
13814 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13816 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
13820 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13822 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13826 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
13827 uint32_t insn_size
)
13830 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13831 static const sti_arm_hdl_fp_t
const arm_handle_insn
[8] =
13833 arm_record_data_proc_misc_ld_str
, /* 000. */
13834 arm_record_data_proc_imm
, /* 001. */
13835 arm_record_ld_st_imm_offset
, /* 010. */
13836 arm_record_ld_st_reg_offset
, /* 011. */
13837 arm_record_ld_st_multiple
, /* 100. */
13838 arm_record_b_bl
, /* 101. */
13839 arm_record_asimd_vfp_coproc
, /* 110. */
13840 arm_record_coproc_data_proc
/* 111. */
13843 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13844 static const sti_arm_hdl_fp_t
const thumb_handle_insn
[8] =
13846 thumb_record_shift_add_sub
, /* 000. */
13847 thumb_record_add_sub_cmp_mov
, /* 001. */
13848 thumb_record_ld_st_reg_offset
, /* 010. */
13849 thumb_record_ld_st_imm_offset
, /* 011. */
13850 thumb_record_ld_st_stack
, /* 100. */
13851 thumb_record_misc
, /* 101. */
13852 thumb_record_ldm_stm_swi
, /* 110. */
13853 thumb_record_branch
/* 111. */
13856 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13857 uint32_t insn_id
= 0;
13859 if (extract_arm_insn (arm_record
, insn_size
))
13863 printf_unfiltered (_("Process record: error reading memory at "
13864 "addr %s len = %d.\n"),
13865 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
13869 else if (ARM_RECORD
== record_type
)
13871 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13872 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13873 ret
= arm_record_extension_space (arm_record
);
13874 /* If this insn has fallen into extension space
13875 then we need not decode it anymore. */
13876 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
13878 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13881 else if (THUMB_RECORD
== record_type
)
13883 /* As thumb does not have condition codes, we set negative. */
13884 arm_record
->cond
= -1;
13885 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13886 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13888 else if (THUMB2_RECORD
== record_type
)
13890 /* As thumb does not have condition codes, we set negative. */
13891 arm_record
->cond
= -1;
13893 /* Swap first half of 32bit thumb instruction with second half. */
13894 arm_record
->arm_insn
13895 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13897 insn_id
= thumb2_record_decode_insn_handler (arm_record
);
13899 if (insn_id
!= ARM_RECORD_SUCCESS
)
13901 arm_record_unsupported_insn (arm_record
);
13907 /* Throw assertion. */
13908 gdb_assert_not_reached ("not a valid instruction, could not decode");
13915 /* Cleans up local record registers and memory allocations. */
13918 deallocate_reg_mem (insn_decode_record
*record
)
13920 xfree (record
->arm_regs
);
13921 xfree (record
->arm_mems
);
13925 /* Parse the current instruction and record the values of the registers and
13926 memory that will be changed in current instruction to record_arch_list".
13927 Return -1 if something is wrong. */
13930 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13931 CORE_ADDR insn_addr
)
13934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
13935 uint32_t no_of_rec
= 0;
13936 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13937 ULONGEST t_bit
= 0, insn_id
= 0;
13939 ULONGEST u_regval
= 0;
13941 insn_decode_record arm_record
;
13943 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13944 arm_record
.regcache
= regcache
;
13945 arm_record
.this_addr
= insn_addr
;
13946 arm_record
.gdbarch
= gdbarch
;
13949 if (record_debug
> 1)
13951 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13953 paddress (gdbarch
, arm_record
.this_addr
));
13956 if (extract_arm_insn (&arm_record
, 2))
13960 printf_unfiltered (_("Process record: error reading memory at "
13961 "addr %s len = %d.\n"),
13962 paddress (arm_record
.gdbarch
,
13963 arm_record
.this_addr
), 2);
13968 /* Check the insn, whether it is thumb or arm one. */
13970 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13971 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13974 if (!(u_regval
& t_bit
))
13976 /* We are decoding arm insn. */
13977 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13981 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13982 /* is it thumb2 insn? */
13983 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13985 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13986 THUMB2_INSN_SIZE_BYTES
);
13990 /* We are decoding thumb insn. */
13991 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13997 /* Record registers. */
13998 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13999 if (arm_record
.arm_regs
)
14001 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
14003 if (record_full_arch_list_add_reg
14004 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
14008 /* Record memories. */
14009 if (arm_record
.arm_mems
)
14011 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
14013 if (record_full_arch_list_add_mem
14014 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
14015 arm_record
.arm_mems
[no_of_rec
].len
))
14020 if (record_full_arch_list_add_end ())
14025 deallocate_reg_mem (&arm_record
);