2003-04-05 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / arm-tdep.c
1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include <ctype.h> /* XXX for isupper () */
23
24 #include "defs.h"
25 #include "frame.h"
26 #include "inferior.h"
27 #include "gdbcmd.h"
28 #include "gdbcore.h"
29 #include "symfile.h"
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
32 #include "regcache.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
37 #include "osabi.h"
38
39 #include "arm-tdep.h"
40 #include "gdb/sim-arm.h"
41
42 #include "elf-bfd.h"
43 #include "coff/internal.h"
44 #include "elf/arm.h"
45
46 #include "gdb_assert.h"
47
48 static int arm_debug;
49
50 /* Each OS has a different mechanism for accessing the various
51 registers stored in the sigcontext structure.
52
53 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
54 function pointer) which may be used to determine the addresses
55 of the various saved registers in the sigcontext structure.
56
57 For the ARM target, there are three parameters to this function.
58 The first is the pc value of the frame under consideration, the
59 second the stack pointer of this frame, and the last is the
60 register number to fetch.
61
62 If the tm.h file does not define this macro, then it's assumed that
63 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
64 be 0.
65
66 When it comes time to multi-arching this code, see the identically
67 named machinery in ia64-tdep.c for an example of how it could be
68 done. It should not be necessary to modify the code below where
69 this macro is used. */
70
71 #ifdef SIGCONTEXT_REGISTER_ADDRESS
72 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
73 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
74 #endif
75 #else
76 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
77 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
78 #endif
79
80 /* Macros for setting and testing a bit in a minimal symbol that marks
81 it as Thumb function. The MSB of the minimal symbol's "info" field
82 is used for this purpose. This field is already being used to store
83 the symbol size, so the assumption is that the symbol size cannot
84 exceed 2^31.
85
86 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
87 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
88 MSYMBOL_SIZE Returns the size of the minimal symbol,
89 i.e. the "info" field with the "special" bit
90 masked out. */
91
92 #define MSYMBOL_SET_SPECIAL(msym) \
93 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
94 | 0x80000000)
95
96 #define MSYMBOL_IS_SPECIAL(msym) \
97 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
98
99 #define MSYMBOL_SIZE(msym) \
100 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
101
102 /* The list of available "set arm ..." and "show arm ..." commands. */
103 static struct cmd_list_element *setarmcmdlist = NULL;
104 static struct cmd_list_element *showarmcmdlist = NULL;
105
106 /* The type of floating-point to use. Keep this in sync with enum
107 arm_float_model, and the help string in _initialize_arm_tdep. */
108 static const char *fp_model_strings[] =
109 {
110 "auto",
111 "softfpa",
112 "fpa",
113 "softvfp",
114 "vfp"
115 };
116
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
119 static const char *current_fp_model = "auto";
120
121 /* Number of different reg name sets (options). */
122 static int num_disassembly_options;
123
124 /* We have more registers than the disassembler as gdb can print the value
125 of special registers as well.
126 The general register names are overwritten by whatever is being used by
127 the disassembler at the moment. We also adjust the case of cpsr and fps. */
128
129 /* Initial value: Register names used in ARM's ISA documentation. */
130 static char * arm_register_name_strings[] =
131 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
132 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
133 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
134 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
135 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
136 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
137 "fps", "cpsr" }; /* 24 25 */
138 static char **arm_register_names = arm_register_name_strings;
139
140 /* Valid register name styles. */
141 static const char **valid_disassembly_styles;
142
143 /* Disassembly style to use. Default to "std" register names. */
144 static const char *disassembly_style;
145 /* Index to that option in the opcodes table. */
146 static int current_option;
147
148 /* This is used to keep the bfd arch_info in sync with the disassembly
149 style. */
150 static void set_disassembly_style_sfunc(char *, int,
151 struct cmd_list_element *);
152 static void set_disassembly_style (void);
153
154 static void convert_from_extended (const struct floatformat *, const void *,
155 void *);
156 static void convert_to_extended (const struct floatformat *, void *,
157 const void *);
158
159 /* Define other aspects of the stack frame. We keep the offsets of
160 all saved registers, 'cause we need 'em a lot! We also keep the
161 current size of the stack frame, and the offset of the frame
162 pointer from the stack pointer (for frameless functions, and when
163 we're still in the prologue of a function with a frame). */
164
165 struct frame_extra_info
166 {
167 int framesize;
168 int frameoffset;
169 int framereg;
170 };
171
172 /* Addresses for calling Thumb functions have the bit 0 set.
173 Here are some macros to test, set, or clear bit 0 of addresses. */
174 #define IS_THUMB_ADDR(addr) ((addr) & 1)
175 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
176 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
177
178 static int
179 arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
180 {
181 return (DEPRECATED_FRAME_SAVED_PC (thisframe) >= LOWEST_PC);
182 }
183
184 /* Set to true if the 32-bit mode is in use. */
185
186 int arm_apcs_32 = 1;
187
188 /* Flag set by arm_fix_call_dummy that tells whether the target
189 function is a Thumb function. This flag is checked by
190 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
191 its use in valops.c) to pass the function address as an additional
192 parameter. */
193
194 static int target_is_thumb;
195
196 /* Flag set by arm_fix_call_dummy that tells whether the calling
197 function is a Thumb function. This flag is checked by
198 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
199
200 static int caller_is_thumb;
201
202 /* Determine if the program counter specified in MEMADDR is in a Thumb
203 function. */
204
205 int
206 arm_pc_is_thumb (CORE_ADDR memaddr)
207 {
208 struct minimal_symbol *sym;
209
210 /* If bit 0 of the address is set, assume this is a Thumb address. */
211 if (IS_THUMB_ADDR (memaddr))
212 return 1;
213
214 /* Thumb functions have a "special" bit set in minimal symbols. */
215 sym = lookup_minimal_symbol_by_pc (memaddr);
216 if (sym)
217 {
218 return (MSYMBOL_IS_SPECIAL (sym));
219 }
220 else
221 {
222 return 0;
223 }
224 }
225
226 /* Determine if the program counter specified in MEMADDR is in a call
227 dummy being called from a Thumb function. */
228
229 int
230 arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
231 {
232 CORE_ADDR sp = read_sp ();
233
234 /* FIXME: Until we switch for the new call dummy macros, this heuristic
235 is the best we can do. We are trying to determine if the pc is on
236 the stack, which (hopefully) will only happen in a call dummy.
237 We hope the current stack pointer is not so far alway from the dummy
238 frame location (true if we have not pushed large data structures or
239 gone too many levels deep) and that our 1024 is not enough to consider
240 code regions as part of the stack (true for most practical purposes). */
241 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
242 return caller_is_thumb;
243 else
244 return 0;
245 }
246
247 /* Remove useless bits from addresses in a running program. */
248 static CORE_ADDR
249 arm_addr_bits_remove (CORE_ADDR val)
250 {
251 if (arm_apcs_32)
252 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
253 else
254 return (val & 0x03fffffc);
255 }
256
257 /* When reading symbols, we need to zap the low bit of the address,
258 which may be set to 1 for Thumb functions. */
259 static CORE_ADDR
260 arm_smash_text_address (CORE_ADDR val)
261 {
262 return val & ~1;
263 }
264
265 /* Immediately after a function call, return the saved pc. Can't
266 always go through the frames for this because on some machines the
267 new frame is not set up until the new function executes some
268 instructions. */
269
270 static CORE_ADDR
271 arm_saved_pc_after_call (struct frame_info *frame)
272 {
273 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
274 }
275
276 /* Determine whether the function invocation represented by FI has a
277 frame on the stack associated with it. If it does return zero,
278 otherwise return 1. */
279
280 static int
281 arm_frameless_function_invocation (struct frame_info *fi)
282 {
283 CORE_ADDR func_start, after_prologue;
284 int frameless;
285
286 /* Sometimes we have functions that do a little setup (like saving the
287 vN registers with the stmdb instruction, but DO NOT set up a frame.
288 The symbol table will report this as a prologue. However, it is
289 important not to try to parse these partial frames as frames, or we
290 will get really confused.
291
292 So I will demand 3 instructions between the start & end of the
293 prologue before I call it a real prologue, i.e. at least
294 mov ip, sp,
295 stmdb sp!, {}
296 sub sp, ip, #4. */
297
298 func_start = (get_frame_func (fi)) + FUNCTION_START_OFFSET);
299 after_prologue = SKIP_PROLOGUE (func_start);
300
301 /* There are some frameless functions whose first two instructions
302 follow the standard APCS form, in which case after_prologue will
303 be func_start + 8. */
304
305 frameless = (after_prologue < func_start + 12);
306 return frameless;
307 }
308
309 /* The address of the arguments in the frame. */
310 static CORE_ADDR
311 arm_frame_args_address (struct frame_info *fi)
312 {
313 return get_frame_base (fi);
314 }
315
316 /* The address of the local variables in the frame. */
317 static CORE_ADDR
318 arm_frame_locals_address (struct frame_info *fi)
319 {
320 return get_frame_base (fi);
321 }
322
323 /* The number of arguments being passed in the frame. */
324 static int
325 arm_frame_num_args (struct frame_info *fi)
326 {
327 /* We have no way of knowing. */
328 return -1;
329 }
330
331 /* A typical Thumb prologue looks like this:
332 push {r7, lr}
333 add sp, sp, #-28
334 add r7, sp, #12
335 Sometimes the latter instruction may be replaced by:
336 mov r7, sp
337
338 or like this:
339 push {r7, lr}
340 mov r7, sp
341 sub sp, #12
342
343 or, on tpcs, like this:
344 sub sp,#16
345 push {r7, lr}
346 (many instructions)
347 mov r7, sp
348 sub sp, #12
349
350 There is always one instruction of three classes:
351 1 - push
352 2 - setting of r7
353 3 - adjusting of sp
354
355 When we have found at least one of each class we are done with the prolog.
356 Note that the "sub sp, #NN" before the push does not count.
357 */
358
359 static CORE_ADDR
360 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
361 {
362 CORE_ADDR current_pc;
363 /* findmask:
364 bit 0 - push { rlist }
365 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
366 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
367 */
368 int findmask = 0;
369
370 for (current_pc = pc;
371 current_pc + 2 < func_end && current_pc < pc + 40;
372 current_pc += 2)
373 {
374 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
375
376 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
377 {
378 findmask |= 1; /* push found */
379 }
380 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
381 sub sp, #simm */
382 {
383 if ((findmask & 1) == 0) /* before push ? */
384 continue;
385 else
386 findmask |= 4; /* add/sub sp found */
387 }
388 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
389 {
390 findmask |= 2; /* setting of r7 found */
391 }
392 else if (insn == 0x466f) /* mov r7, sp */
393 {
394 findmask |= 2; /* setting of r7 found */
395 }
396 else if (findmask == (4+2+1))
397 {
398 /* We have found one of each type of prologue instruction */
399 break;
400 }
401 else
402 /* Something in the prolog that we don't care about or some
403 instruction from outside the prolog scheduled here for
404 optimization. */
405 continue;
406 }
407
408 return current_pc;
409 }
410
411 /* Advance the PC across any function entry prologue instructions to
412 reach some "real" code.
413
414 The APCS (ARM Procedure Call Standard) defines the following
415 prologue:
416
417 mov ip, sp
418 [stmfd sp!, {a1,a2,a3,a4}]
419 stmfd sp!, {...,fp,ip,lr,pc}
420 [stfe f7, [sp, #-12]!]
421 [stfe f6, [sp, #-12]!]
422 [stfe f5, [sp, #-12]!]
423 [stfe f4, [sp, #-12]!]
424 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
425
426 static CORE_ADDR
427 arm_skip_prologue (CORE_ADDR pc)
428 {
429 unsigned long inst;
430 CORE_ADDR skip_pc;
431 CORE_ADDR func_addr, func_end = 0;
432 char *func_name;
433 struct symtab_and_line sal;
434
435 /* If we're in a dummy frame, don't even try to skip the prologue. */
436 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
437 return pc;
438
439 /* See what the symbol table says. */
440
441 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
442 {
443 struct symbol *sym;
444
445 /* Found a function. */
446 sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL);
447 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
448 {
449 /* Don't use this trick for assembly source files. */
450 sal = find_pc_line (func_addr, 0);
451 if ((sal.line != 0) && (sal.end < func_end))
452 return sal.end;
453 }
454 }
455
456 /* Check if this is Thumb code. */
457 if (arm_pc_is_thumb (pc))
458 return thumb_skip_prologue (pc, func_end);
459
460 /* Can't find the prologue end in the symbol table, try it the hard way
461 by disassembling the instructions. */
462
463 /* Like arm_scan_prologue, stop no later than pc + 64. */
464 if (func_end == 0 || func_end > pc + 64)
465 func_end = pc + 64;
466
467 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
468 {
469 inst = read_memory_integer (skip_pc, 4);
470
471 /* "mov ip, sp" is no longer a required part of the prologue. */
472 if (inst == 0xe1a0c00d) /* mov ip, sp */
473 continue;
474
475 /* Some prologues begin with "str lr, [sp, #-4]!". */
476 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
477 continue;
478
479 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
480 continue;
481
482 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
483 continue;
484
485 /* Any insns after this point may float into the code, if it makes
486 for better instruction scheduling, so we skip them only if we
487 find them, but still consider the function to be frame-ful. */
488
489 /* We may have either one sfmfd instruction here, or several stfe
490 insns, depending on the version of floating point code we
491 support. */
492 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
493 continue;
494
495 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
496 continue;
497
498 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
499 continue;
500
501 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
502 continue;
503
504 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
505 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
506 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
507 continue;
508
509 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
510 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
511 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
512 continue;
513
514 /* Un-recognized instruction; stop scanning. */
515 break;
516 }
517
518 return skip_pc; /* End of prologue */
519 }
520
521 /* *INDENT-OFF* */
522 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
523 This function decodes a Thumb function prologue to determine:
524 1) the size of the stack frame
525 2) which registers are saved on it
526 3) the offsets of saved regs
527 4) the offset from the stack pointer to the frame pointer
528 This information is stored in the "extra" fields of the frame_info.
529
530 A typical Thumb function prologue would create this stack frame
531 (offsets relative to FP)
532 old SP -> 24 stack parameters
533 20 LR
534 16 R7
535 R7 -> 0 local variables (16 bytes)
536 SP -> -12 additional stack space (12 bytes)
537 The frame size would thus be 36 bytes, and the frame offset would be
538 12 bytes. The frame register is R7.
539
540 The comments for thumb_skip_prolog() describe the algorithm we use
541 to detect the end of the prolog. */
542 /* *INDENT-ON* */
543
544 static void
545 thumb_scan_prologue (struct frame_info *fi)
546 {
547 CORE_ADDR prologue_start;
548 CORE_ADDR prologue_end;
549 CORE_ADDR current_pc;
550 /* Which register has been copied to register n? */
551 int saved_reg[16];
552 /* findmask:
553 bit 0 - push { rlist }
554 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
555 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
556 */
557 int findmask = 0;
558 int i;
559
560 /* Don't try to scan dummy frames. */
561 if (fi != NULL
562 && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
563 return;
564
565 if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end))
566 {
567 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
568
569 if (sal.line == 0) /* no line info, use current PC */
570 prologue_end = get_frame_pc (fi);
571 else if (sal.end < prologue_end) /* next line begins after fn end */
572 prologue_end = sal.end; /* (probably means no prologue) */
573 }
574 else
575 /* We're in the boondocks: allow for
576 16 pushes, an add, and "mv fp,sp". */
577 prologue_end = prologue_start + 40;
578
579 prologue_end = min (prologue_end, get_frame_pc (fi));
580
581 /* Initialize the saved register map. When register H is copied to
582 register L, we will put H in saved_reg[L]. */
583 for (i = 0; i < 16; i++)
584 saved_reg[i] = i;
585
586 /* Search the prologue looking for instructions that set up the
587 frame pointer, adjust the stack pointer, and save registers.
588 Do this until all basic prolog instructions are found. */
589
590 get_frame_extra_info (fi)->framesize = 0;
591 for (current_pc = prologue_start;
592 (current_pc < prologue_end) && ((findmask & 7) != 7);
593 current_pc += 2)
594 {
595 unsigned short insn;
596 int regno;
597 int offset;
598
599 insn = read_memory_unsigned_integer (current_pc, 2);
600
601 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
602 {
603 int mask;
604 findmask |= 1; /* push found */
605 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
606 whether to save LR (R14). */
607 mask = (insn & 0xff) | ((insn & 0x100) << 6);
608
609 /* Calculate offsets of saved R0-R7 and LR. */
610 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
611 if (mask & (1 << regno))
612 {
613 get_frame_extra_info (fi)->framesize += 4;
614 get_frame_saved_regs (fi)[saved_reg[regno]] =
615 -(get_frame_extra_info (fi)->framesize);
616 /* Reset saved register map. */
617 saved_reg[regno] = regno;
618 }
619 }
620 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
621 sub sp, #simm */
622 {
623 if ((findmask & 1) == 0) /* before push? */
624 continue;
625 else
626 findmask |= 4; /* add/sub sp found */
627
628 offset = (insn & 0x7f) << 2; /* get scaled offset */
629 if (insn & 0x80) /* is it signed? (==subtracting) */
630 {
631 get_frame_extra_info (fi)->frameoffset += offset;
632 offset = -offset;
633 }
634 get_frame_extra_info (fi)->framesize -= offset;
635 }
636 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
637 {
638 findmask |= 2; /* setting of r7 found */
639 get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM;
640 /* get scaled offset */
641 get_frame_extra_info (fi)->frameoffset = (insn & 0xff) << 2;
642 }
643 else if (insn == 0x466f) /* mov r7, sp */
644 {
645 findmask |= 2; /* setting of r7 found */
646 get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM;
647 get_frame_extra_info (fi)->frameoffset = 0;
648 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
649 }
650 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
651 {
652 int lo_reg = insn & 7; /* dest. register (r0-r7) */
653 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
654 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
655 }
656 else
657 /* Something in the prolog that we don't care about or some
658 instruction from outside the prolog scheduled here for
659 optimization. */
660 continue;
661 }
662 }
663
664 /* This function decodes an ARM function prologue to determine:
665 1) the size of the stack frame
666 2) which registers are saved on it
667 3) the offsets of saved regs
668 4) the offset from the stack pointer to the frame pointer
669 This information is stored in the "extra" fields of the frame_info.
670
671 There are two basic forms for the ARM prologue. The fixed argument
672 function call will look like:
673
674 mov ip, sp
675 stmfd sp!, {fp, ip, lr, pc}
676 sub fp, ip, #4
677 [sub sp, sp, #4]
678
679 Which would create this stack frame (offsets relative to FP):
680 IP -> 4 (caller's stack)
681 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
682 -4 LR (return address in caller)
683 -8 IP (copy of caller's SP)
684 -12 FP (caller's FP)
685 SP -> -28 Local variables
686
687 The frame size would thus be 32 bytes, and the frame offset would be
688 28 bytes. The stmfd call can also save any of the vN registers it
689 plans to use, which increases the frame size accordingly.
690
691 Note: The stored PC is 8 off of the STMFD instruction that stored it
692 because the ARM Store instructions always store PC + 8 when you read
693 the PC register.
694
695 A variable argument function call will look like:
696
697 mov ip, sp
698 stmfd sp!, {a1, a2, a3, a4}
699 stmfd sp!, {fp, ip, lr, pc}
700 sub fp, ip, #20
701
702 Which would create this stack frame (offsets relative to FP):
703 IP -> 20 (caller's stack)
704 16 A4
705 12 A3
706 8 A2
707 4 A1
708 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
709 -4 LR (return address in caller)
710 -8 IP (copy of caller's SP)
711 -12 FP (caller's FP)
712 SP -> -28 Local variables
713
714 The frame size would thus be 48 bytes, and the frame offset would be
715 28 bytes.
716
717 There is another potential complication, which is that the optimizer
718 will try to separate the store of fp in the "stmfd" instruction from
719 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
720 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
721
722 Also, note, the original version of the ARM toolchain claimed that there
723 should be an
724
725 instruction at the end of the prologue. I have never seen GCC produce
726 this, and the ARM docs don't mention it. We still test for it below in
727 case it happens...
728
729 */
730
731 static void
732 arm_scan_prologue (struct frame_info *fi)
733 {
734 int regno, sp_offset, fp_offset;
735 LONGEST return_value;
736 CORE_ADDR prologue_start, prologue_end, current_pc;
737
738 /* Assume there is no frame until proven otherwise. */
739 get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM;
740 get_frame_extra_info (fi)->framesize = 0;
741 get_frame_extra_info (fi)->frameoffset = 0;
742
743 /* Check for Thumb prologue. */
744 if (arm_pc_is_thumb (get_frame_pc (fi)))
745 {
746 thumb_scan_prologue (fi);
747 return;
748 }
749
750 /* Find the function prologue. If we can't find the function in
751 the symbol table, peek in the stack frame to find the PC. */
752 if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end))
753 {
754 /* One way to find the end of the prologue (which works well
755 for unoptimized code) is to do the following:
756
757 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
758
759 if (sal.line == 0)
760 prologue_end = get_frame_pc (fi);
761 else if (sal.end < prologue_end)
762 prologue_end = sal.end;
763
764 This mechanism is very accurate so long as the optimizer
765 doesn't move any instructions from the function body into the
766 prologue. If this happens, sal.end will be the last
767 instruction in the first hunk of prologue code just before
768 the first instruction that the scheduler has moved from
769 the body to the prologue.
770
771 In order to make sure that we scan all of the prologue
772 instructions, we use a slightly less accurate mechanism which
773 may scan more than necessary. To help compensate for this
774 lack of accuracy, the prologue scanning loop below contains
775 several clauses which'll cause the loop to terminate early if
776 an implausible prologue instruction is encountered.
777
778 The expression
779
780 prologue_start + 64
781
782 is a suitable endpoint since it accounts for the largest
783 possible prologue plus up to five instructions inserted by
784 the scheduler. */
785
786 if (prologue_end > prologue_start + 64)
787 {
788 prologue_end = prologue_start + 64; /* See above. */
789 }
790 }
791 else
792 {
793 /* Get address of the stmfd in the prologue of the callee;
794 the saved PC is the address of the stmfd + 8. */
795 if (!safe_read_memory_integer (get_frame_base (fi), 4, &return_value))
796 return;
797 else
798 {
799 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
800 prologue_end = prologue_start + 64; /* See above. */
801 }
802 }
803
804 /* Now search the prologue looking for instructions that set up the
805 frame pointer, adjust the stack pointer, and save registers.
806
807 Be careful, however, and if it doesn't look like a prologue,
808 don't try to scan it. If, for instance, a frameless function
809 begins with stmfd sp!, then we will tell ourselves there is
810 a frame, which will confuse stack traceback, as well as "finish"
811 and other operations that rely on a knowledge of the stack
812 traceback.
813
814 In the APCS, the prologue should start with "mov ip, sp" so
815 if we don't see this as the first insn, we will stop.
816
817 [Note: This doesn't seem to be true any longer, so it's now an
818 optional part of the prologue. - Kevin Buettner, 2001-11-20]
819
820 [Note further: The "mov ip,sp" only seems to be missing in
821 frameless functions at optimization level "-O2" or above,
822 in which case it is often (but not always) replaced by
823 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
824
825 sp_offset = fp_offset = 0;
826
827 for (current_pc = prologue_start;
828 current_pc < prologue_end;
829 current_pc += 4)
830 {
831 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
832
833 if (insn == 0xe1a0c00d) /* mov ip, sp */
834 {
835 continue;
836 }
837 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
838 {
839 /* Function is frameless: extra_info defaults OK? */
840 continue;
841 }
842 else if ((insn & 0xffff0000) == 0xe92d0000)
843 /* stmfd sp!, {..., fp, ip, lr, pc}
844 or
845 stmfd sp!, {a1, a2, a3, a4} */
846 {
847 int mask = insn & 0xffff;
848
849 /* Calculate offsets of saved registers. */
850 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
851 if (mask & (1 << regno))
852 {
853 sp_offset -= 4;
854 get_frame_saved_regs (fi)[regno] = sp_offset;
855 }
856 }
857 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
858 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
859 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
860 {
861 /* No need to add this to saved_regs -- it's just an arg reg. */
862 continue;
863 }
864 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
865 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
866 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
867 {
868 /* No need to add this to saved_regs -- it's just an arg reg. */
869 continue;
870 }
871 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
872 {
873 unsigned imm = insn & 0xff; /* immediate value */
874 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
875 imm = (imm >> rot) | (imm << (32 - rot));
876 fp_offset = -imm;
877 get_frame_extra_info (fi)->framereg = ARM_FP_REGNUM;
878 }
879 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
880 {
881 unsigned imm = insn & 0xff; /* immediate value */
882 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
883 imm = (imm >> rot) | (imm << (32 - rot));
884 sp_offset -= imm;
885 }
886 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
887 {
888 sp_offset -= 12;
889 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
890 get_frame_saved_regs (fi)[regno] = sp_offset;
891 }
892 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
893 {
894 int n_saved_fp_regs;
895 unsigned int fp_start_reg, fp_bound_reg;
896
897 if ((insn & 0x800) == 0x800) /* N0 is set */
898 {
899 if ((insn & 0x40000) == 0x40000) /* N1 is set */
900 n_saved_fp_regs = 3;
901 else
902 n_saved_fp_regs = 1;
903 }
904 else
905 {
906 if ((insn & 0x40000) == 0x40000) /* N1 is set */
907 n_saved_fp_regs = 2;
908 else
909 n_saved_fp_regs = 4;
910 }
911
912 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
913 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
914 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
915 {
916 sp_offset -= 12;
917 get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset;
918 }
919 }
920 else if ((insn & 0xf0000000) != 0xe0000000)
921 break; /* Condition not true, exit early */
922 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
923 break; /* Don't scan past a block load */
924 else
925 /* The optimizer might shove anything into the prologue,
926 so we just skip what we don't recognize. */
927 continue;
928 }
929
930 /* The frame size is just the negative of the offset (from the
931 original SP) of the last thing thing we pushed on the stack.
932 The frame offset is [new FP] - [new SP]. */
933 get_frame_extra_info (fi)->framesize = -sp_offset;
934 if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM)
935 get_frame_extra_info (fi)->frameoffset = fp_offset - sp_offset;
936 else
937 get_frame_extra_info (fi)->frameoffset = 0;
938 }
939
940 /* Find REGNUM on the stack. Otherwise, it's in an active register.
941 One thing we might want to do here is to check REGNUM against the
942 clobber mask, and somehow flag it as invalid if it isn't saved on
943 the stack somewhere. This would provide a graceful failure mode
944 when trying to get the value of caller-saves registers for an inner
945 frame. */
946
947 static CORE_ADDR
948 arm_find_callers_reg (struct frame_info *fi, int regnum)
949 {
950 /* NOTE: cagney/2002-05-03: This function really shouldn't be
951 needed. Instead the (still being written) register unwind
952 function could be called directly. */
953 for (; fi; fi = get_next_frame (fi))
954 {
955 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
956 {
957 return deprecated_read_register_dummy (get_frame_pc (fi),
958 get_frame_base (fi), regnum);
959 }
960 else if (get_frame_saved_regs (fi)[regnum] != 0)
961 {
962 /* NOTE: cagney/2002-05-03: This would normally need to
963 handle ARM_SP_REGNUM as a special case as, according to
964 the frame.h comments, saved_regs[SP_REGNUM] contains the
965 SP value not its address. It appears that the ARM isn't
966 doing this though. */
967 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
968 REGISTER_RAW_SIZE (regnum));
969 }
970 }
971 return read_register (regnum);
972 }
973 /* Function: frame_chain Given a GDB frame, determine the address of
974 the calling function's frame. This will be used to create a new
975 GDB frame struct, and then DEPRECATED_INIT_EXTRA_FRAME_INFO and
976 DEPRECATED_INIT_FRAME_PC will be called for the new frame. For
977 ARM, we save the frame size when we initialize the frame_info. */
978
979 static CORE_ADDR
980 arm_frame_chain (struct frame_info *fi)
981 {
982 CORE_ADDR caller_pc;
983 int framereg = get_frame_extra_info (fi)->framereg;
984
985 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
986 /* A generic call dummy's frame is the same as caller's. */
987 return get_frame_base (fi);
988
989 if (get_frame_pc (fi) < LOWEST_PC)
990 return 0;
991
992 /* If the caller is the startup code, we're at the end of the chain. */
993 caller_pc = DEPRECATED_FRAME_SAVED_PC (fi);
994
995 /* If the caller is Thumb and the caller is ARM, or vice versa,
996 the frame register of the caller is different from ours.
997 So we must scan the prologue of the caller to determine its
998 frame register number. */
999 /* XXX Fixme, we should try to do this without creating a temporary
1000 caller_fi. */
1001 if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi)))
1002 {
1003 struct cleanup *old_chain = make_cleanup (null_cleanup, NULL);
1004 struct frame_info *caller_fi =
1005 deprecated_frame_xmalloc_with_cleanup (SIZEOF_FRAME_SAVED_REGS,
1006 sizeof (struct frame_extra_info));
1007
1008 /* Now, scan the prologue and obtain the frame register. */
1009 deprecated_update_frame_pc_hack (caller_fi, caller_pc);
1010 arm_scan_prologue (caller_fi);
1011 framereg = get_frame_extra_info (caller_fi)->framereg;
1012
1013 /* Deallocate the storage associated with the temporary frame
1014 created above. */
1015 do_cleanups (old_chain);
1016 }
1017
1018 /* If the caller used a frame register, return its value.
1019 Otherwise, return the caller's stack pointer. */
1020 if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM)
1021 return arm_find_callers_reg (fi, framereg);
1022 else
1023 return get_frame_base (fi) + get_frame_extra_info (fi)->framesize;
1024 }
1025
1026 /* This function actually figures out the frame address for a given pc
1027 and sp. This is tricky because we sometimes don't use an explicit
1028 frame pointer, and the previous stack pointer isn't necessarily
1029 recorded on the stack. The only reliable way to get this info is
1030 to examine the prologue. FROMLEAF is a little confusing, it means
1031 this is the next frame up the chain AFTER a frameless function. If
1032 this is true, then the frame value for this frame is still in the
1033 fp register. */
1034
1035 static void
1036 arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1037 {
1038 int reg;
1039 CORE_ADDR sp;
1040
1041 if (get_frame_saved_regs (fi) == NULL)
1042 frame_saved_regs_zalloc (fi);
1043
1044 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1045
1046 get_frame_extra_info (fi)->framesize = 0;
1047 get_frame_extra_info (fi)->frameoffset = 0;
1048 get_frame_extra_info (fi)->framereg = 0;
1049
1050 if (get_next_frame (fi))
1051 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1052
1053 memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi));
1054
1055 /* Compute stack pointer for this frame. We use this value for both
1056 the sigtramp and call dummy cases. */
1057 if (!get_next_frame (fi))
1058 sp = read_sp();
1059 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0))
1060 /* For generic dummy frames, pull the value direct from the frame.
1061 Having an unwind function to do this would be nice. */
1062 sp = deprecated_read_register_dummy (get_frame_pc (get_next_frame (fi)),
1063 get_frame_base (get_next_frame (fi)),
1064 ARM_SP_REGNUM);
1065 else
1066 sp = (get_frame_base (get_next_frame (fi))
1067 - get_frame_extra_info (get_next_frame (fi))->frameoffset
1068 + get_frame_extra_info (get_next_frame (fi))->framesize);
1069
1070 /* Determine whether or not we're in a sigtramp frame.
1071 Unfortunately, it isn't sufficient to test (get_frame_type (fi)
1072 == SIGTRAMP_FRAME) because this value is sometimes set after
1073 invoking DEPRECATED_INIT_EXTRA_FRAME_INFO. So we test *both*
1074 (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to
1075 determine if we need to use the sigcontext addresses for the
1076 saved registers.
1077
1078 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1079 against the name of the function, the code below will have to be
1080 changed to first fetch the name of the function and then pass
1081 this name to PC_IN_SIGTRAMP. */
1082
1083 /* FIXME: cagney/2002-11-18: This problem will go away once
1084 frame.c:get_prev_frame() is modified to set the frame's type
1085 before calling functions like this. */
1086
1087 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1088 && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0)))
1089 {
1090 for (reg = 0; reg < NUM_REGS; reg++)
1091 get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg);
1092
1093 /* FIXME: What about thumb mode? */
1094 get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM;
1095 deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (fi)[get_frame_extra_info (fi)->framereg], REGISTER_RAW_SIZE (get_frame_extra_info (fi)->framereg)));
1096 get_frame_extra_info (fi)->framesize = 0;
1097 get_frame_extra_info (fi)->frameoffset = 0;
1098
1099 }
1100 else
1101 {
1102 arm_scan_prologue (fi);
1103
1104 if (!get_next_frame (fi))
1105 /* This is the innermost frame? */
1106 deprecated_update_frame_base_hack (fi, read_register (get_frame_extra_info (fi)->framereg));
1107 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0))
1108 /* Next inner most frame is a dummy, just grab its frame.
1109 Dummy frames always have the same FP as their caller. */
1110 deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi)));
1111 else if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM
1112 || get_frame_extra_info (fi)->framereg == THUMB_FP_REGNUM)
1113 {
1114 /* not the innermost frame */
1115 /* If we have an FP, the callee saved it. */
1116 if (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg] != 0)
1117 deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg], 4));
1118 else if (fromleaf)
1119 /* If we were called by a frameless fn. then our frame is
1120 still in the frame pointer register on the board... */
1121 deprecated_update_frame_base_hack (fi, read_fp ());
1122 }
1123
1124 /* Calculate actual addresses of saved registers using offsets
1125 determined by arm_scan_prologue. */
1126 for (reg = 0; reg < NUM_REGS; reg++)
1127 if (get_frame_saved_regs (fi)[reg] != 0)
1128 get_frame_saved_regs (fi)[reg]
1129 += (get_frame_base (fi)
1130 + get_frame_extra_info (fi)->framesize
1131 - get_frame_extra_info (fi)->frameoffset);
1132 }
1133 }
1134
1135
1136 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1137 is saved in the stack anywhere, otherwise we get it from the
1138 registers.
1139
1140 The old definition of this function was a macro:
1141 #define FRAME_SAVED_PC(FRAME) \
1142 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1143
1144 static CORE_ADDR
1145 arm_frame_saved_pc (struct frame_info *fi)
1146 {
1147 /* If a dummy frame, pull the PC out of the frame's register buffer. */
1148 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
1149 return deprecated_read_register_dummy (get_frame_pc (fi),
1150 get_frame_base (fi), ARM_PC_REGNUM);
1151
1152 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi),
1153 (get_frame_base (fi)
1154 - get_frame_extra_info (fi)->frameoffset),
1155 get_frame_base (fi)))
1156 {
1157 return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM],
1158 REGISTER_RAW_SIZE (ARM_PC_REGNUM));
1159 }
1160 else
1161 {
1162 CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM);
1163 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1164 }
1165 }
1166
1167 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1168 Examine the Program Status Register to decide which state we're in. */
1169
1170 static CORE_ADDR
1171 arm_read_fp (void)
1172 {
1173 if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
1174 return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
1175 else
1176 return read_register (ARM_FP_REGNUM); /* R11 if ARM */
1177 }
1178
1179 /* Store into a struct frame_saved_regs the addresses of the saved
1180 registers of frame described by FRAME_INFO. This includes special
1181 registers such as PC and FP saved in special ways in the stack
1182 frame. SP is even more special: the address we return for it IS
1183 the sp for the next frame. */
1184
1185 static void
1186 arm_frame_init_saved_regs (struct frame_info *fip)
1187 {
1188
1189 if (get_frame_saved_regs (fip))
1190 return;
1191
1192 arm_init_extra_frame_info (0, fip);
1193 }
1194
1195 /* Set the return address for a generic dummy frame. ARM uses the
1196 entry point. */
1197
1198 static CORE_ADDR
1199 arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1200 {
1201 write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ());
1202 return sp;
1203 }
1204
1205 /* Push an empty stack frame, to record the current PC, etc. */
1206
1207 static void
1208 arm_push_dummy_frame (void)
1209 {
1210 CORE_ADDR old_sp = read_register (ARM_SP_REGNUM);
1211 CORE_ADDR sp = old_sp;
1212 CORE_ADDR fp, prologue_start;
1213 int regnum;
1214
1215 /* Push the two dummy prologue instructions in reverse order,
1216 so that they'll be in the correct low-to-high order in memory. */
1217 /* sub fp, ip, #4 */
1218 sp = push_word (sp, 0xe24cb004);
1219 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1220 prologue_start = sp = push_word (sp, 0xe92ddfff);
1221
1222 /* Push a pointer to the dummy prologue + 12, because when stm
1223 instruction stores the PC, it stores the address of the stm
1224 instruction itself plus 12. */
1225 fp = sp = push_word (sp, prologue_start + 12);
1226
1227 /* Push the processor status. */
1228 sp = push_word (sp, read_register (ARM_PS_REGNUM));
1229
1230 /* Push all 16 registers starting with r15. */
1231 for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--)
1232 sp = push_word (sp, read_register (regnum));
1233
1234 /* Update fp (for both Thumb and ARM) and sp. */
1235 write_register (ARM_FP_REGNUM, fp);
1236 write_register (THUMB_FP_REGNUM, fp);
1237 write_register (ARM_SP_REGNUM, sp);
1238 }
1239
1240 /* CALL_DUMMY_WORDS:
1241 This sequence of words is the instructions
1242
1243 mov lr,pc
1244 mov pc,r4
1245 illegal
1246
1247 Note this is 12 bytes. */
1248
1249 static LONGEST arm_call_dummy_words[] =
1250 {
1251 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1252 };
1253
1254 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1255 breakpoint to the proper address in the call dummy, so that
1256 `finish' after a stop in a call dummy works.
1257
1258 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1259 optimal solution, but the call to arm_fix_call_dummy is immediately
1260 followed by a call to run_stack_dummy, which is the only function
1261 where call_dummy_breakpoint_offset is actually used. */
1262
1263
1264 static void
1265 arm_set_call_dummy_breakpoint_offset (void)
1266 {
1267 if (caller_is_thumb)
1268 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4);
1269 else
1270 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8);
1271 }
1272
1273 /* Fix up the call dummy, based on whether the processor is currently
1274 in Thumb or ARM mode, and whether the target function is Thumb or
1275 ARM. There are three different situations requiring three
1276 different dummies:
1277
1278 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1279 been copied into the dummy parameter to this function.
1280 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1281 "mov pc,r4" instruction patched to be a "bx r4" instead.
1282 * Thumb calling anything: uses the Thumb dummy defined below, which
1283 works for calling both ARM and Thumb functions.
1284
1285 All three call dummies expect to receive the target function
1286 address in R4, with the low bit set if it's a Thumb function. */
1287
1288 static void
1289 arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1290 struct value **args, struct type *type, int gcc_p)
1291 {
1292 static short thumb_dummy[4] =
1293 {
1294 0xf000, 0xf801, /* bl label */
1295 0xdf18, /* swi 24 */
1296 0x4720, /* label: bx r4 */
1297 };
1298 static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
1299
1300 /* Set flag indicating whether the current PC is in a Thumb function. */
1301 caller_is_thumb = arm_pc_is_thumb (read_pc ());
1302 arm_set_call_dummy_breakpoint_offset ();
1303
1304 /* If the target function is Thumb, set the low bit of the function
1305 address. And if the CPU is currently in ARM mode, patch the
1306 second instruction of call dummy to use a BX instruction to
1307 switch to Thumb mode. */
1308 target_is_thumb = arm_pc_is_thumb (fun);
1309 if (target_is_thumb)
1310 {
1311 fun |= 1;
1312 if (!caller_is_thumb)
1313 store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
1314 }
1315
1316 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1317 instead of the ARM one that's already been copied. This will
1318 work for both Thumb and ARM target functions. */
1319 if (caller_is_thumb)
1320 {
1321 int i;
1322 char *p = dummy;
1323 int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
1324
1325 for (i = 0; i < len; i++)
1326 {
1327 store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
1328 p += sizeof (thumb_dummy[0]);
1329 }
1330 }
1331
1332 /* Put the target address in r4; the call dummy will copy this to
1333 the PC. */
1334 write_register (4, fun);
1335 }
1336
1337 /* Pop the current frame. So long as the frame info has been
1338 initialized properly (see arm_init_extra_frame_info), this code
1339 works for dummy frames as well as regular frames. I.e, there's no
1340 need to have a special case for dummy frames. */
1341 static void
1342 arm_pop_frame (void)
1343 {
1344 int regnum;
1345 struct frame_info *frame = get_current_frame ();
1346 CORE_ADDR old_SP = (get_frame_base (frame)
1347 - get_frame_extra_info (frame)->frameoffset
1348 + get_frame_extra_info (frame)->framesize);
1349
1350 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1351 get_frame_base (frame),
1352 get_frame_base (frame)))
1353 {
1354 generic_pop_dummy_frame ();
1355 flush_cached_frames ();
1356 return;
1357 }
1358
1359 for (regnum = 0; regnum < NUM_REGS; regnum++)
1360 if (get_frame_saved_regs (frame)[regnum] != 0)
1361 write_register (regnum,
1362 read_memory_integer (get_frame_saved_regs (frame)[regnum],
1363 REGISTER_RAW_SIZE (regnum)));
1364
1365 write_register (ARM_PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame));
1366 write_register (ARM_SP_REGNUM, old_SP);
1367
1368 flush_cached_frames ();
1369 }
1370
1371 /* When arguments must be pushed onto the stack, they go on in reverse
1372 order. The code below implements a FILO (stack) to do this. */
1373
1374 struct stack_item
1375 {
1376 int len;
1377 struct stack_item *prev;
1378 void *data;
1379 };
1380
1381 static struct stack_item *
1382 push_stack_item (struct stack_item *prev, void *contents, int len)
1383 {
1384 struct stack_item *si;
1385 si = xmalloc (sizeof (struct stack_item));
1386 si->data = xmalloc (len);
1387 si->len = len;
1388 si->prev = prev;
1389 memcpy (si->data, contents, len);
1390 return si;
1391 }
1392
1393 static struct stack_item *
1394 pop_stack_item (struct stack_item *si)
1395 {
1396 struct stack_item *dead = si;
1397 si = si->prev;
1398 xfree (dead->data);
1399 xfree (dead);
1400 return si;
1401 }
1402
1403 /* We currently only support passing parameters in integer registers. This
1404 conforms with GCC's default model. Several other variants exist and
1405 we should probably support some of them based on the selected ABI. */
1406
1407 static CORE_ADDR
1408 arm_push_dummy_call (struct gdbarch *gdbarch, struct regcache *regcache,
1409 CORE_ADDR dummy_addr, int nargs, struct value **args,
1410 CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr)
1411 {
1412 int argnum;
1413 int argreg;
1414 int nstack;
1415 struct stack_item *si = NULL;
1416
1417 /* Set the return address. For the ARM, the return breakpoint is always
1418 at DUMMY_ADDR. */
1419 /* XXX Fix for Thumb. */
1420 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, dummy_addr);
1421
1422 /* Walk through the list of args and determine how large a temporary
1423 stack is required. Need to take care here as structs may be
1424 passed on the stack, and we have to to push them. */
1425 nstack = 0;
1426
1427 argreg = ARM_A1_REGNUM;
1428 nstack = 0;
1429
1430 /* Some platforms require a double-word aligned stack. Make sure sp
1431 is correctly aligned before we start. We always do this even if
1432 it isn't really needed -- it can never hurt things. */
1433 sp &= ~(CORE_ADDR)(2 * REGISTER_SIZE - 1);
1434
1435 /* The struct_return pointer occupies the first parameter
1436 passing register. */
1437 if (struct_return)
1438 {
1439 if (arm_debug)
1440 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1441 REGISTER_NAME (argreg), paddr (struct_addr));
1442 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1443 argreg++;
1444 }
1445
1446 for (argnum = 0; argnum < nargs; argnum++)
1447 {
1448 int len;
1449 struct type *arg_type;
1450 struct type *target_type;
1451 enum type_code typecode;
1452 char *val;
1453
1454 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1455 len = TYPE_LENGTH (arg_type);
1456 target_type = TYPE_TARGET_TYPE (arg_type);
1457 typecode = TYPE_CODE (arg_type);
1458 val = VALUE_CONTENTS (args[argnum]);
1459
1460 /* If the argument is a pointer to a function, and it is a
1461 Thumb function, create a LOCAL copy of the value and set
1462 the THUMB bit in it. */
1463 if (TYPE_CODE_PTR == typecode
1464 && target_type != NULL
1465 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1466 {
1467 CORE_ADDR regval = extract_address (val, len);
1468 if (arm_pc_is_thumb (regval))
1469 {
1470 val = alloca (len);
1471 store_address (val, len, MAKE_THUMB_ADDR (regval));
1472 }
1473 }
1474
1475 /* Copy the argument to general registers or the stack in
1476 register-sized pieces. Large arguments are split between
1477 registers and stack. */
1478 while (len > 0)
1479 {
1480 int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
1481
1482 if (argreg <= ARM_LAST_ARG_REGNUM)
1483 {
1484 /* The argument is being passed in a general purpose
1485 register. */
1486 CORE_ADDR regval = extract_address (val, partial_len);
1487 if (arm_debug)
1488 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1489 argnum, REGISTER_NAME (argreg),
1490 phex (regval, REGISTER_SIZE));
1491 regcache_cooked_write_unsigned (regcache, argreg, regval);
1492 argreg++;
1493 }
1494 else
1495 {
1496 /* Push the arguments onto the stack. */
1497 if (arm_debug)
1498 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1499 argnum, nstack);
1500 si = push_stack_item (si, val, REGISTER_SIZE);
1501 nstack += REGISTER_SIZE;
1502 }
1503
1504 len -= partial_len;
1505 val += partial_len;
1506 }
1507 }
1508 /* If we have an odd number of words to push, then decrement the stack
1509 by one word now, so first stack argument will be dword aligned. */
1510 if (nstack & 4)
1511 sp -= 4;
1512
1513 while (si)
1514 {
1515 sp -= si->len;
1516 write_memory (sp, si->data, si->len);
1517 si = pop_stack_item (si);
1518 }
1519
1520 /* Finally, update teh SP register. */
1521 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1522
1523 return sp;
1524 }
1525
1526 static void
1527 print_fpu_flags (int flags)
1528 {
1529 if (flags & (1 << 0))
1530 fputs ("IVO ", stdout);
1531 if (flags & (1 << 1))
1532 fputs ("DVZ ", stdout);
1533 if (flags & (1 << 2))
1534 fputs ("OFL ", stdout);
1535 if (flags & (1 << 3))
1536 fputs ("UFL ", stdout);
1537 if (flags & (1 << 4))
1538 fputs ("INX ", stdout);
1539 putchar ('\n');
1540 }
1541
1542 /* Print interesting information about the floating point processor
1543 (if present) or emulator. */
1544 static void
1545 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1546 struct frame_info *frame, const char *args)
1547 {
1548 register unsigned long status = read_register (ARM_FPS_REGNUM);
1549 int type;
1550
1551 type = (status >> 24) & 127;
1552 printf ("%s FPU type %d\n",
1553 (status & (1 << 31)) ? "Hardware" : "Software",
1554 type);
1555 fputs ("mask: ", stdout);
1556 print_fpu_flags (status >> 16);
1557 fputs ("flags: ", stdout);
1558 print_fpu_flags (status);
1559 }
1560
1561 /* Return the GDB type object for the "standard" data type of data in
1562 register N. */
1563
1564 static struct type *
1565 arm_register_type (int regnum)
1566 {
1567 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1568 {
1569 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1570 return builtin_type_arm_ext_big;
1571 else
1572 return builtin_type_arm_ext_littlebyte_bigword;
1573 }
1574 else
1575 return builtin_type_int32;
1576 }
1577
1578 /* Index within `registers' of the first byte of the space for
1579 register N. */
1580
1581 static int
1582 arm_register_byte (int regnum)
1583 {
1584 if (regnum < ARM_F0_REGNUM)
1585 return regnum * INT_REGISTER_RAW_SIZE;
1586 else if (regnum < ARM_PS_REGNUM)
1587 return (NUM_GREGS * INT_REGISTER_RAW_SIZE
1588 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE);
1589 else
1590 return (NUM_GREGS * INT_REGISTER_RAW_SIZE
1591 + NUM_FREGS * FP_REGISTER_RAW_SIZE
1592 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1593 }
1594
1595 /* Number of bytes of storage in the actual machine representation for
1596 register N. All registers are 4 bytes, except fp0 - fp7, which are
1597 12 bytes in length. */
1598
1599 static int
1600 arm_register_raw_size (int regnum)
1601 {
1602 if (regnum < ARM_F0_REGNUM)
1603 return INT_REGISTER_RAW_SIZE;
1604 else if (regnum < ARM_FPS_REGNUM)
1605 return FP_REGISTER_RAW_SIZE;
1606 else
1607 return STATUS_REGISTER_SIZE;
1608 }
1609
1610 /* Number of bytes of storage in a program's representation
1611 for register N. */
1612 static int
1613 arm_register_virtual_size (int regnum)
1614 {
1615 if (regnum < ARM_F0_REGNUM)
1616 return INT_REGISTER_VIRTUAL_SIZE;
1617 else if (regnum < ARM_FPS_REGNUM)
1618 return FP_REGISTER_VIRTUAL_SIZE;
1619 else
1620 return STATUS_REGISTER_SIZE;
1621 }
1622
1623 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1624 static int
1625 arm_register_sim_regno (int regnum)
1626 {
1627 int reg = regnum;
1628 gdb_assert (reg >= 0 && reg < NUM_REGS);
1629
1630 if (reg < NUM_GREGS)
1631 return SIM_ARM_R0_REGNUM + reg;
1632 reg -= NUM_GREGS;
1633
1634 if (reg < NUM_FREGS)
1635 return SIM_ARM_FP0_REGNUM + reg;
1636 reg -= NUM_FREGS;
1637
1638 if (reg < NUM_SREGS)
1639 return SIM_ARM_FPS_REGNUM + reg;
1640 reg -= NUM_SREGS;
1641
1642 internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
1643 }
1644
1645 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1646 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1647 It is thought that this is is the floating-point register format on
1648 little-endian systems. */
1649
1650 static void
1651 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1652 void *dbl)
1653 {
1654 DOUBLEST d;
1655 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1656 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1657 else
1658 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1659 ptr, &d);
1660 floatformat_from_doublest (fmt, &d, dbl);
1661 }
1662
1663 static void
1664 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1665 {
1666 DOUBLEST d;
1667 floatformat_to_doublest (fmt, ptr, &d);
1668 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1669 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1670 else
1671 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1672 &d, dbl);
1673 }
1674
1675 static int
1676 condition_true (unsigned long cond, unsigned long status_reg)
1677 {
1678 if (cond == INST_AL || cond == INST_NV)
1679 return 1;
1680
1681 switch (cond)
1682 {
1683 case INST_EQ:
1684 return ((status_reg & FLAG_Z) != 0);
1685 case INST_NE:
1686 return ((status_reg & FLAG_Z) == 0);
1687 case INST_CS:
1688 return ((status_reg & FLAG_C) != 0);
1689 case INST_CC:
1690 return ((status_reg & FLAG_C) == 0);
1691 case INST_MI:
1692 return ((status_reg & FLAG_N) != 0);
1693 case INST_PL:
1694 return ((status_reg & FLAG_N) == 0);
1695 case INST_VS:
1696 return ((status_reg & FLAG_V) != 0);
1697 case INST_VC:
1698 return ((status_reg & FLAG_V) == 0);
1699 case INST_HI:
1700 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1701 case INST_LS:
1702 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1703 case INST_GE:
1704 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1705 case INST_LT:
1706 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1707 case INST_GT:
1708 return (((status_reg & FLAG_Z) == 0) &&
1709 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1710 case INST_LE:
1711 return (((status_reg & FLAG_Z) != 0) ||
1712 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1713 }
1714 return 1;
1715 }
1716
1717 /* Support routines for single stepping. Calculate the next PC value. */
1718 #define submask(x) ((1L << ((x) + 1)) - 1)
1719 #define bit(obj,st) (((obj) >> (st)) & 1)
1720 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1721 #define sbits(obj,st,fn) \
1722 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1723 #define BranchDest(addr,instr) \
1724 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1725 #define ARM_PC_32 1
1726
1727 static unsigned long
1728 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1729 unsigned long status_reg)
1730 {
1731 unsigned long res, shift;
1732 int rm = bits (inst, 0, 3);
1733 unsigned long shifttype = bits (inst, 5, 6);
1734
1735 if (bit (inst, 4))
1736 {
1737 int rs = bits (inst, 8, 11);
1738 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1739 }
1740 else
1741 shift = bits (inst, 7, 11);
1742
1743 res = (rm == 15
1744 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1745 + (bit (inst, 4) ? 12 : 8))
1746 : read_register (rm));
1747
1748 switch (shifttype)
1749 {
1750 case 0: /* LSL */
1751 res = shift >= 32 ? 0 : res << shift;
1752 break;
1753
1754 case 1: /* LSR */
1755 res = shift >= 32 ? 0 : res >> shift;
1756 break;
1757
1758 case 2: /* ASR */
1759 if (shift >= 32)
1760 shift = 31;
1761 res = ((res & 0x80000000L)
1762 ? ~((~res) >> shift) : res >> shift);
1763 break;
1764
1765 case 3: /* ROR/RRX */
1766 shift &= 31;
1767 if (shift == 0)
1768 res = (res >> 1) | (carry ? 0x80000000L : 0);
1769 else
1770 res = (res >> shift) | (res << (32 - shift));
1771 break;
1772 }
1773
1774 return res & 0xffffffff;
1775 }
1776
1777 /* Return number of 1-bits in VAL. */
1778
1779 static int
1780 bitcount (unsigned long val)
1781 {
1782 int nbits;
1783 for (nbits = 0; val != 0; nbits++)
1784 val &= val - 1; /* delete rightmost 1-bit in val */
1785 return nbits;
1786 }
1787
1788 CORE_ADDR
1789 thumb_get_next_pc (CORE_ADDR pc)
1790 {
1791 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1792 unsigned short inst1 = read_memory_integer (pc, 2);
1793 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1794 unsigned long offset;
1795
1796 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1797 {
1798 CORE_ADDR sp;
1799
1800 /* Fetch the saved PC from the stack. It's stored above
1801 all of the other registers. */
1802 offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
1803 sp = read_register (ARM_SP_REGNUM);
1804 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1805 nextpc = ADDR_BITS_REMOVE (nextpc);
1806 if (nextpc == pc)
1807 error ("Infinite loop detected");
1808 }
1809 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1810 {
1811 unsigned long status = read_register (ARM_PS_REGNUM);
1812 unsigned long cond = bits (inst1, 8, 11);
1813 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1814 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1815 }
1816 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1817 {
1818 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1819 }
1820 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
1821 {
1822 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1823 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1824 nextpc = pc_val + offset;
1825 }
1826
1827 return nextpc;
1828 }
1829
1830 CORE_ADDR
1831 arm_get_next_pc (CORE_ADDR pc)
1832 {
1833 unsigned long pc_val;
1834 unsigned long this_instr;
1835 unsigned long status;
1836 CORE_ADDR nextpc;
1837
1838 if (arm_pc_is_thumb (pc))
1839 return thumb_get_next_pc (pc);
1840
1841 pc_val = (unsigned long) pc;
1842 this_instr = read_memory_integer (pc, 4);
1843 status = read_register (ARM_PS_REGNUM);
1844 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1845
1846 if (condition_true (bits (this_instr, 28, 31), status))
1847 {
1848 switch (bits (this_instr, 24, 27))
1849 {
1850 case 0x0:
1851 case 0x1: /* data processing */
1852 case 0x2:
1853 case 0x3:
1854 {
1855 unsigned long operand1, operand2, result = 0;
1856 unsigned long rn;
1857 int c;
1858
1859 if (bits (this_instr, 12, 15) != 15)
1860 break;
1861
1862 if (bits (this_instr, 22, 25) == 0
1863 && bits (this_instr, 4, 7) == 9) /* multiply */
1864 error ("Illegal update to pc in instruction");
1865
1866 /* Multiply into PC */
1867 c = (status & FLAG_C) ? 1 : 0;
1868 rn = bits (this_instr, 16, 19);
1869 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1870
1871 if (bit (this_instr, 25))
1872 {
1873 unsigned long immval = bits (this_instr, 0, 7);
1874 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1875 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1876 & 0xffffffff;
1877 }
1878 else /* operand 2 is a shifted register */
1879 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1880
1881 switch (bits (this_instr, 21, 24))
1882 {
1883 case 0x0: /*and */
1884 result = operand1 & operand2;
1885 break;
1886
1887 case 0x1: /*eor */
1888 result = operand1 ^ operand2;
1889 break;
1890
1891 case 0x2: /*sub */
1892 result = operand1 - operand2;
1893 break;
1894
1895 case 0x3: /*rsb */
1896 result = operand2 - operand1;
1897 break;
1898
1899 case 0x4: /*add */
1900 result = operand1 + operand2;
1901 break;
1902
1903 case 0x5: /*adc */
1904 result = operand1 + operand2 + c;
1905 break;
1906
1907 case 0x6: /*sbc */
1908 result = operand1 - operand2 + c;
1909 break;
1910
1911 case 0x7: /*rsc */
1912 result = operand2 - operand1 + c;
1913 break;
1914
1915 case 0x8:
1916 case 0x9:
1917 case 0xa:
1918 case 0xb: /* tst, teq, cmp, cmn */
1919 result = (unsigned long) nextpc;
1920 break;
1921
1922 case 0xc: /*orr */
1923 result = operand1 | operand2;
1924 break;
1925
1926 case 0xd: /*mov */
1927 /* Always step into a function. */
1928 result = operand2;
1929 break;
1930
1931 case 0xe: /*bic */
1932 result = operand1 & ~operand2;
1933 break;
1934
1935 case 0xf: /*mvn */
1936 result = ~operand2;
1937 break;
1938 }
1939 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1940
1941 if (nextpc == pc)
1942 error ("Infinite loop detected");
1943 break;
1944 }
1945
1946 case 0x4:
1947 case 0x5: /* data transfer */
1948 case 0x6:
1949 case 0x7:
1950 if (bit (this_instr, 20))
1951 {
1952 /* load */
1953 if (bits (this_instr, 12, 15) == 15)
1954 {
1955 /* rd == pc */
1956 unsigned long rn;
1957 unsigned long base;
1958
1959 if (bit (this_instr, 22))
1960 error ("Illegal update to pc in instruction");
1961
1962 /* byte write to PC */
1963 rn = bits (this_instr, 16, 19);
1964 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1965 if (bit (this_instr, 24))
1966 {
1967 /* pre-indexed */
1968 int c = (status & FLAG_C) ? 1 : 0;
1969 unsigned long offset =
1970 (bit (this_instr, 25)
1971 ? shifted_reg_val (this_instr, c, pc_val, status)
1972 : bits (this_instr, 0, 11));
1973
1974 if (bit (this_instr, 23))
1975 base += offset;
1976 else
1977 base -= offset;
1978 }
1979 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1980 4);
1981
1982 nextpc = ADDR_BITS_REMOVE (nextpc);
1983
1984 if (nextpc == pc)
1985 error ("Infinite loop detected");
1986 }
1987 }
1988 break;
1989
1990 case 0x8:
1991 case 0x9: /* block transfer */
1992 if (bit (this_instr, 20))
1993 {
1994 /* LDM */
1995 if (bit (this_instr, 15))
1996 {
1997 /* loading pc */
1998 int offset = 0;
1999
2000 if (bit (this_instr, 23))
2001 {
2002 /* up */
2003 unsigned long reglist = bits (this_instr, 0, 14);
2004 offset = bitcount (reglist) * 4;
2005 if (bit (this_instr, 24)) /* pre */
2006 offset += 4;
2007 }
2008 else if (bit (this_instr, 24))
2009 offset = -4;
2010
2011 {
2012 unsigned long rn_val =
2013 read_register (bits (this_instr, 16, 19));
2014 nextpc =
2015 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2016 + offset),
2017 4);
2018 }
2019 nextpc = ADDR_BITS_REMOVE (nextpc);
2020 if (nextpc == pc)
2021 error ("Infinite loop detected");
2022 }
2023 }
2024 break;
2025
2026 case 0xb: /* branch & link */
2027 case 0xa: /* branch */
2028 {
2029 nextpc = BranchDest (pc, this_instr);
2030
2031 nextpc = ADDR_BITS_REMOVE (nextpc);
2032 if (nextpc == pc)
2033 error ("Infinite loop detected");
2034 break;
2035 }
2036
2037 case 0xc:
2038 case 0xd:
2039 case 0xe: /* coproc ops */
2040 case 0xf: /* SWI */
2041 break;
2042
2043 default:
2044 fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
2045 return (pc);
2046 }
2047 }
2048
2049 return nextpc;
2050 }
2051
2052 /* single_step() is called just before we want to resume the inferior,
2053 if we want to single-step it but there is no hardware or kernel
2054 single-step support. We find the target of the coming instruction
2055 and breakpoint it.
2056
2057 single_step() is also called just after the inferior stops. If we
2058 had set up a simulated single-step, we undo our damage. */
2059
2060 static void
2061 arm_software_single_step (enum target_signal sig, int insert_bpt)
2062 {
2063 static int next_pc; /* State between setting and unsetting. */
2064 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
2065
2066 if (insert_bpt)
2067 {
2068 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
2069 target_insert_breakpoint (next_pc, break_mem);
2070 }
2071 else
2072 target_remove_breakpoint (next_pc, break_mem);
2073 }
2074
2075 #include "bfd-in2.h"
2076 #include "libcoff.h"
2077
2078 static int
2079 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2080 {
2081 if (arm_pc_is_thumb (memaddr))
2082 {
2083 static asymbol *asym;
2084 static combined_entry_type ce;
2085 static struct coff_symbol_struct csym;
2086 static struct bfd fake_bfd;
2087 static bfd_target fake_target;
2088
2089 if (csym.native == NULL)
2090 {
2091 /* Create a fake symbol vector containing a Thumb symbol.
2092 This is solely so that the code in print_insn_little_arm()
2093 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2094 the presence of a Thumb symbol and switch to decoding
2095 Thumb instructions. */
2096
2097 fake_target.flavour = bfd_target_coff_flavour;
2098 fake_bfd.xvec = &fake_target;
2099 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2100 csym.native = &ce;
2101 csym.symbol.the_bfd = &fake_bfd;
2102 csym.symbol.name = "fake";
2103 asym = (asymbol *) & csym;
2104 }
2105
2106 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2107 info->symbols = &asym;
2108 }
2109 else
2110 info->symbols = NULL;
2111
2112 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2113 return print_insn_big_arm (memaddr, info);
2114 else
2115 return print_insn_little_arm (memaddr, info);
2116 }
2117
2118 /* The following define instruction sequences that will cause ARM
2119 cpu's to take an undefined instruction trap. These are used to
2120 signal a breakpoint to GDB.
2121
2122 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2123 modes. A different instruction is required for each mode. The ARM
2124 cpu's can also be big or little endian. Thus four different
2125 instructions are needed to support all cases.
2126
2127 Note: ARMv4 defines several new instructions that will take the
2128 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2129 not in fact add the new instructions. The new undefined
2130 instructions in ARMv4 are all instructions that had no defined
2131 behaviour in earlier chips. There is no guarantee that they will
2132 raise an exception, but may be treated as NOP's. In practice, it
2133 may only safe to rely on instructions matching:
2134
2135 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2136 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2137 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2138
2139 Even this may only true if the condition predicate is true. The
2140 following use a condition predicate of ALWAYS so it is always TRUE.
2141
2142 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2143 and NetBSD all use a software interrupt rather than an undefined
2144 instruction to force a trap. This can be handled by by the
2145 abi-specific code during establishment of the gdbarch vector. */
2146
2147
2148 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2149 override these definitions. */
2150 #ifndef ARM_LE_BREAKPOINT
2151 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2152 #endif
2153 #ifndef ARM_BE_BREAKPOINT
2154 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2155 #endif
2156 #ifndef THUMB_LE_BREAKPOINT
2157 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2158 #endif
2159 #ifndef THUMB_BE_BREAKPOINT
2160 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2161 #endif
2162
2163 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2164 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2165 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2166 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2167
2168 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2169 the program counter value to determine whether a 16-bit or 32-bit
2170 breakpoint should be used. It returns a pointer to a string of
2171 bytes that encode a breakpoint instruction, stores the length of
2172 the string to *lenptr, and adjusts the program counter (if
2173 necessary) to point to the actual memory location where the
2174 breakpoint should be inserted. */
2175
2176 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2177 breakpoints and storing their handles instread of what was in
2178 memory. It is nice that this is the same size as a handle -
2179 otherwise remote-rdp will have to change. */
2180
2181 static const unsigned char *
2182 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
2183 {
2184 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2185
2186 if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
2187 {
2188 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2189 *lenptr = tdep->thumb_breakpoint_size;
2190 return tdep->thumb_breakpoint;
2191 }
2192 else
2193 {
2194 *lenptr = tdep->arm_breakpoint_size;
2195 return tdep->arm_breakpoint;
2196 }
2197 }
2198
2199 /* Extract from an array REGBUF containing the (raw) register state a
2200 function return value of type TYPE, and copy that, in virtual
2201 format, into VALBUF. */
2202
2203 static void
2204 arm_extract_return_value (struct type *type,
2205 struct regcache *regs,
2206 void *dst)
2207 {
2208 bfd_byte *valbuf = dst;
2209
2210 if (TYPE_CODE_FLT == TYPE_CODE (type))
2211 {
2212 switch (arm_get_fp_model (current_gdbarch))
2213 {
2214 case ARM_FLOAT_FPA:
2215 {
2216 /* The value is in register F0 in internal format. We need to
2217 extract the raw value and then convert it to the desired
2218 internal type. */
2219 bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE];
2220
2221 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2222 convert_from_extended (floatformat_from_type (type), tmpbuf,
2223 valbuf);
2224 }
2225 break;
2226
2227 case ARM_FLOAT_SOFT_FPA:
2228 case ARM_FLOAT_SOFT_VFP:
2229 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2230 if (TYPE_LENGTH (type) > 4)
2231 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2232 valbuf + INT_REGISTER_RAW_SIZE);
2233 break;
2234
2235 default:
2236 internal_error
2237 (__FILE__, __LINE__,
2238 "arm_extract_return_value: Floating point model not supported");
2239 break;
2240 }
2241 }
2242 else if (TYPE_CODE (type) == TYPE_CODE_INT
2243 || TYPE_CODE (type) == TYPE_CODE_CHAR
2244 || TYPE_CODE (type) == TYPE_CODE_BOOL
2245 || TYPE_CODE (type) == TYPE_CODE_PTR
2246 || TYPE_CODE (type) == TYPE_CODE_REF
2247 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2248 {
2249 /* If the the type is a plain integer, then the access is
2250 straight-forward. Otherwise we have to play around a bit more. */
2251 int len = TYPE_LENGTH (type);
2252 int regno = ARM_A1_REGNUM;
2253 ULONGEST tmp;
2254
2255 while (len > 0)
2256 {
2257 /* By using store_unsigned_integer we avoid having to do
2258 anything special for small big-endian values. */
2259 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2260 store_unsigned_integer (valbuf,
2261 (len > INT_REGISTER_RAW_SIZE
2262 ? INT_REGISTER_RAW_SIZE : len),
2263 tmp);
2264 len -= INT_REGISTER_RAW_SIZE;
2265 valbuf += INT_REGISTER_RAW_SIZE;
2266 }
2267 }
2268 else
2269 {
2270 /* For a structure or union the behaviour is as if the value had
2271 been stored to word-aligned memory and then loaded into
2272 registers with 32-bit load instruction(s). */
2273 int len = TYPE_LENGTH (type);
2274 int regno = ARM_A1_REGNUM;
2275 bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
2276
2277 while (len > 0)
2278 {
2279 regcache_cooked_read (regs, regno++, tmpbuf);
2280 memcpy (valbuf, tmpbuf,
2281 len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
2282 len -= INT_REGISTER_RAW_SIZE;
2283 valbuf += INT_REGISTER_RAW_SIZE;
2284 }
2285 }
2286 }
2287
2288 /* Extract from an array REGBUF containing the (raw) register state
2289 the address in which a function should return its structure value. */
2290
2291 static CORE_ADDR
2292 arm_extract_struct_value_address (struct regcache *regcache)
2293 {
2294 ULONGEST ret;
2295
2296 regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
2297 return ret;
2298 }
2299
2300 /* Will a function return an aggregate type in memory or in a
2301 register? Return 0 if an aggregate type can be returned in a
2302 register, 1 if it must be returned in memory. */
2303
2304 static int
2305 arm_use_struct_convention (int gcc_p, struct type *type)
2306 {
2307 int nRc;
2308 register enum type_code code;
2309
2310 /* In the ARM ABI, "integer" like aggregate types are returned in
2311 registers. For an aggregate type to be integer like, its size
2312 must be less than or equal to REGISTER_SIZE and the offset of
2313 each addressable subfield must be zero. Note that bit fields are
2314 not addressable, and all addressable subfields of unions always
2315 start at offset zero.
2316
2317 This function is based on the behaviour of GCC 2.95.1.
2318 See: gcc/arm.c: arm_return_in_memory() for details.
2319
2320 Note: All versions of GCC before GCC 2.95.2 do not set up the
2321 parameters correctly for a function returning the following
2322 structure: struct { float f;}; This should be returned in memory,
2323 not a register. Richard Earnshaw sent me a patch, but I do not
2324 know of any way to detect if a function like the above has been
2325 compiled with the correct calling convention. */
2326
2327 /* All aggregate types that won't fit in a register must be returned
2328 in memory. */
2329 if (TYPE_LENGTH (type) > REGISTER_SIZE)
2330 {
2331 return 1;
2332 }
2333
2334 /* The only aggregate types that can be returned in a register are
2335 structs and unions. Arrays must be returned in memory. */
2336 code = TYPE_CODE (type);
2337 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2338 {
2339 return 1;
2340 }
2341
2342 /* Assume all other aggregate types can be returned in a register.
2343 Run a check for structures, unions and arrays. */
2344 nRc = 0;
2345
2346 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2347 {
2348 int i;
2349 /* Need to check if this struct/union is "integer" like. For
2350 this to be true, its size must be less than or equal to
2351 REGISTER_SIZE and the offset of each addressable subfield
2352 must be zero. Note that bit fields are not addressable, and
2353 unions always start at offset zero. If any of the subfields
2354 is a floating point type, the struct/union cannot be an
2355 integer type. */
2356
2357 /* For each field in the object, check:
2358 1) Is it FP? --> yes, nRc = 1;
2359 2) Is it addressable (bitpos != 0) and
2360 not packed (bitsize == 0)?
2361 --> yes, nRc = 1
2362 */
2363
2364 for (i = 0; i < TYPE_NFIELDS (type); i++)
2365 {
2366 enum type_code field_type_code;
2367 field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
2368
2369 /* Is it a floating point type field? */
2370 if (field_type_code == TYPE_CODE_FLT)
2371 {
2372 nRc = 1;
2373 break;
2374 }
2375
2376 /* If bitpos != 0, then we have to care about it. */
2377 if (TYPE_FIELD_BITPOS (type, i) != 0)
2378 {
2379 /* Bitfields are not addressable. If the field bitsize is
2380 zero, then the field is not packed. Hence it cannot be
2381 a bitfield or any other packed type. */
2382 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2383 {
2384 nRc = 1;
2385 break;
2386 }
2387 }
2388 }
2389 }
2390
2391 return nRc;
2392 }
2393
2394 /* Write into appropriate registers a function return value of type
2395 TYPE, given in virtual format. */
2396
2397 static void
2398 arm_store_return_value (struct type *type, struct regcache *regs,
2399 const void *src)
2400 {
2401 const bfd_byte *valbuf = src;
2402
2403 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2404 {
2405 char buf[ARM_MAX_REGISTER_RAW_SIZE];
2406
2407 switch (arm_get_fp_model (current_gdbarch))
2408 {
2409 case ARM_FLOAT_FPA:
2410
2411 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2412 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2413 break;
2414
2415 case ARM_FLOAT_SOFT_FPA:
2416 case ARM_FLOAT_SOFT_VFP:
2417 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2418 if (TYPE_LENGTH (type) > 4)
2419 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2420 valbuf + INT_REGISTER_RAW_SIZE);
2421 break;
2422
2423 default:
2424 internal_error
2425 (__FILE__, __LINE__,
2426 "arm_store_return_value: Floating point model not supported");
2427 break;
2428 }
2429 }
2430 else if (TYPE_CODE (type) == TYPE_CODE_INT
2431 || TYPE_CODE (type) == TYPE_CODE_CHAR
2432 || TYPE_CODE (type) == TYPE_CODE_BOOL
2433 || TYPE_CODE (type) == TYPE_CODE_PTR
2434 || TYPE_CODE (type) == TYPE_CODE_REF
2435 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2436 {
2437 if (TYPE_LENGTH (type) <= 4)
2438 {
2439 /* Values of one word or less are zero/sign-extended and
2440 returned in r0. */
2441 bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
2442 LONGEST val = unpack_long (type, valbuf);
2443
2444 store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val);
2445 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2446 }
2447 else
2448 {
2449 /* Integral values greater than one word are stored in consecutive
2450 registers starting with r0. This will always be a multiple of
2451 the regiser size. */
2452 int len = TYPE_LENGTH (type);
2453 int regno = ARM_A1_REGNUM;
2454
2455 while (len > 0)
2456 {
2457 regcache_cooked_write (regs, regno++, valbuf);
2458 len -= INT_REGISTER_RAW_SIZE;
2459 valbuf += INT_REGISTER_RAW_SIZE;
2460 }
2461 }
2462 }
2463 else
2464 {
2465 /* For a structure or union the behaviour is as if the value had
2466 been stored to word-aligned memory and then loaded into
2467 registers with 32-bit load instruction(s). */
2468 int len = TYPE_LENGTH (type);
2469 int regno = ARM_A1_REGNUM;
2470 bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
2471
2472 while (len > 0)
2473 {
2474 memcpy (tmpbuf, valbuf,
2475 len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
2476 regcache_cooked_write (regs, regno++, tmpbuf);
2477 len -= INT_REGISTER_RAW_SIZE;
2478 valbuf += INT_REGISTER_RAW_SIZE;
2479 }
2480 }
2481 }
2482
2483 static int
2484 arm_get_longjmp_target (CORE_ADDR *pc)
2485 {
2486 CORE_ADDR jb_addr;
2487 char buf[INT_REGISTER_RAW_SIZE];
2488 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2489
2490 jb_addr = read_register (ARM_A1_REGNUM);
2491
2492 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2493 INT_REGISTER_RAW_SIZE))
2494 return 0;
2495
2496 *pc = extract_address (buf, INT_REGISTER_RAW_SIZE);
2497 return 1;
2498 }
2499
2500 /* Return non-zero if the PC is inside a thumb call thunk. */
2501
2502 int
2503 arm_in_call_stub (CORE_ADDR pc, char *name)
2504 {
2505 CORE_ADDR start_addr;
2506
2507 /* Find the starting address of the function containing the PC. If
2508 the caller didn't give us a name, look it up at the same time. */
2509 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2510 &start_addr, NULL))
2511 return 0;
2512
2513 return strncmp (name, "_call_via_r", 11) == 0;
2514 }
2515
2516 /* If PC is in a Thumb call or return stub, return the address of the
2517 target PC, which is in a register. The thunk functions are called
2518 _called_via_xx, where x is the register name. The possible names
2519 are r0-r9, sl, fp, ip, sp, and lr. */
2520
2521 CORE_ADDR
2522 arm_skip_stub (CORE_ADDR pc)
2523 {
2524 char *name;
2525 CORE_ADDR start_addr;
2526
2527 /* Find the starting address and name of the function containing the PC. */
2528 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2529 return 0;
2530
2531 /* Call thunks always start with "_call_via_". */
2532 if (strncmp (name, "_call_via_", 10) == 0)
2533 {
2534 /* Use the name suffix to determine which register contains the
2535 target PC. */
2536 static char *table[15] =
2537 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2538 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2539 };
2540 int regno;
2541
2542 for (regno = 0; regno <= 14; regno++)
2543 if (strcmp (&name[10], table[regno]) == 0)
2544 return read_register (regno);
2545 }
2546
2547 return 0; /* not a stub */
2548 }
2549
2550 static void
2551 set_arm_command (char *args, int from_tty)
2552 {
2553 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2554 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2555 }
2556
2557 static void
2558 show_arm_command (char *args, int from_tty)
2559 {
2560 cmd_show_list (showarmcmdlist, from_tty, "");
2561 }
2562
2563 enum arm_float_model
2564 arm_get_fp_model (struct gdbarch *gdbarch)
2565 {
2566 if (arm_fp_model == ARM_FLOAT_AUTO)
2567 return gdbarch_tdep (gdbarch)->fp_model;
2568
2569 return arm_fp_model;
2570 }
2571
2572 static void
2573 arm_set_fp (struct gdbarch *gdbarch)
2574 {
2575 enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
2576
2577 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2578 && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
2579 {
2580 set_gdbarch_double_format (gdbarch,
2581 &floatformat_ieee_double_littlebyte_bigword);
2582 set_gdbarch_long_double_format
2583 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2584 }
2585 else
2586 {
2587 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2588 set_gdbarch_long_double_format (gdbarch,
2589 &floatformat_ieee_double_little);
2590 }
2591 }
2592
2593 static void
2594 set_fp_model_sfunc (char *args, int from_tty,
2595 struct cmd_list_element *c)
2596 {
2597 enum arm_float_model fp_model;
2598
2599 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2600 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2601 {
2602 arm_fp_model = fp_model;
2603 break;
2604 }
2605
2606 if (fp_model == ARM_FLOAT_LAST)
2607 internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.",
2608 current_fp_model);
2609
2610 if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2611 arm_set_fp (current_gdbarch);
2612 }
2613
2614 static void
2615 show_fp_model (char *args, int from_tty,
2616 struct cmd_list_element *c)
2617 {
2618 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2619
2620 if (arm_fp_model == ARM_FLOAT_AUTO
2621 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2622 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2623 fp_model_strings[tdep->fp_model]);
2624 }
2625
2626 /* If the user changes the register disassembly style used for info
2627 register and other commands, we have to also switch the style used
2628 in opcodes for disassembly output. This function is run in the "set
2629 arm disassembly" command, and does that. */
2630
2631 static void
2632 set_disassembly_style_sfunc (char *args, int from_tty,
2633 struct cmd_list_element *c)
2634 {
2635 set_disassembly_style ();
2636 }
2637 \f
2638 /* Return the ARM register name corresponding to register I. */
2639 static const char *
2640 arm_register_name (int i)
2641 {
2642 return arm_register_names[i];
2643 }
2644
2645 static void
2646 set_disassembly_style (void)
2647 {
2648 const char *setname, *setdesc, **regnames;
2649 int numregs, j;
2650
2651 /* Find the style that the user wants in the opcodes table. */
2652 int current = 0;
2653 numregs = get_arm_regnames (current, &setname, &setdesc, &regnames);
2654 while ((disassembly_style != setname)
2655 && (current < num_disassembly_options))
2656 get_arm_regnames (++current, &setname, &setdesc, &regnames);
2657 current_option = current;
2658
2659 /* Fill our copy. */
2660 for (j = 0; j < numregs; j++)
2661 arm_register_names[j] = (char *) regnames[j];
2662
2663 /* Adjust case. */
2664 if (isupper (*regnames[ARM_PC_REGNUM]))
2665 {
2666 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2667 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2668 }
2669 else
2670 {
2671 arm_register_names[ARM_FPS_REGNUM] = "fps";
2672 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2673 }
2674
2675 /* Synchronize the disassembler. */
2676 set_arm_regname_option (current);
2677 }
2678
2679 /* arm_othernames implements the "othernames" command. This is deprecated
2680 by the "set arm disassembly" command. */
2681
2682 static void
2683 arm_othernames (char *names, int n)
2684 {
2685 /* Circle through the various flavors. */
2686 current_option = (current_option + 1) % num_disassembly_options;
2687
2688 disassembly_style = valid_disassembly_styles[current_option];
2689 set_disassembly_style ();
2690 }
2691
2692 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2693 for ARM linux targets using the struct offsets defined in <link.h>.
2694 Note, however, that link.h is not actually referred to in this file.
2695 Instead, the relevant structs offsets were obtained from examining
2696 link.h. (We can't refer to link.h from this file because the host
2697 system won't necessarily have it, or if it does, the structs which
2698 it defines will refer to the host system, not the target). */
2699
2700 struct link_map_offsets *
2701 arm_linux_svr4_fetch_link_map_offsets (void)
2702 {
2703 static struct link_map_offsets lmo;
2704 static struct link_map_offsets *lmp = 0;
2705
2706 if (lmp == 0)
2707 {
2708 lmp = &lmo;
2709
2710 lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
2711 need. */
2712
2713 lmo.r_map_offset = 4;
2714 lmo.r_map_size = 4;
2715
2716 lmo.link_map_size = 20; /* Actual size is 552, but this is all we
2717 need. */
2718
2719 lmo.l_addr_offset = 0;
2720 lmo.l_addr_size = 4;
2721
2722 lmo.l_name_offset = 4;
2723 lmo.l_name_size = 4;
2724
2725 lmo.l_next_offset = 12;
2726 lmo.l_next_size = 4;
2727
2728 lmo.l_prev_offset = 16;
2729 lmo.l_prev_size = 4;
2730 }
2731
2732 return lmp;
2733 }
2734
2735 /* Test whether the coff symbol specific value corresponds to a Thumb
2736 function. */
2737
2738 static int
2739 coff_sym_is_thumb (int val)
2740 {
2741 return (val == C_THUMBEXT ||
2742 val == C_THUMBSTAT ||
2743 val == C_THUMBEXTFUNC ||
2744 val == C_THUMBSTATFUNC ||
2745 val == C_THUMBLABEL);
2746 }
2747
2748 /* arm_coff_make_msymbol_special()
2749 arm_elf_make_msymbol_special()
2750
2751 These functions test whether the COFF or ELF symbol corresponds to
2752 an address in thumb code, and set a "special" bit in a minimal
2753 symbol to indicate that it does. */
2754
2755 static void
2756 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2757 {
2758 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2759 STT_ARM_TFUNC). */
2760 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2761 == STT_LOPROC)
2762 MSYMBOL_SET_SPECIAL (msym);
2763 }
2764
2765 static void
2766 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2767 {
2768 if (coff_sym_is_thumb (val))
2769 MSYMBOL_SET_SPECIAL (msym);
2770 }
2771
2772 \f
2773 static enum gdb_osabi
2774 arm_elf_osabi_sniffer (bfd *abfd)
2775 {
2776 unsigned int elfosabi, eflags;
2777 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2778
2779 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2780
2781 switch (elfosabi)
2782 {
2783 case ELFOSABI_NONE:
2784 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2785 file are conforming to the base specification for that machine
2786 (there are no OS-specific extensions). In order to determine the
2787 real OS in use we must look for OS notes that have been added. */
2788 bfd_map_over_sections (abfd,
2789 generic_elf_osabi_sniff_abi_tag_sections,
2790 &osabi);
2791 if (osabi == GDB_OSABI_UNKNOWN)
2792 {
2793 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2794 field for more information. */
2795 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2796 switch (eflags)
2797 {
2798 case EF_ARM_EABI_VER1:
2799 osabi = GDB_OSABI_ARM_EABI_V1;
2800 break;
2801
2802 case EF_ARM_EABI_VER2:
2803 osabi = GDB_OSABI_ARM_EABI_V2;
2804 break;
2805
2806 case EF_ARM_EABI_UNKNOWN:
2807 /* Assume GNU tools. */
2808 osabi = GDB_OSABI_ARM_APCS;
2809 break;
2810
2811 default:
2812 internal_error (__FILE__, __LINE__,
2813 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2814 "version 0x%x", eflags);
2815 }
2816 }
2817 break;
2818
2819 case ELFOSABI_ARM:
2820 /* GNU tools use this value. Check note sections in this case,
2821 as well. */
2822 bfd_map_over_sections (abfd,
2823 generic_elf_osabi_sniff_abi_tag_sections,
2824 &osabi);
2825 if (osabi == GDB_OSABI_UNKNOWN)
2826 {
2827 /* Assume APCS ABI. */
2828 osabi = GDB_OSABI_ARM_APCS;
2829 }
2830 break;
2831
2832 case ELFOSABI_FREEBSD:
2833 osabi = GDB_OSABI_FREEBSD_ELF;
2834 break;
2835
2836 case ELFOSABI_NETBSD:
2837 osabi = GDB_OSABI_NETBSD_ELF;
2838 break;
2839
2840 case ELFOSABI_LINUX:
2841 osabi = GDB_OSABI_LINUX;
2842 break;
2843 }
2844
2845 return osabi;
2846 }
2847
2848 \f
2849 /* Initialize the current architecture based on INFO. If possible,
2850 re-use an architecture from ARCHES, which is a list of
2851 architectures already created during this debugging session.
2852
2853 Called e.g. at program startup, when reading a core file, and when
2854 reading a binary file. */
2855
2856 static struct gdbarch *
2857 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2858 {
2859 struct gdbarch_tdep *tdep;
2860 struct gdbarch *gdbarch;
2861
2862 /* Try to deterimine the ABI of the object we are loading. */
2863
2864 if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
2865 {
2866 switch (bfd_get_flavour (info.abfd))
2867 {
2868 case bfd_target_aout_flavour:
2869 /* Assume it's an old APCS-style ABI. */
2870 info.osabi = GDB_OSABI_ARM_APCS;
2871 break;
2872
2873 case bfd_target_coff_flavour:
2874 /* Assume it's an old APCS-style ABI. */
2875 /* XXX WinCE? */
2876 info.osabi = GDB_OSABI_ARM_APCS;
2877 break;
2878
2879 default:
2880 /* Leave it as "unknown". */
2881 break;
2882 }
2883 }
2884
2885 /* If there is already a candidate, use it. */
2886 arches = gdbarch_list_lookup_by_info (arches, &info);
2887 if (arches != NULL)
2888 return arches->gdbarch;
2889
2890 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2891 gdbarch = gdbarch_alloc (&info, tdep);
2892
2893 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2894 ready to unwind the PC first (see frame.c:get_prev_frame()). */
2895 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
2896
2897 /* We used to default to FPA for generic ARM, but almost nobody uses that
2898 now, and we now provide a way for the user to force the model. So
2899 default to the most useful variant. */
2900 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
2901
2902 /* Breakpoints. */
2903 switch (info.byte_order)
2904 {
2905 case BFD_ENDIAN_BIG:
2906 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2907 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2908 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2909 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2910
2911 break;
2912
2913 case BFD_ENDIAN_LITTLE:
2914 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2915 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2916 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2917 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2918
2919 break;
2920
2921 default:
2922 internal_error (__FILE__, __LINE__,
2923 "arm_gdbarch_init: bad byte order for float format");
2924 }
2925
2926 /* On ARM targets char defaults to unsigned. */
2927 set_gdbarch_char_signed (gdbarch, 0);
2928
2929 /* This should be low enough for everything. */
2930 tdep->lowest_pc = 0x20;
2931 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2932
2933 set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
2934 set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
2935
2936 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2937
2938 /* Frame handling. */
2939 set_gdbarch_deprecated_frame_chain_valid (gdbarch, arm_frame_chain_valid);
2940 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, arm_init_extra_frame_info);
2941 set_gdbarch_read_fp (gdbarch, arm_read_fp);
2942 set_gdbarch_deprecated_frame_chain (gdbarch, arm_frame_chain);
2943 set_gdbarch_frameless_function_invocation
2944 (gdbarch, arm_frameless_function_invocation);
2945 set_gdbarch_deprecated_frame_saved_pc (gdbarch, arm_frame_saved_pc);
2946 set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address);
2947 set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address);
2948 set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args);
2949 set_gdbarch_frame_args_skip (gdbarch, 0);
2950 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs);
2951 set_gdbarch_deprecated_pop_frame (gdbarch, arm_pop_frame);
2952
2953 /* Address manipulation. */
2954 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2955 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2956
2957 /* Offset from address of function to start of its code. */
2958 set_gdbarch_function_start_offset (gdbarch, 0);
2959
2960 /* Advance PC across function entry code. */
2961 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2962
2963 /* Get the PC when a frame might not be available. */
2964 set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2965
2966 /* The stack grows downward. */
2967 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2968
2969 /* Breakpoint manipulation. */
2970 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2971 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2972
2973 /* Information about registers, etc. */
2974 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2975 set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2976 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2977 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2978 set_gdbarch_register_byte (gdbarch, arm_register_byte);
2979 set_gdbarch_register_bytes (gdbarch,
2980 (NUM_GREGS * INT_REGISTER_RAW_SIZE
2981 + NUM_FREGS * FP_REGISTER_RAW_SIZE
2982 + NUM_SREGS * STATUS_REGISTER_SIZE));
2983 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2984 set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size);
2985 set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size);
2986 set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
2987 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
2988 set_gdbarch_register_virtual_type (gdbarch, arm_register_type);
2989
2990 /* Internal <-> external register number maps. */
2991 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2992
2993 /* Integer registers are 4 bytes. */
2994 set_gdbarch_register_size (gdbarch, 4);
2995 set_gdbarch_register_name (gdbarch, arm_register_name);
2996
2997 /* Returning results. */
2998 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2999 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
3000 set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
3001 set_gdbarch_extract_struct_value_address (gdbarch,
3002 arm_extract_struct_value_address);
3003
3004 /* Single stepping. */
3005 /* XXX For an RDI target we should ask the target if it can single-step. */
3006 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
3007
3008 /* Disassembly. */
3009 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3010
3011 /* Minsymbol frobbing. */
3012 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3013 set_gdbarch_coff_make_msymbol_special (gdbarch,
3014 arm_coff_make_msymbol_special);
3015
3016 /* Hook in the ABI-specific overrides, if they have been registered. */
3017 gdbarch_init_osabi (info, gdbarch);
3018
3019 /* Now we have tuned the configuration, set a few final things,
3020 based on what the OS ABI has told us. */
3021
3022 if (tdep->jb_pc >= 0)
3023 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3024
3025 /* Floating point sizes and format. */
3026 switch (info.byte_order)
3027 {
3028 case BFD_ENDIAN_BIG:
3029 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
3030 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
3031 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
3032
3033 break;
3034
3035 case BFD_ENDIAN_LITTLE:
3036 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
3037 arm_set_fp (gdbarch);
3038 break;
3039
3040 default:
3041 internal_error (__FILE__, __LINE__,
3042 "arm_gdbarch_init: bad byte order for float format");
3043 }
3044
3045 return gdbarch;
3046 }
3047
3048 static void
3049 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3050 {
3051 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3052
3053 if (tdep == NULL)
3054 return;
3055
3056 fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
3057 (unsigned long) tdep->lowest_pc);
3058 }
3059
3060 static void
3061 arm_init_abi_eabi_v1 (struct gdbarch_info info,
3062 struct gdbarch *gdbarch)
3063 {
3064 /* Place-holder. */
3065 }
3066
3067 static void
3068 arm_init_abi_eabi_v2 (struct gdbarch_info info,
3069 struct gdbarch *gdbarch)
3070 {
3071 /* Place-holder. */
3072 }
3073
3074 static void
3075 arm_init_abi_apcs (struct gdbarch_info info,
3076 struct gdbarch *gdbarch)
3077 {
3078 /* Place-holder. */
3079 }
3080
3081 void
3082 _initialize_arm_tdep (void)
3083 {
3084 struct ui_file *stb;
3085 long length;
3086 struct cmd_list_element *new_set, *new_show;
3087 const char *setname;
3088 const char *setdesc;
3089 const char **regnames;
3090 int numregs, i, j;
3091 static char *helptext;
3092
3093 if (GDB_MULTI_ARCH)
3094 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3095
3096 /* Register an ELF OS ABI sniffer for ARM binaries. */
3097 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3098 bfd_target_elf_flavour,
3099 arm_elf_osabi_sniffer);
3100
3101 /* Register some ABI variants for embedded systems. */
3102 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
3103 arm_init_abi_eabi_v1);
3104 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
3105 arm_init_abi_eabi_v2);
3106 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
3107 arm_init_abi_apcs);
3108
3109 /* Get the number of possible sets of register names defined in opcodes. */
3110 num_disassembly_options = get_arm_regname_num_options ();
3111
3112 /* Add root prefix command for all "set arm"/"show arm" commands. */
3113 add_prefix_cmd ("arm", no_class, set_arm_command,
3114 "Various ARM-specific commands.",
3115 &setarmcmdlist, "set arm ", 0, &setlist);
3116
3117 add_prefix_cmd ("arm", no_class, show_arm_command,
3118 "Various ARM-specific commands.",
3119 &showarmcmdlist, "show arm ", 0, &showlist);
3120
3121 /* Sync the opcode insn printer with our register viewer. */
3122 parse_arm_disassembler_option ("reg-names-std");
3123
3124 /* Begin creating the help text. */
3125 stb = mem_fileopen ();
3126 fprintf_unfiltered (stb, "Set the disassembly style.\n"
3127 "The valid values are:\n");
3128
3129 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3130 valid_disassembly_styles
3131 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3132 for (i = 0; i < num_disassembly_options; i++)
3133 {
3134 numregs = get_arm_regnames (i, &setname, &setdesc, &regnames);
3135 valid_disassembly_styles[i] = setname;
3136 fprintf_unfiltered (stb, "%s - %s\n", setname,
3137 setdesc);
3138 /* Copy the default names (if found) and synchronize disassembler. */
3139 if (!strcmp (setname, "std"))
3140 {
3141 disassembly_style = setname;
3142 current_option = i;
3143 for (j = 0; j < numregs; j++)
3144 arm_register_names[j] = (char *) regnames[j];
3145 set_arm_regname_option (i);
3146 }
3147 }
3148 /* Mark the end of valid options. */
3149 valid_disassembly_styles[num_disassembly_options] = NULL;
3150
3151 /* Finish the creation of the help text. */
3152 fprintf_unfiltered (stb, "The default is \"std\".");
3153 helptext = ui_file_xstrdup (stb, &length);
3154 ui_file_delete (stb);
3155
3156 /* Add the deprecated disassembly-flavor command. */
3157 new_set = add_set_enum_cmd ("disassembly-flavor", no_class,
3158 valid_disassembly_styles,
3159 &disassembly_style,
3160 helptext,
3161 &setlist);
3162 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
3163 deprecate_cmd (new_set, "set arm disassembly");
3164 deprecate_cmd (add_show_from_set (new_set, &showlist),
3165 "show arm disassembly");
3166
3167 /* And now add the new interface. */
3168 new_set = add_set_enum_cmd ("disassembler", no_class,
3169 valid_disassembly_styles, &disassembly_style,
3170 helptext, &setarmcmdlist);
3171
3172 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
3173 add_show_from_set (new_set, &showarmcmdlist);
3174
3175 add_setshow_cmd_full ("apcs32", no_class,
3176 var_boolean, (char *) &arm_apcs_32,
3177 "Set usage of ARM 32-bit mode.",
3178 "Show usage of ARM 32-bit mode.",
3179 NULL, NULL,
3180 &setlist, &showlist, &new_set, &new_show);
3181 deprecate_cmd (new_set, "set arm apcs32");
3182 deprecate_cmd (new_show, "show arm apcs32");
3183
3184 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3185 "Set usage of ARM 32-bit mode. "
3186 "When off, a 26-bit PC will be used.",
3187 "Show usage of ARM 32-bit mode. "
3188 "When off, a 26-bit PC will be used.",
3189 NULL, NULL,
3190 &setarmcmdlist, &showarmcmdlist);
3191
3192 /* Add a command to allow the user to force the FPU model. */
3193 new_set = add_set_enum_cmd
3194 ("fpu", no_class, fp_model_strings, &current_fp_model,
3195 "Set the floating point type.\n"
3196 "auto - Determine the FP typefrom the OS-ABI.\n"
3197 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
3198 "fpa - FPA co-processor (GCC compiled).\n"
3199 "softvfp - Software FP with pure-endian doubles.\n"
3200 "vfp - VFP co-processor.",
3201 &setarmcmdlist);
3202 set_cmd_sfunc (new_set, set_fp_model_sfunc);
3203 set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model);
3204
3205 /* Add the deprecated "othernames" command. */
3206 deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames,
3207 "Switch to the next set of register names."),
3208 "set arm disassembly");
3209
3210 /* Debugging flag. */
3211 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3212 "Set ARM debugging. "
3213 "When on, arm-specific debugging is enabled.",
3214 "Show ARM debugging. "
3215 "When on, arm-specific debugging is enabled.",
3216 NULL, NULL,
3217 &setdebuglist, &showdebuglist);
3218 }
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