1 /* Common target dependent code for GDB on ARM systems.
3 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose.
86 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
87 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
89 #define MSYMBOL_SET_SPECIAL(msym) \
90 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
93 #define MSYMBOL_IS_SPECIAL(msym) \
94 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
96 /* The list of available "set arm ..." and "show arm ..." commands. */
97 static struct cmd_list_element
*setarmcmdlist
= NULL
;
98 static struct cmd_list_element
*showarmcmdlist
= NULL
;
100 /* The type of floating-point to use. Keep this in sync with enum
101 arm_float_model, and the help string in _initialize_arm_tdep. */
102 static const char *fp_model_strings
[] =
111 /* A variable that can be configured by the user. */
112 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
113 static const char *current_fp_model
= "auto";
115 /* Number of different reg name sets (options). */
116 static int num_disassembly_options
;
118 /* We have more registers than the disassembler as gdb can print the value
119 of special registers as well.
120 The general register names are overwritten by whatever is being used by
121 the disassembler at the moment. We also adjust the case of cpsr and fps. */
123 /* Initial value: Register names used in ARM's ISA documentation. */
124 static char * arm_register_name_strings
[] =
125 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
126 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
127 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
128 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
129 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
130 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
131 "fps", "cpsr" }; /* 24 25 */
132 static char **arm_register_names
= arm_register_name_strings
;
134 /* Valid register name styles. */
135 static const char **valid_disassembly_styles
;
137 /* Disassembly style to use. Default to "std" register names. */
138 static const char *disassembly_style
;
139 /* Index to that option in the opcodes table. */
140 static int current_option
;
142 /* This is used to keep the bfd arch_info in sync with the disassembly
144 static void set_disassembly_style_sfunc(char *, int,
145 struct cmd_list_element
*);
146 static void set_disassembly_style (void);
148 static void convert_from_extended (const struct floatformat
*, const void *,
150 static void convert_to_extended (const struct floatformat
*, void *,
153 struct arm_prologue_cache
155 /* The stack pointer at the time this frame was created; i.e. the
156 caller's stack pointer when this function was called. It is used
157 to identify this frame. */
160 /* The frame base for this frame is just prev_sp + frame offset -
161 frame size. FRAMESIZE is the size of this stack frame, and
162 FRAMEOFFSET if the initial offset from the stack pointer (this
163 frame's stack pointer, not PREV_SP) to the frame base. */
168 /* The register used to hold the frame pointer for this frame. */
171 /* Saved register offsets. */
172 struct trad_frame_saved_reg
*saved_regs
;
175 /* Addresses for calling Thumb functions have the bit 0 set.
176 Here are some macros to test, set, or clear bit 0 of addresses. */
177 #define IS_THUMB_ADDR(addr) ((addr) & 1)
178 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
179 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
181 /* Set to true if the 32-bit mode is in use. */
185 /* Flag set by arm_fix_call_dummy that tells whether the target
186 function is a Thumb function. This flag is checked by
187 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
188 its use in valops.c) to pass the function address as an additional
191 static int target_is_thumb
;
193 /* Flag set by arm_fix_call_dummy that tells whether the calling
194 function is a Thumb function. This flag is checked by
197 static int caller_is_thumb
;
199 /* Determine if the program counter specified in MEMADDR is in a Thumb
203 arm_pc_is_thumb (CORE_ADDR memaddr
)
205 struct minimal_symbol
*sym
;
207 /* If bit 0 of the address is set, assume this is a Thumb address. */
208 if (IS_THUMB_ADDR (memaddr
))
211 /* Thumb functions have a "special" bit set in minimal symbols. */
212 sym
= lookup_minimal_symbol_by_pc (memaddr
);
215 return (MSYMBOL_IS_SPECIAL (sym
));
223 /* Determine if the program counter specified in MEMADDR is in a call
224 dummy being called from a Thumb function. */
227 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
229 CORE_ADDR sp
= read_sp ();
231 /* FIXME: Until we switch for the new call dummy macros, this heuristic
232 is the best we can do. We are trying to determine if the pc is on
233 the stack, which (hopefully) will only happen in a call dummy.
234 We hope the current stack pointer is not so far alway from the dummy
235 frame location (true if we have not pushed large data structures or
236 gone too many levels deep) and that our 1024 is not enough to consider
237 code regions as part of the stack (true for most practical purposes). */
238 if (deprecated_pc_in_call_dummy (memaddr
))
239 return caller_is_thumb
;
244 /* Remove useless bits from addresses in a running program. */
246 arm_addr_bits_remove (CORE_ADDR val
)
249 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
251 return (val
& 0x03fffffc);
254 /* When reading symbols, we need to zap the low bit of the address,
255 which may be set to 1 for Thumb functions. */
257 arm_smash_text_address (CORE_ADDR val
)
262 /* Immediately after a function call, return the saved pc. Can't
263 always go through the frames for this because on some machines the
264 new frame is not set up until the new function executes some
268 arm_saved_pc_after_call (struct frame_info
*frame
)
270 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
273 /* A typical Thumb prologue looks like this:
277 Sometimes the latter instruction may be replaced by:
285 or, on tpcs, like this:
292 There is always one instruction of three classes:
297 When we have found at least one of each class we are done with the prolog.
298 Note that the "sub sp, #NN" before the push does not count.
302 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
304 CORE_ADDR current_pc
;
306 bit 0 - push { rlist }
307 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
308 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
312 for (current_pc
= pc
;
313 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
316 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
318 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
320 findmask
|= 1; /* push found */
322 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
325 if ((findmask
& 1) == 0) /* before push ? */
328 findmask
|= 4; /* add/sub sp found */
330 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
332 findmask
|= 2; /* setting of r7 found */
334 else if (insn
== 0x466f) /* mov r7, sp */
336 findmask
|= 2; /* setting of r7 found */
338 else if (findmask
== (4+2+1))
340 /* We have found one of each type of prologue instruction */
344 /* Something in the prolog that we don't care about or some
345 instruction from outside the prolog scheduled here for
353 /* Advance the PC across any function entry prologue instructions to
354 reach some "real" code.
356 The APCS (ARM Procedure Call Standard) defines the following
360 [stmfd sp!, {a1,a2,a3,a4}]
361 stmfd sp!, {...,fp,ip,lr,pc}
362 [stfe f7, [sp, #-12]!]
363 [stfe f6, [sp, #-12]!]
364 [stfe f5, [sp, #-12]!]
365 [stfe f4, [sp, #-12]!]
366 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
369 arm_skip_prologue (CORE_ADDR pc
)
373 CORE_ADDR func_addr
, func_end
= 0;
375 struct symtab_and_line sal
;
377 /* If we're in a dummy frame, don't even try to skip the prologue. */
378 if (deprecated_pc_in_call_dummy (pc
))
381 /* See what the symbol table says. */
383 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
387 /* Found a function. */
388 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
389 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
391 /* Don't use this trick for assembly source files. */
392 sal
= find_pc_line (func_addr
, 0);
393 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
398 /* Check if this is Thumb code. */
399 if (arm_pc_is_thumb (pc
))
400 return thumb_skip_prologue (pc
, func_end
);
402 /* Can't find the prologue end in the symbol table, try it the hard way
403 by disassembling the instructions. */
405 /* Like arm_scan_prologue, stop no later than pc + 64. */
406 if (func_end
== 0 || func_end
> pc
+ 64)
409 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
411 inst
= read_memory_integer (skip_pc
, 4);
413 /* "mov ip, sp" is no longer a required part of the prologue. */
414 if (inst
== 0xe1a0c00d) /* mov ip, sp */
417 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
420 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
423 /* Some prologues begin with "str lr, [sp, #-4]!". */
424 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
427 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
430 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
433 /* Any insns after this point may float into the code, if it makes
434 for better instruction scheduling, so we skip them only if we
435 find them, but still consider the function to be frame-ful. */
437 /* We may have either one sfmfd instruction here, or several stfe
438 insns, depending on the version of floating point code we
440 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
443 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
446 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
449 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
452 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
453 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
454 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
457 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
458 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
459 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
462 /* Un-recognized instruction; stop scanning. */
466 return skip_pc
; /* End of prologue */
470 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
471 This function decodes a Thumb function prologue to determine:
472 1) the size of the stack frame
473 2) which registers are saved on it
474 3) the offsets of saved regs
475 4) the offset from the stack pointer to the frame pointer
477 A typical Thumb function prologue would create this stack frame
478 (offsets relative to FP)
479 old SP -> 24 stack parameters
482 R7 -> 0 local variables (16 bytes)
483 SP -> -12 additional stack space (12 bytes)
484 The frame size would thus be 36 bytes, and the frame offset would be
485 12 bytes. The frame register is R7.
487 The comments for thumb_skip_prolog() describe the algorithm we use
488 to detect the end of the prolog. */
492 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
494 CORE_ADDR prologue_start
;
495 CORE_ADDR prologue_end
;
496 CORE_ADDR current_pc
;
497 /* Which register has been copied to register n? */
500 bit 0 - push { rlist }
501 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
502 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
507 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
509 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
511 if (sal
.line
== 0) /* no line info, use current PC */
512 prologue_end
= prev_pc
;
513 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
514 prologue_end
= sal
.end
; /* (probably means no prologue) */
517 /* We're in the boondocks: allow for
518 16 pushes, an add, and "mv fp,sp". */
519 prologue_end
= prologue_start
+ 40;
521 prologue_end
= min (prologue_end
, prev_pc
);
523 /* Initialize the saved register map. When register H is copied to
524 register L, we will put H in saved_reg[L]. */
525 for (i
= 0; i
< 16; i
++)
528 /* Search the prologue looking for instructions that set up the
529 frame pointer, adjust the stack pointer, and save registers.
530 Do this until all basic prolog instructions are found. */
532 cache
->framesize
= 0;
533 for (current_pc
= prologue_start
;
534 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
541 insn
= read_memory_unsigned_integer (current_pc
, 2);
543 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
546 findmask
|= 1; /* push found */
547 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
548 whether to save LR (R14). */
549 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
551 /* Calculate offsets of saved R0-R7 and LR. */
552 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
553 if (mask
& (1 << regno
))
555 cache
->framesize
+= 4;
556 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
557 /* Reset saved register map. */
558 saved_reg
[regno
] = regno
;
561 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
564 if ((findmask
& 1) == 0) /* before push? */
567 findmask
|= 4; /* add/sub sp found */
569 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
570 if (insn
& 0x80) /* is it signed? (==subtracting) */
572 cache
->frameoffset
+= offset
;
575 cache
->framesize
-= offset
;
577 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
579 findmask
|= 2; /* setting of r7 found */
580 cache
->framereg
= THUMB_FP_REGNUM
;
581 /* get scaled offset */
582 cache
->frameoffset
= (insn
& 0xff) << 2;
584 else if (insn
== 0x466f) /* mov r7, sp */
586 findmask
|= 2; /* setting of r7 found */
587 cache
->framereg
= THUMB_FP_REGNUM
;
588 cache
->frameoffset
= 0;
589 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
591 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
593 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
594 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
595 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
598 /* Something in the prolog that we don't care about or some
599 instruction from outside the prolog scheduled here for
605 /* This function decodes an ARM function prologue to determine:
606 1) the size of the stack frame
607 2) which registers are saved on it
608 3) the offsets of saved regs
609 4) the offset from the stack pointer to the frame pointer
610 This information is stored in the "extra" fields of the frame_info.
612 There are two basic forms for the ARM prologue. The fixed argument
613 function call will look like:
616 stmfd sp!, {fp, ip, lr, pc}
620 Which would create this stack frame (offsets relative to FP):
621 IP -> 4 (caller's stack)
622 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
623 -4 LR (return address in caller)
624 -8 IP (copy of caller's SP)
626 SP -> -28 Local variables
628 The frame size would thus be 32 bytes, and the frame offset would be
629 28 bytes. The stmfd call can also save any of the vN registers it
630 plans to use, which increases the frame size accordingly.
632 Note: The stored PC is 8 off of the STMFD instruction that stored it
633 because the ARM Store instructions always store PC + 8 when you read
636 A variable argument function call will look like:
639 stmfd sp!, {a1, a2, a3, a4}
640 stmfd sp!, {fp, ip, lr, pc}
643 Which would create this stack frame (offsets relative to FP):
644 IP -> 20 (caller's stack)
649 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
650 -4 LR (return address in caller)
651 -8 IP (copy of caller's SP)
653 SP -> -28 Local variables
655 The frame size would thus be 48 bytes, and the frame offset would be
658 There is another potential complication, which is that the optimizer
659 will try to separate the store of fp in the "stmfd" instruction from
660 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
661 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
663 Also, note, the original version of the ARM toolchain claimed that there
666 instruction at the end of the prologue. I have never seen GCC produce
667 this, and the ARM docs don't mention it. We still test for it below in
673 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
675 int regno
, sp_offset
, fp_offset
, ip_offset
;
676 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
677 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
679 /* Assume there is no frame until proven otherwise. */
680 cache
->framereg
= ARM_SP_REGNUM
;
681 cache
->framesize
= 0;
682 cache
->frameoffset
= 0;
684 /* Check for Thumb prologue. */
685 if (arm_pc_is_thumb (prev_pc
))
687 thumb_scan_prologue (prev_pc
, cache
);
691 /* Find the function prologue. If we can't find the function in
692 the symbol table, peek in the stack frame to find the PC. */
693 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
695 /* One way to find the end of the prologue (which works well
696 for unoptimized code) is to do the following:
698 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
701 prologue_end = prev_pc;
702 else if (sal.end < prologue_end)
703 prologue_end = sal.end;
705 This mechanism is very accurate so long as the optimizer
706 doesn't move any instructions from the function body into the
707 prologue. If this happens, sal.end will be the last
708 instruction in the first hunk of prologue code just before
709 the first instruction that the scheduler has moved from
710 the body to the prologue.
712 In order to make sure that we scan all of the prologue
713 instructions, we use a slightly less accurate mechanism which
714 may scan more than necessary. To help compensate for this
715 lack of accuracy, the prologue scanning loop below contains
716 several clauses which'll cause the loop to terminate early if
717 an implausible prologue instruction is encountered.
723 is a suitable endpoint since it accounts for the largest
724 possible prologue plus up to five instructions inserted by
727 if (prologue_end
> prologue_start
+ 64)
729 prologue_end
= prologue_start
+ 64; /* See above. */
734 /* We have no symbol information. Our only option is to assume this
735 function has a standard stack frame and the normal frame register.
736 Then, we can find the value of our frame pointer on entrance to
737 the callee (or at the present moment if this is the innermost frame).
738 The value stored there should be the address of the stmfd + 8. */
740 LONGEST return_value
;
742 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
743 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
747 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
748 prologue_end
= prologue_start
+ 64; /* See above. */
752 if (prev_pc
< prologue_end
)
753 prologue_end
= prev_pc
;
755 /* Now search the prologue looking for instructions that set up the
756 frame pointer, adjust the stack pointer, and save registers.
758 Be careful, however, and if it doesn't look like a prologue,
759 don't try to scan it. If, for instance, a frameless function
760 begins with stmfd sp!, then we will tell ourselves there is
761 a frame, which will confuse stack traceback, as well as "finish"
762 and other operations that rely on a knowledge of the stack
765 In the APCS, the prologue should start with "mov ip, sp" so
766 if we don't see this as the first insn, we will stop.
768 [Note: This doesn't seem to be true any longer, so it's now an
769 optional part of the prologue. - Kevin Buettner, 2001-11-20]
771 [Note further: The "mov ip,sp" only seems to be missing in
772 frameless functions at optimization level "-O2" or above,
773 in which case it is often (but not always) replaced by
774 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
776 sp_offset
= fp_offset
= ip_offset
= 0;
778 for (current_pc
= prologue_start
;
779 current_pc
< prologue_end
;
782 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
784 if (insn
== 0xe1a0c00d) /* mov ip, sp */
789 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
791 unsigned imm
= insn
& 0xff; /* immediate value */
792 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
793 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
797 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
799 unsigned imm
= insn
& 0xff; /* immediate value */
800 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
801 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
805 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
808 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
811 else if ((insn
& 0xffff0000) == 0xe92d0000)
812 /* stmfd sp!, {..., fp, ip, lr, pc}
814 stmfd sp!, {a1, a2, a3, a4} */
816 int mask
= insn
& 0xffff;
818 /* Calculate offsets of saved registers. */
819 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
820 if (mask
& (1 << regno
))
823 cache
->saved_regs
[regno
].addr
= sp_offset
;
826 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
827 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
828 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
830 /* No need to add this to saved_regs -- it's just an arg reg. */
833 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
834 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
835 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
837 /* No need to add this to saved_regs -- it's just an arg reg. */
840 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
842 unsigned imm
= insn
& 0xff; /* immediate value */
843 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
844 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
845 fp_offset
= -imm
+ ip_offset
;
846 cache
->framereg
= ARM_FP_REGNUM
;
848 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
850 unsigned imm
= insn
& 0xff; /* immediate value */
851 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
852 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
855 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
858 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
859 cache
->saved_regs
[regno
].addr
= sp_offset
;
861 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
864 unsigned int fp_start_reg
, fp_bound_reg
;
866 if ((insn
& 0x800) == 0x800) /* N0 is set */
868 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
875 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
881 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
882 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
883 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
886 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
889 else if ((insn
& 0xf0000000) != 0xe0000000)
890 break; /* Condition not true, exit early */
891 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
892 break; /* Don't scan past a block load */
894 /* The optimizer might shove anything into the prologue,
895 so we just skip what we don't recognize. */
899 /* The frame size is just the negative of the offset (from the
900 original SP) of the last thing thing we pushed on the stack.
901 The frame offset is [new FP] - [new SP]. */
902 cache
->framesize
= -sp_offset
;
903 if (cache
->framereg
== ARM_FP_REGNUM
)
904 cache
->frameoffset
= fp_offset
- sp_offset
;
906 cache
->frameoffset
= 0;
909 static struct arm_prologue_cache
*
910 arm_make_prologue_cache (struct frame_info
*next_frame
)
913 struct arm_prologue_cache
*cache
;
914 CORE_ADDR unwound_fp
;
916 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
917 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
919 arm_scan_prologue (next_frame
, cache
);
921 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
925 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
927 /* Calculate actual addresses of saved registers using offsets
928 determined by arm_scan_prologue. */
929 for (reg
= 0; reg
< NUM_REGS
; reg
++)
930 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
931 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
936 /* Our frame ID for a normal frame is the current function's starting PC
937 and the caller's SP when we were called. */
940 arm_prologue_this_id (struct frame_info
*next_frame
,
942 struct frame_id
*this_id
)
944 struct arm_prologue_cache
*cache
;
948 if (*this_cache
== NULL
)
949 *this_cache
= arm_make_prologue_cache (next_frame
);
952 func
= frame_func_unwind (next_frame
);
954 /* This is meant to halt the backtrace at "_start". Make sure we
955 don't halt it at a generic dummy frame. */
956 if (func
<= LOWEST_PC
)
959 /* If we've hit a wall, stop. */
960 if (cache
->prev_sp
== 0)
963 id
= frame_id_build (cache
->prev_sp
, func
);
968 arm_prologue_prev_register (struct frame_info
*next_frame
,
972 enum lval_type
*lvalp
,
977 struct arm_prologue_cache
*cache
;
979 if (*this_cache
== NULL
)
980 *this_cache
= arm_make_prologue_cache (next_frame
);
983 /* If we are asked to unwind the PC, then we need to return the LR
984 instead. The saved value of PC points into this frame's
985 prologue, not the next frame's resume location. */
986 if (prev_regnum
== ARM_PC_REGNUM
)
987 prev_regnum
= ARM_LR_REGNUM
;
989 /* SP is generally not saved to the stack, but this frame is
990 identified by NEXT_FRAME's stack pointer at the time of the call.
991 The value was already reconstructed into PREV_SP. */
992 if (prev_regnum
== ARM_SP_REGNUM
)
996 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1000 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1001 optimized
, lvalp
, addrp
, realnump
, valuep
);
1004 struct frame_unwind arm_prologue_unwind
= {
1006 arm_prologue_this_id
,
1007 arm_prologue_prev_register
1010 static const struct frame_unwind
*
1011 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1013 return &arm_prologue_unwind
;
1017 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1019 struct arm_prologue_cache
*cache
;
1021 if (*this_cache
== NULL
)
1022 *this_cache
= arm_make_prologue_cache (next_frame
);
1023 cache
= *this_cache
;
1025 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1028 struct frame_base arm_normal_base
= {
1029 &arm_prologue_unwind
,
1030 arm_normal_frame_base
,
1031 arm_normal_frame_base
,
1032 arm_normal_frame_base
1035 static struct arm_prologue_cache
*
1036 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1038 struct arm_prologue_cache
*cache
;
1041 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1043 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1045 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1047 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1048 cache
->saved_regs
[reg
].addr
1049 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1050 frame_pc_unwind (next_frame
), reg
);
1052 /* FIXME: What about thumb mode? */
1053 cache
->framereg
= ARM_SP_REGNUM
;
1055 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1056 register_size (current_gdbarch
, cache
->framereg
));
1062 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1064 struct frame_id
*this_id
)
1066 struct arm_prologue_cache
*cache
;
1068 if (*this_cache
== NULL
)
1069 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1070 cache
= *this_cache
;
1072 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1073 the sigtramp frame; the PC should be the beginning of the trampoline. */
1074 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1078 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1082 enum lval_type
*lvalp
,
1087 struct arm_prologue_cache
*cache
;
1089 if (*this_cache
== NULL
)
1090 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1091 cache
= *this_cache
;
1093 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1094 optimized
, lvalp
, addrp
, realnump
, valuep
);
1097 struct frame_unwind arm_sigtramp_unwind
= {
1099 arm_sigtramp_this_id
,
1100 arm_sigtramp_prev_register
1103 static const struct frame_unwind
*
1104 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1106 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1107 && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame
), (char *) 0))
1108 return &arm_sigtramp_unwind
;
1113 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1114 dummy frame. The frame ID's base needs to match the TOS value
1115 saved by save_dummy_frame_tos() and returned from
1116 arm_push_dummy_call, and the PC needs to match the dummy frame's
1119 static struct frame_id
1120 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1122 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1123 frame_pc_unwind (next_frame
));
1126 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1127 be used to construct the previous frame's ID, after looking up the
1128 containing function). */
1131 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1134 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1135 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1139 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1141 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1144 /* When arguments must be pushed onto the stack, they go on in reverse
1145 order. The code below implements a FILO (stack) to do this. */
1150 struct stack_item
*prev
;
1154 static struct stack_item
*
1155 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1157 struct stack_item
*si
;
1158 si
= xmalloc (sizeof (struct stack_item
));
1159 si
->data
= xmalloc (len
);
1162 memcpy (si
->data
, contents
, len
);
1166 static struct stack_item
*
1167 pop_stack_item (struct stack_item
*si
)
1169 struct stack_item
*dead
= si
;
1176 /* We currently only support passing parameters in integer registers. This
1177 conforms with GCC's default model. Several other variants exist and
1178 we should probably support some of them based on the selected ABI. */
1181 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1182 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1183 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1184 CORE_ADDR struct_addr
)
1189 struct stack_item
*si
= NULL
;
1191 /* Set the return address. For the ARM, the return breakpoint is
1192 always at BP_ADDR. */
1193 /* XXX Fix for Thumb. */
1194 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1196 /* Walk through the list of args and determine how large a temporary
1197 stack is required. Need to take care here as structs may be
1198 passed on the stack, and we have to to push them. */
1201 argreg
= ARM_A1_REGNUM
;
1204 /* Some platforms require a double-word aligned stack. Make sure sp
1205 is correctly aligned before we start. We always do this even if
1206 it isn't really needed -- it can never hurt things. */
1207 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1209 /* The struct_return pointer occupies the first parameter
1210 passing register. */
1214 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1215 REGISTER_NAME (argreg
), paddr (struct_addr
));
1216 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1220 for (argnum
= 0; argnum
< nargs
; argnum
++)
1223 struct type
*arg_type
;
1224 struct type
*target_type
;
1225 enum type_code typecode
;
1228 arg_type
= check_typedef (value_type (args
[argnum
]));
1229 len
= TYPE_LENGTH (arg_type
);
1230 target_type
= TYPE_TARGET_TYPE (arg_type
);
1231 typecode
= TYPE_CODE (arg_type
);
1232 val
= value_contents_writeable (args
[argnum
]);
1234 /* If the argument is a pointer to a function, and it is a
1235 Thumb function, create a LOCAL copy of the value and set
1236 the THUMB bit in it. */
1237 if (TYPE_CODE_PTR
== typecode
1238 && target_type
!= NULL
1239 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1241 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1242 if (arm_pc_is_thumb (regval
))
1245 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1249 /* Copy the argument to general registers or the stack in
1250 register-sized pieces. Large arguments are split between
1251 registers and stack. */
1254 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1256 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1258 /* The argument is being passed in a general purpose
1260 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1262 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1263 argnum
, REGISTER_NAME (argreg
),
1264 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1265 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1270 /* Push the arguments onto the stack. */
1272 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1274 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1275 nstack
+= DEPRECATED_REGISTER_SIZE
;
1282 /* If we have an odd number of words to push, then decrement the stack
1283 by one word now, so first stack argument will be dword aligned. */
1290 write_memory (sp
, si
->data
, si
->len
);
1291 si
= pop_stack_item (si
);
1294 /* Finally, update teh SP register. */
1295 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1301 print_fpu_flags (int flags
)
1303 if (flags
& (1 << 0))
1304 fputs ("IVO ", stdout
);
1305 if (flags
& (1 << 1))
1306 fputs ("DVZ ", stdout
);
1307 if (flags
& (1 << 2))
1308 fputs ("OFL ", stdout
);
1309 if (flags
& (1 << 3))
1310 fputs ("UFL ", stdout
);
1311 if (flags
& (1 << 4))
1312 fputs ("INX ", stdout
);
1316 /* Print interesting information about the floating point processor
1317 (if present) or emulator. */
1319 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1320 struct frame_info
*frame
, const char *args
)
1322 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1325 type
= (status
>> 24) & 127;
1326 if (status
& (1 << 31))
1327 printf (_("Hardware FPU type %d\n"), type
);
1329 printf (_("Software FPU type %d\n"), type
);
1330 /* i18n: [floating point unit] mask */
1331 fputs (_("mask: "), stdout
);
1332 print_fpu_flags (status
>> 16);
1333 /* i18n: [floating point unit] flags */
1334 fputs (_("flags: "), stdout
);
1335 print_fpu_flags (status
);
1338 /* Return the GDB type object for the "standard" data type of data in
1341 static struct type
*
1342 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1344 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1346 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1347 return builtin_type_arm_ext_big
;
1349 return builtin_type_arm_ext_littlebyte_bigword
;
1352 return builtin_type_int32
;
1355 /* Index within `registers' of the first byte of the space for
1359 arm_register_byte (int regnum
)
1361 if (regnum
< ARM_F0_REGNUM
)
1362 return regnum
* INT_REGISTER_SIZE
;
1363 else if (regnum
< ARM_PS_REGNUM
)
1364 return (NUM_GREGS
* INT_REGISTER_SIZE
1365 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_SIZE
);
1367 return (NUM_GREGS
* INT_REGISTER_SIZE
1368 + NUM_FREGS
* FP_REGISTER_SIZE
1369 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1372 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1374 arm_register_sim_regno (int regnum
)
1377 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1379 if (reg
< NUM_GREGS
)
1380 return SIM_ARM_R0_REGNUM
+ reg
;
1383 if (reg
< NUM_FREGS
)
1384 return SIM_ARM_FP0_REGNUM
+ reg
;
1387 if (reg
< NUM_SREGS
)
1388 return SIM_ARM_FPS_REGNUM
+ reg
;
1391 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1394 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1395 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1396 It is thought that this is is the floating-point register format on
1397 little-endian systems. */
1400 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1404 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1405 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1407 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1409 floatformat_from_doublest (fmt
, &d
, dbl
);
1413 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1416 floatformat_to_doublest (fmt
, ptr
, &d
);
1417 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1418 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1420 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1425 condition_true (unsigned long cond
, unsigned long status_reg
)
1427 if (cond
== INST_AL
|| cond
== INST_NV
)
1433 return ((status_reg
& FLAG_Z
) != 0);
1435 return ((status_reg
& FLAG_Z
) == 0);
1437 return ((status_reg
& FLAG_C
) != 0);
1439 return ((status_reg
& FLAG_C
) == 0);
1441 return ((status_reg
& FLAG_N
) != 0);
1443 return ((status_reg
& FLAG_N
) == 0);
1445 return ((status_reg
& FLAG_V
) != 0);
1447 return ((status_reg
& FLAG_V
) == 0);
1449 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1451 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1453 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1455 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1457 return (((status_reg
& FLAG_Z
) == 0) &&
1458 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1460 return (((status_reg
& FLAG_Z
) != 0) ||
1461 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1466 /* Support routines for single stepping. Calculate the next PC value. */
1467 #define submask(x) ((1L << ((x) + 1)) - 1)
1468 #define bit(obj,st) (((obj) >> (st)) & 1)
1469 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1470 #define sbits(obj,st,fn) \
1471 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1472 #define BranchDest(addr,instr) \
1473 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1476 static unsigned long
1477 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1478 unsigned long status_reg
)
1480 unsigned long res
, shift
;
1481 int rm
= bits (inst
, 0, 3);
1482 unsigned long shifttype
= bits (inst
, 5, 6);
1486 int rs
= bits (inst
, 8, 11);
1487 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1490 shift
= bits (inst
, 7, 11);
1493 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1494 + (bit (inst
, 4) ? 12 : 8))
1495 : read_register (rm
));
1500 res
= shift
>= 32 ? 0 : res
<< shift
;
1504 res
= shift
>= 32 ? 0 : res
>> shift
;
1510 res
= ((res
& 0x80000000L
)
1511 ? ~((~res
) >> shift
) : res
>> shift
);
1514 case 3: /* ROR/RRX */
1517 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1519 res
= (res
>> shift
) | (res
<< (32 - shift
));
1523 return res
& 0xffffffff;
1526 /* Return number of 1-bits in VAL. */
1529 bitcount (unsigned long val
)
1532 for (nbits
= 0; val
!= 0; nbits
++)
1533 val
&= val
- 1; /* delete rightmost 1-bit in val */
1538 thumb_get_next_pc (CORE_ADDR pc
)
1540 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1541 unsigned short inst1
= read_memory_integer (pc
, 2);
1542 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1543 unsigned long offset
;
1545 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1549 /* Fetch the saved PC from the stack. It's stored above
1550 all of the other registers. */
1551 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1552 sp
= read_register (ARM_SP_REGNUM
);
1553 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1554 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1556 error (_("Infinite loop detected"));
1558 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1560 unsigned long status
= read_register (ARM_PS_REGNUM
);
1561 unsigned long cond
= bits (inst1
, 8, 11);
1562 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1563 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1565 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1567 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1569 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1571 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1572 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1573 nextpc
= pc_val
+ offset
;
1574 /* For BLX make sure to clear the low bits. */
1575 if (bits (inst2
, 11, 12) == 1)
1576 nextpc
= nextpc
& 0xfffffffc;
1578 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1580 if (bits (inst1
, 3, 6) == 0x0f)
1583 nextpc
= read_register (bits (inst1
, 3, 6));
1585 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1587 error (_("Infinite loop detected"));
1594 arm_get_next_pc (CORE_ADDR pc
)
1596 unsigned long pc_val
;
1597 unsigned long this_instr
;
1598 unsigned long status
;
1601 if (arm_pc_is_thumb (pc
))
1602 return thumb_get_next_pc (pc
);
1604 pc_val
= (unsigned long) pc
;
1605 this_instr
= read_memory_integer (pc
, 4);
1606 status
= read_register (ARM_PS_REGNUM
);
1607 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1609 if (condition_true (bits (this_instr
, 28, 31), status
))
1611 switch (bits (this_instr
, 24, 27))
1614 case 0x1: /* data processing */
1618 unsigned long operand1
, operand2
, result
= 0;
1622 if (bits (this_instr
, 12, 15) != 15)
1625 if (bits (this_instr
, 22, 25) == 0
1626 && bits (this_instr
, 4, 7) == 9) /* multiply */
1627 error (_("Invalid update to pc in instruction"));
1629 /* BX <reg>, BLX <reg> */
1630 if (bits (this_instr
, 4, 28) == 0x12fff1
1631 || bits (this_instr
, 4, 28) == 0x12fff3)
1633 rn
= bits (this_instr
, 0, 3);
1634 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1635 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1638 error (_("Infinite loop detected"));
1643 /* Multiply into PC */
1644 c
= (status
& FLAG_C
) ? 1 : 0;
1645 rn
= bits (this_instr
, 16, 19);
1646 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1648 if (bit (this_instr
, 25))
1650 unsigned long immval
= bits (this_instr
, 0, 7);
1651 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1652 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1655 else /* operand 2 is a shifted register */
1656 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1658 switch (bits (this_instr
, 21, 24))
1661 result
= operand1
& operand2
;
1665 result
= operand1
^ operand2
;
1669 result
= operand1
- operand2
;
1673 result
= operand2
- operand1
;
1677 result
= operand1
+ operand2
;
1681 result
= operand1
+ operand2
+ c
;
1685 result
= operand1
- operand2
+ c
;
1689 result
= operand2
- operand1
+ c
;
1695 case 0xb: /* tst, teq, cmp, cmn */
1696 result
= (unsigned long) nextpc
;
1700 result
= operand1
| operand2
;
1704 /* Always step into a function. */
1709 result
= operand1
& ~operand2
;
1716 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1719 error (_("Infinite loop detected"));
1724 case 0x5: /* data transfer */
1727 if (bit (this_instr
, 20))
1730 if (bits (this_instr
, 12, 15) == 15)
1736 if (bit (this_instr
, 22))
1737 error (_("Invalid update to pc in instruction"));
1739 /* byte write to PC */
1740 rn
= bits (this_instr
, 16, 19);
1741 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1742 if (bit (this_instr
, 24))
1745 int c
= (status
& FLAG_C
) ? 1 : 0;
1746 unsigned long offset
=
1747 (bit (this_instr
, 25)
1748 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1749 : bits (this_instr
, 0, 11));
1751 if (bit (this_instr
, 23))
1756 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1759 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1762 error (_("Infinite loop detected"));
1768 case 0x9: /* block transfer */
1769 if (bit (this_instr
, 20))
1772 if (bit (this_instr
, 15))
1777 if (bit (this_instr
, 23))
1780 unsigned long reglist
= bits (this_instr
, 0, 14);
1781 offset
= bitcount (reglist
) * 4;
1782 if (bit (this_instr
, 24)) /* pre */
1785 else if (bit (this_instr
, 24))
1789 unsigned long rn_val
=
1790 read_register (bits (this_instr
, 16, 19));
1792 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1796 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1798 error (_("Infinite loop detected"));
1803 case 0xb: /* branch & link */
1804 case 0xa: /* branch */
1806 nextpc
= BranchDest (pc
, this_instr
);
1809 if (bits (this_instr
, 28, 31) == INST_NV
)
1810 nextpc
|= bit (this_instr
, 24) << 1;
1812 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1814 error (_("Infinite loop detected"));
1820 case 0xe: /* coproc ops */
1825 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1833 /* single_step() is called just before we want to resume the inferior,
1834 if we want to single-step it but there is no hardware or kernel
1835 single-step support. We find the target of the coming instruction
1838 single_step() is also called just after the inferior stops. If we
1839 had set up a simulated single-step, we undo our damage. */
1842 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1844 static int next_pc
; /* State between setting and unsetting. */
1845 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1849 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1850 target_insert_breakpoint (next_pc
, break_mem
);
1853 target_remove_breakpoint (next_pc
, break_mem
);
1856 #include "bfd-in2.h"
1857 #include "libcoff.h"
1860 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1862 if (arm_pc_is_thumb (memaddr
))
1864 static asymbol
*asym
;
1865 static combined_entry_type ce
;
1866 static struct coff_symbol_struct csym
;
1867 static struct bfd fake_bfd
;
1868 static bfd_target fake_target
;
1870 if (csym
.native
== NULL
)
1872 /* Create a fake symbol vector containing a Thumb symbol.
1873 This is solely so that the code in print_insn_little_arm()
1874 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1875 the presence of a Thumb symbol and switch to decoding
1876 Thumb instructions. */
1878 fake_target
.flavour
= bfd_target_coff_flavour
;
1879 fake_bfd
.xvec
= &fake_target
;
1880 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1882 csym
.symbol
.the_bfd
= &fake_bfd
;
1883 csym
.symbol
.name
= "fake";
1884 asym
= (asymbol
*) & csym
;
1887 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1888 info
->symbols
= &asym
;
1891 info
->symbols
= NULL
;
1893 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1894 return print_insn_big_arm (memaddr
, info
);
1896 return print_insn_little_arm (memaddr
, info
);
1899 /* The following define instruction sequences that will cause ARM
1900 cpu's to take an undefined instruction trap. These are used to
1901 signal a breakpoint to GDB.
1903 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1904 modes. A different instruction is required for each mode. The ARM
1905 cpu's can also be big or little endian. Thus four different
1906 instructions are needed to support all cases.
1908 Note: ARMv4 defines several new instructions that will take the
1909 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1910 not in fact add the new instructions. The new undefined
1911 instructions in ARMv4 are all instructions that had no defined
1912 behaviour in earlier chips. There is no guarantee that they will
1913 raise an exception, but may be treated as NOP's. In practice, it
1914 may only safe to rely on instructions matching:
1916 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1917 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1918 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1920 Even this may only true if the condition predicate is true. The
1921 following use a condition predicate of ALWAYS so it is always TRUE.
1923 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1924 and NetBSD all use a software interrupt rather than an undefined
1925 instruction to force a trap. This can be handled by by the
1926 abi-specific code during establishment of the gdbarch vector. */
1929 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1930 override these definitions. */
1931 #ifndef ARM_LE_BREAKPOINT
1932 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1934 #ifndef ARM_BE_BREAKPOINT
1935 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1937 #ifndef THUMB_LE_BREAKPOINT
1938 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1940 #ifndef THUMB_BE_BREAKPOINT
1941 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1944 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
1945 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
1946 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1947 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1949 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1950 the program counter value to determine whether a 16-bit or 32-bit
1951 breakpoint should be used. It returns a pointer to a string of
1952 bytes that encode a breakpoint instruction, stores the length of
1953 the string to *lenptr, and adjusts the program counter (if
1954 necessary) to point to the actual memory location where the
1955 breakpoint should be inserted. */
1957 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1958 breakpoints and storing their handles instread of what was in
1959 memory. It is nice that this is the same size as a handle -
1960 otherwise remote-rdp will have to change. */
1962 static const unsigned char *
1963 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1965 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1967 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1969 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1970 *lenptr
= tdep
->thumb_breakpoint_size
;
1971 return tdep
->thumb_breakpoint
;
1975 *lenptr
= tdep
->arm_breakpoint_size
;
1976 return tdep
->arm_breakpoint
;
1980 /* Extract from an array REGBUF containing the (raw) register state a
1981 function return value of type TYPE, and copy that, in virtual
1982 format, into VALBUF. */
1985 arm_extract_return_value (struct type
*type
,
1986 struct regcache
*regs
,
1989 bfd_byte
*valbuf
= dst
;
1991 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1993 switch (arm_get_fp_model (current_gdbarch
))
1997 /* The value is in register F0 in internal format. We need to
1998 extract the raw value and then convert it to the desired
2000 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2002 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2003 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2008 case ARM_FLOAT_SOFT_FPA
:
2009 case ARM_FLOAT_SOFT_VFP
:
2010 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2011 if (TYPE_LENGTH (type
) > 4)
2012 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2013 valbuf
+ INT_REGISTER_SIZE
);
2018 (__FILE__
, __LINE__
,
2019 _("arm_extract_return_value: Floating point model not supported"));
2023 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2024 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2025 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2026 || TYPE_CODE (type
) == TYPE_CODE_PTR
2027 || TYPE_CODE (type
) == TYPE_CODE_REF
2028 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2030 /* If the the type is a plain integer, then the access is
2031 straight-forward. Otherwise we have to play around a bit more. */
2032 int len
= TYPE_LENGTH (type
);
2033 int regno
= ARM_A1_REGNUM
;
2038 /* By using store_unsigned_integer we avoid having to do
2039 anything special for small big-endian values. */
2040 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2041 store_unsigned_integer (valbuf
,
2042 (len
> INT_REGISTER_SIZE
2043 ? INT_REGISTER_SIZE
: len
),
2045 len
-= INT_REGISTER_SIZE
;
2046 valbuf
+= INT_REGISTER_SIZE
;
2051 /* For a structure or union the behaviour is as if the value had
2052 been stored to word-aligned memory and then loaded into
2053 registers with 32-bit load instruction(s). */
2054 int len
= TYPE_LENGTH (type
);
2055 int regno
= ARM_A1_REGNUM
;
2056 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2060 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2061 memcpy (valbuf
, tmpbuf
,
2062 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2063 len
-= INT_REGISTER_SIZE
;
2064 valbuf
+= INT_REGISTER_SIZE
;
2069 /* Extract from an array REGBUF containing the (raw) register state
2070 the address in which a function should return its structure value. */
2073 arm_extract_struct_value_address (struct regcache
*regcache
)
2077 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2081 /* Will a function return an aggregate type in memory or in a
2082 register? Return 0 if an aggregate type can be returned in a
2083 register, 1 if it must be returned in memory. */
2086 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2089 enum type_code code
;
2091 CHECK_TYPEDEF (type
);
2093 /* In the ARM ABI, "integer" like aggregate types are returned in
2094 registers. For an aggregate type to be integer like, its size
2095 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2096 offset of each addressable subfield must be zero. Note that bit
2097 fields are not addressable, and all addressable subfields of
2098 unions always start at offset zero.
2100 This function is based on the behaviour of GCC 2.95.1.
2101 See: gcc/arm.c: arm_return_in_memory() for details.
2103 Note: All versions of GCC before GCC 2.95.2 do not set up the
2104 parameters correctly for a function returning the following
2105 structure: struct { float f;}; This should be returned in memory,
2106 not a register. Richard Earnshaw sent me a patch, but I do not
2107 know of any way to detect if a function like the above has been
2108 compiled with the correct calling convention. */
2110 /* All aggregate types that won't fit in a register must be returned
2112 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2117 /* The only aggregate types that can be returned in a register are
2118 structs and unions. Arrays must be returned in memory. */
2119 code
= TYPE_CODE (type
);
2120 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2125 /* Assume all other aggregate types can be returned in a register.
2126 Run a check for structures, unions and arrays. */
2129 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2132 /* Need to check if this struct/union is "integer" like. For
2133 this to be true, its size must be less than or equal to
2134 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2135 subfield must be zero. Note that bit fields are not
2136 addressable, and unions always start at offset zero. If any
2137 of the subfields is a floating point type, the struct/union
2138 cannot be an integer type. */
2140 /* For each field in the object, check:
2141 1) Is it FP? --> yes, nRc = 1;
2142 2) Is it addressable (bitpos != 0) and
2143 not packed (bitsize == 0)?
2147 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2149 enum type_code field_type_code
;
2150 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2152 /* Is it a floating point type field? */
2153 if (field_type_code
== TYPE_CODE_FLT
)
2159 /* If bitpos != 0, then we have to care about it. */
2160 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2162 /* Bitfields are not addressable. If the field bitsize is
2163 zero, then the field is not packed. Hence it cannot be
2164 a bitfield or any other packed type. */
2165 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2177 /* Write into appropriate registers a function return value of type
2178 TYPE, given in virtual format. */
2181 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2184 const bfd_byte
*valbuf
= src
;
2186 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2188 char buf
[MAX_REGISTER_SIZE
];
2190 switch (arm_get_fp_model (current_gdbarch
))
2194 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2195 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2198 case ARM_FLOAT_SOFT_FPA
:
2199 case ARM_FLOAT_SOFT_VFP
:
2200 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2201 if (TYPE_LENGTH (type
) > 4)
2202 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2203 valbuf
+ INT_REGISTER_SIZE
);
2208 (__FILE__
, __LINE__
,
2209 _("arm_store_return_value: Floating point model not supported"));
2213 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2214 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2215 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2216 || TYPE_CODE (type
) == TYPE_CODE_PTR
2217 || TYPE_CODE (type
) == TYPE_CODE_REF
2218 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2220 if (TYPE_LENGTH (type
) <= 4)
2222 /* Values of one word or less are zero/sign-extended and
2224 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2225 LONGEST val
= unpack_long (type
, valbuf
);
2227 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2228 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2232 /* Integral values greater than one word are stored in consecutive
2233 registers starting with r0. This will always be a multiple of
2234 the regiser size. */
2235 int len
= TYPE_LENGTH (type
);
2236 int regno
= ARM_A1_REGNUM
;
2240 regcache_cooked_write (regs
, regno
++, valbuf
);
2241 len
-= INT_REGISTER_SIZE
;
2242 valbuf
+= INT_REGISTER_SIZE
;
2248 /* For a structure or union the behaviour is as if the value had
2249 been stored to word-aligned memory and then loaded into
2250 registers with 32-bit load instruction(s). */
2251 int len
= TYPE_LENGTH (type
);
2252 int regno
= ARM_A1_REGNUM
;
2253 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2257 memcpy (tmpbuf
, valbuf
,
2258 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2259 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2260 len
-= INT_REGISTER_SIZE
;
2261 valbuf
+= INT_REGISTER_SIZE
;
2267 arm_get_longjmp_target (CORE_ADDR
*pc
)
2270 char buf
[INT_REGISTER_SIZE
];
2271 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2273 jb_addr
= read_register (ARM_A1_REGNUM
);
2275 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2279 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2283 /* Return non-zero if the PC is inside a thumb call thunk. */
2286 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2288 CORE_ADDR start_addr
;
2290 /* Find the starting address of the function containing the PC. If
2291 the caller didn't give us a name, look it up at the same time. */
2292 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2296 return strncmp (name
, "_call_via_r", 11) == 0;
2299 /* If PC is in a Thumb call or return stub, return the address of the
2300 target PC, which is in a register. The thunk functions are called
2301 _called_via_xx, where x is the register name. The possible names
2302 are r0-r9, sl, fp, ip, sp, and lr. */
2305 arm_skip_stub (CORE_ADDR pc
)
2308 CORE_ADDR start_addr
;
2310 /* Find the starting address and name of the function containing the PC. */
2311 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2314 /* Call thunks always start with "_call_via_". */
2315 if (strncmp (name
, "_call_via_", 10) == 0)
2317 /* Use the name suffix to determine which register contains the
2319 static char *table
[15] =
2320 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2321 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2325 for (regno
= 0; regno
<= 14; regno
++)
2326 if (strcmp (&name
[10], table
[regno
]) == 0)
2327 return read_register (regno
);
2330 return 0; /* not a stub */
2334 set_arm_command (char *args
, int from_tty
)
2336 printf_unfiltered (_("\
2337 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2338 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2342 show_arm_command (char *args
, int from_tty
)
2344 cmd_show_list (showarmcmdlist
, from_tty
, "");
2347 enum arm_float_model
2348 arm_get_fp_model (struct gdbarch
*gdbarch
)
2350 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2351 return gdbarch_tdep (gdbarch
)->fp_model
;
2353 return arm_fp_model
;
2357 arm_set_fp (struct gdbarch
*gdbarch
)
2359 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2361 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2362 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2364 set_gdbarch_double_format (gdbarch
,
2365 &floatformat_ieee_double_littlebyte_bigword
);
2366 set_gdbarch_long_double_format
2367 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2371 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2372 set_gdbarch_long_double_format (gdbarch
,
2373 &floatformat_ieee_double_little
);
2378 set_fp_model_sfunc (char *args
, int from_tty
,
2379 struct cmd_list_element
*c
)
2381 enum arm_float_model fp_model
;
2383 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2384 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2386 arm_fp_model
= fp_model
;
2390 if (fp_model
== ARM_FLOAT_LAST
)
2391 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2394 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2395 arm_set_fp (current_gdbarch
);
2399 show_fp_model (struct ui_file
*file
, int from_tty
,
2400 struct cmd_list_element
*c
, const char *value
)
2402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2404 deprecated_show_value_hack (file
, from_tty
, c
, value
);
2405 if (arm_fp_model
== ARM_FLOAT_AUTO
2406 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2407 /* i18n: "the default [floating point model] for the current ABI..." */
2408 printf_filtered (_(" - the default for the current ABI is \"%s\".\n"),
2409 fp_model_strings
[tdep
->fp_model
]);
2412 /* If the user changes the register disassembly style used for info
2413 register and other commands, we have to also switch the style used
2414 in opcodes for disassembly output. This function is run in the "set
2415 arm disassembly" command, and does that. */
2418 set_disassembly_style_sfunc (char *args
, int from_tty
,
2419 struct cmd_list_element
*c
)
2421 set_disassembly_style ();
2424 /* Return the ARM register name corresponding to register I. */
2426 arm_register_name (int i
)
2428 return arm_register_names
[i
];
2432 set_disassembly_style (void)
2434 const char *setname
, *setdesc
, **regnames
;
2437 /* Find the style that the user wants in the opcodes table. */
2439 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2440 while ((disassembly_style
!= setname
)
2441 && (current
< num_disassembly_options
))
2442 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2443 current_option
= current
;
2445 /* Fill our copy. */
2446 for (j
= 0; j
< numregs
; j
++)
2447 arm_register_names
[j
] = (char *) regnames
[j
];
2450 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2452 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2453 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2457 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2458 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2461 /* Synchronize the disassembler. */
2462 set_arm_regname_option (current
);
2465 /* Test whether the coff symbol specific value corresponds to a Thumb
2469 coff_sym_is_thumb (int val
)
2471 return (val
== C_THUMBEXT
||
2472 val
== C_THUMBSTAT
||
2473 val
== C_THUMBEXTFUNC
||
2474 val
== C_THUMBSTATFUNC
||
2475 val
== C_THUMBLABEL
);
2478 /* arm_coff_make_msymbol_special()
2479 arm_elf_make_msymbol_special()
2481 These functions test whether the COFF or ELF symbol corresponds to
2482 an address in thumb code, and set a "special" bit in a minimal
2483 symbol to indicate that it does. */
2486 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2488 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2490 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2492 MSYMBOL_SET_SPECIAL (msym
);
2496 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2498 if (coff_sym_is_thumb (val
))
2499 MSYMBOL_SET_SPECIAL (msym
);
2503 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2505 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2507 /* If necessary, set the T bit. */
2510 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2511 if (arm_pc_is_thumb (pc
))
2512 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2514 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2518 static enum gdb_osabi
2519 arm_elf_osabi_sniffer (bfd
*abfd
)
2521 unsigned int elfosabi
, eflags
;
2522 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2524 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2529 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2530 file are conforming to the base specification for that machine
2531 (there are no OS-specific extensions). In order to determine the
2532 real OS in use we must look for OS notes that have been added. */
2533 bfd_map_over_sections (abfd
,
2534 generic_elf_osabi_sniff_abi_tag_sections
,
2536 if (osabi
== GDB_OSABI_UNKNOWN
)
2538 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2539 field for more information. */
2540 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2543 case EF_ARM_EABI_VER1
:
2544 osabi
= GDB_OSABI_ARM_EABI_V1
;
2547 case EF_ARM_EABI_VER2
:
2548 osabi
= GDB_OSABI_ARM_EABI_V2
;
2551 case EF_ARM_EABI_UNKNOWN
:
2552 /* Assume GNU tools. */
2553 osabi
= GDB_OSABI_ARM_APCS
;
2557 internal_error (__FILE__
, __LINE__
,
2559 arm_elf_osabi_sniffer: Unknown ARM EABI version 0x%x"),
2566 /* GNU tools use this value. Check note sections in this case,
2568 bfd_map_over_sections (abfd
,
2569 generic_elf_osabi_sniff_abi_tag_sections
,
2571 if (osabi
== GDB_OSABI_UNKNOWN
)
2573 /* Assume APCS ABI. */
2574 osabi
= GDB_OSABI_ARM_APCS
;
2578 case ELFOSABI_FREEBSD
:
2579 osabi
= GDB_OSABI_FREEBSD_ELF
;
2582 case ELFOSABI_NETBSD
:
2583 osabi
= GDB_OSABI_NETBSD_ELF
;
2586 case ELFOSABI_LINUX
:
2587 osabi
= GDB_OSABI_LINUX
;
2595 /* Initialize the current architecture based on INFO. If possible,
2596 re-use an architecture from ARCHES, which is a list of
2597 architectures already created during this debugging session.
2599 Called e.g. at program startup, when reading a core file, and when
2600 reading a binary file. */
2602 static struct gdbarch
*
2603 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2605 struct gdbarch_tdep
*tdep
;
2606 struct gdbarch
*gdbarch
;
2608 /* Try to deterimine the ABI of the object we are loading. */
2610 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2612 switch (bfd_get_flavour (info
.abfd
))
2614 case bfd_target_aout_flavour
:
2615 /* Assume it's an old APCS-style ABI. */
2616 info
.osabi
= GDB_OSABI_ARM_APCS
;
2619 case bfd_target_coff_flavour
:
2620 /* Assume it's an old APCS-style ABI. */
2622 info
.osabi
= GDB_OSABI_ARM_APCS
;
2626 /* Leave it as "unknown". */
2631 /* If there is already a candidate, use it. */
2632 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2634 return arches
->gdbarch
;
2636 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2637 gdbarch
= gdbarch_alloc (&info
, tdep
);
2639 /* We used to default to FPA for generic ARM, but almost nobody uses that
2640 now, and we now provide a way for the user to force the model. So
2641 default to the most useful variant. */
2642 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2645 switch (info
.byte_order
)
2647 case BFD_ENDIAN_BIG
:
2648 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2649 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2650 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2651 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2655 case BFD_ENDIAN_LITTLE
:
2656 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2657 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2658 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2659 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2664 internal_error (__FILE__
, __LINE__
,
2665 _("arm_gdbarch_init: bad byte order for float format"));
2668 /* On ARM targets char defaults to unsigned. */
2669 set_gdbarch_char_signed (gdbarch
, 0);
2671 /* This should be low enough for everything. */
2672 tdep
->lowest_pc
= 0x20;
2673 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2675 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2677 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2679 /* Frame handling. */
2680 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2681 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2682 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2684 frame_base_set_default (gdbarch
, &arm_normal_base
);
2686 /* Address manipulation. */
2687 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2688 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2690 /* Advance PC across function entry code. */
2691 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2693 /* Get the PC when a frame might not be available. */
2694 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2696 /* The stack grows downward. */
2697 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2699 /* Breakpoint manipulation. */
2700 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2702 /* Information about registers, etc. */
2703 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2704 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2705 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2706 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2707 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2708 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2709 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2711 /* Internal <-> external register number maps. */
2712 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2714 /* Integer registers are 4 bytes. */
2715 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2716 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2718 /* Returning results. */
2719 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2720 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2721 set_gdbarch_deprecated_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2722 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, arm_extract_struct_value_address
);
2724 /* Single stepping. */
2725 /* XXX For an RDI target we should ask the target if it can single-step. */
2726 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2729 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2731 /* Minsymbol frobbing. */
2732 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2733 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2734 arm_coff_make_msymbol_special
);
2736 /* Hook in the ABI-specific overrides, if they have been registered. */
2737 gdbarch_init_osabi (info
, gdbarch
);
2739 /* Add some default predicates. */
2740 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2741 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2743 /* Now we have tuned the configuration, set a few final things,
2744 based on what the OS ABI has told us. */
2746 if (tdep
->jb_pc
>= 0)
2747 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2749 /* Floating point sizes and format. */
2750 switch (info
.byte_order
)
2752 case BFD_ENDIAN_BIG
:
2753 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2754 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2755 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2759 case BFD_ENDIAN_LITTLE
:
2760 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2761 arm_set_fp (gdbarch
);
2765 internal_error (__FILE__
, __LINE__
,
2766 _("arm_gdbarch_init: bad byte order for float format"));
2773 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2775 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2780 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2781 (unsigned long) tdep
->lowest_pc
);
2785 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2786 struct gdbarch
*gdbarch
)
2792 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2793 struct gdbarch
*gdbarch
)
2799 arm_init_abi_apcs (struct gdbarch_info info
,
2800 struct gdbarch
*gdbarch
)
2805 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2808 _initialize_arm_tdep (void)
2810 struct ui_file
*stb
;
2812 struct cmd_list_element
*new_set
, *new_show
;
2813 const char *setname
;
2814 const char *setdesc
;
2815 const char **regnames
;
2817 static char *helptext
;
2818 char regdesc
[1024], *rdptr
= regdesc
;
2819 size_t rest
= sizeof (regdesc
);
2821 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2823 /* Register an ELF OS ABI sniffer for ARM binaries. */
2824 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2825 bfd_target_elf_flavour
,
2826 arm_elf_osabi_sniffer
);
2828 /* Register some ABI variants for embedded systems. */
2829 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
2830 arm_init_abi_eabi_v1
);
2831 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
2832 arm_init_abi_eabi_v2
);
2833 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
2836 /* Get the number of possible sets of register names defined in opcodes. */
2837 num_disassembly_options
= get_arm_regname_num_options ();
2839 /* Add root prefix command for all "set arm"/"show arm" commands. */
2840 add_prefix_cmd ("arm", no_class
, set_arm_command
,
2841 _("Various ARM-specific commands."),
2842 &setarmcmdlist
, "set arm ", 0, &setlist
);
2844 add_prefix_cmd ("arm", no_class
, show_arm_command
,
2845 _("Various ARM-specific commands."),
2846 &showarmcmdlist
, "show arm ", 0, &showlist
);
2848 /* Sync the opcode insn printer with our register viewer. */
2849 parse_arm_disassembler_option ("reg-names-std");
2851 /* Initialize the array that will be passed to
2852 add_setshow_enum_cmd(). */
2853 valid_disassembly_styles
2854 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
2855 for (i
= 0; i
< num_disassembly_options
; i
++)
2857 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2858 valid_disassembly_styles
[i
] = setname
;
2859 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
2862 /* Copy the default names (if found) and synchronize disassembler. */
2863 if (!strcmp (setname
, "std"))
2865 disassembly_style
= setname
;
2867 for (j
= 0; j
< numregs
; j
++)
2868 arm_register_names
[j
] = (char *) regnames
[j
];
2869 set_arm_regname_option (i
);
2872 /* Mark the end of valid options. */
2873 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
2875 /* Create the help text. */
2876 stb
= mem_fileopen ();
2877 fprintf_unfiltered (stb
, "%s%s%s",
2878 _("The valid values are:\n"),
2880 _("The default is \"std\"."));
2881 helptext
= ui_file_xstrdup (stb
, &length
);
2882 ui_file_delete (stb
);
2884 add_setshow_enum_cmd("disassembler", no_class
,
2885 valid_disassembly_styles
, &disassembly_style
,
2886 _("Set the disassembly style."),
2887 _("Show the disassembly style."),
2889 set_disassembly_style_sfunc
,
2890 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
2891 &setarmcmdlist
, &showarmcmdlist
);
2893 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
2894 _("Set usage of ARM 32-bit mode."),
2895 _("Show usage of ARM 32-bit mode."),
2896 _("When off, a 26-bit PC will be used."),
2898 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2899 &setarmcmdlist
, &showarmcmdlist
);
2901 /* Add a command to allow the user to force the FPU model. */
2902 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
2903 _("Set the floating point type."),
2904 _("Show the floating point type."),
2905 _("auto - Determine the FP typefrom the OS-ABI.\n\
2906 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2907 fpa - FPA co-processor (GCC compiled).\n\
2908 softvfp - Software FP with pure-endian doubles.\n\
2909 vfp - VFP co-processor."),
2910 set_fp_model_sfunc
, show_fp_model
,
2911 &setarmcmdlist
, &showarmcmdlist
);
2913 /* Debugging flag. */
2914 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
2915 _("Set ARM debugging."),
2916 _("Show ARM debugging."),
2917 _("When on, arm-specific debugging is enabled."),
2919 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
2920 &setdebuglist
, &showdebuglist
);