1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Per-objfile data used for mapping symbols. */
72 static const struct objfile_data
*arm_objfile_data_key
;
74 struct arm_mapping_symbol
79 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
80 DEF_VEC_O(arm_mapping_symbol_s
);
82 struct arm_per_objfile
84 VEC(arm_mapping_symbol_s
) **section_maps
;
87 /* The list of available "set arm ..." and "show arm ..." commands. */
88 static struct cmd_list_element
*setarmcmdlist
= NULL
;
89 static struct cmd_list_element
*showarmcmdlist
= NULL
;
91 /* The type of floating-point to use. Keep this in sync with enum
92 arm_float_model, and the help string in _initialize_arm_tdep. */
93 static const char *fp_model_strings
[] =
103 /* A variable that can be configured by the user. */
104 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
105 static const char *current_fp_model
= "auto";
107 /* The ABI to use. Keep this in sync with arm_abi_kind. */
108 static const char *arm_abi_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
118 static const char *arm_abi_string
= "auto";
120 /* The execution mode to assume. */
121 static const char *arm_mode_strings
[] =
128 static const char *arm_fallback_mode_string
= "auto";
129 static const char *arm_force_mode_string
= "auto";
131 /* Number of different reg name sets (options). */
132 static int num_disassembly_options
;
134 /* The standard register names, and all the valid aliases for them. */
139 } arm_register_aliases
[] = {
140 /* Basic register numbers. */
157 /* Synonyms (argument and variable registers). */
170 /* Other platform-specific names for r9. */
178 /* Names used by GCC (not listed in the ARM EABI). */
181 /* A special name from the older ATPCS. */
185 static const char *const arm_register_names
[] =
186 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
187 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
188 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
189 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
190 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
191 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
192 "fps", "cpsr" }; /* 24 25 */
194 /* Valid register name styles. */
195 static const char **valid_disassembly_styles
;
197 /* Disassembly style to use. Default to "std" register names. */
198 static const char *disassembly_style
;
200 /* This is used to keep the bfd arch_info in sync with the disassembly
202 static void set_disassembly_style_sfunc(char *, int,
203 struct cmd_list_element
*);
204 static void set_disassembly_style (void);
206 static void convert_from_extended (const struct floatformat
*, const void *,
208 static void convert_to_extended (const struct floatformat
*, void *,
211 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
212 struct regcache
*regcache
,
213 int regnum
, gdb_byte
*buf
);
214 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
215 struct regcache
*regcache
,
216 int regnum
, const gdb_byte
*buf
);
218 struct arm_prologue_cache
220 /* The stack pointer at the time this frame was created; i.e. the
221 caller's stack pointer when this function was called. It is used
222 to identify this frame. */
225 /* The frame base for this frame is just prev_sp - frame size.
226 FRAMESIZE is the distance from the frame pointer to the
227 initial stack pointer. */
231 /* The register used to hold the frame pointer for this frame. */
234 /* Saved register offsets. */
235 struct trad_frame_saved_reg
*saved_regs
;
238 /* Architecture version for displaced stepping. This effects the behaviour of
239 certain instructions, and really should not be hard-wired. */
241 #define DISPLACED_STEPPING_ARCH_VERSION 5
243 /* Addresses for calling Thumb functions have the bit 0 set.
244 Here are some macros to test, set, or clear bit 0 of addresses. */
245 #define IS_THUMB_ADDR(addr) ((addr) & 1)
246 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
247 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
249 /* Set to true if the 32-bit mode is in use. */
253 /* Determine if FRAME is executing in Thumb mode. */
256 arm_frame_is_thumb (struct frame_info
*frame
)
260 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
261 directly (from a signal frame or dummy frame) or by interpreting
262 the saved LR (from a prologue or DWARF frame). So consult it and
263 trust the unwinders. */
264 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
266 return (cpsr
& CPSR_T
) != 0;
269 /* Callback for VEC_lower_bound. */
272 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
273 const struct arm_mapping_symbol
*rhs
)
275 return lhs
->value
< rhs
->value
;
278 /* Search for the mapping symbol covering MEMADDR. If one is found,
279 return its type. Otherwise, return 0. If START is non-NULL,
280 set *START to the location of the mapping symbol. */
283 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
285 struct obj_section
*sec
;
287 /* If there are mapping symbols, consult them. */
288 sec
= find_pc_section (memaddr
);
291 struct arm_per_objfile
*data
;
292 VEC(arm_mapping_symbol_s
) *map
;
293 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
297 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
300 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
301 if (!VEC_empty (arm_mapping_symbol_s
, map
))
303 struct arm_mapping_symbol
*map_sym
;
305 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
306 arm_compare_mapping_symbols
);
308 /* VEC_lower_bound finds the earliest ordered insertion
309 point. If the following symbol starts at this exact
310 address, we use that; otherwise, the preceding
311 mapping symbol covers this address. */
312 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
314 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
315 if (map_sym
->value
== map_key
.value
)
318 *start
= map_sym
->value
+ obj_section_addr (sec
);
319 return map_sym
->type
;
325 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
327 *start
= map_sym
->value
+ obj_section_addr (sec
);
328 return map_sym
->type
;
337 static CORE_ADDR
arm_get_next_pc_raw (struct frame_info
*frame
,
338 CORE_ADDR pc
, int insert_bkpt
);
340 /* Determine if the program counter specified in MEMADDR is in a Thumb
341 function. This function should be called for addresses unrelated to
342 any executing frame; otherwise, prefer arm_frame_is_thumb. */
345 arm_pc_is_thumb (CORE_ADDR memaddr
)
347 struct obj_section
*sec
;
348 struct minimal_symbol
*sym
;
351 /* If bit 0 of the address is set, assume this is a Thumb address. */
352 if (IS_THUMB_ADDR (memaddr
))
355 /* If the user wants to override the symbol table, let him. */
356 if (strcmp (arm_force_mode_string
, "arm") == 0)
358 if (strcmp (arm_force_mode_string
, "thumb") == 0)
361 /* If there are mapping symbols, consult them. */
362 type
= arm_find_mapping_symbol (memaddr
, NULL
);
366 /* Thumb functions have a "special" bit set in minimal symbols. */
367 sym
= lookup_minimal_symbol_by_pc (memaddr
);
369 return (MSYMBOL_IS_SPECIAL (sym
));
371 /* If the user wants to override the fallback mode, let them. */
372 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
374 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
377 /* If we couldn't find any symbol, but we're talking to a running
378 target, then trust the current value of $cpsr. This lets
379 "display/i $pc" always show the correct mode (though if there is
380 a symbol table we will not reach here, so it still may not be
381 displayed in the mode it will be executed).
383 As a further heuristic if we detect that we are doing a single-step we
384 see what state executing the current instruction ends up with us being
386 if (target_has_registers
)
388 struct frame_info
*current_frame
= get_current_frame ();
389 CORE_ADDR current_pc
= get_frame_pc (current_frame
);
390 int is_thumb
= arm_frame_is_thumb (current_frame
);
392 if (memaddr
== current_pc
)
396 struct gdbarch
*gdbarch
= get_frame_arch (current_frame
);
397 next_pc
= arm_get_next_pc_raw (current_frame
, current_pc
, FALSE
);
398 if (memaddr
== gdbarch_addr_bits_remove (gdbarch
, next_pc
))
399 return IS_THUMB_ADDR (next_pc
);
405 /* Otherwise we're out of luck; we assume ARM. */
409 /* Remove useless bits from addresses in a running program. */
411 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
414 return UNMAKE_THUMB_ADDR (val
);
416 return (val
& 0x03fffffc);
419 /* When reading symbols, we need to zap the low bit of the address,
420 which may be set to 1 for Thumb functions. */
422 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
427 /* Analyze a Thumb prologue, looking for a recognizable stack frame
428 and frame pointer. Scan until we encounter a store that could
429 clobber the stack frame unexpectedly, or an unknown instruction. */
432 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
433 CORE_ADDR start
, CORE_ADDR limit
,
434 struct arm_prologue_cache
*cache
)
436 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
439 struct pv_area
*stack
;
440 struct cleanup
*back_to
;
443 for (i
= 0; i
< 16; i
++)
444 regs
[i
] = pv_register (i
, 0);
445 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
446 back_to
= make_cleanup_free_pv_area (stack
);
448 while (start
< limit
)
452 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
454 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
459 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
462 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
463 whether to save LR (R14). */
464 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
466 /* Calculate offsets of saved R0-R7 and LR. */
467 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
468 if (mask
& (1 << regno
))
470 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
472 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
475 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
478 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
479 if (insn
& 0x80) /* Check for SUB. */
480 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
483 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
486 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
487 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
489 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
491 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
492 int src_reg
= (insn
& 0x78) >> 3;
493 regs
[dst_reg
] = regs
[src_reg
];
495 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
497 /* Handle stores to the stack. Normally pushes are used,
498 but with GCC -mtpcs-frame, there may be other stores
499 in the prologue to create the frame. */
500 int regno
= (insn
>> 8) & 0x7;
503 offset
= (insn
& 0xff) << 2;
504 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
506 if (pv_area_store_would_trash (stack
, addr
))
509 pv_area_store (stack
, addr
, 4, regs
[regno
]);
513 /* We don't know what this instruction is. We're finished
514 scanning. NOTE: Recognizing more safe-to-ignore
515 instructions here will improve support for optimized
525 do_cleanups (back_to
);
529 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
531 /* Frame pointer is fp. Frame size is constant. */
532 cache
->framereg
= ARM_FP_REGNUM
;
533 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
535 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
537 /* Frame pointer is r7. Frame size is constant. */
538 cache
->framereg
= THUMB_FP_REGNUM
;
539 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
541 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
543 /* Try the stack pointer... this is a bit desperate. */
544 cache
->framereg
= ARM_SP_REGNUM
;
545 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
549 /* We're just out of luck. We don't know where the frame is. */
550 cache
->framereg
= -1;
551 cache
->framesize
= 0;
554 for (i
= 0; i
< 16; i
++)
555 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
556 cache
->saved_regs
[i
].addr
= offset
;
558 do_cleanups (back_to
);
562 /* Advance the PC across any function entry prologue instructions to
563 reach some "real" code.
565 The APCS (ARM Procedure Call Standard) defines the following
569 [stmfd sp!, {a1,a2,a3,a4}]
570 stmfd sp!, {...,fp,ip,lr,pc}
571 [stfe f7, [sp, #-12]!]
572 [stfe f6, [sp, #-12]!]
573 [stfe f5, [sp, #-12]!]
574 [stfe f4, [sp, #-12]!]
575 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
578 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
580 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
583 CORE_ADDR func_addr
, limit_pc
;
584 struct symtab_and_line sal
;
586 /* If we're in a dummy frame, don't even try to skip the prologue. */
587 if (deprecated_pc_in_call_dummy (gdbarch
, pc
))
590 /* See if we can determine the end of the prologue via the symbol table.
591 If so, then return either PC, or the PC after the prologue, whichever
593 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
595 CORE_ADDR post_prologue_pc
596 = skip_prologue_using_sal (gdbarch
, func_addr
);
597 if (post_prologue_pc
!= 0)
598 return max (pc
, post_prologue_pc
);
601 /* Can't determine prologue from the symbol table, need to examine
604 /* Find an upper limit on the function prologue using the debug
605 information. If the debug information could not be used to provide
606 that bound, then use an arbitrary large number as the upper bound. */
607 /* Like arm_scan_prologue, stop no later than pc + 64. */
608 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
610 limit_pc
= pc
+ 64; /* Magic. */
613 /* Check if this is Thumb code. */
614 if (arm_pc_is_thumb (pc
))
615 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
617 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
619 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
621 /* "mov ip, sp" is no longer a required part of the prologue. */
622 if (inst
== 0xe1a0c00d) /* mov ip, sp */
625 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
628 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
631 /* Some prologues begin with "str lr, [sp, #-4]!". */
632 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
635 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
638 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
641 /* Any insns after this point may float into the code, if it makes
642 for better instruction scheduling, so we skip them only if we
643 find them, but still consider the function to be frame-ful. */
645 /* We may have either one sfmfd instruction here, or several stfe
646 insns, depending on the version of floating point code we
648 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
651 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
654 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
657 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
660 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
661 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
662 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
665 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
666 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
667 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
670 /* Un-recognized instruction; stop scanning. */
674 return skip_pc
; /* End of prologue */
678 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
679 This function decodes a Thumb function prologue to determine:
680 1) the size of the stack frame
681 2) which registers are saved on it
682 3) the offsets of saved regs
683 4) the offset from the stack pointer to the frame pointer
685 A typical Thumb function prologue would create this stack frame
686 (offsets relative to FP)
687 old SP -> 24 stack parameters
690 R7 -> 0 local variables (16 bytes)
691 SP -> -12 additional stack space (12 bytes)
692 The frame size would thus be 36 bytes, and the frame offset would be
693 12 bytes. The frame register is R7.
695 The comments for thumb_skip_prolog() describe the algorithm we use
696 to detect the end of the prolog. */
700 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
701 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
703 CORE_ADDR prologue_start
;
704 CORE_ADDR prologue_end
;
705 CORE_ADDR current_pc
;
707 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
710 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
712 if (sal
.line
== 0) /* no line info, use current PC */
713 prologue_end
= prev_pc
;
714 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
715 prologue_end
= sal
.end
; /* (probably means no prologue) */
718 /* We're in the boondocks: we have no idea where the start of the
722 prologue_end
= min (prologue_end
, prev_pc
);
724 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
727 /* This function decodes an ARM function prologue to determine:
728 1) the size of the stack frame
729 2) which registers are saved on it
730 3) the offsets of saved regs
731 4) the offset from the stack pointer to the frame pointer
732 This information is stored in the "extra" fields of the frame_info.
734 There are two basic forms for the ARM prologue. The fixed argument
735 function call will look like:
738 stmfd sp!, {fp, ip, lr, pc}
742 Which would create this stack frame (offsets relative to FP):
743 IP -> 4 (caller's stack)
744 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
745 -4 LR (return address in caller)
746 -8 IP (copy of caller's SP)
748 SP -> -28 Local variables
750 The frame size would thus be 32 bytes, and the frame offset would be
751 28 bytes. The stmfd call can also save any of the vN registers it
752 plans to use, which increases the frame size accordingly.
754 Note: The stored PC is 8 off of the STMFD instruction that stored it
755 because the ARM Store instructions always store PC + 8 when you read
758 A variable argument function call will look like:
761 stmfd sp!, {a1, a2, a3, a4}
762 stmfd sp!, {fp, ip, lr, pc}
765 Which would create this stack frame (offsets relative to FP):
766 IP -> 20 (caller's stack)
771 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
772 -4 LR (return address in caller)
773 -8 IP (copy of caller's SP)
775 SP -> -28 Local variables
777 The frame size would thus be 48 bytes, and the frame offset would be
780 There is another potential complication, which is that the optimizer
781 will try to separate the store of fp in the "stmfd" instruction from
782 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
783 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
785 Also, note, the original version of the ARM toolchain claimed that there
788 instruction at the end of the prologue. I have never seen GCC produce
789 this, and the ARM docs don't mention it. We still test for it below in
795 arm_scan_prologue (struct frame_info
*this_frame
,
796 struct arm_prologue_cache
*cache
)
798 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
799 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
800 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
802 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
803 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
804 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
805 pv_t regs
[ARM_FPS_REGNUM
];
806 struct pv_area
*stack
;
807 struct cleanup
*back_to
;
810 /* Assume there is no frame until proven otherwise. */
811 cache
->framereg
= ARM_SP_REGNUM
;
812 cache
->framesize
= 0;
814 /* Check for Thumb prologue. */
815 if (arm_frame_is_thumb (this_frame
))
817 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
821 /* Find the function prologue. If we can't find the function in
822 the symbol table, peek in the stack frame to find the PC. */
823 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
826 /* One way to find the end of the prologue (which works well
827 for unoptimized code) is to do the following:
829 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
832 prologue_end = prev_pc;
833 else if (sal.end < prologue_end)
834 prologue_end = sal.end;
836 This mechanism is very accurate so long as the optimizer
837 doesn't move any instructions from the function body into the
838 prologue. If this happens, sal.end will be the last
839 instruction in the first hunk of prologue code just before
840 the first instruction that the scheduler has moved from
841 the body to the prologue.
843 In order to make sure that we scan all of the prologue
844 instructions, we use a slightly less accurate mechanism which
845 may scan more than necessary. To help compensate for this
846 lack of accuracy, the prologue scanning loop below contains
847 several clauses which'll cause the loop to terminate early if
848 an implausible prologue instruction is encountered.
854 is a suitable endpoint since it accounts for the largest
855 possible prologue plus up to five instructions inserted by
858 if (prologue_end
> prologue_start
+ 64)
860 prologue_end
= prologue_start
+ 64; /* See above. */
865 /* We have no symbol information. Our only option is to assume this
866 function has a standard stack frame and the normal frame register.
867 Then, we can find the value of our frame pointer on entrance to
868 the callee (or at the present moment if this is the innermost frame).
869 The value stored there should be the address of the stmfd + 8. */
871 LONGEST return_value
;
873 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
874 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
878 prologue_start
= gdbarch_addr_bits_remove
879 (gdbarch
, return_value
) - 8;
880 prologue_end
= prologue_start
+ 64; /* See above. */
884 if (prev_pc
< prologue_end
)
885 prologue_end
= prev_pc
;
887 /* Now search the prologue looking for instructions that set up the
888 frame pointer, adjust the stack pointer, and save registers.
890 Be careful, however, and if it doesn't look like a prologue,
891 don't try to scan it. If, for instance, a frameless function
892 begins with stmfd sp!, then we will tell ourselves there is
893 a frame, which will confuse stack traceback, as well as "finish"
894 and other operations that rely on a knowledge of the stack
897 In the APCS, the prologue should start with "mov ip, sp" so
898 if we don't see this as the first insn, we will stop.
900 [Note: This doesn't seem to be true any longer, so it's now an
901 optional part of the prologue. - Kevin Buettner, 2001-11-20]
903 [Note further: The "mov ip,sp" only seems to be missing in
904 frameless functions at optimization level "-O2" or above,
905 in which case it is often (but not always) replaced by
906 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
908 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
909 regs
[regno
] = pv_register (regno
, 0);
910 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
911 back_to
= make_cleanup_free_pv_area (stack
);
913 for (current_pc
= prologue_start
;
914 current_pc
< prologue_end
;
918 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
920 if (insn
== 0xe1a0c00d) /* mov ip, sp */
922 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
925 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
927 unsigned imm
= insn
& 0xff; /* immediate value */
928 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
929 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
930 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
933 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
935 unsigned imm
= insn
& 0xff; /* immediate value */
936 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
937 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
938 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
941 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
943 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
945 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
946 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
949 else if ((insn
& 0xffff0000) == 0xe92d0000)
950 /* stmfd sp!, {..., fp, ip, lr, pc}
952 stmfd sp!, {a1, a2, a3, a4} */
954 int mask
= insn
& 0xffff;
956 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
959 /* Calculate offsets of saved registers. */
960 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
961 if (mask
& (1 << regno
))
963 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
964 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
967 else if ((insn
& 0xffffc000) == 0xe54b0000 /* strb rx,[r11,#-n] */
968 || (insn
& 0xffffc0f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
969 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
971 /* No need to add this to saved_regs -- it's just an arg reg. */
974 else if ((insn
& 0xffffc000) == 0xe5cd0000 /* strb rx,[sp,#n] */
975 || (insn
& 0xffffc0f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
976 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
978 /* No need to add this to saved_regs -- it's just an arg reg. */
981 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
983 unsigned imm
= insn
& 0xff; /* immediate value */
984 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
985 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
986 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
988 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
990 unsigned imm
= insn
& 0xff; /* immediate value */
991 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
992 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
993 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
995 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
996 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
998 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1001 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1002 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1003 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1005 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
1006 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1008 int n_saved_fp_regs
;
1009 unsigned int fp_start_reg
, fp_bound_reg
;
1011 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1014 if ((insn
& 0x800) == 0x800) /* N0 is set */
1016 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1017 n_saved_fp_regs
= 3;
1019 n_saved_fp_regs
= 1;
1023 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1024 n_saved_fp_regs
= 2;
1026 n_saved_fp_regs
= 4;
1029 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1030 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1031 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1033 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1034 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1035 regs
[fp_start_reg
++]);
1038 else if ((insn
& 0xf0000000) != 0xe0000000)
1039 break; /* Condition not true, exit early */
1040 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
1041 break; /* Don't scan past a block load */
1043 /* The optimizer might shove anything into the prologue,
1044 so we just skip what we don't recognize. */
1048 /* The frame size is just the distance from the frame register
1049 to the original stack pointer. */
1050 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1052 /* Frame pointer is fp. */
1053 cache
->framereg
= ARM_FP_REGNUM
;
1054 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1056 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1058 /* Try the stack pointer... this is a bit desperate. */
1059 cache
->framereg
= ARM_SP_REGNUM
;
1060 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1064 /* We're just out of luck. We don't know where the frame is. */
1065 cache
->framereg
= -1;
1066 cache
->framesize
= 0;
1069 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1070 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1071 cache
->saved_regs
[regno
].addr
= offset
;
1073 do_cleanups (back_to
);
1076 static struct arm_prologue_cache
*
1077 arm_make_prologue_cache (struct frame_info
*this_frame
)
1080 struct arm_prologue_cache
*cache
;
1081 CORE_ADDR unwound_fp
;
1083 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1084 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1086 arm_scan_prologue (this_frame
, cache
);
1088 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1089 if (unwound_fp
== 0)
1092 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1094 /* Calculate actual addresses of saved registers using offsets
1095 determined by arm_scan_prologue. */
1096 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1097 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1098 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1103 /* Our frame ID for a normal frame is the current function's starting PC
1104 and the caller's SP when we were called. */
1107 arm_prologue_this_id (struct frame_info
*this_frame
,
1109 struct frame_id
*this_id
)
1111 struct arm_prologue_cache
*cache
;
1115 if (*this_cache
== NULL
)
1116 *this_cache
= arm_make_prologue_cache (this_frame
);
1117 cache
= *this_cache
;
1119 /* This is meant to halt the backtrace at "_start". */
1120 pc
= get_frame_pc (this_frame
);
1121 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1124 /* If we've hit a wall, stop. */
1125 if (cache
->prev_sp
== 0)
1128 func
= get_frame_func (this_frame
);
1129 id
= frame_id_build (cache
->prev_sp
, func
);
1133 static struct value
*
1134 arm_prologue_prev_register (struct frame_info
*this_frame
,
1138 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1139 struct arm_prologue_cache
*cache
;
1141 if (*this_cache
== NULL
)
1142 *this_cache
= arm_make_prologue_cache (this_frame
);
1143 cache
= *this_cache
;
1145 /* If we are asked to unwind the PC, then we need to return the LR
1146 instead. The prologue may save PC, but it will point into this
1147 frame's prologue, not the next frame's resume location. Also
1148 strip the saved T bit. A valid LR may have the low bit set, but
1149 a valid PC never does. */
1150 if (prev_regnum
== ARM_PC_REGNUM
)
1154 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1155 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1156 arm_addr_bits_remove (gdbarch
, lr
));
1159 /* SP is generally not saved to the stack, but this frame is
1160 identified by the next frame's stack pointer at the time of the call.
1161 The value was already reconstructed into PREV_SP. */
1162 if (prev_regnum
== ARM_SP_REGNUM
)
1163 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1165 /* The CPSR may have been changed by the call instruction and by the
1166 called function. The only bit we can reconstruct is the T bit,
1167 by checking the low bit of LR as of the call. This is a reliable
1168 indicator of Thumb-ness except for some ARM v4T pre-interworking
1169 Thumb code, which could get away with a clear low bit as long as
1170 the called function did not use bx. Guess that all other
1171 bits are unchanged; the condition flags are presumably lost,
1172 but the processor status is likely valid. */
1173 if (prev_regnum
== ARM_PS_REGNUM
)
1177 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1178 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1179 if (IS_THUMB_ADDR (lr
))
1183 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1186 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1190 struct frame_unwind arm_prologue_unwind
= {
1192 arm_prologue_this_id
,
1193 arm_prologue_prev_register
,
1195 default_frame_sniffer
1198 static struct arm_prologue_cache
*
1199 arm_make_stub_cache (struct frame_info
*this_frame
)
1202 struct arm_prologue_cache
*cache
;
1203 CORE_ADDR unwound_fp
;
1205 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1206 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1208 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1213 /* Our frame ID for a stub frame is the current SP and LR. */
1216 arm_stub_this_id (struct frame_info
*this_frame
,
1218 struct frame_id
*this_id
)
1220 struct arm_prologue_cache
*cache
;
1222 if (*this_cache
== NULL
)
1223 *this_cache
= arm_make_stub_cache (this_frame
);
1224 cache
= *this_cache
;
1226 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1230 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1231 struct frame_info
*this_frame
,
1232 void **this_prologue_cache
)
1234 CORE_ADDR addr_in_block
;
1237 addr_in_block
= get_frame_address_in_block (this_frame
);
1238 if (in_plt_section (addr_in_block
, NULL
)
1239 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1245 struct frame_unwind arm_stub_unwind
= {
1248 arm_prologue_prev_register
,
1250 arm_stub_unwind_sniffer
1254 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1256 struct arm_prologue_cache
*cache
;
1258 if (*this_cache
== NULL
)
1259 *this_cache
= arm_make_prologue_cache (this_frame
);
1260 cache
= *this_cache
;
1262 return cache
->prev_sp
- cache
->framesize
;
1265 struct frame_base arm_normal_base
= {
1266 &arm_prologue_unwind
,
1267 arm_normal_frame_base
,
1268 arm_normal_frame_base
,
1269 arm_normal_frame_base
1272 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1273 dummy frame. The frame ID's base needs to match the TOS value
1274 saved by save_dummy_frame_tos() and returned from
1275 arm_push_dummy_call, and the PC needs to match the dummy frame's
1278 static struct frame_id
1279 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1281 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1282 get_frame_pc (this_frame
));
1285 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1286 be used to construct the previous frame's ID, after looking up the
1287 containing function). */
1290 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1293 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1294 return arm_addr_bits_remove (gdbarch
, pc
);
1298 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1300 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1303 static struct value
*
1304 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1307 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1313 /* The PC is normally copied from the return column, which
1314 describes saves of LR. However, that version may have an
1315 extra bit set to indicate Thumb state. The bit is not
1317 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1318 return frame_unwind_got_constant (this_frame
, regnum
,
1319 arm_addr_bits_remove (gdbarch
, lr
));
1322 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1323 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1324 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1325 if (IS_THUMB_ADDR (lr
))
1329 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1332 internal_error (__FILE__
, __LINE__
,
1333 _("Unexpected register %d"), regnum
);
1338 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1339 struct dwarf2_frame_state_reg
*reg
,
1340 struct frame_info
*this_frame
)
1346 reg
->how
= DWARF2_FRAME_REG_FN
;
1347 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1350 reg
->how
= DWARF2_FRAME_REG_CFA
;
1355 /* When arguments must be pushed onto the stack, they go on in reverse
1356 order. The code below implements a FILO (stack) to do this. */
1361 struct stack_item
*prev
;
1365 static struct stack_item
*
1366 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1368 struct stack_item
*si
;
1369 si
= xmalloc (sizeof (struct stack_item
));
1370 si
->data
= xmalloc (len
);
1373 memcpy (si
->data
, contents
, len
);
1377 static struct stack_item
*
1378 pop_stack_item (struct stack_item
*si
)
1380 struct stack_item
*dead
= si
;
1388 /* Return the alignment (in bytes) of the given type. */
1391 arm_type_align (struct type
*t
)
1397 t
= check_typedef (t
);
1398 switch (TYPE_CODE (t
))
1401 /* Should never happen. */
1402 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1406 case TYPE_CODE_ENUM
:
1410 case TYPE_CODE_RANGE
:
1411 case TYPE_CODE_BITSTRING
:
1413 case TYPE_CODE_CHAR
:
1414 case TYPE_CODE_BOOL
:
1415 return TYPE_LENGTH (t
);
1417 case TYPE_CODE_ARRAY
:
1418 case TYPE_CODE_COMPLEX
:
1419 /* TODO: What about vector types? */
1420 return arm_type_align (TYPE_TARGET_TYPE (t
));
1422 case TYPE_CODE_STRUCT
:
1423 case TYPE_CODE_UNION
:
1425 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1427 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1435 /* Possible base types for a candidate for passing and returning in
1438 enum arm_vfp_cprc_base_type
1447 /* The length of one element of base type B. */
1450 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
1454 case VFP_CPRC_SINGLE
:
1456 case VFP_CPRC_DOUBLE
:
1458 case VFP_CPRC_VEC64
:
1460 case VFP_CPRC_VEC128
:
1463 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1468 /* The character ('s', 'd' or 'q') for the type of VFP register used
1469 for passing base type B. */
1472 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
1476 case VFP_CPRC_SINGLE
:
1478 case VFP_CPRC_DOUBLE
:
1480 case VFP_CPRC_VEC64
:
1482 case VFP_CPRC_VEC128
:
1485 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1490 /* Determine whether T may be part of a candidate for passing and
1491 returning in VFP registers, ignoring the limit on the total number
1492 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
1493 classification of the first valid component found; if it is not
1494 VFP_CPRC_UNKNOWN, all components must have the same classification
1495 as *BASE_TYPE. If it is found that T contains a type not permitted
1496 for passing and returning in VFP registers, a type differently
1497 classified from *BASE_TYPE, or two types differently classified
1498 from each other, return -1, otherwise return the total number of
1499 base-type elements found (possibly 0 in an empty structure or
1500 array). Vectors and complex types are not currently supported,
1501 matching the generic AAPCS support. */
1504 arm_vfp_cprc_sub_candidate (struct type
*t
,
1505 enum arm_vfp_cprc_base_type
*base_type
)
1507 t
= check_typedef (t
);
1508 switch (TYPE_CODE (t
))
1511 switch (TYPE_LENGTH (t
))
1514 if (*base_type
== VFP_CPRC_UNKNOWN
)
1515 *base_type
= VFP_CPRC_SINGLE
;
1516 else if (*base_type
!= VFP_CPRC_SINGLE
)
1521 if (*base_type
== VFP_CPRC_UNKNOWN
)
1522 *base_type
= VFP_CPRC_DOUBLE
;
1523 else if (*base_type
!= VFP_CPRC_DOUBLE
)
1532 case TYPE_CODE_ARRAY
:
1536 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
1539 if (TYPE_LENGTH (t
) == 0)
1541 gdb_assert (count
== 0);
1544 else if (count
== 0)
1546 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1547 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
1548 return TYPE_LENGTH (t
) / unitlen
;
1552 case TYPE_CODE_STRUCT
:
1557 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1559 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1561 if (sub_count
== -1)
1565 if (TYPE_LENGTH (t
) == 0)
1567 gdb_assert (count
== 0);
1570 else if (count
== 0)
1572 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1573 if (TYPE_LENGTH (t
) != unitlen
* count
)
1578 case TYPE_CODE_UNION
:
1583 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1585 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1587 if (sub_count
== -1)
1589 count
= (count
> sub_count
? count
: sub_count
);
1591 if (TYPE_LENGTH (t
) == 0)
1593 gdb_assert (count
== 0);
1596 else if (count
== 0)
1598 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1599 if (TYPE_LENGTH (t
) != unitlen
* count
)
1611 /* Determine whether T is a VFP co-processor register candidate (CPRC)
1612 if passed to or returned from a non-variadic function with the VFP
1613 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
1614 *BASE_TYPE to the base type for T and *COUNT to the number of
1615 elements of that base type before returning. */
1618 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
1621 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
1622 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
1623 if (c
<= 0 || c
> 4)
1630 /* Return 1 if the VFP ABI should be used for passing arguments to and
1631 returning values from a function of type FUNC_TYPE, 0
1635 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
1637 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1638 /* Variadic functions always use the base ABI. Assume that functions
1639 without debug info are not variadic. */
1640 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
1642 /* The VFP ABI is only supported as a variant of AAPCS. */
1643 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
1645 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
1648 /* We currently only support passing parameters in integer registers, which
1649 conforms with GCC's default model, and VFP argument passing following
1650 the VFP variant of AAPCS. Several other variants exist and
1651 we should probably support some of them based on the selected ABI. */
1654 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1655 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1656 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1657 CORE_ADDR struct_addr
)
1659 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1663 struct stack_item
*si
= NULL
;
1666 unsigned vfp_regs_free
= (1 << 16) - 1;
1668 /* Determine the type of this function and whether the VFP ABI
1670 ftype
= check_typedef (value_type (function
));
1671 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
1672 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
1673 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
1675 /* Set the return address. For the ARM, the return breakpoint is
1676 always at BP_ADDR. */
1677 if (arm_pc_is_thumb (bp_addr
))
1679 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1681 /* Walk through the list of args and determine how large a temporary
1682 stack is required. Need to take care here as structs may be
1683 passed on the stack, and we have to to push them. */
1686 argreg
= ARM_A1_REGNUM
;
1689 /* The struct_return pointer occupies the first parameter
1690 passing register. */
1694 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
1695 gdbarch_register_name (gdbarch
, argreg
),
1696 paddress (gdbarch
, struct_addr
));
1697 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1701 for (argnum
= 0; argnum
< nargs
; argnum
++)
1704 struct type
*arg_type
;
1705 struct type
*target_type
;
1706 enum type_code typecode
;
1709 enum arm_vfp_cprc_base_type vfp_base_type
;
1711 int may_use_core_reg
= 1;
1713 arg_type
= check_typedef (value_type (args
[argnum
]));
1714 len
= TYPE_LENGTH (arg_type
);
1715 target_type
= TYPE_TARGET_TYPE (arg_type
);
1716 typecode
= TYPE_CODE (arg_type
);
1717 val
= value_contents_writeable (args
[argnum
]);
1719 align
= arm_type_align (arg_type
);
1720 /* Round alignment up to a whole number of words. */
1721 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1722 /* Different ABIs have different maximum alignments. */
1723 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1725 /* The APCS ABI only requires word alignment. */
1726 align
= INT_REGISTER_SIZE
;
1730 /* The AAPCS requires at most doubleword alignment. */
1731 if (align
> INT_REGISTER_SIZE
* 2)
1732 align
= INT_REGISTER_SIZE
* 2;
1736 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
1744 /* Because this is a CPRC it cannot go in a core register or
1745 cause a core register to be skipped for alignment.
1746 Either it goes in VFP registers and the rest of this loop
1747 iteration is skipped for this argument, or it goes on the
1748 stack (and the stack alignment code is correct for this
1750 may_use_core_reg
= 0;
1752 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
1753 shift
= unit_length
/ 4;
1754 mask
= (1 << (shift
* vfp_base_count
)) - 1;
1755 for (regno
= 0; regno
< 16; regno
+= shift
)
1756 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
1765 vfp_regs_free
&= ~(mask
<< regno
);
1766 reg_scaled
= regno
/ shift
;
1767 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
1768 for (i
= 0; i
< vfp_base_count
; i
++)
1772 if (reg_char
== 'q')
1773 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
1774 val
+ i
* unit_length
);
1777 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
1778 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
1780 regcache_cooked_write (regcache
, regnum
,
1781 val
+ i
* unit_length
);
1788 /* This CPRC could not go in VFP registers, so all VFP
1789 registers are now marked as used. */
1794 /* Push stack padding for dowubleword alignment. */
1795 if (nstack
& (align
- 1))
1797 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1798 nstack
+= INT_REGISTER_SIZE
;
1801 /* Doubleword aligned quantities must go in even register pairs. */
1802 if (may_use_core_reg
1803 && argreg
<= ARM_LAST_ARG_REGNUM
1804 && align
> INT_REGISTER_SIZE
1808 /* If the argument is a pointer to a function, and it is a
1809 Thumb function, create a LOCAL copy of the value and set
1810 the THUMB bit in it. */
1811 if (TYPE_CODE_PTR
== typecode
1812 && target_type
!= NULL
1813 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1815 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
1816 if (arm_pc_is_thumb (regval
))
1819 store_unsigned_integer (val
, len
, byte_order
,
1820 MAKE_THUMB_ADDR (regval
));
1824 /* Copy the argument to general registers or the stack in
1825 register-sized pieces. Large arguments are split between
1826 registers and stack. */
1829 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1831 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
1833 /* The argument is being passed in a general purpose
1836 = extract_unsigned_integer (val
, partial_len
, byte_order
);
1837 if (byte_order
== BFD_ENDIAN_BIG
)
1838 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1840 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1842 gdbarch_register_name
1844 phex (regval
, INT_REGISTER_SIZE
));
1845 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1850 /* Push the arguments onto the stack. */
1852 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1854 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1855 nstack
+= INT_REGISTER_SIZE
;
1862 /* If we have an odd number of words to push, then decrement the stack
1863 by one word now, so first stack argument will be dword aligned. */
1870 write_memory (sp
, si
->data
, si
->len
);
1871 si
= pop_stack_item (si
);
1874 /* Finally, update teh SP register. */
1875 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1881 /* Always align the frame to an 8-byte boundary. This is required on
1882 some platforms and harmless on the rest. */
1885 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1887 /* Align the stack to eight bytes. */
1888 return sp
& ~ (CORE_ADDR
) 7;
1892 print_fpu_flags (int flags
)
1894 if (flags
& (1 << 0))
1895 fputs ("IVO ", stdout
);
1896 if (flags
& (1 << 1))
1897 fputs ("DVZ ", stdout
);
1898 if (flags
& (1 << 2))
1899 fputs ("OFL ", stdout
);
1900 if (flags
& (1 << 3))
1901 fputs ("UFL ", stdout
);
1902 if (flags
& (1 << 4))
1903 fputs ("INX ", stdout
);
1907 /* Print interesting information about the floating point processor
1908 (if present) or emulator. */
1910 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1911 struct frame_info
*frame
, const char *args
)
1913 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1916 type
= (status
>> 24) & 127;
1917 if (status
& (1 << 31))
1918 printf (_("Hardware FPU type %d\n"), type
);
1920 printf (_("Software FPU type %d\n"), type
);
1921 /* i18n: [floating point unit] mask */
1922 fputs (_("mask: "), stdout
);
1923 print_fpu_flags (status
>> 16);
1924 /* i18n: [floating point unit] flags */
1925 fputs (_("flags: "), stdout
);
1926 print_fpu_flags (status
);
1929 /* Construct the ARM extended floating point type. */
1930 static struct type
*
1931 arm_ext_type (struct gdbarch
*gdbarch
)
1933 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1935 if (!tdep
->arm_ext_type
)
1937 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
1938 floatformats_arm_ext
);
1940 return tdep
->arm_ext_type
;
1943 static struct type
*
1944 arm_neon_double_type (struct gdbarch
*gdbarch
)
1946 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1948 if (tdep
->neon_double_type
== NULL
)
1950 struct type
*t
, *elem
;
1952 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
1954 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1955 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
1956 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1957 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
1958 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1959 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
1960 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1961 append_composite_type_field (t
, "u64", elem
);
1962 elem
= builtin_type (gdbarch
)->builtin_float
;
1963 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
1964 elem
= builtin_type (gdbarch
)->builtin_double
;
1965 append_composite_type_field (t
, "f64", elem
);
1967 TYPE_VECTOR (t
) = 1;
1968 TYPE_NAME (t
) = "neon_d";
1969 tdep
->neon_double_type
= t
;
1972 return tdep
->neon_double_type
;
1975 /* FIXME: The vector types are not correctly ordered on big-endian
1976 targets. Just as s0 is the low bits of d0, d0[0] is also the low
1977 bits of d0 - regardless of what unit size is being held in d0. So
1978 the offset of the first uint8 in d0 is 7, but the offset of the
1979 first float is 4. This code works as-is for little-endian
1982 static struct type
*
1983 arm_neon_quad_type (struct gdbarch
*gdbarch
)
1985 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1987 if (tdep
->neon_quad_type
== NULL
)
1989 struct type
*t
, *elem
;
1991 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
1993 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1994 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
1995 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1996 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
1997 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1998 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
1999 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2000 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
2001 elem
= builtin_type (gdbarch
)->builtin_float
;
2002 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
2003 elem
= builtin_type (gdbarch
)->builtin_double
;
2004 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
2006 TYPE_VECTOR (t
) = 1;
2007 TYPE_NAME (t
) = "neon_q";
2008 tdep
->neon_quad_type
= t
;
2011 return tdep
->neon_quad_type
;
2014 /* Return the GDB type object for the "standard" data type of data in
2017 static struct type
*
2018 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
2020 int num_regs
= gdbarch_num_regs (gdbarch
);
2022 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
2023 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
2024 return builtin_type (gdbarch
)->builtin_float
;
2026 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
2027 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
2028 return arm_neon_quad_type (gdbarch
);
2030 /* If the target description has register information, we are only
2031 in this function so that we can override the types of
2032 double-precision registers for NEON. */
2033 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
2035 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
2037 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
2038 && TYPE_CODE (t
) == TYPE_CODE_FLT
2039 && gdbarch_tdep (gdbarch
)->have_neon
)
2040 return arm_neon_double_type (gdbarch
);
2045 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
2047 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2048 return builtin_type (gdbarch
)->builtin_void
;
2050 return arm_ext_type (gdbarch
);
2052 else if (regnum
== ARM_SP_REGNUM
)
2053 return builtin_type (gdbarch
)->builtin_data_ptr
;
2054 else if (regnum
== ARM_PC_REGNUM
)
2055 return builtin_type (gdbarch
)->builtin_func_ptr
;
2056 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
2057 /* These registers are only supported on targets which supply
2058 an XML description. */
2059 return builtin_type (gdbarch
)->builtin_int0
;
2061 return builtin_type (gdbarch
)->builtin_uint32
;
2064 /* Map a DWARF register REGNUM onto the appropriate GDB register
2068 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2070 /* Core integer regs. */
2071 if (reg
>= 0 && reg
<= 15)
2074 /* Legacy FPA encoding. These were once used in a way which
2075 overlapped with VFP register numbering, so their use is
2076 discouraged, but GDB doesn't support the ARM toolchain
2077 which used them for VFP. */
2078 if (reg
>= 16 && reg
<= 23)
2079 return ARM_F0_REGNUM
+ reg
- 16;
2081 /* New assignments for the FPA registers. */
2082 if (reg
>= 96 && reg
<= 103)
2083 return ARM_F0_REGNUM
+ reg
- 96;
2085 /* WMMX register assignments. */
2086 if (reg
>= 104 && reg
<= 111)
2087 return ARM_WCGR0_REGNUM
+ reg
- 104;
2089 if (reg
>= 112 && reg
<= 127)
2090 return ARM_WR0_REGNUM
+ reg
- 112;
2092 if (reg
>= 192 && reg
<= 199)
2093 return ARM_WC0_REGNUM
+ reg
- 192;
2095 /* VFP v2 registers. A double precision value is actually
2096 in d1 rather than s2, but the ABI only defines numbering
2097 for the single precision registers. This will "just work"
2098 in GDB for little endian targets (we'll read eight bytes,
2099 starting in s0 and then progressing to s1), but will be
2100 reversed on big endian targets with VFP. This won't
2101 be a problem for the new Neon quad registers; you're supposed
2102 to use DW_OP_piece for those. */
2103 if (reg
>= 64 && reg
<= 95)
2107 sprintf (name_buf
, "s%d", reg
- 64);
2108 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2112 /* VFP v3 / Neon registers. This range is also used for VFP v2
2113 registers, except that it now describes d0 instead of s0. */
2114 if (reg
>= 256 && reg
<= 287)
2118 sprintf (name_buf
, "d%d", reg
- 256);
2119 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2126 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
2128 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
2131 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
2133 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
2134 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
2136 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
2137 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
2139 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
2140 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
2142 if (reg
< NUM_GREGS
)
2143 return SIM_ARM_R0_REGNUM
+ reg
;
2146 if (reg
< NUM_FREGS
)
2147 return SIM_ARM_FP0_REGNUM
+ reg
;
2150 if (reg
< NUM_SREGS
)
2151 return SIM_ARM_FPS_REGNUM
+ reg
;
2154 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
2157 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
2158 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
2159 It is thought that this is is the floating-point register format on
2160 little-endian systems. */
2163 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
2164 void *dbl
, int endianess
)
2168 if (endianess
== BFD_ENDIAN_BIG
)
2169 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
2171 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2173 floatformat_from_doublest (fmt
, &d
, dbl
);
2177 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
2182 floatformat_to_doublest (fmt
, ptr
, &d
);
2183 if (endianess
== BFD_ENDIAN_BIG
)
2184 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
2186 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2191 condition_true (unsigned long cond
, unsigned long status_reg
)
2193 if (cond
== INST_AL
|| cond
== INST_NV
)
2199 return ((status_reg
& FLAG_Z
) != 0);
2201 return ((status_reg
& FLAG_Z
) == 0);
2203 return ((status_reg
& FLAG_C
) != 0);
2205 return ((status_reg
& FLAG_C
) == 0);
2207 return ((status_reg
& FLAG_N
) != 0);
2209 return ((status_reg
& FLAG_N
) == 0);
2211 return ((status_reg
& FLAG_V
) != 0);
2213 return ((status_reg
& FLAG_V
) == 0);
2215 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
2217 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
2219 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
2221 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
2223 return (((status_reg
& FLAG_Z
) == 0)
2224 && (((status_reg
& FLAG_N
) == 0)
2225 == ((status_reg
& FLAG_V
) == 0)));
2227 return (((status_reg
& FLAG_Z
) != 0)
2228 || (((status_reg
& FLAG_N
) == 0)
2229 != ((status_reg
& FLAG_V
) == 0)));
2234 /* Support routines for single stepping. Calculate the next PC value. */
2235 #define submask(x) ((1L << ((x) + 1)) - 1)
2236 #define bit(obj,st) (((obj) >> (st)) & 1)
2237 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
2238 #define sbits(obj,st,fn) \
2239 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
2240 #define BranchDest(addr,instr) \
2241 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
2244 static unsigned long
2245 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
2246 unsigned long pc_val
, unsigned long status_reg
)
2248 unsigned long res
, shift
;
2249 int rm
= bits (inst
, 0, 3);
2250 unsigned long shifttype
= bits (inst
, 5, 6);
2254 int rs
= bits (inst
, 8, 11);
2255 shift
= (rs
== 15 ? pc_val
+ 8
2256 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
2259 shift
= bits (inst
, 7, 11);
2262 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
2263 + (bit (inst
, 4) ? 12 : 8))
2264 : get_frame_register_unsigned (frame
, rm
));
2269 res
= shift
>= 32 ? 0 : res
<< shift
;
2273 res
= shift
>= 32 ? 0 : res
>> shift
;
2279 res
= ((res
& 0x80000000L
)
2280 ? ~((~res
) >> shift
) : res
>> shift
);
2283 case 3: /* ROR/RRX */
2286 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
2288 res
= (res
>> shift
) | (res
<< (32 - shift
));
2292 return res
& 0xffffffff;
2295 /* Return number of 1-bits in VAL. */
2298 bitcount (unsigned long val
)
2301 for (nbits
= 0; val
!= 0; nbits
++)
2302 val
&= val
- 1; /* delete rightmost 1-bit in val */
2306 /* Return the size in bytes of the complete Thumb instruction whose
2307 first halfword is INST1. */
2310 thumb_insn_size (unsigned short inst1
)
2312 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2319 thumb_advance_itstate (unsigned int itstate
)
2321 /* Preserve IT[7:5], the first three bits of the condition. Shift
2322 the upcoming condition flags left by one bit. */
2323 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
2325 /* If we have finished the IT block, clear the state. */
2326 if ((itstate
& 0x0f) == 0)
2332 /* Find the next PC after the current instruction executes. In some
2333 cases we can not statically determine the answer (see the IT state
2334 handling in this function); in that case, a breakpoint may be
2335 inserted in addition to the returned PC, which will be used to set
2336 another breakpoint by our caller. */
2339 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
2341 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2342 struct address_space
*aspace
= get_frame_address_space (frame
);
2343 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2344 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2345 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
2346 unsigned short inst1
;
2347 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
2348 unsigned long offset
;
2349 ULONGEST status
, itstate
;
2351 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2352 pc_val
= MAKE_THUMB_ADDR (pc_val
);
2354 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2356 /* Thumb-2 conditional execution support. There are eight bits in
2357 the CPSR which describe conditional execution state. Once
2358 reconstructed (they're in a funny order), the low five bits
2359 describe the low bit of the condition for each instruction and
2360 how many instructions remain. The high three bits describe the
2361 base condition. One of the low four bits will be set if an IT
2362 block is active. These bits read as zero on earlier
2364 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2365 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
2367 /* If-Then handling. On GNU/Linux, where this routine is used, we
2368 use an undefined instruction as a breakpoint. Unlike BKPT, IT
2369 can disable execution of the undefined instruction. So we might
2370 miss the breakpoint if we set it on a skipped conditional
2371 instruction. Because conditional instructions can change the
2372 flags, affecting the execution of further instructions, we may
2373 need to set two breakpoints. */
2375 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
2377 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
2379 /* An IT instruction. Because this instruction does not
2380 modify the flags, we can accurately predict the next
2381 executed instruction. */
2382 itstate
= inst1
& 0x00ff;
2383 pc
+= thumb_insn_size (inst1
);
2385 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2387 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2388 pc
+= thumb_insn_size (inst1
);
2389 itstate
= thumb_advance_itstate (itstate
);
2392 return MAKE_THUMB_ADDR (pc
);
2394 else if (itstate
!= 0)
2396 /* We are in a conditional block. Check the condition. */
2397 if (! condition_true (itstate
>> 4, status
))
2399 /* Advance to the next executed instruction. */
2400 pc
+= thumb_insn_size (inst1
);
2401 itstate
= thumb_advance_itstate (itstate
);
2403 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2405 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2406 pc
+= thumb_insn_size (inst1
);
2407 itstate
= thumb_advance_itstate (itstate
);
2410 return MAKE_THUMB_ADDR (pc
);
2412 else if ((itstate
& 0x0f) == 0x08)
2414 /* This is the last instruction of the conditional
2415 block, and it is executed. We can handle it normally
2416 because the following instruction is not conditional,
2417 and we must handle it normally because it is
2418 permitted to branch. Fall through. */
2424 /* There are conditional instructions after this one.
2425 If this instruction modifies the flags, then we can
2426 not predict what the next executed instruction will
2427 be. Fortunately, this instruction is architecturally
2428 forbidden to branch; we know it will fall through.
2429 Start by skipping past it. */
2430 pc
+= thumb_insn_size (inst1
);
2431 itstate
= thumb_advance_itstate (itstate
);
2433 /* Set a breakpoint on the following instruction. */
2434 gdb_assert ((itstate
& 0x0f) != 0);
2436 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
2437 cond_negated
= (itstate
>> 4) & 1;
2439 /* Skip all following instructions with the same
2440 condition. If there is a later instruction in the IT
2441 block with the opposite condition, set the other
2442 breakpoint there. If not, then set a breakpoint on
2443 the instruction after the IT block. */
2446 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2447 pc
+= thumb_insn_size (inst1
);
2448 itstate
= thumb_advance_itstate (itstate
);
2450 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
2452 return MAKE_THUMB_ADDR (pc
);
2456 else if (itstate
& 0x0f)
2458 /* We are in a conditional block. Check the condition. */
2459 int cond
= itstate
>> 4;
2461 if (! condition_true (cond
, status
))
2463 /* Advance to the next instruction. All the 32-bit
2464 instructions share a common prefix. */
2465 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2466 return MAKE_THUMB_ADDR (pc
+ 4);
2468 return MAKE_THUMB_ADDR (pc
+ 2);
2471 /* Otherwise, handle the instruction normally. */
2474 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
2478 /* Fetch the saved PC from the stack. It's stored above
2479 all of the other registers. */
2480 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
2481 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
2482 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
2484 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
2486 unsigned long cond
= bits (inst1
, 8, 11);
2487 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
2488 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
2490 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
2492 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
2494 else if ((inst1
& 0xe000) == 0xe000) /* 32-bit instruction */
2496 unsigned short inst2
;
2497 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
2499 /* Default to the next instruction. */
2501 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2503 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
2505 /* Branches and miscellaneous control instructions. */
2507 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
2510 int j1
, j2
, imm1
, imm2
;
2512 imm1
= sbits (inst1
, 0, 10);
2513 imm2
= bits (inst2
, 0, 10);
2514 j1
= bit (inst2
, 13);
2515 j2
= bit (inst2
, 11);
2517 offset
= ((imm1
<< 12) + (imm2
<< 1));
2518 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
2520 nextpc
= pc_val
+ offset
;
2521 /* For BLX make sure to clear the low bits. */
2522 if (bit (inst2
, 12) == 0)
2523 nextpc
= nextpc
& 0xfffffffc;
2525 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
2527 /* SUBS PC, LR, #imm8. */
2528 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
2529 nextpc
-= inst2
& 0x00ff;
2531 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
2533 /* Conditional branch. */
2534 if (condition_true (bits (inst1
, 6, 9), status
))
2536 int sign
, j1
, j2
, imm1
, imm2
;
2538 sign
= sbits (inst1
, 10, 10);
2539 imm1
= bits (inst1
, 0, 5);
2540 imm2
= bits (inst2
, 0, 10);
2541 j1
= bit (inst2
, 13);
2542 j2
= bit (inst2
, 11);
2544 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
2545 offset
+= (imm1
<< 12) + (imm2
<< 1);
2547 nextpc
= pc_val
+ offset
;
2551 else if ((inst1
& 0xfe50) == 0xe810)
2553 /* Load multiple or RFE. */
2554 int rn
, offset
, load_pc
= 1;
2556 rn
= bits (inst1
, 0, 3);
2557 if (bit (inst1
, 7) && !bit (inst1
, 8))
2560 if (!bit (inst2
, 15))
2562 offset
= bitcount (inst2
) * 4 - 4;
2564 else if (!bit (inst1
, 7) && bit (inst1
, 8))
2567 if (!bit (inst2
, 15))
2571 else if (bit (inst1
, 7) && bit (inst1
, 8))
2576 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
2586 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
2587 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
2590 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
2592 /* MOV PC or MOVS PC. */
2593 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2594 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2596 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
2600 int rn
, load_pc
= 1;
2602 rn
= bits (inst1
, 0, 3);
2603 base
= get_frame_register_unsigned (frame
, rn
);
2606 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
2608 base
+= bits (inst2
, 0, 11);
2610 base
-= bits (inst2
, 0, 11);
2612 else if (bit (inst1
, 7))
2613 base
+= bits (inst2
, 0, 11);
2614 else if (bit (inst2
, 11))
2616 if (bit (inst2
, 10))
2619 base
+= bits (inst2
, 0, 7);
2621 base
-= bits (inst2
, 0, 7);
2624 else if ((inst2
& 0x0fc0) == 0x0000)
2626 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
2627 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
2634 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
2636 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
2639 CORE_ADDR table
, offset
, length
;
2641 table
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 3));
2642 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2643 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
2644 nextpc
= pc_val
+ length
;
2646 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
2649 CORE_ADDR table
, offset
, length
;
2651 table
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 3));
2652 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2653 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
2654 nextpc
= pc_val
+ length
;
2657 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
2659 if (bits (inst1
, 3, 6) == 0x0f)
2662 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
2664 else if ((inst1
& 0xf500) == 0xb100)
2667 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
2668 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
2670 if (bit (inst1
, 11) && reg
!= 0)
2671 nextpc
= pc_val
+ imm
;
2672 else if (!bit (inst1
, 11) && reg
== 0)
2673 nextpc
= pc_val
+ imm
;
2678 /* Get the raw next address. PC is the current program counter, in
2679 FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on
2680 the alternative next instruction if there are two options.
2682 The value returned has the execution state of the next instruction
2683 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
2684 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
2688 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
2690 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2691 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2692 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2693 unsigned long pc_val
;
2694 unsigned long this_instr
;
2695 unsigned long status
;
2698 if (arm_frame_is_thumb (frame
))
2699 return thumb_get_next_pc_raw (frame
, pc
, insert_bkpt
);
2701 pc_val
= (unsigned long) pc
;
2702 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
2704 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2705 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
2707 if (bits (this_instr
, 28, 31) == INST_NV
)
2708 switch (bits (this_instr
, 24, 27))
2713 /* Branch with Link and change to Thumb. */
2714 nextpc
= BranchDest (pc
, this_instr
);
2715 nextpc
|= bit (this_instr
, 24) << 1;
2716 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2722 /* Coprocessor register transfer. */
2723 if (bits (this_instr
, 12, 15) == 15)
2724 error (_("Invalid update to pc in instruction"));
2727 else if (condition_true (bits (this_instr
, 28, 31), status
))
2729 switch (bits (this_instr
, 24, 27))
2732 case 0x1: /* data processing */
2736 unsigned long operand1
, operand2
, result
= 0;
2740 if (bits (this_instr
, 12, 15) != 15)
2743 if (bits (this_instr
, 22, 25) == 0
2744 && bits (this_instr
, 4, 7) == 9) /* multiply */
2745 error (_("Invalid update to pc in instruction"));
2747 /* BX <reg>, BLX <reg> */
2748 if (bits (this_instr
, 4, 27) == 0x12fff1
2749 || bits (this_instr
, 4, 27) == 0x12fff3)
2751 rn
= bits (this_instr
, 0, 3);
2752 nextpc
= (rn
== 15) ? pc_val
+ 8
2753 : get_frame_register_unsigned (frame
, rn
);
2757 /* Multiply into PC */
2758 c
= (status
& FLAG_C
) ? 1 : 0;
2759 rn
= bits (this_instr
, 16, 19);
2760 operand1
= (rn
== 15) ? pc_val
+ 8
2761 : get_frame_register_unsigned (frame
, rn
);
2763 if (bit (this_instr
, 25))
2765 unsigned long immval
= bits (this_instr
, 0, 7);
2766 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
2767 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
2770 else /* operand 2 is a shifted register */
2771 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
2773 switch (bits (this_instr
, 21, 24))
2776 result
= operand1
& operand2
;
2780 result
= operand1
^ operand2
;
2784 result
= operand1
- operand2
;
2788 result
= operand2
- operand1
;
2792 result
= operand1
+ operand2
;
2796 result
= operand1
+ operand2
+ c
;
2800 result
= operand1
- operand2
+ c
;
2804 result
= operand2
- operand1
+ c
;
2810 case 0xb: /* tst, teq, cmp, cmn */
2811 result
= (unsigned long) nextpc
;
2815 result
= operand1
| operand2
;
2819 /* Always step into a function. */
2824 result
= operand1
& ~operand2
;
2832 /* In 26-bit APCS the bottom two bits of the result are
2833 ignored, and we always end up in ARM state. */
2835 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
2843 case 0x5: /* data transfer */
2846 if (bit (this_instr
, 20))
2849 if (bits (this_instr
, 12, 15) == 15)
2855 if (bit (this_instr
, 22))
2856 error (_("Invalid update to pc in instruction"));
2858 /* byte write to PC */
2859 rn
= bits (this_instr
, 16, 19);
2860 base
= (rn
== 15) ? pc_val
+ 8
2861 : get_frame_register_unsigned (frame
, rn
);
2862 if (bit (this_instr
, 24))
2865 int c
= (status
& FLAG_C
) ? 1 : 0;
2866 unsigned long offset
=
2867 (bit (this_instr
, 25)
2868 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
2869 : bits (this_instr
, 0, 11));
2871 if (bit (this_instr
, 23))
2876 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2883 case 0x9: /* block transfer */
2884 if (bit (this_instr
, 20))
2887 if (bit (this_instr
, 15))
2892 if (bit (this_instr
, 23))
2895 unsigned long reglist
= bits (this_instr
, 0, 14);
2896 offset
= bitcount (reglist
) * 4;
2897 if (bit (this_instr
, 24)) /* pre */
2900 else if (bit (this_instr
, 24))
2904 unsigned long rn_val
=
2905 get_frame_register_unsigned (frame
,
2906 bits (this_instr
, 16, 19));
2908 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2916 case 0xb: /* branch & link */
2917 case 0xa: /* branch */
2919 nextpc
= BranchDest (pc
, this_instr
);
2925 case 0xe: /* coproc ops */
2930 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2939 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2941 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2943 gdbarch_addr_bits_remove (gdbarch
,
2944 arm_get_next_pc_raw (frame
, pc
, TRUE
));
2946 error (_("Infinite loop detected"));
2950 /* single_step() is called just before we want to resume the inferior,
2951 if we want to single-step it but there is no hardware or kernel
2952 single-step support. We find the target of the coming instruction
2953 and breakpoint it. */
2956 arm_software_single_step (struct frame_info
*frame
)
2958 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2959 struct address_space
*aspace
= get_frame_address_space (frame
);
2961 /* NOTE: This may insert the wrong breakpoint instruction when
2962 single-stepping over a mode-changing instruction, if the
2963 CPSR heuristics are used. */
2965 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2966 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2971 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
2972 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
2973 NULL if an error occurs. BUF is freed. */
2976 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
2977 int old_len
, int new_len
)
2979 gdb_byte
*new_buf
, *middle
;
2980 int bytes_to_read
= new_len
- old_len
;
2982 new_buf
= xmalloc (new_len
);
2983 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
2985 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
2993 /* An IT block is at most the 2-byte IT instruction followed by
2994 four 4-byte instructions. The furthest back we must search to
2995 find an IT block that affects the current instruction is thus
2996 2 + 3 * 4 == 14 bytes. */
2997 #define MAX_IT_BLOCK_PREFIX 14
2999 /* Use a quick scan if there are more than this many bytes of
3001 #define IT_SCAN_THRESHOLD 32
3003 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
3004 A breakpoint in an IT block may not be hit, depending on the
3007 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
3011 CORE_ADDR boundary
, func_start
;
3012 int buf_len
, buf2_len
;
3013 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
3014 int i
, any
, last_it
, last_it_count
;
3016 /* If we are using BKPT breakpoints, none of this is necessary. */
3017 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
3020 /* ARM mode does not have this problem. */
3021 if (!arm_pc_is_thumb (bpaddr
))
3024 /* We are setting a breakpoint in Thumb code that could potentially
3025 contain an IT block. The first step is to find how much Thumb
3026 code there is; we do not need to read outside of known Thumb
3028 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
3030 /* Thumb-2 code must have mapping symbols to have a chance. */
3033 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
3035 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
3036 && func_start
> boundary
)
3037 boundary
= func_start
;
3039 /* Search for a candidate IT instruction. We have to do some fancy
3040 footwork to distinguish a real IT instruction from the second
3041 half of a 32-bit instruction, but there is no need for that if
3042 there's no candidate. */
3043 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
3045 /* No room for an IT instruction. */
3048 buf
= xmalloc (buf_len
);
3049 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
3052 for (i
= 0; i
< buf_len
; i
+= 2)
3054 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3055 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3067 /* OK, the code bytes before this instruction contain at least one
3068 halfword which resembles an IT instruction. We know that it's
3069 Thumb code, but there are still two possibilities. Either the
3070 halfword really is an IT instruction, or it is the second half of
3071 a 32-bit Thumb instruction. The only way we can tell is to
3072 scan forwards from a known instruction boundary. */
3073 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
3077 /* There's a lot of code before this instruction. Start with an
3078 optimistic search; it's easy to recognize halfwords that can
3079 not be the start of a 32-bit instruction, and use that to
3080 lock on to the instruction boundaries. */
3081 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
3084 buf_len
= IT_SCAN_THRESHOLD
;
3087 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
3089 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3090 if (thumb_insn_size (inst1
) == 2)
3097 /* At this point, if DEFINITE, BUF[I] is the first place we
3098 are sure that we know the instruction boundaries, and it is far
3099 enough from BPADDR that we could not miss an IT instruction
3100 affecting BPADDR. If ! DEFINITE, give up - start from a
3104 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3107 buf_len
= bpaddr
- boundary
;
3113 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3116 buf_len
= bpaddr
- boundary
;
3120 /* Scan forwards. Find the last IT instruction before BPADDR. */
3125 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3127 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3132 else if (inst1
& 0x0002)
3134 else if (inst1
& 0x0004)
3139 i
+= thumb_insn_size (inst1
);
3145 /* There wasn't really an IT instruction after all. */
3148 if (last_it_count
< 1)
3149 /* It was too far away. */
3152 /* This really is a trouble spot. Move the breakpoint to the IT
3154 return bpaddr
- buf_len
+ last_it
;
3157 /* ARM displaced stepping support.
3159 Generally ARM displaced stepping works as follows:
3161 1. When an instruction is to be single-stepped, it is first decoded by
3162 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
3163 Depending on the type of instruction, it is then copied to a scratch
3164 location, possibly in a modified form. The copy_* set of functions
3165 performs such modification, as necessary. A breakpoint is placed after
3166 the modified instruction in the scratch space to return control to GDB.
3167 Note in particular that instructions which modify the PC will no longer
3168 do so after modification.
3170 2. The instruction is single-stepped, by setting the PC to the scratch
3171 location address, and resuming. Control returns to GDB when the
3174 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
3175 function used for the current instruction. This function's job is to
3176 put the CPU/memory state back to what it would have been if the
3177 instruction had been executed unmodified in its original location. */
3179 /* NOP instruction (mov r0, r0). */
3180 #define ARM_NOP 0xe1a00000
3182 /* Helper for register reads for displaced stepping. In particular, this
3183 returns the PC as it would be seen by the instruction at its original
3187 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
3193 if (debug_displaced
)
3194 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
3195 (unsigned long) from
+ 8);
3196 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
3200 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
3201 if (debug_displaced
)
3202 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
3203 regno
, (unsigned long) ret
);
3209 displaced_in_arm_mode (struct regcache
*regs
)
3213 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3215 return (ps
& CPSR_T
) == 0;
3218 /* Write to the PC as from a branch instruction. */
3221 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
3223 if (displaced_in_arm_mode (regs
))
3224 /* Note: If bits 0/1 are set, this branch would be unpredictable for
3225 architecture versions < 6. */
3226 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x3);
3228 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x1);
3231 /* Write to the PC as from a branch-exchange instruction. */
3234 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
3238 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3242 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| CPSR_T
);
3243 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
3245 else if ((val
& 2) == 0)
3247 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
3248 ps
& ~(ULONGEST
) CPSR_T
);
3249 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
3253 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
3254 mode, align dest to 4 bytes). */
3255 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
3256 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
3257 ps
& ~(ULONGEST
) CPSR_T
);
3258 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
3262 /* Write to the PC as if from a load instruction. */
3265 load_write_pc (struct regcache
*regs
, ULONGEST val
)
3267 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
3268 bx_write_pc (regs
, val
);
3270 branch_write_pc (regs
, val
);
3273 /* Write to the PC as if from an ALU instruction. */
3276 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
3278 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
3279 bx_write_pc (regs
, val
);
3281 branch_write_pc (regs
, val
);
3284 /* Helper for writing to registers for displaced stepping. Writing to the PC
3285 has a varying effects depending on the instruction which does the write:
3286 this is controlled by the WRITE_PC argument. */
3289 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
3290 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
3294 if (debug_displaced
)
3295 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
3296 (unsigned long) val
);
3299 case BRANCH_WRITE_PC
:
3300 branch_write_pc (regs
, val
);
3304 bx_write_pc (regs
, val
);
3308 load_write_pc (regs
, val
);
3312 alu_write_pc (regs
, val
);
3315 case CANNOT_WRITE_PC
:
3316 warning (_("Instruction wrote to PC in an unexpected way when "
3317 "single-stepping"));
3321 internal_error (__FILE__
, __LINE__
,
3322 _("Invalid argument to displaced_write_reg"));
3325 dsc
->wrote_to_pc
= 1;
3329 if (debug_displaced
)
3330 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
3331 regno
, (unsigned long) val
);
3332 regcache_cooked_write_unsigned (regs
, regno
, val
);
3336 /* This function is used to concisely determine if an instruction INSN
3337 references PC. Register fields of interest in INSN should have the
3338 corresponding fields of BITMASK set to 0b1111. The function returns return 1
3339 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
3343 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
3345 uint32_t lowbit
= 1;
3347 while (bitmask
!= 0)
3351 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
3357 mask
= lowbit
* 0xf;
3359 if ((insn
& mask
) == mask
)
3368 /* The simplest copy function. Many instructions have the same effect no
3369 matter what address they are executed at: in those cases, use this. */
3372 copy_unmodified (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3373 const char *iname
, struct displaced_step_closure
*dsc
)
3375 if (debug_displaced
)
3376 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
3377 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
3380 dsc
->modinsn
[0] = insn
;
3385 /* Preload instructions with immediate offset. */
3388 cleanup_preload (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3389 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3391 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3392 if (!dsc
->u
.preload
.immed
)
3393 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3397 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3398 struct displaced_step_closure
*dsc
)
3400 unsigned int rn
= bits (insn
, 16, 19);
3402 CORE_ADDR from
= dsc
->insn_addr
;
3404 if (!insn_references_pc (insn
, 0x000f0000ul
))
3405 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
3407 if (debug_displaced
)
3408 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3409 (unsigned long) insn
);
3411 /* Preload instructions:
3413 {pli/pld} [rn, #+/-imm]
3415 {pli/pld} [r0, #+/-imm]. */
3417 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3418 rn_val
= displaced_read_reg (regs
, from
, rn
);
3419 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3421 dsc
->u
.preload
.immed
= 1;
3423 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3425 dsc
->cleanup
= &cleanup_preload
;
3430 /* Preload instructions with register offset. */
3433 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3434 struct displaced_step_closure
*dsc
)
3436 unsigned int rn
= bits (insn
, 16, 19);
3437 unsigned int rm
= bits (insn
, 0, 3);
3438 ULONGEST rn_val
, rm_val
;
3439 CORE_ADDR from
= dsc
->insn_addr
;
3441 if (!insn_references_pc (insn
, 0x000f000ful
))
3442 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
3444 if (debug_displaced
)
3445 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3446 (unsigned long) insn
);
3448 /* Preload register-offset instructions:
3450 {pli/pld} [rn, rm {, shift}]
3452 {pli/pld} [r0, r1 {, shift}]. */
3454 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3455 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3456 rn_val
= displaced_read_reg (regs
, from
, rn
);
3457 rm_val
= displaced_read_reg (regs
, from
, rm
);
3458 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3459 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
3461 dsc
->u
.preload
.immed
= 0;
3463 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
3465 dsc
->cleanup
= &cleanup_preload
;
3470 /* Copy/cleanup coprocessor load and store instructions. */
3473 cleanup_copro_load_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3474 struct regcache
*regs
,
3475 struct displaced_step_closure
*dsc
)
3477 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3479 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3481 if (dsc
->u
.ldst
.writeback
)
3482 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
3486 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
3487 struct regcache
*regs
,
3488 struct displaced_step_closure
*dsc
)
3490 unsigned int rn
= bits (insn
, 16, 19);
3492 CORE_ADDR from
= dsc
->insn_addr
;
3494 if (!insn_references_pc (insn
, 0x000f0000ul
))
3495 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
3497 if (debug_displaced
)
3498 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
3499 "load/store insn %.8lx\n", (unsigned long) insn
);
3501 /* Coprocessor load/store instructions:
3503 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
3505 {stc/stc2} [r0, #+/-imm].
3507 ldc/ldc2 are handled identically. */
3509 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3510 rn_val
= displaced_read_reg (regs
, from
, rn
);
3511 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3513 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
3514 dsc
->u
.ldst
.rn
= rn
;
3516 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3518 dsc
->cleanup
= &cleanup_copro_load_store
;
3523 /* Clean up branch instructions (actually perform the branch, by setting
3527 cleanup_branch (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3528 struct displaced_step_closure
*dsc
)
3530 ULONGEST from
= dsc
->insn_addr
;
3531 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3532 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
3533 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
3534 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
3539 if (dsc
->u
.branch
.link
)
3541 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
3542 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
3545 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
3548 /* Copy B/BL/BLX instructions with immediate destinations. */
3551 copy_b_bl_blx (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3552 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3554 unsigned int cond
= bits (insn
, 28, 31);
3555 int exchange
= (cond
== 0xf);
3556 int link
= exchange
|| bit (insn
, 24);
3557 CORE_ADDR from
= dsc
->insn_addr
;
3560 if (debug_displaced
)
3561 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
3562 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
3563 (unsigned long) insn
);
3565 /* Implement "BL<cond> <label>" as:
3567 Preparation: cond <- instruction condition
3568 Insn: mov r0, r0 (nop)
3569 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
3571 B<cond> similar, but don't set r14 in cleanup. */
3574 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
3575 then arrange the switch into Thumb mode. */
3576 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
3578 offset
= bits (insn
, 0, 23) << 2;
3580 if (bit (offset
, 25))
3581 offset
= offset
| ~0x3ffffff;
3583 dsc
->u
.branch
.cond
= cond
;
3584 dsc
->u
.branch
.link
= link
;
3585 dsc
->u
.branch
.exchange
= exchange
;
3586 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
3588 dsc
->modinsn
[0] = ARM_NOP
;
3590 dsc
->cleanup
= &cleanup_branch
;
3595 /* Copy BX/BLX with register-specified destinations. */
3598 copy_bx_blx_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3599 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3601 unsigned int cond
= bits (insn
, 28, 31);
3604 int link
= bit (insn
, 5);
3605 unsigned int rm
= bits (insn
, 0, 3);
3606 CORE_ADDR from
= dsc
->insn_addr
;
3608 if (debug_displaced
)
3609 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
3610 "%.8lx\n", (link
) ? "blx" : "bx", (unsigned long) insn
);
3612 /* Implement {BX,BLX}<cond> <reg>" as:
3614 Preparation: cond <- instruction condition
3615 Insn: mov r0, r0 (nop)
3616 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
3618 Don't set r14 in cleanup for BX. */
3620 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
3622 dsc
->u
.branch
.cond
= cond
;
3623 dsc
->u
.branch
.link
= link
;
3624 dsc
->u
.branch
.exchange
= 1;
3626 dsc
->modinsn
[0] = ARM_NOP
;
3628 dsc
->cleanup
= &cleanup_branch
;
3633 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
3636 cleanup_alu_imm (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3637 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3639 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3640 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3641 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3642 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3646 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3647 struct displaced_step_closure
*dsc
)
3649 unsigned int rn
= bits (insn
, 16, 19);
3650 unsigned int rd
= bits (insn
, 12, 15);
3651 unsigned int op
= bits (insn
, 21, 24);
3652 int is_mov
= (op
== 0xd);
3653 ULONGEST rd_val
, rn_val
;
3654 CORE_ADDR from
= dsc
->insn_addr
;
3656 if (!insn_references_pc (insn
, 0x000ff000ul
))
3657 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
3659 if (debug_displaced
)
3660 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
3661 "%.8lx\n", is_mov
? "move" : "ALU",
3662 (unsigned long) insn
);
3664 /* Instruction is of form:
3666 <op><cond> rd, [rn,] #imm
3670 Preparation: tmp1, tmp2 <- r0, r1;
3672 Insn: <op><cond> r0, r1, #imm
3673 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
3676 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3677 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3678 rn_val
= displaced_read_reg (regs
, from
, rn
);
3679 rd_val
= displaced_read_reg (regs
, from
, rd
);
3680 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3681 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3685 dsc
->modinsn
[0] = insn
& 0xfff00fff;
3687 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
3689 dsc
->cleanup
= &cleanup_alu_imm
;
3694 /* Copy/cleanup arithmetic/logic insns with register RHS. */
3697 cleanup_alu_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3698 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3703 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3705 for (i
= 0; i
< 3; i
++)
3706 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
3708 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3712 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3713 struct displaced_step_closure
*dsc
)
3715 unsigned int rn
= bits (insn
, 16, 19);
3716 unsigned int rm
= bits (insn
, 0, 3);
3717 unsigned int rd
= bits (insn
, 12, 15);
3718 unsigned int op
= bits (insn
, 21, 24);
3719 int is_mov
= (op
== 0xd);
3720 ULONGEST rd_val
, rn_val
, rm_val
;
3721 CORE_ADDR from
= dsc
->insn_addr
;
3723 if (!insn_references_pc (insn
, 0x000ff00ful
))
3724 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
3726 if (debug_displaced
)
3727 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
3728 is_mov
? "move" : "ALU", (unsigned long) insn
);
3730 /* Instruction is of form:
3732 <op><cond> rd, [rn,] rm [, <shift>]
3736 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
3737 r0, r1, r2 <- rd, rn, rm
3738 Insn: <op><cond> r0, r1, r2 [, <shift>]
3739 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
3742 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3743 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3744 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3745 rd_val
= displaced_read_reg (regs
, from
, rd
);
3746 rn_val
= displaced_read_reg (regs
, from
, rn
);
3747 rm_val
= displaced_read_reg (regs
, from
, rm
);
3748 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3749 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3750 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
3754 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
3756 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
3758 dsc
->cleanup
= &cleanup_alu_reg
;
3763 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
3766 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3767 struct regcache
*regs
,
3768 struct displaced_step_closure
*dsc
)
3770 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3773 for (i
= 0; i
< 4; i
++)
3774 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
3776 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3780 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
3781 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3783 unsigned int rn
= bits (insn
, 16, 19);
3784 unsigned int rm
= bits (insn
, 0, 3);
3785 unsigned int rd
= bits (insn
, 12, 15);
3786 unsigned int rs
= bits (insn
, 8, 11);
3787 unsigned int op
= bits (insn
, 21, 24);
3788 int is_mov
= (op
== 0xd), i
;
3789 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
3790 CORE_ADDR from
= dsc
->insn_addr
;
3792 if (!insn_references_pc (insn
, 0x000fff0ful
))
3793 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
3795 if (debug_displaced
)
3796 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
3797 "%.8lx\n", is_mov
? "move" : "ALU",
3798 (unsigned long) insn
);
3800 /* Instruction is of form:
3802 <op><cond> rd, [rn,] rm, <shift> rs
3806 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
3807 r0, r1, r2, r3 <- rd, rn, rm, rs
3808 Insn: <op><cond> r0, r1, r2, <shift> r3
3810 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
3814 for (i
= 0; i
< 4; i
++)
3815 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
3817 rd_val
= displaced_read_reg (regs
, from
, rd
);
3818 rn_val
= displaced_read_reg (regs
, from
, rn
);
3819 rm_val
= displaced_read_reg (regs
, from
, rm
);
3820 rs_val
= displaced_read_reg (regs
, from
, rs
);
3821 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3822 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3823 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
3824 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
3828 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
3830 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
3832 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
3837 /* Clean up load instructions. */
3840 cleanup_load (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3841 struct displaced_step_closure
*dsc
)
3843 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
3844 CORE_ADDR from
= dsc
->insn_addr
;
3846 rt_val
= displaced_read_reg (regs
, from
, 0);
3847 if (dsc
->u
.ldst
.xfersize
== 8)
3848 rt_val2
= displaced_read_reg (regs
, from
, 1);
3849 rn_val
= displaced_read_reg (regs
, from
, 2);
3851 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3852 if (dsc
->u
.ldst
.xfersize
> 4)
3853 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3854 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
3855 if (!dsc
->u
.ldst
.immed
)
3856 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
3858 /* Handle register writeback. */
3859 if (dsc
->u
.ldst
.writeback
)
3860 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
3861 /* Put result in right place. */
3862 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
3863 if (dsc
->u
.ldst
.xfersize
== 8)
3864 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
3867 /* Clean up store instructions. */
3870 cleanup_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3871 struct displaced_step_closure
*dsc
)
3873 CORE_ADDR from
= dsc
->insn_addr
;
3874 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
3876 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3877 if (dsc
->u
.ldst
.xfersize
> 4)
3878 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3879 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
3880 if (!dsc
->u
.ldst
.immed
)
3881 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
3882 if (!dsc
->u
.ldst
.restore_r4
)
3883 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
3886 if (dsc
->u
.ldst
.writeback
)
3887 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
3890 /* Copy "extra" load/store instructions. These are halfword/doubleword
3891 transfers, which have a different encoding to byte/word transfers. */
3894 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
3895 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3897 unsigned int op1
= bits (insn
, 20, 24);
3898 unsigned int op2
= bits (insn
, 5, 6);
3899 unsigned int rt
= bits (insn
, 12, 15);
3900 unsigned int rn
= bits (insn
, 16, 19);
3901 unsigned int rm
= bits (insn
, 0, 3);
3902 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
3903 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
3904 int immed
= (op1
& 0x4) != 0;
3906 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
3907 CORE_ADDR from
= dsc
->insn_addr
;
3909 if (!insn_references_pc (insn
, 0x000ff00ful
))
3910 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
3912 if (debug_displaced
)
3913 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
3914 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
3915 (unsigned long) insn
);
3917 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
3920 internal_error (__FILE__
, __LINE__
,
3921 _("copy_extra_ld_st: instruction decode error"));
3923 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3924 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3925 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3927 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
3929 rt_val
= displaced_read_reg (regs
, from
, rt
);
3930 if (bytesize
[opcode
] == 8)
3931 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
3932 rn_val
= displaced_read_reg (regs
, from
, rn
);
3934 rm_val
= displaced_read_reg (regs
, from
, rm
);
3936 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
3937 if (bytesize
[opcode
] == 8)
3938 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
3939 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
3941 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
3944 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
3945 dsc
->u
.ldst
.rn
= rn
;
3946 dsc
->u
.ldst
.immed
= immed
;
3947 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
3948 dsc
->u
.ldst
.restore_r4
= 0;
3951 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
3953 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
3954 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
3956 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
3958 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
3959 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
3961 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
3966 /* Copy byte/word loads and stores. */
3969 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
3970 struct regcache
*regs
,
3971 struct displaced_step_closure
*dsc
, int load
, int byte
,
3974 int immed
= !bit (insn
, 25);
3975 unsigned int rt
= bits (insn
, 12, 15);
3976 unsigned int rn
= bits (insn
, 16, 19);
3977 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
3978 ULONGEST rt_val
, rn_val
, rm_val
= 0;
3979 CORE_ADDR from
= dsc
->insn_addr
;
3981 if (!insn_references_pc (insn
, 0x000ff00ful
))
3982 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
3984 if (debug_displaced
)
3985 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
3986 load
? (byte
? "ldrb" : "ldr")
3987 : (byte
? "strb" : "str"), usermode
? "t" : "",
3988 (unsigned long) insn
);
3990 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3991 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3993 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
3995 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
3997 rt_val
= displaced_read_reg (regs
, from
, rt
);
3998 rn_val
= displaced_read_reg (regs
, from
, rn
);
4000 rm_val
= displaced_read_reg (regs
, from
, rm
);
4002 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4003 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4005 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4008 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
4009 dsc
->u
.ldst
.rn
= rn
;
4010 dsc
->u
.ldst
.immed
= immed
;
4011 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4013 /* To write PC we can do:
4015 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
4016 scratch+4: ldr r4, temp
4017 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
4018 scratch+12: add r4, r4, #8 (r4 = offset)
4019 scratch+16: add r0, r0, r4
4020 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
4023 Otherwise we don't know what value to write for PC, since the offset is
4024 architecture-dependent (sometimes PC+8, sometimes PC+12). */
4026 if (load
|| rt
!= 15)
4028 dsc
->u
.ldst
.restore_r4
= 0;
4031 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
4033 {ldr,str}[b]<cond> r0, [r2, #imm]. */
4034 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4036 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
4038 {ldr,str}[b]<cond> r0, [r2, r3]. */
4039 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4043 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
4044 dsc
->u
.ldst
.restore_r4
= 1;
4046 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
4047 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
4048 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
4049 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
4050 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
4054 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
4056 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
4058 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
4059 dsc
->modinsn
[7] = 0x0; /* scratch space. */
4064 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
4069 /* Cleanup LDM instructions with fully-populated register list. This is an
4070 unfortunate corner case: it's impossible to implement correctly by modifying
4071 the instruction. The issue is as follows: we have an instruction,
4075 which we must rewrite to avoid loading PC. A possible solution would be to
4076 do the load in two halves, something like (with suitable cleanup
4080 ldm[id][ab] r8!, {r0-r7}
4082 ldm[id][ab] r8, {r7-r14}
4085 but at present there's no suitable place for <temp>, since the scratch space
4086 is overwritten before the cleanup routine is called. For now, we simply
4087 emulate the instruction. */
4090 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4091 struct displaced_step_closure
*dsc
)
4093 ULONGEST from
= dsc
->insn_addr
;
4094 int inc
= dsc
->u
.block
.increment
;
4095 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
4096 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
4097 uint32_t regmask
= dsc
->u
.block
.regmask
;
4098 int regno
= inc
? 0 : 15;
4099 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
4100 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
4101 && (regmask
& 0x8000) != 0;
4102 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4103 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
4104 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4109 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
4110 sensible we can do here. Complain loudly. */
4111 if (exception_return
)
4112 error (_("Cannot single-step exception return"));
4114 /* We don't handle any stores here for now. */
4115 gdb_assert (dsc
->u
.block
.load
!= 0);
4117 if (debug_displaced
)
4118 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
4119 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
4120 dsc
->u
.block
.increment
? "inc" : "dec",
4121 dsc
->u
.block
.before
? "before" : "after");
4128 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
4131 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
4134 xfer_addr
+= bump_before
;
4136 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
4137 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
4139 xfer_addr
+= bump_after
;
4141 regmask
&= ~(1 << regno
);
4144 if (dsc
->u
.block
.writeback
)
4145 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
4149 /* Clean up an STM which included the PC in the register list. */
4152 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4153 struct displaced_step_closure
*dsc
)
4155 ULONGEST from
= dsc
->insn_addr
;
4156 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4157 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
4158 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
4159 CORE_ADDR stm_insn_addr
;
4162 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4164 /* If condition code fails, there's nothing else to do. */
4165 if (!store_executed
)
4168 if (dsc
->u
.block
.increment
)
4170 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
4172 if (dsc
->u
.block
.before
)
4177 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
4179 if (dsc
->u
.block
.before
)
4183 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
4184 stm_insn_addr
= dsc
->scratch_base
;
4185 offset
= pc_val
- stm_insn_addr
;
4187 if (debug_displaced
)
4188 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
4189 "STM instruction\n", offset
);
4191 /* Rewrite the stored PC to the proper value for the non-displaced original
4193 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
4194 dsc
->insn_addr
+ offset
);
4197 /* Clean up an LDM which includes the PC in the register list. We clumped all
4198 the registers in the transferred list into a contiguous range r0...rX (to
4199 avoid loading PC directly and losing control of the debugged program), so we
4200 must undo that here. */
4203 cleanup_block_load_pc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
4204 struct regcache
*regs
,
4205 struct displaced_step_closure
*dsc
)
4207 ULONGEST from
= dsc
->insn_addr
;
4208 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4209 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
4210 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
4211 unsigned int regs_loaded
= bitcount (mask
);
4212 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
4214 /* The method employed here will fail if the register list is fully populated
4215 (we need to avoid loading PC directly). */
4216 gdb_assert (num_to_shuffle
< 16);
4221 clobbered
= (1 << num_to_shuffle
) - 1;
4223 while (num_to_shuffle
> 0)
4225 if ((mask
& (1 << write_reg
)) != 0)
4227 unsigned int read_reg
= num_to_shuffle
- 1;
4229 if (read_reg
!= write_reg
)
4231 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
4232 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
4233 if (debug_displaced
)
4234 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
4235 "loaded register r%d to r%d\n"), read_reg
,
4238 else if (debug_displaced
)
4239 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
4240 "r%d already in the right place\n"),
4243 clobbered
&= ~(1 << write_reg
);
4251 /* Restore any registers we scribbled over. */
4252 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
4254 if ((clobbered
& (1 << write_reg
)) != 0)
4256 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
4258 if (debug_displaced
)
4259 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
4260 "clobbered register r%d\n"), write_reg
);
4261 clobbered
&= ~(1 << write_reg
);
4265 /* Perform register writeback manually. */
4266 if (dsc
->u
.block
.writeback
)
4268 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
4270 if (dsc
->u
.block
.increment
)
4271 new_rn_val
+= regs_loaded
* 4;
4273 new_rn_val
-= regs_loaded
* 4;
4275 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
4280 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
4281 in user-level code (in particular exception return, ldm rn, {...pc}^). */
4284 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4285 struct displaced_step_closure
*dsc
)
4287 int load
= bit (insn
, 20);
4288 int user
= bit (insn
, 22);
4289 int increment
= bit (insn
, 23);
4290 int before
= bit (insn
, 24);
4291 int writeback
= bit (insn
, 21);
4292 int rn
= bits (insn
, 16, 19);
4293 CORE_ADDR from
= dsc
->insn_addr
;
4295 /* Block transfers which don't mention PC can be run directly out-of-line. */
4296 if (rn
!= 15 && (insn
& 0x8000) == 0)
4297 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
4301 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
4302 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
4305 if (debug_displaced
)
4306 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
4307 "%.8lx\n", (unsigned long) insn
);
4309 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
4310 dsc
->u
.block
.rn
= rn
;
4312 dsc
->u
.block
.load
= load
;
4313 dsc
->u
.block
.user
= user
;
4314 dsc
->u
.block
.increment
= increment
;
4315 dsc
->u
.block
.before
= before
;
4316 dsc
->u
.block
.writeback
= writeback
;
4317 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
4319 dsc
->u
.block
.regmask
= insn
& 0xffff;
4323 if ((insn
& 0xffff) == 0xffff)
4325 /* LDM with a fully-populated register list. This case is
4326 particularly tricky. Implement for now by fully emulating the
4327 instruction (which might not behave perfectly in all cases, but
4328 these instructions should be rare enough for that not to matter
4330 dsc
->modinsn
[0] = ARM_NOP
;
4332 dsc
->cleanup
= &cleanup_block_load_all
;
4336 /* LDM of a list of registers which includes PC. Implement by
4337 rewriting the list of registers to be transferred into a
4338 contiguous chunk r0...rX before doing the transfer, then shuffling
4339 registers into the correct places in the cleanup routine. */
4340 unsigned int regmask
= insn
& 0xffff;
4341 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
4342 unsigned int to
= 0, from
= 0, i
, new_rn
;
4344 for (i
= 0; i
< num_in_list
; i
++)
4345 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4347 /* Writeback makes things complicated. We need to avoid clobbering
4348 the base register with one of the registers in our modified
4349 register list, but just using a different register can't work in
4352 ldm r14!, {r0-r13,pc}
4354 which would need to be rewritten as:
4358 but that can't work, because there's no free register for N.
4360 Solve this by turning off the writeback bit, and emulating
4361 writeback manually in the cleanup routine. */
4366 new_regmask
= (1 << num_in_list
) - 1;
4368 if (debug_displaced
)
4369 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
4370 "{..., pc}: original reg list %.4x, modified "
4371 "list %.4x\n"), rn
, writeback
? "!" : "",
4372 (int) insn
& 0xffff, new_regmask
);
4374 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
4376 dsc
->cleanup
= &cleanup_block_load_pc
;
4381 /* STM of a list of registers which includes PC. Run the instruction
4382 as-is, but out of line: this will store the wrong value for the PC,
4383 so we must manually fix up the memory in the cleanup routine.
4384 Doing things this way has the advantage that we can auto-detect
4385 the offset of the PC write (which is architecture-dependent) in
4386 the cleanup routine. */
4387 dsc
->modinsn
[0] = insn
;
4389 dsc
->cleanup
= &cleanup_block_store_pc
;
4395 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
4396 for Linux, where some SVC instructions must be treated specially. */
4399 cleanup_svc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
4400 struct displaced_step_closure
*dsc
)
4402 CORE_ADDR from
= dsc
->insn_addr
;
4403 CORE_ADDR resume_addr
= from
+ 4;
4405 if (debug_displaced
)
4406 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
4407 "%.8lx\n", (unsigned long) resume_addr
);
4409 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
4413 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4414 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4416 CORE_ADDR from
= dsc
->insn_addr
;
4418 /* Allow OS-specific code to override SVC handling. */
4419 if (dsc
->u
.svc
.copy_svc_os
)
4420 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
4422 if (debug_displaced
)
4423 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
4424 (unsigned long) insn
);
4426 /* Preparation: none.
4427 Insn: unmodified svc.
4428 Cleanup: pc <- insn_addr + 4. */
4430 dsc
->modinsn
[0] = insn
;
4432 dsc
->cleanup
= &cleanup_svc
;
4433 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
4435 dsc
->wrote_to_pc
= 1;
4440 /* Copy undefined instructions. */
4443 copy_undef (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
4444 struct displaced_step_closure
*dsc
)
4446 if (debug_displaced
)
4447 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn %.8lx\n",
4448 (unsigned long) insn
);
4450 dsc
->modinsn
[0] = insn
;
4455 /* Copy unpredictable instructions. */
4458 copy_unpred (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
4459 struct displaced_step_closure
*dsc
)
4461 if (debug_displaced
)
4462 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
4463 "%.8lx\n", (unsigned long) insn
);
4465 dsc
->modinsn
[0] = insn
;
4470 /* The decode_* functions are instruction decoding helpers. They mostly follow
4471 the presentation in the ARM ARM. */
4474 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
4475 struct regcache
*regs
,
4476 struct displaced_step_closure
*dsc
)
4478 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
4479 unsigned int rn
= bits (insn
, 16, 19);
4481 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
4482 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
4483 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
4484 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
4485 else if ((op1
& 0x60) == 0x20)
4486 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
4487 else if ((op1
& 0x71) == 0x40)
4488 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
4489 else if ((op1
& 0x77) == 0x41)
4490 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4491 else if ((op1
& 0x77) == 0x45)
4492 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
4493 else if ((op1
& 0x77) == 0x51)
4496 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4498 return copy_unpred (gdbarch
, insn
, dsc
);
4500 else if ((op1
& 0x77) == 0x55)
4501 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4502 else if (op1
== 0x57)
4505 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
4506 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
4507 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
4508 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
4509 default: return copy_unpred (gdbarch
, insn
, dsc
);
4511 else if ((op1
& 0x63) == 0x43)
4512 return copy_unpred (gdbarch
, insn
, dsc
);
4513 else if ((op2
& 0x1) == 0x0)
4514 switch (op1
& ~0x80)
4517 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4519 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
4520 case 0x71: case 0x75:
4522 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
4523 case 0x63: case 0x67: case 0x73: case 0x77:
4524 return copy_unpred (gdbarch
, insn
, dsc
);
4526 return copy_undef (gdbarch
, insn
, dsc
);
4529 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
4533 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
4534 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4536 if (bit (insn
, 27) == 0)
4537 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
4538 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
4539 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
4542 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
4545 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
4547 case 0x4: case 0x5: case 0x6: case 0x7:
4548 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4551 switch ((insn
& 0xe00000) >> 21)
4553 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
4555 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4558 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4561 return copy_undef (gdbarch
, insn
, dsc
);
4566 int rn_f
= (bits (insn
, 16, 19) == 0xf);
4567 switch ((insn
& 0xe00000) >> 21)
4570 /* ldc/ldc2 imm (undefined for rn == pc). */
4571 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
4572 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4575 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4577 case 0x4: case 0x5: case 0x6: case 0x7:
4578 /* ldc/ldc2 lit (undefined for rn != pc). */
4579 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
4580 : copy_undef (gdbarch
, insn
, dsc
);
4583 return copy_undef (gdbarch
, insn
, dsc
);
4588 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
4591 if (bits (insn
, 16, 19) == 0xf)
4593 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4595 return copy_undef (gdbarch
, insn
, dsc
);
4599 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4601 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4605 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4607 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4610 return copy_undef (gdbarch
, insn
, dsc
);
4614 /* Decode miscellaneous instructions in dp/misc encoding space. */
4617 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
4618 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4620 unsigned int op2
= bits (insn
, 4, 6);
4621 unsigned int op
= bits (insn
, 21, 22);
4622 unsigned int op1
= bits (insn
, 16, 19);
4627 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
4630 if (op
== 0x1) /* bx. */
4631 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
4633 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
4635 return copy_undef (gdbarch
, insn
, dsc
);
4639 /* Not really supported. */
4640 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
4642 return copy_undef (gdbarch
, insn
, dsc
);
4646 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
); /* blx register. */
4648 return copy_undef (gdbarch
, insn
, dsc
);
4651 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
4655 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
4657 /* Not really supported. */
4658 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
4661 return copy_undef (gdbarch
, insn
, dsc
);
4666 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4667 struct displaced_step_closure
*dsc
)
4670 switch (bits (insn
, 20, 24))
4673 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
4676 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
4678 case 0x12: case 0x16:
4679 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
4682 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
4686 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
4688 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
4689 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
4690 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
4691 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
4692 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
4693 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
4694 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
4695 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
4696 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
4697 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
4698 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
4699 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
4700 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
4701 /* 2nd arg means "unpriveleged". */
4702 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
4706 /* Should be unreachable. */
4711 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
4712 struct regcache
*regs
,
4713 struct displaced_step_closure
*dsc
)
4715 int a
= bit (insn
, 25), b
= bit (insn
, 4);
4716 uint32_t op1
= bits (insn
, 20, 24);
4717 int rn_f
= bits (insn
, 16, 19) == 0xf;
4719 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
4720 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
4721 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
4722 else if ((!a
&& (op1
& 0x17) == 0x02)
4723 || (a
&& (op1
& 0x17) == 0x02 && !b
))
4724 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
4725 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
4726 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
4727 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
4728 else if ((!a
&& (op1
& 0x17) == 0x03)
4729 || (a
&& (op1
& 0x17) == 0x03 && !b
))
4730 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
4731 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
4732 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
4733 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
4734 else if ((!a
&& (op1
& 0x17) == 0x06)
4735 || (a
&& (op1
& 0x17) == 0x06 && !b
))
4736 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
4737 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
4738 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
4739 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
4740 else if ((!a
&& (op1
& 0x17) == 0x07)
4741 || (a
&& (op1
& 0x17) == 0x07 && !b
))
4742 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
4744 /* Should be unreachable. */
4749 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
4750 struct displaced_step_closure
*dsc
)
4752 switch (bits (insn
, 20, 24))
4754 case 0x00: case 0x01: case 0x02: case 0x03:
4755 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
4757 case 0x04: case 0x05: case 0x06: case 0x07:
4758 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
4760 case 0x08: case 0x09: case 0x0a: case 0x0b:
4761 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
4762 return copy_unmodified (gdbarch
, insn
,
4763 "decode/pack/unpack/saturate/reverse", dsc
);
4766 if (bits (insn
, 5, 7) == 0) /* op2. */
4768 if (bits (insn
, 12, 15) == 0xf)
4769 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
4771 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
4774 return copy_undef (gdbarch
, insn
, dsc
);
4776 case 0x1a: case 0x1b:
4777 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
4778 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
4780 return copy_undef (gdbarch
, insn
, dsc
);
4782 case 0x1c: case 0x1d:
4783 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
4785 if (bits (insn
, 0, 3) == 0xf)
4786 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
4788 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
4791 return copy_undef (gdbarch
, insn
, dsc
);
4793 case 0x1e: case 0x1f:
4794 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
4795 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
4797 return copy_undef (gdbarch
, insn
, dsc
);
4800 /* Should be unreachable. */
4805 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
4806 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4809 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4811 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
4815 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
4816 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4818 unsigned int opcode
= bits (insn
, 20, 24);
4822 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
4823 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
4825 case 0x08: case 0x0a: case 0x0c: case 0x0e:
4826 case 0x12: case 0x16:
4827 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
4829 case 0x09: case 0x0b: case 0x0d: case 0x0f:
4830 case 0x13: case 0x17:
4831 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
4833 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
4834 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
4835 /* Note: no writeback for these instructions. Bit 25 will always be
4836 zero though (via caller), so the following works OK. */
4837 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4840 /* Should be unreachable. */
4845 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4846 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4848 unsigned int op1
= bits (insn
, 20, 25);
4849 int op
= bit (insn
, 4);
4850 unsigned int coproc
= bits (insn
, 8, 11);
4851 unsigned int rn
= bits (insn
, 16, 19);
4853 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
4854 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
4855 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
4856 && (coproc
& 0xe) != 0xa)
4858 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4859 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
4860 && (coproc
& 0xe) != 0xa)
4861 /* ldc/ldc2 imm/lit. */
4862 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4863 else if ((op1
& 0x3e) == 0x00)
4864 return copy_undef (gdbarch
, insn
, dsc
);
4865 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
4866 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
4867 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
4868 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4869 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
4870 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4871 else if ((op1
& 0x30) == 0x20 && !op
)
4873 if ((coproc
& 0xe) == 0xa)
4874 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
4876 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4878 else if ((op1
& 0x30) == 0x20 && op
)
4879 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
4880 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
4881 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4882 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
4883 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4884 else if ((op1
& 0x30) == 0x30)
4885 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
4887 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
4891 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
4892 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
,
4893 struct displaced_step_closure
*dsc
)
4897 if (!displaced_in_arm_mode (regs
))
4898 error (_("Displaced stepping is only supported in ARM mode"));
4900 /* Most displaced instructions use a 1-instruction scratch space, so set this
4901 here and override below if/when necessary. */
4903 dsc
->insn_addr
= from
;
4904 dsc
->scratch_base
= to
;
4905 dsc
->cleanup
= NULL
;
4906 dsc
->wrote_to_pc
= 0;
4908 if ((insn
& 0xf0000000) == 0xf0000000)
4909 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
4910 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
4912 case 0x0: case 0x1: case 0x2: case 0x3:
4913 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
4916 case 0x4: case 0x5: case 0x6:
4917 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
4921 err
= decode_media (gdbarch
, insn
, dsc
);
4924 case 0x8: case 0x9: case 0xa: case 0xb:
4925 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
4928 case 0xc: case 0xd: case 0xe: case 0xf:
4929 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
4934 internal_error (__FILE__
, __LINE__
,
4935 _("arm_process_displaced_insn: Instruction decode error"));
4938 /* Actually set up the scratch space for a displaced instruction. */
4941 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
4942 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
4944 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4946 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4948 /* Poke modified instruction(s). */
4949 for (i
= 0; i
< dsc
->numinsns
; i
++)
4951 if (debug_displaced
)
4952 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
4953 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
4954 (unsigned long) to
+ i
* 4);
4955 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
4959 /* Put breakpoint afterwards. */
4960 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
4961 tdep
->arm_breakpoint_size
);
4963 if (debug_displaced
)
4964 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
4965 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
4968 /* Entry point for copying an instruction into scratch space for displaced
4971 struct displaced_step_closure
*
4972 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
4973 CORE_ADDR from
, CORE_ADDR to
,
4974 struct regcache
*regs
)
4976 struct displaced_step_closure
*dsc
4977 = xmalloc (sizeof (struct displaced_step_closure
));
4978 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4979 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
4981 if (debug_displaced
)
4982 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
4983 "at %.8lx\n", (unsigned long) insn
,
4984 (unsigned long) from
);
4986 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
4987 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
4992 /* Entry point for cleaning things up after a displaced instruction has been
4996 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
4997 struct displaced_step_closure
*dsc
,
4998 CORE_ADDR from
, CORE_ADDR to
,
4999 struct regcache
*regs
)
5002 dsc
->cleanup (gdbarch
, regs
, dsc
);
5004 if (!dsc
->wrote_to_pc
)
5005 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
5008 #include "bfd-in2.h"
5009 #include "libcoff.h"
5012 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
5014 if (arm_pc_is_thumb (memaddr
))
5016 static asymbol
*asym
;
5017 static combined_entry_type ce
;
5018 static struct coff_symbol_struct csym
;
5019 static struct bfd fake_bfd
;
5020 static bfd_target fake_target
;
5022 if (csym
.native
== NULL
)
5024 /* Create a fake symbol vector containing a Thumb symbol.
5025 This is solely so that the code in print_insn_little_arm()
5026 and print_insn_big_arm() in opcodes/arm-dis.c will detect
5027 the presence of a Thumb symbol and switch to decoding
5028 Thumb instructions. */
5030 fake_target
.flavour
= bfd_target_coff_flavour
;
5031 fake_bfd
.xvec
= &fake_target
;
5032 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
5034 csym
.symbol
.the_bfd
= &fake_bfd
;
5035 csym
.symbol
.name
= "fake";
5036 asym
= (asymbol
*) & csym
;
5039 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
5040 info
->symbols
= &asym
;
5043 info
->symbols
= NULL
;
5045 if (info
->endian
== BFD_ENDIAN_BIG
)
5046 return print_insn_big_arm (memaddr
, info
);
5048 return print_insn_little_arm (memaddr
, info
);
5051 /* The following define instruction sequences that will cause ARM
5052 cpu's to take an undefined instruction trap. These are used to
5053 signal a breakpoint to GDB.
5055 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
5056 modes. A different instruction is required for each mode. The ARM
5057 cpu's can also be big or little endian. Thus four different
5058 instructions are needed to support all cases.
5060 Note: ARMv4 defines several new instructions that will take the
5061 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
5062 not in fact add the new instructions. The new undefined
5063 instructions in ARMv4 are all instructions that had no defined
5064 behaviour in earlier chips. There is no guarantee that they will
5065 raise an exception, but may be treated as NOP's. In practice, it
5066 may only safe to rely on instructions matching:
5068 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
5069 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
5070 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
5072 Even this may only true if the condition predicate is true. The
5073 following use a condition predicate of ALWAYS so it is always TRUE.
5075 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
5076 and NetBSD all use a software interrupt rather than an undefined
5077 instruction to force a trap. This can be handled by by the
5078 abi-specific code during establishment of the gdbarch vector. */
5080 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
5081 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
5082 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
5083 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
5085 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
5086 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
5087 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
5088 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
5090 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
5091 the program counter value to determine whether a 16-bit or 32-bit
5092 breakpoint should be used. It returns a pointer to a string of
5093 bytes that encode a breakpoint instruction, stores the length of
5094 the string to *lenptr, and adjusts the program counter (if
5095 necessary) to point to the actual memory location where the
5096 breakpoint should be inserted. */
5098 static const unsigned char *
5099 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5102 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5104 if (arm_pc_is_thumb (*pcptr
))
5106 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
5108 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
5109 check whether we are replacing a 32-bit instruction. */
5110 if (tdep
->thumb2_breakpoint
!= NULL
)
5113 if (target_read_memory (*pcptr
, buf
, 2) == 0)
5115 unsigned short inst1
;
5116 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
5117 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
5119 *lenptr
= tdep
->thumb2_breakpoint_size
;
5120 return tdep
->thumb2_breakpoint
;
5125 *lenptr
= tdep
->thumb_breakpoint_size
;
5126 return tdep
->thumb_breakpoint
;
5130 *lenptr
= tdep
->arm_breakpoint_size
;
5131 return tdep
->arm_breakpoint
;
5136 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
5139 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5141 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
5143 if (arm_pc_is_thumb (*pcptr
) && *kindptr
== 4)
5144 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
5145 that this is not confused with a 32-bit ARM breakpoint. */
5149 /* Extract from an array REGBUF containing the (raw) register state a
5150 function return value of type TYPE, and copy that, in virtual
5151 format, into VALBUF. */
5154 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
5157 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5158 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5160 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
5162 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5166 /* The value is in register F0 in internal format. We need to
5167 extract the raw value and then convert it to the desired
5169 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
5171 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
5172 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
5173 valbuf
, gdbarch_byte_order (gdbarch
));
5177 case ARM_FLOAT_SOFT_FPA
:
5178 case ARM_FLOAT_SOFT_VFP
:
5179 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5180 not using the VFP ABI code. */
5182 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
5183 if (TYPE_LENGTH (type
) > 4)
5184 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
5185 valbuf
+ INT_REGISTER_SIZE
);
5190 (__FILE__
, __LINE__
,
5191 _("arm_extract_return_value: Floating point model not supported"));
5195 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5196 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5197 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5198 || TYPE_CODE (type
) == TYPE_CODE_PTR
5199 || TYPE_CODE (type
) == TYPE_CODE_REF
5200 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5202 /* If the the type is a plain integer, then the access is
5203 straight-forward. Otherwise we have to play around a bit more. */
5204 int len
= TYPE_LENGTH (type
);
5205 int regno
= ARM_A1_REGNUM
;
5210 /* By using store_unsigned_integer we avoid having to do
5211 anything special for small big-endian values. */
5212 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
5213 store_unsigned_integer (valbuf
,
5214 (len
> INT_REGISTER_SIZE
5215 ? INT_REGISTER_SIZE
: len
),
5217 len
-= INT_REGISTER_SIZE
;
5218 valbuf
+= INT_REGISTER_SIZE
;
5223 /* For a structure or union the behaviour is as if the value had
5224 been stored to word-aligned memory and then loaded into
5225 registers with 32-bit load instruction(s). */
5226 int len
= TYPE_LENGTH (type
);
5227 int regno
= ARM_A1_REGNUM
;
5228 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5232 regcache_cooked_read (regs
, regno
++, tmpbuf
);
5233 memcpy (valbuf
, tmpbuf
,
5234 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5235 len
-= INT_REGISTER_SIZE
;
5236 valbuf
+= INT_REGISTER_SIZE
;
5242 /* Will a function return an aggregate type in memory or in a
5243 register? Return 0 if an aggregate type can be returned in a
5244 register, 1 if it must be returned in memory. */
5247 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
5250 enum type_code code
;
5252 CHECK_TYPEDEF (type
);
5254 /* In the ARM ABI, "integer" like aggregate types are returned in
5255 registers. For an aggregate type to be integer like, its size
5256 must be less than or equal to INT_REGISTER_SIZE and the
5257 offset of each addressable subfield must be zero. Note that bit
5258 fields are not addressable, and all addressable subfields of
5259 unions always start at offset zero.
5261 This function is based on the behaviour of GCC 2.95.1.
5262 See: gcc/arm.c: arm_return_in_memory() for details.
5264 Note: All versions of GCC before GCC 2.95.2 do not set up the
5265 parameters correctly for a function returning the following
5266 structure: struct { float f;}; This should be returned in memory,
5267 not a register. Richard Earnshaw sent me a patch, but I do not
5268 know of any way to detect if a function like the above has been
5269 compiled with the correct calling convention. */
5271 /* All aggregate types that won't fit in a register must be returned
5273 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
5278 /* The AAPCS says all aggregates not larger than a word are returned
5280 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
5283 /* The only aggregate types that can be returned in a register are
5284 structs and unions. Arrays must be returned in memory. */
5285 code
= TYPE_CODE (type
);
5286 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
5291 /* Assume all other aggregate types can be returned in a register.
5292 Run a check for structures, unions and arrays. */
5295 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
5298 /* Need to check if this struct/union is "integer" like. For
5299 this to be true, its size must be less than or equal to
5300 INT_REGISTER_SIZE and the offset of each addressable
5301 subfield must be zero. Note that bit fields are not
5302 addressable, and unions always start at offset zero. If any
5303 of the subfields is a floating point type, the struct/union
5304 cannot be an integer type. */
5306 /* For each field in the object, check:
5307 1) Is it FP? --> yes, nRc = 1;
5308 2) Is it addressable (bitpos != 0) and
5309 not packed (bitsize == 0)?
5313 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
5315 enum type_code field_type_code
;
5316 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
5318 /* Is it a floating point type field? */
5319 if (field_type_code
== TYPE_CODE_FLT
)
5325 /* If bitpos != 0, then we have to care about it. */
5326 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
5328 /* Bitfields are not addressable. If the field bitsize is
5329 zero, then the field is not packed. Hence it cannot be
5330 a bitfield or any other packed type. */
5331 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
5343 /* Write into appropriate registers a function return value of type
5344 TYPE, given in virtual format. */
5347 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
5348 const gdb_byte
*valbuf
)
5350 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5351 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5353 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
5355 char buf
[MAX_REGISTER_SIZE
];
5357 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5361 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
5362 gdbarch_byte_order (gdbarch
));
5363 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
5366 case ARM_FLOAT_SOFT_FPA
:
5367 case ARM_FLOAT_SOFT_VFP
:
5368 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5369 not using the VFP ABI code. */
5371 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
5372 if (TYPE_LENGTH (type
) > 4)
5373 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
5374 valbuf
+ INT_REGISTER_SIZE
);
5379 (__FILE__
, __LINE__
,
5380 _("arm_store_return_value: Floating point model not supported"));
5384 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5385 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5386 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5387 || TYPE_CODE (type
) == TYPE_CODE_PTR
5388 || TYPE_CODE (type
) == TYPE_CODE_REF
5389 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5391 if (TYPE_LENGTH (type
) <= 4)
5393 /* Values of one word or less are zero/sign-extended and
5395 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5396 LONGEST val
= unpack_long (type
, valbuf
);
5398 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
5399 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
5403 /* Integral values greater than one word are stored in consecutive
5404 registers starting with r0. This will always be a multiple of
5405 the regiser size. */
5406 int len
= TYPE_LENGTH (type
);
5407 int regno
= ARM_A1_REGNUM
;
5411 regcache_cooked_write (regs
, regno
++, valbuf
);
5412 len
-= INT_REGISTER_SIZE
;
5413 valbuf
+= INT_REGISTER_SIZE
;
5419 /* For a structure or union the behaviour is as if the value had
5420 been stored to word-aligned memory and then loaded into
5421 registers with 32-bit load instruction(s). */
5422 int len
= TYPE_LENGTH (type
);
5423 int regno
= ARM_A1_REGNUM
;
5424 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5428 memcpy (tmpbuf
, valbuf
,
5429 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5430 regcache_cooked_write (regs
, regno
++, tmpbuf
);
5431 len
-= INT_REGISTER_SIZE
;
5432 valbuf
+= INT_REGISTER_SIZE
;
5438 /* Handle function return values. */
5440 static enum return_value_convention
5441 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
5442 struct type
*valtype
, struct regcache
*regcache
,
5443 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5446 enum arm_vfp_cprc_base_type vfp_base_type
;
5449 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
5450 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
5452 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
5453 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
5455 for (i
= 0; i
< vfp_base_count
; i
++)
5457 if (reg_char
== 'q')
5460 arm_neon_quad_write (gdbarch
, regcache
, i
,
5461 writebuf
+ i
* unit_length
);
5464 arm_neon_quad_read (gdbarch
, regcache
, i
,
5465 readbuf
+ i
* unit_length
);
5472 sprintf (name_buf
, "%c%d", reg_char
, i
);
5473 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5476 regcache_cooked_write (regcache
, regnum
,
5477 writebuf
+ i
* unit_length
);
5479 regcache_cooked_read (regcache
, regnum
,
5480 readbuf
+ i
* unit_length
);
5483 return RETURN_VALUE_REGISTER_CONVENTION
;
5486 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
5487 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
5488 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
5490 if (tdep
->struct_return
== pcc_struct_return
5491 || arm_return_in_memory (gdbarch
, valtype
))
5492 return RETURN_VALUE_STRUCT_CONVENTION
;
5496 arm_store_return_value (valtype
, regcache
, writebuf
);
5499 arm_extract_return_value (valtype
, regcache
, readbuf
);
5501 return RETURN_VALUE_REGISTER_CONVENTION
;
5506 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
5508 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5510 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5512 char buf
[INT_REGISTER_SIZE
];
5514 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
5516 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
5520 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
5524 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
5525 return the target PC. Otherwise return 0. */
5528 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
5532 CORE_ADDR start_addr
;
5534 /* Find the starting address and name of the function containing the PC. */
5535 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5538 /* If PC is in a Thumb call or return stub, return the address of the
5539 target PC, which is in a register. The thunk functions are called
5540 _call_via_xx, where x is the register name. The possible names
5541 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
5542 functions, named __ARM_call_via_r[0-7]. */
5543 if (strncmp (name
, "_call_via_", 10) == 0
5544 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
5546 /* Use the name suffix to determine which register contains the
5548 static char *table
[15] =
5549 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5550 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
5553 int offset
= strlen (name
) - 2;
5555 for (regno
= 0; regno
<= 14; regno
++)
5556 if (strcmp (&name
[offset
], table
[regno
]) == 0)
5557 return get_frame_register_unsigned (frame
, regno
);
5560 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
5561 non-interworking calls to foo. We could decode the stubs
5562 to find the target but it's easier to use the symbol table. */
5563 namelen
= strlen (name
);
5564 if (name
[0] == '_' && name
[1] == '_'
5565 && ((namelen
> 2 + strlen ("_from_thumb")
5566 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
5567 strlen ("_from_thumb")) == 0)
5568 || (namelen
> 2 + strlen ("_from_arm")
5569 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
5570 strlen ("_from_arm")) == 0)))
5573 int target_len
= namelen
- 2;
5574 struct minimal_symbol
*minsym
;
5575 struct objfile
*objfile
;
5576 struct obj_section
*sec
;
5578 if (name
[namelen
- 1] == 'b')
5579 target_len
-= strlen ("_from_thumb");
5581 target_len
-= strlen ("_from_arm");
5583 target_name
= alloca (target_len
+ 1);
5584 memcpy (target_name
, name
+ 2, target_len
);
5585 target_name
[target_len
] = '\0';
5587 sec
= find_pc_section (pc
);
5588 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
5589 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
5591 return SYMBOL_VALUE_ADDRESS (minsym
);
5596 return 0; /* not a stub */
5600 set_arm_command (char *args
, int from_tty
)
5602 printf_unfiltered (_("\
5603 \"set arm\" must be followed by an apporpriate subcommand.\n"));
5604 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
5608 show_arm_command (char *args
, int from_tty
)
5610 cmd_show_list (showarmcmdlist
, from_tty
, "");
5614 arm_update_current_architecture (void)
5616 struct gdbarch_info info
;
5618 /* If the current architecture is not ARM, we have nothing to do. */
5619 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
5622 /* Update the architecture. */
5623 gdbarch_info_init (&info
);
5625 if (!gdbarch_update_p (info
))
5626 internal_error (__FILE__
, __LINE__
, "could not update architecture");
5630 set_fp_model_sfunc (char *args
, int from_tty
,
5631 struct cmd_list_element
*c
)
5633 enum arm_float_model fp_model
;
5635 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
5636 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
5638 arm_fp_model
= fp_model
;
5642 if (fp_model
== ARM_FLOAT_LAST
)
5643 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
5646 arm_update_current_architecture ();
5650 show_fp_model (struct ui_file
*file
, int from_tty
,
5651 struct cmd_list_element
*c
, const char *value
)
5653 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5655 if (arm_fp_model
== ARM_FLOAT_AUTO
5656 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5657 fprintf_filtered (file
, _("\
5658 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
5659 fp_model_strings
[tdep
->fp_model
]);
5661 fprintf_filtered (file
, _("\
5662 The current ARM floating point model is \"%s\".\n"),
5663 fp_model_strings
[arm_fp_model
]);
5667 arm_set_abi (char *args
, int from_tty
,
5668 struct cmd_list_element
*c
)
5670 enum arm_abi_kind arm_abi
;
5672 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
5673 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
5675 arm_abi_global
= arm_abi
;
5679 if (arm_abi
== ARM_ABI_LAST
)
5680 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
5683 arm_update_current_architecture ();
5687 arm_show_abi (struct ui_file
*file
, int from_tty
,
5688 struct cmd_list_element
*c
, const char *value
)
5690 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5692 if (arm_abi_global
== ARM_ABI_AUTO
5693 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5694 fprintf_filtered (file
, _("\
5695 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
5696 arm_abi_strings
[tdep
->arm_abi
]);
5698 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
5703 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
5704 struct cmd_list_element
*c
, const char *value
)
5706 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5708 fprintf_filtered (file
, _("\
5709 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
5710 arm_fallback_mode_string
);
5714 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
5715 struct cmd_list_element
*c
, const char *value
)
5717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5719 fprintf_filtered (file
, _("\
5720 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
5721 arm_force_mode_string
);
5724 /* If the user changes the register disassembly style used for info
5725 register and other commands, we have to also switch the style used
5726 in opcodes for disassembly output. This function is run in the "set
5727 arm disassembly" command, and does that. */
5730 set_disassembly_style_sfunc (char *args
, int from_tty
,
5731 struct cmd_list_element
*c
)
5733 set_disassembly_style ();
5736 /* Return the ARM register name corresponding to register I. */
5738 arm_register_name (struct gdbarch
*gdbarch
, int i
)
5740 const int num_regs
= gdbarch_num_regs (gdbarch
);
5742 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
5743 && i
>= num_regs
&& i
< num_regs
+ 32)
5745 static const char *const vfp_pseudo_names
[] = {
5746 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5747 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5748 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5749 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5752 return vfp_pseudo_names
[i
- num_regs
];
5755 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
5756 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
5758 static const char *const neon_pseudo_names
[] = {
5759 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5760 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
5763 return neon_pseudo_names
[i
- num_regs
- 32];
5766 if (i
>= ARRAY_SIZE (arm_register_names
))
5767 /* These registers are only supported on targets which supply
5768 an XML description. */
5771 return arm_register_names
[i
];
5775 set_disassembly_style (void)
5779 /* Find the style that the user wants. */
5780 for (current
= 0; current
< num_disassembly_options
; current
++)
5781 if (disassembly_style
== valid_disassembly_styles
[current
])
5783 gdb_assert (current
< num_disassembly_options
);
5785 /* Synchronize the disassembler. */
5786 set_arm_regname_option (current
);
5789 /* Test whether the coff symbol specific value corresponds to a Thumb
5793 coff_sym_is_thumb (int val
)
5795 return (val
== C_THUMBEXT
5796 || val
== C_THUMBSTAT
5797 || val
== C_THUMBEXTFUNC
5798 || val
== C_THUMBSTATFUNC
5799 || val
== C_THUMBLABEL
);
5802 /* arm_coff_make_msymbol_special()
5803 arm_elf_make_msymbol_special()
5805 These functions test whether the COFF or ELF symbol corresponds to
5806 an address in thumb code, and set a "special" bit in a minimal
5807 symbol to indicate that it does. */
5810 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
5812 /* Thumb symbols are of type STT_LOPROC, (synonymous with
5814 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
5816 MSYMBOL_SET_SPECIAL (msym
);
5820 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
5822 if (coff_sym_is_thumb (val
))
5823 MSYMBOL_SET_SPECIAL (msym
);
5827 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
5829 struct arm_per_objfile
*data
= arg
;
5832 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
5833 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
5837 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
5840 const char *name
= bfd_asymbol_name (sym
);
5841 struct arm_per_objfile
*data
;
5842 VEC(arm_mapping_symbol_s
) **map_p
;
5843 struct arm_mapping_symbol new_map_sym
;
5845 gdb_assert (name
[0] == '$');
5846 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
5849 data
= objfile_data (objfile
, arm_objfile_data_key
);
5852 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
5853 struct arm_per_objfile
);
5854 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
5855 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
5856 objfile
->obfd
->section_count
,
5857 VEC(arm_mapping_symbol_s
) *);
5859 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
5861 new_map_sym
.value
= sym
->value
;
5862 new_map_sym
.type
= name
[1];
5864 /* Assume that most mapping symbols appear in order of increasing
5865 value. If they were randomly distributed, it would be faster to
5866 always push here and then sort at first use. */
5867 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
5869 struct arm_mapping_symbol
*prev_map_sym
;
5871 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
5872 if (prev_map_sym
->value
>= sym
->value
)
5875 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
5876 arm_compare_mapping_symbols
);
5877 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
5882 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
5886 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
5888 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
5890 /* If necessary, set the T bit. */
5894 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
5895 if (arm_pc_is_thumb (pc
))
5896 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
5898 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
5899 val
& ~(ULONGEST
) CPSR_T
);
5903 /* Read the contents of a NEON quad register, by reading from two
5904 double registers. This is used to implement the quad pseudo
5905 registers, and for argument passing in case the quad registers are
5906 missing; vectors are passed in quad registers when using the VFP
5907 ABI, even if a NEON unit is not present. REGNUM is the index of
5908 the quad register, in [0, 15]. */
5911 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5912 int regnum
, gdb_byte
*buf
)
5915 gdb_byte reg_buf
[8];
5916 int offset
, double_regnum
;
5918 sprintf (name_buf
, "d%d", regnum
<< 1);
5919 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5922 /* d0 is always the least significant half of q0. */
5923 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5928 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5929 memcpy (buf
+ offset
, reg_buf
, 8);
5931 offset
= 8 - offset
;
5932 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
5933 memcpy (buf
+ offset
, reg_buf
, 8);
5937 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5938 int regnum
, gdb_byte
*buf
)
5940 const int num_regs
= gdbarch_num_regs (gdbarch
);
5942 gdb_byte reg_buf
[8];
5943 int offset
, double_regnum
;
5945 gdb_assert (regnum
>= num_regs
);
5948 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
5949 /* Quad-precision register. */
5950 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
5953 /* Single-precision register. */
5954 gdb_assert (regnum
< 32);
5956 /* s0 is always the least significant half of d0. */
5957 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5958 offset
= (regnum
& 1) ? 0 : 4;
5960 offset
= (regnum
& 1) ? 4 : 0;
5962 sprintf (name_buf
, "d%d", regnum
>> 1);
5963 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5966 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5967 memcpy (buf
, reg_buf
+ offset
, 4);
5971 /* Store the contents of BUF to a NEON quad register, by writing to
5972 two double registers. This is used to implement the quad pseudo
5973 registers, and for argument passing in case the quad registers are
5974 missing; vectors are passed in quad registers when using the VFP
5975 ABI, even if a NEON unit is not present. REGNUM is the index
5976 of the quad register, in [0, 15]. */
5979 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5980 int regnum
, const gdb_byte
*buf
)
5983 gdb_byte reg_buf
[8];
5984 int offset
, double_regnum
;
5986 sprintf (name_buf
, "d%d", regnum
<< 1);
5987 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5990 /* d0 is always the least significant half of q0. */
5991 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5996 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
5997 offset
= 8 - offset
;
5998 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
6002 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6003 int regnum
, const gdb_byte
*buf
)
6005 const int num_regs
= gdbarch_num_regs (gdbarch
);
6007 gdb_byte reg_buf
[8];
6008 int offset
, double_regnum
;
6010 gdb_assert (regnum
>= num_regs
);
6013 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6014 /* Quad-precision register. */
6015 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
6018 /* Single-precision register. */
6019 gdb_assert (regnum
< 32);
6021 /* s0 is always the least significant half of d0. */
6022 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6023 offset
= (regnum
& 1) ? 0 : 4;
6025 offset
= (regnum
& 1) ? 4 : 0;
6027 sprintf (name_buf
, "d%d", regnum
>> 1);
6028 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6031 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6032 memcpy (reg_buf
+ offset
, buf
, 4);
6033 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
6037 static struct value
*
6038 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
6040 const int *reg_p
= baton
;
6041 return value_of_register (*reg_p
, frame
);
6044 static enum gdb_osabi
6045 arm_elf_osabi_sniffer (bfd
*abfd
)
6047 unsigned int elfosabi
;
6048 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
6050 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
6052 if (elfosabi
== ELFOSABI_ARM
)
6053 /* GNU tools use this value. Check note sections in this case,
6055 bfd_map_over_sections (abfd
,
6056 generic_elf_osabi_sniff_abi_tag_sections
,
6059 /* Anything else will be handled by the generic ELF sniffer. */
6064 /* Initialize the current architecture based on INFO. If possible,
6065 re-use an architecture from ARCHES, which is a list of
6066 architectures already created during this debugging session.
6068 Called e.g. at program startup, when reading a core file, and when
6069 reading a binary file. */
6071 static struct gdbarch
*
6072 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6074 struct gdbarch_tdep
*tdep
;
6075 struct gdbarch
*gdbarch
;
6076 struct gdbarch_list
*best_arch
;
6077 enum arm_abi_kind arm_abi
= arm_abi_global
;
6078 enum arm_float_model fp_model
= arm_fp_model
;
6079 struct tdesc_arch_data
*tdesc_data
= NULL
;
6081 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
6083 int have_fpa_registers
= 1;
6085 /* Check any target description for validity. */
6086 if (tdesc_has_registers (info
.target_desc
))
6088 /* For most registers we require GDB's default names; but also allow
6089 the numeric names for sp / lr / pc, as a convenience. */
6090 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
6091 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
6092 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
6094 const struct tdesc_feature
*feature
;
6097 feature
= tdesc_find_feature (info
.target_desc
,
6098 "org.gnu.gdb.arm.core");
6099 if (feature
== NULL
)
6102 tdesc_data
= tdesc_data_alloc ();
6105 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
6106 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6107 arm_register_names
[i
]);
6108 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6111 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6114 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6117 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6118 ARM_PS_REGNUM
, "cpsr");
6122 tdesc_data_cleanup (tdesc_data
);
6126 feature
= tdesc_find_feature (info
.target_desc
,
6127 "org.gnu.gdb.arm.fpa");
6128 if (feature
!= NULL
)
6131 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
6132 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6133 arm_register_names
[i
]);
6136 tdesc_data_cleanup (tdesc_data
);
6141 have_fpa_registers
= 0;
6143 feature
= tdesc_find_feature (info
.target_desc
,
6144 "org.gnu.gdb.xscale.iwmmxt");
6145 if (feature
!= NULL
)
6147 static const char *const iwmmxt_names
[] = {
6148 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
6149 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
6150 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
6151 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
6155 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
6157 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6158 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6160 /* Check for the control registers, but do not fail if they
6162 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
6163 tdesc_numbered_register (feature
, tdesc_data
, i
,
6164 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6166 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
6168 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6169 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6173 tdesc_data_cleanup (tdesc_data
);
6178 /* If we have a VFP unit, check whether the single precision registers
6179 are present. If not, then we will synthesize them as pseudo
6181 feature
= tdesc_find_feature (info
.target_desc
,
6182 "org.gnu.gdb.arm.vfp");
6183 if (feature
!= NULL
)
6185 static const char *const vfp_double_names
[] = {
6186 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
6187 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
6188 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
6189 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6192 /* Require the double precision registers. There must be either
6195 for (i
= 0; i
< 32; i
++)
6197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6199 vfp_double_names
[i
]);
6204 if (!valid_p
&& i
!= 16)
6206 tdesc_data_cleanup (tdesc_data
);
6210 if (tdesc_unnumbered_register (feature
, "s0") == 0)
6211 have_vfp_pseudos
= 1;
6213 have_vfp_registers
= 1;
6215 /* If we have VFP, also check for NEON. The architecture allows
6216 NEON without VFP (integer vector operations only), but GDB
6217 does not support that. */
6218 feature
= tdesc_find_feature (info
.target_desc
,
6219 "org.gnu.gdb.arm.neon");
6220 if (feature
!= NULL
)
6222 /* NEON requires 32 double-precision registers. */
6225 tdesc_data_cleanup (tdesc_data
);
6229 /* If there are quad registers defined by the stub, use
6230 their type; otherwise (normally) provide them with
6231 the default type. */
6232 if (tdesc_unnumbered_register (feature
, "q0") == 0)
6233 have_neon_pseudos
= 1;
6240 /* If we have an object to base this architecture on, try to determine
6243 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
6245 int ei_osabi
, e_flags
;
6247 switch (bfd_get_flavour (info
.abfd
))
6249 case bfd_target_aout_flavour
:
6250 /* Assume it's an old APCS-style ABI. */
6251 arm_abi
= ARM_ABI_APCS
;
6254 case bfd_target_coff_flavour
:
6255 /* Assume it's an old APCS-style ABI. */
6257 arm_abi
= ARM_ABI_APCS
;
6260 case bfd_target_elf_flavour
:
6261 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
6262 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6264 if (ei_osabi
== ELFOSABI_ARM
)
6266 /* GNU tools used to use this value, but do not for EABI
6267 objects. There's nowhere to tag an EABI version
6268 anyway, so assume APCS. */
6269 arm_abi
= ARM_ABI_APCS
;
6271 else if (ei_osabi
== ELFOSABI_NONE
)
6273 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
6277 case EF_ARM_EABI_UNKNOWN
:
6278 /* Assume GNU tools. */
6279 arm_abi
= ARM_ABI_APCS
;
6282 case EF_ARM_EABI_VER4
:
6283 case EF_ARM_EABI_VER5
:
6284 arm_abi
= ARM_ABI_AAPCS
;
6285 /* EABI binaries default to VFP float ordering.
6286 They may also contain build attributes that can
6287 be used to identify if the VFP argument-passing
6289 if (fp_model
== ARM_FLOAT_AUTO
)
6292 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
6297 /* "The user intended FP parameter/result
6298 passing to conform to AAPCS, base
6300 fp_model
= ARM_FLOAT_SOFT_VFP
;
6303 /* "The user intended FP parameter/result
6304 passing to conform to AAPCS, VFP
6306 fp_model
= ARM_FLOAT_VFP
;
6309 /* "The user intended FP parameter/result
6310 passing to conform to tool chain-specific
6311 conventions" - we don't know any such
6312 conventions, so leave it as "auto". */
6315 /* Attribute value not mentioned in the
6316 October 2008 ABI, so leave it as
6321 fp_model
= ARM_FLOAT_SOFT_VFP
;
6327 /* Leave it as "auto". */
6328 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
6333 if (fp_model
== ARM_FLOAT_AUTO
)
6335 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6337 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
6340 /* Leave it as "auto". Strictly speaking this case
6341 means FPA, but almost nobody uses that now, and
6342 many toolchains fail to set the appropriate bits
6343 for the floating-point model they use. */
6345 case EF_ARM_SOFT_FLOAT
:
6346 fp_model
= ARM_FLOAT_SOFT_FPA
;
6348 case EF_ARM_VFP_FLOAT
:
6349 fp_model
= ARM_FLOAT_VFP
;
6351 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
6352 fp_model
= ARM_FLOAT_SOFT_VFP
;
6357 if (e_flags
& EF_ARM_BE8
)
6358 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
6363 /* Leave it as "auto". */
6368 /* If there is already a candidate, use it. */
6369 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
6371 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
6373 if (arm_abi
!= ARM_ABI_AUTO
6374 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
6377 if (fp_model
!= ARM_FLOAT_AUTO
6378 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
6381 /* There are various other properties in tdep that we do not
6382 need to check here: those derived from a target description,
6383 since gdbarches with a different target description are
6384 automatically disqualified. */
6386 /* Found a match. */
6390 if (best_arch
!= NULL
)
6392 if (tdesc_data
!= NULL
)
6393 tdesc_data_cleanup (tdesc_data
);
6394 return best_arch
->gdbarch
;
6397 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
6398 gdbarch
= gdbarch_alloc (&info
, tdep
);
6400 /* Record additional information about the architecture we are defining.
6401 These are gdbarch discriminators, like the OSABI. */
6402 tdep
->arm_abi
= arm_abi
;
6403 tdep
->fp_model
= fp_model
;
6404 tdep
->have_fpa_registers
= have_fpa_registers
;
6405 tdep
->have_vfp_registers
= have_vfp_registers
;
6406 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
6407 tdep
->have_neon_pseudos
= have_neon_pseudos
;
6408 tdep
->have_neon
= have_neon
;
6411 switch (info
.byte_order_for_code
)
6413 case BFD_ENDIAN_BIG
:
6414 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
6415 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
6416 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
6417 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
6421 case BFD_ENDIAN_LITTLE
:
6422 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
6423 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
6424 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
6425 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
6430 internal_error (__FILE__
, __LINE__
,
6431 _("arm_gdbarch_init: bad byte order for float format"));
6434 /* On ARM targets char defaults to unsigned. */
6435 set_gdbarch_char_signed (gdbarch
, 0);
6437 /* Note: for displaced stepping, this includes the breakpoint, and one word
6438 of additional scratch space. This setting isn't used for anything beside
6439 displaced stepping at present. */
6440 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
6442 /* This should be low enough for everything. */
6443 tdep
->lowest_pc
= 0x20;
6444 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
6446 /* The default, for both APCS and AAPCS, is to return small
6447 structures in registers. */
6448 tdep
->struct_return
= reg_struct_return
;
6450 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
6451 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
6453 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
6455 /* Frame handling. */
6456 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
6457 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
6458 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
6460 frame_base_set_default (gdbarch
, &arm_normal_base
);
6462 /* Address manipulation. */
6463 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
6464 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
6466 /* Advance PC across function entry code. */
6467 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
6469 /* Skip trampolines. */
6470 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
6472 /* The stack grows downward. */
6473 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6475 /* Breakpoint manipulation. */
6476 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
6477 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
6478 arm_remote_breakpoint_from_pc
);
6480 /* Information about registers, etc. */
6481 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
6482 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
6483 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
6484 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
6485 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6487 /* This "info float" is FPA-specific. Use the generic version if we
6489 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
6490 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
6492 /* Internal <-> external register number maps. */
6493 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
6494 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
6496 set_gdbarch_register_name (gdbarch
, arm_register_name
);
6498 /* Returning results. */
6499 set_gdbarch_return_value (gdbarch
, arm_return_value
);
6502 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
6504 /* Minsymbol frobbing. */
6505 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
6506 set_gdbarch_coff_make_msymbol_special (gdbarch
,
6507 arm_coff_make_msymbol_special
);
6508 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
6510 /* Thumb-2 IT block support. */
6511 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6512 arm_adjust_breakpoint_address
);
6514 /* Virtual tables. */
6515 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6517 /* Hook in the ABI-specific overrides, if they have been registered. */
6518 gdbarch_init_osabi (info
, gdbarch
);
6520 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
6522 /* Add some default predicates. */
6523 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
6524 dwarf2_append_unwinders (gdbarch
);
6525 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
6527 /* Now we have tuned the configuration, set a few final things,
6528 based on what the OS ABI has told us. */
6530 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
6531 binaries are always marked. */
6532 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
6533 tdep
->arm_abi
= ARM_ABI_APCS
;
6535 /* We used to default to FPA for generic ARM, but almost nobody
6536 uses that now, and we now provide a way for the user to force
6537 the model. So default to the most useful variant. */
6538 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
6539 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
6541 if (tdep
->jb_pc
>= 0)
6542 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
6544 /* Floating point sizes and format. */
6545 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
6546 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
6548 set_gdbarch_double_format
6549 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6550 set_gdbarch_long_double_format
6551 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6555 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
6556 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
6559 if (have_vfp_pseudos
)
6561 /* NOTE: These are the only pseudo registers used by
6562 the ARM target at the moment. If more are added, a
6563 little more care in numbering will be needed. */
6565 int num_pseudos
= 32;
6566 if (have_neon_pseudos
)
6568 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
6569 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
6570 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
6575 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
6577 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6579 /* Override tdesc_register_type to adjust the types of VFP
6580 registers for NEON. */
6581 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6584 /* Add standard register aliases. We add aliases even for those
6585 nanes which are used by the current architecture - it's simpler,
6586 and does no harm, since nothing ever lists user registers. */
6587 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
6588 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
6589 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
6595 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6602 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
6603 (unsigned long) tdep
->lowest_pc
);
6606 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
6609 _initialize_arm_tdep (void)
6611 struct ui_file
*stb
;
6613 struct cmd_list_element
*new_set
, *new_show
;
6614 const char *setname
;
6615 const char *setdesc
;
6616 const char *const *regnames
;
6618 static char *helptext
;
6619 char regdesc
[1024], *rdptr
= regdesc
;
6620 size_t rest
= sizeof (regdesc
);
6622 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
6624 arm_objfile_data_key
6625 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
6627 /* Register an ELF OS ABI sniffer for ARM binaries. */
6628 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
6629 bfd_target_elf_flavour
,
6630 arm_elf_osabi_sniffer
);
6632 /* Get the number of possible sets of register names defined in opcodes. */
6633 num_disassembly_options
= get_arm_regname_num_options ();
6635 /* Add root prefix command for all "set arm"/"show arm" commands. */
6636 add_prefix_cmd ("arm", no_class
, set_arm_command
,
6637 _("Various ARM-specific commands."),
6638 &setarmcmdlist
, "set arm ", 0, &setlist
);
6640 add_prefix_cmd ("arm", no_class
, show_arm_command
,
6641 _("Various ARM-specific commands."),
6642 &showarmcmdlist
, "show arm ", 0, &showlist
);
6644 /* Sync the opcode insn printer with our register viewer. */
6645 parse_arm_disassembler_option ("reg-names-std");
6647 /* Initialize the array that will be passed to
6648 add_setshow_enum_cmd(). */
6649 valid_disassembly_styles
6650 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
6651 for (i
= 0; i
< num_disassembly_options
; i
++)
6653 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
6654 valid_disassembly_styles
[i
] = setname
;
6655 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
6658 /* When we find the default names, tell the disassembler to use
6660 if (!strcmp (setname
, "std"))
6662 disassembly_style
= setname
;
6663 set_arm_regname_option (i
);
6666 /* Mark the end of valid options. */
6667 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
6669 /* Create the help text. */
6670 stb
= mem_fileopen ();
6671 fprintf_unfiltered (stb
, "%s%s%s",
6672 _("The valid values are:\n"),
6674 _("The default is \"std\"."));
6675 helptext
= ui_file_xstrdup (stb
, NULL
);
6676 ui_file_delete (stb
);
6678 add_setshow_enum_cmd("disassembler", no_class
,
6679 valid_disassembly_styles
, &disassembly_style
,
6680 _("Set the disassembly style."),
6681 _("Show the disassembly style."),
6683 set_disassembly_style_sfunc
,
6684 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
6685 &setarmcmdlist
, &showarmcmdlist
);
6687 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
6688 _("Set usage of ARM 32-bit mode."),
6689 _("Show usage of ARM 32-bit mode."),
6690 _("When off, a 26-bit PC will be used."),
6692 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
6693 &setarmcmdlist
, &showarmcmdlist
);
6695 /* Add a command to allow the user to force the FPU model. */
6696 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
6697 _("Set the floating point type."),
6698 _("Show the floating point type."),
6699 _("auto - Determine the FP typefrom the OS-ABI.\n\
6700 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
6701 fpa - FPA co-processor (GCC compiled).\n\
6702 softvfp - Software FP with pure-endian doubles.\n\
6703 vfp - VFP co-processor."),
6704 set_fp_model_sfunc
, show_fp_model
,
6705 &setarmcmdlist
, &showarmcmdlist
);
6707 /* Add a command to allow the user to force the ABI. */
6708 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
6711 NULL
, arm_set_abi
, arm_show_abi
,
6712 &setarmcmdlist
, &showarmcmdlist
);
6714 /* Add two commands to allow the user to force the assumed
6716 add_setshow_enum_cmd ("fallback-mode", class_support
,
6717 arm_mode_strings
, &arm_fallback_mode_string
,
6718 _("Set the mode assumed when symbols are unavailable."),
6719 _("Show the mode assumed when symbols are unavailable."),
6720 NULL
, NULL
, arm_show_fallback_mode
,
6721 &setarmcmdlist
, &showarmcmdlist
);
6722 add_setshow_enum_cmd ("force-mode", class_support
,
6723 arm_mode_strings
, &arm_force_mode_string
,
6724 _("Set the mode assumed even when symbols are available."),
6725 _("Show the mode assumed even when symbols are available."),
6726 NULL
, NULL
, arm_show_force_mode
,
6727 &setarmcmdlist
, &showarmcmdlist
);
6729 /* Debugging flag. */
6730 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
6731 _("Set ARM debugging."),
6732 _("Show ARM debugging."),
6733 _("When on, arm-specific debugging is enabled."),
6735 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
6736 &setdebuglist
, &showdebuglist
);