1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "arch/arm-get-next-pcs.h"
52 #include "gdb/sim-arm.h"
55 #include "coff/internal.h"
61 #include "record-full.h"
64 #include "features/arm/arm-with-m.c"
65 #include "features/arm/arm-with-m-fpa-layout.c"
66 #include "features/arm/arm-with-m-vfp-d16.c"
67 #include "features/arm/arm-with-iwmmxt.c"
68 #include "features/arm/arm-with-vfpv2.c"
69 #include "features/arm/arm-with-vfpv3.c"
70 #include "features/arm/arm-with-neon.c"
78 /* Macros for setting and testing a bit in a minimal symbol that marks
79 it as Thumb function. The MSB of the minimal symbol's "info" field
80 is used for this purpose.
82 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
83 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_TARGET_FLAG_1 (msym) = 1
88 #define MSYMBOL_IS_SPECIAL(msym) \
89 MSYMBOL_TARGET_FLAG_1 (msym)
91 /* Per-objfile data used for mapping symbols. */
92 static const struct objfile_data
*arm_objfile_data_key
;
94 struct arm_mapping_symbol
99 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
100 DEF_VEC_O(arm_mapping_symbol_s
);
102 struct arm_per_objfile
104 VEC(arm_mapping_symbol_s
) **section_maps
;
107 /* The list of available "set arm ..." and "show arm ..." commands. */
108 static struct cmd_list_element
*setarmcmdlist
= NULL
;
109 static struct cmd_list_element
*showarmcmdlist
= NULL
;
111 /* The type of floating-point to use. Keep this in sync with enum
112 arm_float_model, and the help string in _initialize_arm_tdep. */
113 static const char *const fp_model_strings
[] =
123 /* A variable that can be configured by the user. */
124 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
125 static const char *current_fp_model
= "auto";
127 /* The ABI to use. Keep this in sync with arm_abi_kind. */
128 static const char *const arm_abi_strings
[] =
136 /* A variable that can be configured by the user. */
137 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
138 static const char *arm_abi_string
= "auto";
140 /* The execution mode to assume. */
141 static const char *const arm_mode_strings
[] =
149 static const char *arm_fallback_mode_string
= "auto";
150 static const char *arm_force_mode_string
= "auto";
152 /* The standard register names, and all the valid aliases for them. Note
153 that `fp', `sp' and `pc' are not added in this alias list, because they
154 have been added as builtin user registers in
155 std-regs.c:_initialize_frame_reg. */
160 } arm_register_aliases
[] = {
161 /* Basic register numbers. */
178 /* Synonyms (argument and variable registers). */
191 /* Other platform-specific names for r9. */
197 /* Names used by GCC (not listed in the ARM EABI). */
199 /* A special name from the older ATPCS. */
203 static const char *const arm_register_names
[] =
204 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
205 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
206 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
207 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
208 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
209 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
210 "fps", "cpsr" }; /* 24 25 */
212 /* Holds the current set of options to be passed to the disassembler. */
213 static char *arm_disassembler_options
;
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles
;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style
;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element
*);
225 static void show_disassembly_style_sfunc (struct ui_file
*, int,
226 struct cmd_list_element
*,
229 static void convert_from_extended (const struct floatformat
*, const void *,
231 static void convert_to_extended (const struct floatformat
*, void *,
234 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, gdb_byte
*buf
);
237 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
238 struct regcache
*regcache
,
239 int regnum
, const gdb_byte
*buf
);
242 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
245 /* get_next_pcs operations. */
246 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
247 arm_get_next_pcs_read_memory_unsigned_integer
,
248 arm_get_next_pcs_syscall_next_pc
,
249 arm_get_next_pcs_addr_bits_remove
,
250 arm_get_next_pcs_is_thumb
,
254 struct arm_prologue_cache
256 /* The stack pointer at the time this frame was created; i.e. the
257 caller's stack pointer when this function was called. It is used
258 to identify this frame. */
261 /* The frame base for this frame is just prev_sp - frame size.
262 FRAMESIZE is the distance from the frame pointer to the
263 initial stack pointer. */
267 /* The register used to hold the frame pointer for this frame. */
270 /* Saved register offsets. */
271 struct trad_frame_saved_reg
*saved_regs
;
274 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
275 CORE_ADDR prologue_start
,
276 CORE_ADDR prologue_end
,
277 struct arm_prologue_cache
*cache
);
279 /* Architecture version for displaced stepping. This effects the behaviour of
280 certain instructions, and really should not be hard-wired. */
282 #define DISPLACED_STEPPING_ARCH_VERSION 5
284 /* Set to true if the 32-bit mode is in use. */
288 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
291 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
293 if (gdbarch_tdep (gdbarch
)->is_m
)
299 /* Determine if the processor is currently executing in Thumb mode. */
302 arm_is_thumb (struct regcache
*regcache
)
305 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
307 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
309 return (cpsr
& t_bit
) != 0;
312 /* Determine if FRAME is executing in Thumb mode. */
315 arm_frame_is_thumb (struct frame_info
*frame
)
318 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
320 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
321 directly (from a signal frame or dummy frame) or by interpreting
322 the saved LR (from a prologue or DWARF frame). So consult it and
323 trust the unwinders. */
324 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
326 return (cpsr
& t_bit
) != 0;
329 /* Callback for VEC_lower_bound. */
332 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
333 const struct arm_mapping_symbol
*rhs
)
335 return lhs
->value
< rhs
->value
;
338 /* Search for the mapping symbol covering MEMADDR. If one is found,
339 return its type. Otherwise, return 0. If START is non-NULL,
340 set *START to the location of the mapping symbol. */
343 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
345 struct obj_section
*sec
;
347 /* If there are mapping symbols, consult them. */
348 sec
= find_pc_section (memaddr
);
351 struct arm_per_objfile
*data
;
352 VEC(arm_mapping_symbol_s
) *map
;
353 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
357 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
358 arm_objfile_data_key
);
361 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
362 if (!VEC_empty (arm_mapping_symbol_s
, map
))
364 struct arm_mapping_symbol
*map_sym
;
366 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
367 arm_compare_mapping_symbols
);
369 /* VEC_lower_bound finds the earliest ordered insertion
370 point. If the following symbol starts at this exact
371 address, we use that; otherwise, the preceding
372 mapping symbol covers this address. */
373 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
375 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
376 if (map_sym
->value
== map_key
.value
)
379 *start
= map_sym
->value
+ obj_section_addr (sec
);
380 return map_sym
->type
;
386 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
388 *start
= map_sym
->value
+ obj_section_addr (sec
);
389 return map_sym
->type
;
398 /* Determine if the program counter specified in MEMADDR is in a Thumb
399 function. This function should be called for addresses unrelated to
400 any executing frame; otherwise, prefer arm_frame_is_thumb. */
403 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
405 struct bound_minimal_symbol sym
;
407 struct displaced_step_closure
* dsc
408 = get_displaced_step_closure_by_addr(memaddr
);
410 /* If checking the mode of displaced instruction in copy area, the mode
411 should be determined by instruction on the original address. */
415 fprintf_unfiltered (gdb_stdlog
,
416 "displaced: check mode of %.8lx instead of %.8lx\n",
417 (unsigned long) dsc
->insn_addr
,
418 (unsigned long) memaddr
);
419 memaddr
= dsc
->insn_addr
;
422 /* If bit 0 of the address is set, assume this is a Thumb address. */
423 if (IS_THUMB_ADDR (memaddr
))
426 /* If the user wants to override the symbol table, let him. */
427 if (strcmp (arm_force_mode_string
, "arm") == 0)
429 if (strcmp (arm_force_mode_string
, "thumb") == 0)
432 /* ARM v6-M and v7-M are always in Thumb mode. */
433 if (gdbarch_tdep (gdbarch
)->is_m
)
436 /* If there are mapping symbols, consult them. */
437 type
= arm_find_mapping_symbol (memaddr
, NULL
);
441 /* Thumb functions have a "special" bit set in minimal symbols. */
442 sym
= lookup_minimal_symbol_by_pc (memaddr
);
444 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
446 /* If the user wants to override the fallback mode, let them. */
447 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
449 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
452 /* If we couldn't find any symbol, but we're talking to a running
453 target, then trust the current value of $cpsr. This lets
454 "display/i $pc" always show the correct mode (though if there is
455 a symbol table we will not reach here, so it still may not be
456 displayed in the mode it will be executed). */
457 if (target_has_registers
)
458 return arm_frame_is_thumb (get_current_frame ());
460 /* Otherwise we're out of luck; we assume ARM. */
464 /* Determine if the address specified equals any of these magic return
465 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
468 From ARMv6-M Reference Manual B1.5.8
469 Table B1-5 Exception return behavior
471 EXC_RETURN Return To Return Stack
472 0xFFFFFFF1 Handler mode Main
473 0xFFFFFFF9 Thread mode Main
474 0xFFFFFFFD Thread mode Process
476 From ARMv7-M Reference Manual B1.5.8
477 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
479 EXC_RETURN Return To Return Stack
480 0xFFFFFFF1 Handler mode Main
481 0xFFFFFFF9 Thread mode Main
482 0xFFFFFFFD Thread mode Process
484 Table B1-9 EXC_RETURN definition of exception return behavior, with
487 EXC_RETURN Return To Return Stack Frame Type
488 0xFFFFFFE1 Handler mode Main Extended
489 0xFFFFFFE9 Thread mode Main Extended
490 0xFFFFFFED Thread mode Process Extended
491 0xFFFFFFF1 Handler mode Main Basic
492 0xFFFFFFF9 Thread mode Main Basic
493 0xFFFFFFFD Thread mode Process Basic
495 For more details see "B1.5.8 Exception return behavior"
496 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
499 arm_m_addr_is_magic (CORE_ADDR addr
)
503 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
504 the exception return behavior. */
511 /* Address is magic. */
515 /* Address is not magic. */
520 /* Remove useless bits from addresses in a running program. */
522 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
524 /* On M-profile devices, do not strip the low bit from EXC_RETURN
525 (the magic exception return address). */
526 if (gdbarch_tdep (gdbarch
)->is_m
527 && arm_m_addr_is_magic (val
))
531 return UNMAKE_THUMB_ADDR (val
);
533 return (val
& 0x03fffffc);
536 /* Return 1 if PC is the start of a compiler helper function which
537 can be safely ignored during prologue skipping. IS_THUMB is true
538 if the function is known to be a Thumb function due to the way it
541 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
543 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
544 struct bound_minimal_symbol msym
;
546 msym
= lookup_minimal_symbol_by_pc (pc
);
547 if (msym
.minsym
!= NULL
548 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
549 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
551 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
553 /* The GNU linker's Thumb call stub to foo is named
555 if (strstr (name
, "_from_thumb") != NULL
)
558 /* On soft-float targets, __truncdfsf2 is called to convert promoted
559 arguments to their argument types in non-prototyped
561 if (startswith (name
, "__truncdfsf2"))
563 if (startswith (name
, "__aeabi_d2f"))
566 /* Internal functions related to thread-local storage. */
567 if (startswith (name
, "__tls_get_addr"))
569 if (startswith (name
, "__aeabi_read_tp"))
574 /* If we run against a stripped glibc, we may be unable to identify
575 special functions by name. Check for one important case,
576 __aeabi_read_tp, by comparing the *code* against the default
577 implementation (this is hand-written ARM assembler in glibc). */
580 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
581 == 0xe3e00a0f /* mov r0, #0xffff0fff */
582 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
583 == 0xe240f01f) /* sub pc, r0, #31 */
590 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
591 the first 16-bit of instruction, and INSN2 is the second 16-bit of
593 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
594 ((bits ((insn1), 0, 3) << 12) \
595 | (bits ((insn1), 10, 10) << 11) \
596 | (bits ((insn2), 12, 14) << 8) \
597 | bits ((insn2), 0, 7))
599 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
600 the 32-bit instruction. */
601 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
602 ((bits ((insn), 16, 19) << 12) \
603 | bits ((insn), 0, 11))
605 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
608 thumb_expand_immediate (unsigned int imm
)
610 unsigned int count
= imm
>> 7;
618 return (imm
& 0xff) | ((imm
& 0xff) << 16);
620 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
622 return (imm
& 0xff) | ((imm
& 0xff) << 8)
623 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
626 return (0x80 | (imm
& 0x7f)) << (32 - count
);
629 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
630 epilogue, 0 otherwise. */
633 thumb_instruction_restores_sp (unsigned short insn
)
635 return (insn
== 0x46bd /* mov sp, r7 */
636 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
637 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
640 /* Analyze a Thumb prologue, looking for a recognizable stack frame
641 and frame pointer. Scan until we encounter a store that could
642 clobber the stack frame unexpectedly, or an unknown instruction.
643 Return the last address which is definitely safe to skip for an
644 initial breakpoint. */
647 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
648 CORE_ADDR start
, CORE_ADDR limit
,
649 struct arm_prologue_cache
*cache
)
651 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
652 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
655 struct pv_area
*stack
;
656 struct cleanup
*back_to
;
658 CORE_ADDR unrecognized_pc
= 0;
660 for (i
= 0; i
< 16; i
++)
661 regs
[i
] = pv_register (i
, 0);
662 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
663 back_to
= make_cleanup_free_pv_area (stack
);
665 while (start
< limit
)
669 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
671 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
676 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
679 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
680 whether to save LR (R14). */
681 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
683 /* Calculate offsets of saved R0-R7 and LR. */
684 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
685 if (mask
& (1 << regno
))
687 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
689 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
692 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
694 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
695 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
698 else if (thumb_instruction_restores_sp (insn
))
700 /* Don't scan past the epilogue. */
703 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
704 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
706 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
707 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
708 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
710 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
711 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
712 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
714 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
715 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
716 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
717 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
718 regs
[bits (insn
, 6, 8)]);
719 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
720 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
722 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
723 int rm
= bits (insn
, 3, 6);
724 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
726 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
728 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
729 int src_reg
= (insn
& 0x78) >> 3;
730 regs
[dst_reg
] = regs
[src_reg
];
732 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
734 /* Handle stores to the stack. Normally pushes are used,
735 but with GCC -mtpcs-frame, there may be other stores
736 in the prologue to create the frame. */
737 int regno
= (insn
>> 8) & 0x7;
740 offset
= (insn
& 0xff) << 2;
741 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
743 if (pv_area_store_would_trash (stack
, addr
))
746 pv_area_store (stack
, addr
, 4, regs
[regno
]);
748 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
750 int rd
= bits (insn
, 0, 2);
751 int rn
= bits (insn
, 3, 5);
754 offset
= bits (insn
, 6, 10) << 2;
755 addr
= pv_add_constant (regs
[rn
], offset
);
757 if (pv_area_store_would_trash (stack
, addr
))
760 pv_area_store (stack
, addr
, 4, regs
[rd
]);
762 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
763 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
764 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
765 /* Ignore stores of argument registers to the stack. */
767 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
768 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
769 /* Ignore block loads from the stack, potentially copying
770 parameters from memory. */
772 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
773 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
774 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
775 /* Similarly ignore single loads from the stack. */
777 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
778 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
779 /* Skip register copies, i.e. saves to another register
780 instead of the stack. */
782 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
783 /* Recognize constant loads; even with small stacks these are necessary
785 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
786 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
788 /* Constant pool loads, for the same reason. */
789 unsigned int constant
;
792 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
793 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
794 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
796 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
798 unsigned short inst2
;
800 inst2
= read_code_unsigned_integer (start
+ 2, 2,
801 byte_order_for_code
);
803 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
805 /* BL, BLX. Allow some special function calls when
806 skipping the prologue; GCC generates these before
807 storing arguments to the stack. */
809 int j1
, j2
, imm1
, imm2
;
811 imm1
= sbits (insn
, 0, 10);
812 imm2
= bits (inst2
, 0, 10);
813 j1
= bit (inst2
, 13);
814 j2
= bit (inst2
, 11);
816 offset
= ((imm1
<< 12) + (imm2
<< 1));
817 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
819 nextpc
= start
+ 4 + offset
;
820 /* For BLX make sure to clear the low bits. */
821 if (bit (inst2
, 12) == 0)
822 nextpc
= nextpc
& 0xfffffffc;
824 if (!skip_prologue_function (gdbarch
, nextpc
,
825 bit (inst2
, 12) != 0))
829 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
831 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
833 pv_t addr
= regs
[bits (insn
, 0, 3)];
836 if (pv_area_store_would_trash (stack
, addr
))
839 /* Calculate offsets of saved registers. */
840 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
841 if (inst2
& (1 << regno
))
843 addr
= pv_add_constant (addr
, -4);
844 pv_area_store (stack
, addr
, 4, regs
[regno
]);
848 regs
[bits (insn
, 0, 3)] = addr
;
851 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
853 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
855 int regno1
= bits (inst2
, 12, 15);
856 int regno2
= bits (inst2
, 8, 11);
857 pv_t addr
= regs
[bits (insn
, 0, 3)];
859 offset
= inst2
& 0xff;
861 addr
= pv_add_constant (addr
, offset
);
863 addr
= pv_add_constant (addr
, -offset
);
865 if (pv_area_store_would_trash (stack
, addr
))
868 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
869 pv_area_store (stack
, pv_add_constant (addr
, 4),
873 regs
[bits (insn
, 0, 3)] = addr
;
876 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
877 && (inst2
& 0x0c00) == 0x0c00
878 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
880 int regno
= bits (inst2
, 12, 15);
881 pv_t addr
= regs
[bits (insn
, 0, 3)];
883 offset
= inst2
& 0xff;
885 addr
= pv_add_constant (addr
, offset
);
887 addr
= pv_add_constant (addr
, -offset
);
889 if (pv_area_store_would_trash (stack
, addr
))
892 pv_area_store (stack
, addr
, 4, regs
[regno
]);
895 regs
[bits (insn
, 0, 3)] = addr
;
898 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
899 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
901 int regno
= bits (inst2
, 12, 15);
904 offset
= inst2
& 0xfff;
905 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
907 if (pv_area_store_would_trash (stack
, addr
))
910 pv_area_store (stack
, addr
, 4, regs
[regno
]);
913 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
914 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
915 /* Ignore stores of argument registers to the stack. */
918 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
919 && (inst2
& 0x0d00) == 0x0c00
920 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
921 /* Ignore stores of argument registers to the stack. */
924 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
926 && (inst2
& 0x8000) == 0x0000
927 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
928 /* Ignore block loads from the stack, potentially copying
929 parameters from memory. */
932 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
934 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
935 /* Similarly ignore dual loads from the stack. */
938 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
939 && (inst2
& 0x0d00) == 0x0c00
940 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
941 /* Similarly ignore single loads from the stack. */
944 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
945 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
946 /* Similarly ignore single loads from the stack. */
949 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
950 && (inst2
& 0x8000) == 0x0000)
952 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
953 | (bits (inst2
, 12, 14) << 8)
954 | bits (inst2
, 0, 7));
956 regs
[bits (inst2
, 8, 11)]
957 = pv_add_constant (regs
[bits (insn
, 0, 3)],
958 thumb_expand_immediate (imm
));
961 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
962 && (inst2
& 0x8000) == 0x0000)
964 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
965 | (bits (inst2
, 12, 14) << 8)
966 | bits (inst2
, 0, 7));
968 regs
[bits (inst2
, 8, 11)]
969 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
972 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
973 && (inst2
& 0x8000) == 0x0000)
975 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
976 | (bits (inst2
, 12, 14) << 8)
977 | bits (inst2
, 0, 7));
979 regs
[bits (inst2
, 8, 11)]
980 = pv_add_constant (regs
[bits (insn
, 0, 3)],
981 - (CORE_ADDR
) thumb_expand_immediate (imm
));
984 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
985 && (inst2
& 0x8000) == 0x0000)
987 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
988 | (bits (inst2
, 12, 14) << 8)
989 | bits (inst2
, 0, 7));
991 regs
[bits (inst2
, 8, 11)]
992 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
995 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
997 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
998 | (bits (inst2
, 12, 14) << 8)
999 | bits (inst2
, 0, 7));
1001 regs
[bits (inst2
, 8, 11)]
1002 = pv_constant (thumb_expand_immediate (imm
));
1005 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1008 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1010 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1013 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1014 && (inst2
& 0xf0f0) == 0)
1016 int dst_reg
= (inst2
& 0x0f00) >> 8;
1017 int src_reg
= inst2
& 0xf;
1018 regs
[dst_reg
] = regs
[src_reg
];
1021 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1023 /* Constant pool loads. */
1024 unsigned int constant
;
1027 offset
= bits (inst2
, 0, 11);
1029 loc
= start
+ 4 + offset
;
1031 loc
= start
+ 4 - offset
;
1033 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1034 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1037 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1039 /* Constant pool loads. */
1040 unsigned int constant
;
1043 offset
= bits (inst2
, 0, 7) << 2;
1045 loc
= start
+ 4 + offset
;
1047 loc
= start
+ 4 - offset
;
1049 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1050 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1052 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1053 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1056 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1058 /* Don't scan past anything that might change control flow. */
1063 /* The optimizer might shove anything into the prologue,
1064 so we just skip what we don't recognize. */
1065 unrecognized_pc
= start
;
1070 else if (thumb_instruction_changes_pc (insn
))
1072 /* Don't scan past anything that might change control flow. */
1077 /* The optimizer might shove anything into the prologue,
1078 so we just skip what we don't recognize. */
1079 unrecognized_pc
= start
;
1086 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1087 paddress (gdbarch
, start
));
1089 if (unrecognized_pc
== 0)
1090 unrecognized_pc
= start
;
1094 do_cleanups (back_to
);
1095 return unrecognized_pc
;
1098 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1100 /* Frame pointer is fp. Frame size is constant. */
1101 cache
->framereg
= ARM_FP_REGNUM
;
1102 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1104 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1106 /* Frame pointer is r7. Frame size is constant. */
1107 cache
->framereg
= THUMB_FP_REGNUM
;
1108 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1112 /* Try the stack pointer... this is a bit desperate. */
1113 cache
->framereg
= ARM_SP_REGNUM
;
1114 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1117 for (i
= 0; i
< 16; i
++)
1118 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1119 cache
->saved_regs
[i
].addr
= offset
;
1121 do_cleanups (back_to
);
1122 return unrecognized_pc
;
1126 /* Try to analyze the instructions starting from PC, which load symbol
1127 __stack_chk_guard. Return the address of instruction after loading this
1128 symbol, set the dest register number to *BASEREG, and set the size of
1129 instructions for loading symbol in OFFSET. Return 0 if instructions are
1133 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1134 unsigned int *destreg
, int *offset
)
1136 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1137 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1138 unsigned int low
, high
, address
;
1143 unsigned short insn1
1144 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1146 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1148 *destreg
= bits (insn1
, 8, 10);
1150 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1151 address
= read_memory_unsigned_integer (address
, 4,
1152 byte_order_for_code
);
1154 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1156 unsigned short insn2
1157 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1159 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1162 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1164 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1166 /* movt Rd, #const */
1167 if ((insn1
& 0xfbc0) == 0xf2c0)
1169 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1170 *destreg
= bits (insn2
, 8, 11);
1172 address
= (high
<< 16 | low
);
1179 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1181 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1183 address
= bits (insn
, 0, 11) + pc
+ 8;
1184 address
= read_memory_unsigned_integer (address
, 4,
1185 byte_order_for_code
);
1187 *destreg
= bits (insn
, 12, 15);
1190 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1192 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1195 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1197 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1199 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1200 *destreg
= bits (insn
, 12, 15);
1202 address
= (high
<< 16 | low
);
1210 /* Try to skip a sequence of instructions used for stack protector. If PC
1211 points to the first instruction of this sequence, return the address of
1212 first instruction after this sequence, otherwise, return original PC.
1214 On arm, this sequence of instructions is composed of mainly three steps,
1215 Step 1: load symbol __stack_chk_guard,
1216 Step 2: load from address of __stack_chk_guard,
1217 Step 3: store it to somewhere else.
1219 Usually, instructions on step 2 and step 3 are the same on various ARM
1220 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1221 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1222 instructions in step 1 vary from different ARM architectures. On ARMv7,
1225 movw Rn, #:lower16:__stack_chk_guard
1226 movt Rn, #:upper16:__stack_chk_guard
1233 .word __stack_chk_guard
1235 Since ldr/str is a very popular instruction, we can't use them as
1236 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1237 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1238 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1241 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1243 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1244 unsigned int basereg
;
1245 struct bound_minimal_symbol stack_chk_guard
;
1247 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1250 /* Try to parse the instructions in Step 1. */
1251 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1256 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1257 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1258 Otherwise, this sequence cannot be for stack protector. */
1259 if (stack_chk_guard
.minsym
== NULL
1260 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1265 unsigned int destreg
;
1267 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1269 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1270 if ((insn
& 0xf800) != 0x6800)
1272 if (bits (insn
, 3, 5) != basereg
)
1274 destreg
= bits (insn
, 0, 2);
1276 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1277 byte_order_for_code
);
1278 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1279 if ((insn
& 0xf800) != 0x6000)
1281 if (destreg
!= bits (insn
, 0, 2))
1286 unsigned int destreg
;
1288 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1290 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1291 if ((insn
& 0x0e500000) != 0x04100000)
1293 if (bits (insn
, 16, 19) != basereg
)
1295 destreg
= bits (insn
, 12, 15);
1296 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1297 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1298 4, byte_order_for_code
);
1299 if ((insn
& 0x0e500000) != 0x04000000)
1301 if (bits (insn
, 12, 15) != destreg
)
1304 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1307 return pc
+ offset
+ 4;
1309 return pc
+ offset
+ 8;
1312 /* Advance the PC across any function entry prologue instructions to
1313 reach some "real" code.
1315 The APCS (ARM Procedure Call Standard) defines the following
1319 [stmfd sp!, {a1,a2,a3,a4}]
1320 stmfd sp!, {...,fp,ip,lr,pc}
1321 [stfe f7, [sp, #-12]!]
1322 [stfe f6, [sp, #-12]!]
1323 [stfe f5, [sp, #-12]!]
1324 [stfe f4, [sp, #-12]!]
1325 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1328 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1330 CORE_ADDR func_addr
, limit_pc
;
1332 /* See if we can determine the end of the prologue via the symbol table.
1333 If so, then return either PC, or the PC after the prologue, whichever
1335 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1337 CORE_ADDR post_prologue_pc
1338 = skip_prologue_using_sal (gdbarch
, func_addr
);
1339 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1341 if (post_prologue_pc
)
1343 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1346 /* GCC always emits a line note before the prologue and another
1347 one after, even if the two are at the same address or on the
1348 same line. Take advantage of this so that we do not need to
1349 know every instruction that might appear in the prologue. We
1350 will have producer information for most binaries; if it is
1351 missing (e.g. for -gstabs), assuming the GNU tools. */
1352 if (post_prologue_pc
1354 || COMPUNIT_PRODUCER (cust
) == NULL
1355 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1356 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1357 return post_prologue_pc
;
1359 if (post_prologue_pc
!= 0)
1361 CORE_ADDR analyzed_limit
;
1363 /* For non-GCC compilers, make sure the entire line is an
1364 acceptable prologue; GDB will round this function's
1365 return value up to the end of the following line so we
1366 can not skip just part of a line (and we do not want to).
1368 RealView does not treat the prologue specially, but does
1369 associate prologue code with the opening brace; so this
1370 lets us skip the first line if we think it is the opening
1372 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1373 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1374 post_prologue_pc
, NULL
);
1376 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1377 post_prologue_pc
, NULL
);
1379 if (analyzed_limit
!= post_prologue_pc
)
1382 return post_prologue_pc
;
1386 /* Can't determine prologue from the symbol table, need to examine
1389 /* Find an upper limit on the function prologue using the debug
1390 information. If the debug information could not be used to provide
1391 that bound, then use an arbitrary large number as the upper bound. */
1392 /* Like arm_scan_prologue, stop no later than pc + 64. */
1393 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1395 limit_pc
= pc
+ 64; /* Magic. */
1398 /* Check if this is Thumb code. */
1399 if (arm_pc_is_thumb (gdbarch
, pc
))
1400 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1402 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1406 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1407 This function decodes a Thumb function prologue to determine:
1408 1) the size of the stack frame
1409 2) which registers are saved on it
1410 3) the offsets of saved regs
1411 4) the offset from the stack pointer to the frame pointer
1413 A typical Thumb function prologue would create this stack frame
1414 (offsets relative to FP)
1415 old SP -> 24 stack parameters
1418 R7 -> 0 local variables (16 bytes)
1419 SP -> -12 additional stack space (12 bytes)
1420 The frame size would thus be 36 bytes, and the frame offset would be
1421 12 bytes. The frame register is R7.
1423 The comments for thumb_skip_prolog() describe the algorithm we use
1424 to detect the end of the prolog. */
1428 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1429 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1431 CORE_ADDR prologue_start
;
1432 CORE_ADDR prologue_end
;
1434 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1437 /* See comment in arm_scan_prologue for an explanation of
1439 if (prologue_end
> prologue_start
+ 64)
1441 prologue_end
= prologue_start
+ 64;
1445 /* We're in the boondocks: we have no idea where the start of the
1449 prologue_end
= std::min (prologue_end
, prev_pc
);
1451 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1454 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1458 arm_instruction_restores_sp (unsigned int insn
)
1460 if (bits (insn
, 28, 31) != INST_NV
)
1462 if ((insn
& 0x0df0f000) == 0x0080d000
1463 /* ADD SP (register or immediate). */
1464 || (insn
& 0x0df0f000) == 0x0040d000
1465 /* SUB SP (register or immediate). */
1466 || (insn
& 0x0ffffff0) == 0x01a0d000
1468 || (insn
& 0x0fff0000) == 0x08bd0000
1470 || (insn
& 0x0fff0000) == 0x049d0000)
1471 /* POP of a single register. */
1478 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1479 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1480 fill it in. Return the first address not recognized as a prologue
1483 We recognize all the instructions typically found in ARM prologues,
1484 plus harmless instructions which can be skipped (either for analysis
1485 purposes, or a more restrictive set that can be skipped when finding
1486 the end of the prologue). */
1489 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1490 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1491 struct arm_prologue_cache
*cache
)
1493 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1495 CORE_ADDR offset
, current_pc
;
1496 pv_t regs
[ARM_FPS_REGNUM
];
1497 struct pv_area
*stack
;
1498 struct cleanup
*back_to
;
1499 CORE_ADDR unrecognized_pc
= 0;
1501 /* Search the prologue looking for instructions that set up the
1502 frame pointer, adjust the stack pointer, and save registers.
1504 Be careful, however, and if it doesn't look like a prologue,
1505 don't try to scan it. If, for instance, a frameless function
1506 begins with stmfd sp!, then we will tell ourselves there is
1507 a frame, which will confuse stack traceback, as well as "finish"
1508 and other operations that rely on a knowledge of the stack
1511 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1512 regs
[regno
] = pv_register (regno
, 0);
1513 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1514 back_to
= make_cleanup_free_pv_area (stack
);
1516 for (current_pc
= prologue_start
;
1517 current_pc
< prologue_end
;
1521 = read_code_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1523 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1525 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1528 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1529 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1531 unsigned imm
= insn
& 0xff; /* immediate value */
1532 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1533 int rd
= bits (insn
, 12, 15);
1534 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1535 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1538 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1539 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1541 unsigned imm
= insn
& 0xff; /* immediate value */
1542 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1543 int rd
= bits (insn
, 12, 15);
1544 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1545 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1548 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1551 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1553 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1554 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1555 regs
[bits (insn
, 12, 15)]);
1558 else if ((insn
& 0xffff0000) == 0xe92d0000)
1559 /* stmfd sp!, {..., fp, ip, lr, pc}
1561 stmfd sp!, {a1, a2, a3, a4} */
1563 int mask
= insn
& 0xffff;
1565 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1568 /* Calculate offsets of saved registers. */
1569 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1570 if (mask
& (1 << regno
))
1573 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1574 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1577 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1578 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1579 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1581 /* No need to add this to saved_regs -- it's just an arg reg. */
1584 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1585 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1586 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1588 /* No need to add this to saved_regs -- it's just an arg reg. */
1591 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1593 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1595 /* No need to add this to saved_regs -- it's just arg regs. */
1598 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1600 unsigned imm
= insn
& 0xff; /* immediate value */
1601 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1602 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1603 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1605 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1607 unsigned imm
= insn
& 0xff; /* immediate value */
1608 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1609 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1610 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1612 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1614 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1616 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1619 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1620 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1621 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1623 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1625 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1627 int n_saved_fp_regs
;
1628 unsigned int fp_start_reg
, fp_bound_reg
;
1630 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1633 if ((insn
& 0x800) == 0x800) /* N0 is set */
1635 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1636 n_saved_fp_regs
= 3;
1638 n_saved_fp_regs
= 1;
1642 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1643 n_saved_fp_regs
= 2;
1645 n_saved_fp_regs
= 4;
1648 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1649 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1650 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1652 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1653 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1654 regs
[fp_start_reg
++]);
1657 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1659 /* Allow some special function calls when skipping the
1660 prologue; GCC generates these before storing arguments to
1662 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1664 if (skip_prologue_function (gdbarch
, dest
, 0))
1669 else if ((insn
& 0xf0000000) != 0xe0000000)
1670 break; /* Condition not true, exit early. */
1671 else if (arm_instruction_changes_pc (insn
))
1672 /* Don't scan past anything that might change control flow. */
1674 else if (arm_instruction_restores_sp (insn
))
1676 /* Don't scan past the epilogue. */
1679 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1680 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1681 /* Ignore block loads from the stack, potentially copying
1682 parameters from memory. */
1684 else if ((insn
& 0xfc500000) == 0xe4100000
1685 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1686 /* Similarly ignore single loads from the stack. */
1688 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1689 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1690 register instead of the stack. */
1694 /* The optimizer might shove anything into the prologue, if
1695 we build up cache (cache != NULL) from scanning prologue,
1696 we just skip what we don't recognize and scan further to
1697 make cache as complete as possible. However, if we skip
1698 prologue, we'll stop immediately on unrecognized
1700 unrecognized_pc
= current_pc
;
1708 if (unrecognized_pc
== 0)
1709 unrecognized_pc
= current_pc
;
1713 int framereg
, framesize
;
1715 /* The frame size is just the distance from the frame register
1716 to the original stack pointer. */
1717 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1719 /* Frame pointer is fp. */
1720 framereg
= ARM_FP_REGNUM
;
1721 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1725 /* Try the stack pointer... this is a bit desperate. */
1726 framereg
= ARM_SP_REGNUM
;
1727 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1730 cache
->framereg
= framereg
;
1731 cache
->framesize
= framesize
;
1733 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1734 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1735 cache
->saved_regs
[regno
].addr
= offset
;
1739 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1740 paddress (gdbarch
, unrecognized_pc
));
1742 do_cleanups (back_to
);
1743 return unrecognized_pc
;
1747 arm_scan_prologue (struct frame_info
*this_frame
,
1748 struct arm_prologue_cache
*cache
)
1750 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1751 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1752 CORE_ADDR prologue_start
, prologue_end
;
1753 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1754 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1756 /* Assume there is no frame until proven otherwise. */
1757 cache
->framereg
= ARM_SP_REGNUM
;
1758 cache
->framesize
= 0;
1760 /* Check for Thumb prologue. */
1761 if (arm_frame_is_thumb (this_frame
))
1763 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1767 /* Find the function prologue. If we can't find the function in
1768 the symbol table, peek in the stack frame to find the PC. */
1769 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1772 /* One way to find the end of the prologue (which works well
1773 for unoptimized code) is to do the following:
1775 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1778 prologue_end = prev_pc;
1779 else if (sal.end < prologue_end)
1780 prologue_end = sal.end;
1782 This mechanism is very accurate so long as the optimizer
1783 doesn't move any instructions from the function body into the
1784 prologue. If this happens, sal.end will be the last
1785 instruction in the first hunk of prologue code just before
1786 the first instruction that the scheduler has moved from
1787 the body to the prologue.
1789 In order to make sure that we scan all of the prologue
1790 instructions, we use a slightly less accurate mechanism which
1791 may scan more than necessary. To help compensate for this
1792 lack of accuracy, the prologue scanning loop below contains
1793 several clauses which'll cause the loop to terminate early if
1794 an implausible prologue instruction is encountered.
1800 is a suitable endpoint since it accounts for the largest
1801 possible prologue plus up to five instructions inserted by
1804 if (prologue_end
> prologue_start
+ 64)
1806 prologue_end
= prologue_start
+ 64; /* See above. */
1811 /* We have no symbol information. Our only option is to assume this
1812 function has a standard stack frame and the normal frame register.
1813 Then, we can find the value of our frame pointer on entrance to
1814 the callee (or at the present moment if this is the innermost frame).
1815 The value stored there should be the address of the stmfd + 8. */
1816 CORE_ADDR frame_loc
;
1817 ULONGEST return_value
;
1819 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1820 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
1825 prologue_start
= gdbarch_addr_bits_remove
1826 (gdbarch
, return_value
) - 8;
1827 prologue_end
= prologue_start
+ 64; /* See above. */
1831 if (prev_pc
< prologue_end
)
1832 prologue_end
= prev_pc
;
1834 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1837 static struct arm_prologue_cache
*
1838 arm_make_prologue_cache (struct frame_info
*this_frame
)
1841 struct arm_prologue_cache
*cache
;
1842 CORE_ADDR unwound_fp
;
1844 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1845 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1847 arm_scan_prologue (this_frame
, cache
);
1849 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1850 if (unwound_fp
== 0)
1853 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1855 /* Calculate actual addresses of saved registers using offsets
1856 determined by arm_scan_prologue. */
1857 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1858 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1859 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1864 /* Implementation of the stop_reason hook for arm_prologue frames. */
1866 static enum unwind_stop_reason
1867 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1870 struct arm_prologue_cache
*cache
;
1873 if (*this_cache
== NULL
)
1874 *this_cache
= arm_make_prologue_cache (this_frame
);
1875 cache
= (struct arm_prologue_cache
*) *this_cache
;
1877 /* This is meant to halt the backtrace at "_start". */
1878 pc
= get_frame_pc (this_frame
);
1879 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1880 return UNWIND_OUTERMOST
;
1882 /* If we've hit a wall, stop. */
1883 if (cache
->prev_sp
== 0)
1884 return UNWIND_OUTERMOST
;
1886 return UNWIND_NO_REASON
;
1889 /* Our frame ID for a normal frame is the current function's starting PC
1890 and the caller's SP when we were called. */
1893 arm_prologue_this_id (struct frame_info
*this_frame
,
1895 struct frame_id
*this_id
)
1897 struct arm_prologue_cache
*cache
;
1901 if (*this_cache
== NULL
)
1902 *this_cache
= arm_make_prologue_cache (this_frame
);
1903 cache
= (struct arm_prologue_cache
*) *this_cache
;
1905 /* Use function start address as part of the frame ID. If we cannot
1906 identify the start address (due to missing symbol information),
1907 fall back to just using the current PC. */
1908 pc
= get_frame_pc (this_frame
);
1909 func
= get_frame_func (this_frame
);
1913 id
= frame_id_build (cache
->prev_sp
, func
);
1917 static struct value
*
1918 arm_prologue_prev_register (struct frame_info
*this_frame
,
1922 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1923 struct arm_prologue_cache
*cache
;
1925 if (*this_cache
== NULL
)
1926 *this_cache
= arm_make_prologue_cache (this_frame
);
1927 cache
= (struct arm_prologue_cache
*) *this_cache
;
1929 /* If we are asked to unwind the PC, then we need to return the LR
1930 instead. The prologue may save PC, but it will point into this
1931 frame's prologue, not the next frame's resume location. Also
1932 strip the saved T bit. A valid LR may have the low bit set, but
1933 a valid PC never does. */
1934 if (prev_regnum
== ARM_PC_REGNUM
)
1938 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1939 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1940 arm_addr_bits_remove (gdbarch
, lr
));
1943 /* SP is generally not saved to the stack, but this frame is
1944 identified by the next frame's stack pointer at the time of the call.
1945 The value was already reconstructed into PREV_SP. */
1946 if (prev_regnum
== ARM_SP_REGNUM
)
1947 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1949 /* The CPSR may have been changed by the call instruction and by the
1950 called function. The only bit we can reconstruct is the T bit,
1951 by checking the low bit of LR as of the call. This is a reliable
1952 indicator of Thumb-ness except for some ARM v4T pre-interworking
1953 Thumb code, which could get away with a clear low bit as long as
1954 the called function did not use bx. Guess that all other
1955 bits are unchanged; the condition flags are presumably lost,
1956 but the processor status is likely valid. */
1957 if (prev_regnum
== ARM_PS_REGNUM
)
1960 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1962 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1963 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1964 if (IS_THUMB_ADDR (lr
))
1968 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1971 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1975 struct frame_unwind arm_prologue_unwind
= {
1977 arm_prologue_unwind_stop_reason
,
1978 arm_prologue_this_id
,
1979 arm_prologue_prev_register
,
1981 default_frame_sniffer
1984 /* Maintain a list of ARM exception table entries per objfile, similar to the
1985 list of mapping symbols. We only cache entries for standard ARM-defined
1986 personality routines; the cache will contain only the frame unwinding
1987 instructions associated with the entry (not the descriptors). */
1989 static const struct objfile_data
*arm_exidx_data_key
;
1991 struct arm_exidx_entry
1996 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1997 DEF_VEC_O(arm_exidx_entry_s
);
1999 struct arm_exidx_data
2001 VEC(arm_exidx_entry_s
) **section_maps
;
2005 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2007 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2010 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2011 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2015 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2016 const struct arm_exidx_entry
*rhs
)
2018 return lhs
->addr
< rhs
->addr
;
2021 static struct obj_section
*
2022 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2024 struct obj_section
*osect
;
2026 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2027 if (bfd_get_section_flags (objfile
->obfd
,
2028 osect
->the_bfd_section
) & SEC_ALLOC
)
2030 bfd_vma start
, size
;
2031 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2032 size
= bfd_get_section_size (osect
->the_bfd_section
);
2034 if (start
<= vma
&& vma
< start
+ size
)
2041 /* Parse contents of exception table and exception index sections
2042 of OBJFILE, and fill in the exception table entry cache.
2044 For each entry that refers to a standard ARM-defined personality
2045 routine, extract the frame unwinding instructions (from either
2046 the index or the table section). The unwinding instructions
2048 - extracting them from the rest of the table data
2049 - converting to host endianness
2050 - appending the implicit 0xb0 ("Finish") code
2052 The extracted and normalized instructions are stored for later
2053 retrieval by the arm_find_exidx_entry routine. */
2056 arm_exidx_new_objfile (struct objfile
*objfile
)
2058 struct cleanup
*cleanups
;
2059 struct arm_exidx_data
*data
;
2060 asection
*exidx
, *extab
;
2061 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2062 bfd_size_type exidx_size
= 0, extab_size
= 0;
2063 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2066 /* If we've already touched this file, do nothing. */
2067 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2069 cleanups
= make_cleanup (null_cleanup
, NULL
);
2071 /* Read contents of exception table and index. */
2072 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2075 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2076 exidx_size
= bfd_get_section_size (exidx
);
2077 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2078 make_cleanup (xfree
, exidx_data
);
2080 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2081 exidx_data
, 0, exidx_size
))
2083 do_cleanups (cleanups
);
2088 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2091 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2092 extab_size
= bfd_get_section_size (extab
);
2093 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2094 make_cleanup (xfree
, extab_data
);
2096 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2097 extab_data
, 0, extab_size
))
2099 do_cleanups (cleanups
);
2104 /* Allocate exception table data structure. */
2105 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2106 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2107 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2108 objfile
->obfd
->section_count
,
2109 VEC(arm_exidx_entry_s
) *);
2111 /* Fill in exception table. */
2112 for (i
= 0; i
< exidx_size
/ 8; i
++)
2114 struct arm_exidx_entry new_exidx_entry
;
2115 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2116 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2117 bfd_vma addr
= 0, word
= 0;
2118 int n_bytes
= 0, n_words
= 0;
2119 struct obj_section
*sec
;
2120 gdb_byte
*entry
= NULL
;
2122 /* Extract address of start of function. */
2123 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2124 idx
+= exidx_vma
+ i
* 8;
2126 /* Find section containing function and compute section offset. */
2127 sec
= arm_obj_section_from_vma (objfile
, idx
);
2130 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2132 /* Determine address of exception table entry. */
2135 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2137 else if ((val
& 0xff000000) == 0x80000000)
2139 /* Exception table entry embedded in .ARM.exidx
2140 -- must be short form. */
2144 else if (!(val
& 0x80000000))
2146 /* Exception table entry in .ARM.extab. */
2147 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2148 addr
+= exidx_vma
+ i
* 8 + 4;
2150 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2152 word
= bfd_h_get_32 (objfile
->obfd
,
2153 extab_data
+ addr
- extab_vma
);
2156 if ((word
& 0xff000000) == 0x80000000)
2161 else if ((word
& 0xff000000) == 0x81000000
2162 || (word
& 0xff000000) == 0x82000000)
2166 n_words
= ((word
>> 16) & 0xff);
2168 else if (!(word
& 0x80000000))
2171 struct obj_section
*pers_sec
;
2172 int gnu_personality
= 0;
2174 /* Custom personality routine. */
2175 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2176 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2178 /* Check whether we've got one of the variants of the
2179 GNU personality routines. */
2180 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2183 static const char *personality
[] =
2185 "__gcc_personality_v0",
2186 "__gxx_personality_v0",
2187 "__gcj_personality_v0",
2188 "__gnu_objc_personality_v0",
2192 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2195 for (k
= 0; personality
[k
]; k
++)
2196 if (lookup_minimal_symbol_by_pc_name
2197 (pc
, personality
[k
], objfile
))
2199 gnu_personality
= 1;
2204 /* If so, the next word contains a word count in the high
2205 byte, followed by the same unwind instructions as the
2206 pre-defined forms. */
2208 && addr
+ 4 <= extab_vma
+ extab_size
)
2210 word
= bfd_h_get_32 (objfile
->obfd
,
2211 extab_data
+ addr
- extab_vma
);
2214 n_words
= ((word
>> 24) & 0xff);
2220 /* Sanity check address. */
2222 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2223 n_words
= n_bytes
= 0;
2225 /* The unwind instructions reside in WORD (only the N_BYTES least
2226 significant bytes are valid), followed by N_WORDS words in the
2227 extab section starting at ADDR. */
2228 if (n_bytes
|| n_words
)
2231 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2232 n_bytes
+ n_words
* 4 + 1);
2235 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2239 word
= bfd_h_get_32 (objfile
->obfd
,
2240 extab_data
+ addr
- extab_vma
);
2243 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2244 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2245 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2246 *p
++ = (gdb_byte
) (word
& 0xff);
2249 /* Implied "Finish" to terminate the list. */
2253 /* Push entry onto vector. They are guaranteed to always
2254 appear in order of increasing addresses. */
2255 new_exidx_entry
.addr
= idx
;
2256 new_exidx_entry
.entry
= entry
;
2257 VEC_safe_push (arm_exidx_entry_s
,
2258 data
->section_maps
[sec
->the_bfd_section
->index
],
2262 do_cleanups (cleanups
);
2265 /* Search for the exception table entry covering MEMADDR. If one is found,
2266 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2267 set *START to the start of the region covered by this entry. */
2270 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2272 struct obj_section
*sec
;
2274 sec
= find_pc_section (memaddr
);
2277 struct arm_exidx_data
*data
;
2278 VEC(arm_exidx_entry_s
) *map
;
2279 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2282 data
= ((struct arm_exidx_data
*)
2283 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2286 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2287 if (!VEC_empty (arm_exidx_entry_s
, map
))
2289 struct arm_exidx_entry
*map_sym
;
2291 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2292 arm_compare_exidx_entries
);
2294 /* VEC_lower_bound finds the earliest ordered insertion
2295 point. If the following symbol starts at this exact
2296 address, we use that; otherwise, the preceding
2297 exception table entry covers this address. */
2298 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2300 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2301 if (map_sym
->addr
== map_key
.addr
)
2304 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2305 return map_sym
->entry
;
2311 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2313 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2314 return map_sym
->entry
;
2323 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2324 instruction list from the ARM exception table entry ENTRY, allocate and
2325 return a prologue cache structure describing how to unwind this frame.
2327 Return NULL if the unwinding instruction list contains a "spare",
2328 "reserved" or "refuse to unwind" instruction as defined in section
2329 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2330 for the ARM Architecture" document. */
2332 static struct arm_prologue_cache
*
2333 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2338 struct arm_prologue_cache
*cache
;
2339 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2340 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2346 /* Whenever we reload SP, we actually have to retrieve its
2347 actual value in the current frame. */
2350 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2352 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2353 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2357 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2358 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2364 /* Decode next unwind instruction. */
2367 if ((insn
& 0xc0) == 0)
2369 int offset
= insn
& 0x3f;
2370 vsp
+= (offset
<< 2) + 4;
2372 else if ((insn
& 0xc0) == 0x40)
2374 int offset
= insn
& 0x3f;
2375 vsp
-= (offset
<< 2) + 4;
2377 else if ((insn
& 0xf0) == 0x80)
2379 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2382 /* The special case of an all-zero mask identifies
2383 "Refuse to unwind". We return NULL to fall back
2384 to the prologue analyzer. */
2388 /* Pop registers r4..r15 under mask. */
2389 for (i
= 0; i
< 12; i
++)
2390 if (mask
& (1 << i
))
2392 cache
->saved_regs
[4 + i
].addr
= vsp
;
2396 /* Special-case popping SP -- we need to reload vsp. */
2397 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2400 else if ((insn
& 0xf0) == 0x90)
2402 int reg
= insn
& 0xf;
2404 /* Reserved cases. */
2405 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2408 /* Set SP from another register and mark VSP for reload. */
2409 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2412 else if ((insn
& 0xf0) == 0xa0)
2414 int count
= insn
& 0x7;
2415 int pop_lr
= (insn
& 0x8) != 0;
2418 /* Pop r4..r[4+count]. */
2419 for (i
= 0; i
<= count
; i
++)
2421 cache
->saved_regs
[4 + i
].addr
= vsp
;
2425 /* If indicated by flag, pop LR as well. */
2428 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2432 else if (insn
== 0xb0)
2434 /* We could only have updated PC by popping into it; if so, it
2435 will show up as address. Otherwise, copy LR into PC. */
2436 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2437 cache
->saved_regs
[ARM_PC_REGNUM
]
2438 = cache
->saved_regs
[ARM_LR_REGNUM
];
2443 else if (insn
== 0xb1)
2445 int mask
= *entry
++;
2448 /* All-zero mask and mask >= 16 is "spare". */
2449 if (mask
== 0 || mask
>= 16)
2452 /* Pop r0..r3 under mask. */
2453 for (i
= 0; i
< 4; i
++)
2454 if (mask
& (1 << i
))
2456 cache
->saved_regs
[i
].addr
= vsp
;
2460 else if (insn
== 0xb2)
2462 ULONGEST offset
= 0;
2467 offset
|= (*entry
& 0x7f) << shift
;
2470 while (*entry
++ & 0x80);
2472 vsp
+= 0x204 + (offset
<< 2);
2474 else if (insn
== 0xb3)
2476 int start
= *entry
>> 4;
2477 int count
= (*entry
++) & 0xf;
2480 /* Only registers D0..D15 are valid here. */
2481 if (start
+ count
>= 16)
2484 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2485 for (i
= 0; i
<= count
; i
++)
2487 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2491 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2494 else if ((insn
& 0xf8) == 0xb8)
2496 int count
= insn
& 0x7;
2499 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2500 for (i
= 0; i
<= count
; i
++)
2502 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2506 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2509 else if (insn
== 0xc6)
2511 int start
= *entry
>> 4;
2512 int count
= (*entry
++) & 0xf;
2515 /* Only registers WR0..WR15 are valid. */
2516 if (start
+ count
>= 16)
2519 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2520 for (i
= 0; i
<= count
; i
++)
2522 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2526 else if (insn
== 0xc7)
2528 int mask
= *entry
++;
2531 /* All-zero mask and mask >= 16 is "spare". */
2532 if (mask
== 0 || mask
>= 16)
2535 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2536 for (i
= 0; i
< 4; i
++)
2537 if (mask
& (1 << i
))
2539 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2543 else if ((insn
& 0xf8) == 0xc0)
2545 int count
= insn
& 0x7;
2548 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2549 for (i
= 0; i
<= count
; i
++)
2551 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2555 else if (insn
== 0xc8)
2557 int start
= *entry
>> 4;
2558 int count
= (*entry
++) & 0xf;
2561 /* Only registers D0..D31 are valid. */
2562 if (start
+ count
>= 16)
2565 /* Pop VFP double-precision registers
2566 D[16+start]..D[16+start+count]. */
2567 for (i
= 0; i
<= count
; i
++)
2569 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2573 else if (insn
== 0xc9)
2575 int start
= *entry
>> 4;
2576 int count
= (*entry
++) & 0xf;
2579 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2580 for (i
= 0; i
<= count
; i
++)
2582 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2586 else if ((insn
& 0xf8) == 0xd0)
2588 int count
= insn
& 0x7;
2591 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2592 for (i
= 0; i
<= count
; i
++)
2594 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2600 /* Everything else is "spare". */
2605 /* If we restore SP from a register, assume this was the frame register.
2606 Otherwise just fall back to SP as frame register. */
2607 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2608 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2610 cache
->framereg
= ARM_SP_REGNUM
;
2612 /* Determine offset to previous frame. */
2614 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2616 /* We already got the previous SP. */
2617 cache
->prev_sp
= vsp
;
2622 /* Unwinding via ARM exception table entries. Note that the sniffer
2623 already computes a filled-in prologue cache, which is then used
2624 with the same arm_prologue_this_id and arm_prologue_prev_register
2625 routines also used for prologue-parsing based unwinding. */
2628 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2629 struct frame_info
*this_frame
,
2630 void **this_prologue_cache
)
2632 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2633 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2634 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2635 struct arm_prologue_cache
*cache
;
2638 /* See if we have an ARM exception table entry covering this address. */
2639 addr_in_block
= get_frame_address_in_block (this_frame
);
2640 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2644 /* The ARM exception table does not describe unwind information
2645 for arbitrary PC values, but is guaranteed to be correct only
2646 at call sites. We have to decide here whether we want to use
2647 ARM exception table information for this frame, or fall back
2648 to using prologue parsing. (Note that if we have DWARF CFI,
2649 this sniffer isn't even called -- CFI is always preferred.)
2651 Before we make this decision, however, we check whether we
2652 actually have *symbol* information for the current frame.
2653 If not, prologue parsing would not work anyway, so we might
2654 as well use the exception table and hope for the best. */
2655 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2659 /* If the next frame is "normal", we are at a call site in this
2660 frame, so exception information is guaranteed to be valid. */
2661 if (get_next_frame (this_frame
)
2662 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2665 /* We also assume exception information is valid if we're currently
2666 blocked in a system call. The system library is supposed to
2667 ensure this, so that e.g. pthread cancellation works. */
2668 if (arm_frame_is_thumb (this_frame
))
2672 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
2673 2, byte_order_for_code
, &insn
)
2674 && (insn
& 0xff00) == 0xdf00 /* svc */)
2681 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
2682 4, byte_order_for_code
, &insn
)
2683 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2687 /* Bail out if we don't know that exception information is valid. */
2691 /* The ARM exception index does not mark the *end* of the region
2692 covered by the entry, and some functions will not have any entry.
2693 To correctly recognize the end of the covered region, the linker
2694 should have inserted dummy records with a CANTUNWIND marker.
2696 Unfortunately, current versions of GNU ld do not reliably do
2697 this, and thus we may have found an incorrect entry above.
2698 As a (temporary) sanity check, we only use the entry if it
2699 lies *within* the bounds of the function. Note that this check
2700 might reject perfectly valid entries that just happen to cover
2701 multiple functions; therefore this check ought to be removed
2702 once the linker is fixed. */
2703 if (func_start
> exidx_region
)
2707 /* Decode the list of unwinding instructions into a prologue cache.
2708 Note that this may fail due to e.g. a "refuse to unwind" code. */
2709 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2713 *this_prologue_cache
= cache
;
2717 struct frame_unwind arm_exidx_unwind
= {
2719 default_frame_unwind_stop_reason
,
2720 arm_prologue_this_id
,
2721 arm_prologue_prev_register
,
2723 arm_exidx_unwind_sniffer
2726 static struct arm_prologue_cache
*
2727 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2729 struct arm_prologue_cache
*cache
;
2732 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2733 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2735 /* Still rely on the offset calculated from prologue. */
2736 arm_scan_prologue (this_frame
, cache
);
2738 /* Since we are in epilogue, the SP has been restored. */
2739 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2741 /* Calculate actual addresses of saved registers using offsets
2742 determined by arm_scan_prologue. */
2743 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2744 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2745 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2750 /* Implementation of function hook 'this_id' in
2751 'struct frame_uwnind' for epilogue unwinder. */
2754 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2756 struct frame_id
*this_id
)
2758 struct arm_prologue_cache
*cache
;
2761 if (*this_cache
== NULL
)
2762 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2763 cache
= (struct arm_prologue_cache
*) *this_cache
;
2765 /* Use function start address as part of the frame ID. If we cannot
2766 identify the start address (due to missing symbol information),
2767 fall back to just using the current PC. */
2768 pc
= get_frame_pc (this_frame
);
2769 func
= get_frame_func (this_frame
);
2773 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2776 /* Implementation of function hook 'prev_register' in
2777 'struct frame_uwnind' for epilogue unwinder. */
2779 static struct value
*
2780 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2781 void **this_cache
, int regnum
)
2783 if (*this_cache
== NULL
)
2784 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2786 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2789 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2791 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2794 /* Implementation of function hook 'sniffer' in
2795 'struct frame_uwnind' for epilogue unwinder. */
2798 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2799 struct frame_info
*this_frame
,
2800 void **this_prologue_cache
)
2802 if (frame_relative_level (this_frame
) == 0)
2804 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2805 CORE_ADDR pc
= get_frame_pc (this_frame
);
2807 if (arm_frame_is_thumb (this_frame
))
2808 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2810 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2816 /* Frame unwinder from epilogue. */
2818 static const struct frame_unwind arm_epilogue_frame_unwind
=
2821 default_frame_unwind_stop_reason
,
2822 arm_epilogue_frame_this_id
,
2823 arm_epilogue_frame_prev_register
,
2825 arm_epilogue_frame_sniffer
,
2828 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2829 trampoline, return the target PC. Otherwise return 0.
2831 void call0a (char c, short s, int i, long l) {}
2835 (*pointer_to_call0a) (c, s, i, l);
2838 Instead of calling a stub library function _call_via_xx (xx is
2839 the register name), GCC may inline the trampoline in the object
2840 file as below (register r2 has the address of call0a).
2843 .type main, %function
2852 The trampoline 'bx r2' doesn't belong to main. */
2855 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2857 /* The heuristics of recognizing such trampoline is that FRAME is
2858 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2859 if (arm_frame_is_thumb (frame
))
2863 if (target_read_memory (pc
, buf
, 2) == 0)
2865 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2866 enum bfd_endian byte_order_for_code
2867 = gdbarch_byte_order_for_code (gdbarch
);
2869 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2871 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2874 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2876 /* Clear the LSB so that gdb core sets step-resume
2877 breakpoint at the right address. */
2878 return UNMAKE_THUMB_ADDR (dest
);
2886 static struct arm_prologue_cache
*
2887 arm_make_stub_cache (struct frame_info
*this_frame
)
2889 struct arm_prologue_cache
*cache
;
2891 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2892 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2894 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2899 /* Our frame ID for a stub frame is the current SP and LR. */
2902 arm_stub_this_id (struct frame_info
*this_frame
,
2904 struct frame_id
*this_id
)
2906 struct arm_prologue_cache
*cache
;
2908 if (*this_cache
== NULL
)
2909 *this_cache
= arm_make_stub_cache (this_frame
);
2910 cache
= (struct arm_prologue_cache
*) *this_cache
;
2912 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2916 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2917 struct frame_info
*this_frame
,
2918 void **this_prologue_cache
)
2920 CORE_ADDR addr_in_block
;
2922 CORE_ADDR pc
, start_addr
;
2925 addr_in_block
= get_frame_address_in_block (this_frame
);
2926 pc
= get_frame_pc (this_frame
);
2927 if (in_plt_section (addr_in_block
)
2928 /* We also use the stub winder if the target memory is unreadable
2929 to avoid having the prologue unwinder trying to read it. */
2930 || target_read_memory (pc
, dummy
, 4) != 0)
2933 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2934 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2940 struct frame_unwind arm_stub_unwind
= {
2942 default_frame_unwind_stop_reason
,
2944 arm_prologue_prev_register
,
2946 arm_stub_unwind_sniffer
2949 /* Put here the code to store, into CACHE->saved_regs, the addresses
2950 of the saved registers of frame described by THIS_FRAME. CACHE is
2953 static struct arm_prologue_cache
*
2954 arm_m_exception_cache (struct frame_info
*this_frame
)
2956 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2957 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2958 struct arm_prologue_cache
*cache
;
2959 CORE_ADDR unwound_sp
;
2962 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2963 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2965 unwound_sp
= get_frame_register_unsigned (this_frame
,
2968 /* The hardware saves eight 32-bit words, comprising xPSR,
2969 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2970 "B1.5.6 Exception entry behavior" in
2971 "ARMv7-M Architecture Reference Manual". */
2972 cache
->saved_regs
[0].addr
= unwound_sp
;
2973 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2974 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2975 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2976 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2977 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2978 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2979 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2981 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2982 aligner between the top of the 32-byte stack frame and the
2983 previous context's stack pointer. */
2984 cache
->prev_sp
= unwound_sp
+ 32;
2985 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2986 && (xpsr
& (1 << 9)) != 0)
2987 cache
->prev_sp
+= 4;
2992 /* Implementation of function hook 'this_id' in
2993 'struct frame_uwnind'. */
2996 arm_m_exception_this_id (struct frame_info
*this_frame
,
2998 struct frame_id
*this_id
)
3000 struct arm_prologue_cache
*cache
;
3002 if (*this_cache
== NULL
)
3003 *this_cache
= arm_m_exception_cache (this_frame
);
3004 cache
= (struct arm_prologue_cache
*) *this_cache
;
3006 /* Our frame ID for a stub frame is the current SP and LR. */
3007 *this_id
= frame_id_build (cache
->prev_sp
,
3008 get_frame_pc (this_frame
));
3011 /* Implementation of function hook 'prev_register' in
3012 'struct frame_uwnind'. */
3014 static struct value
*
3015 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3019 struct arm_prologue_cache
*cache
;
3021 if (*this_cache
== NULL
)
3022 *this_cache
= arm_m_exception_cache (this_frame
);
3023 cache
= (struct arm_prologue_cache
*) *this_cache
;
3025 /* The value was already reconstructed into PREV_SP. */
3026 if (prev_regnum
== ARM_SP_REGNUM
)
3027 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3030 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3034 /* Implementation of function hook 'sniffer' in
3035 'struct frame_uwnind'. */
3038 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3039 struct frame_info
*this_frame
,
3040 void **this_prologue_cache
)
3042 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3044 /* No need to check is_m; this sniffer is only registered for
3045 M-profile architectures. */
3047 /* Check if exception frame returns to a magic PC value. */
3048 return arm_m_addr_is_magic (this_pc
);
3051 /* Frame unwinder for M-profile exceptions. */
3053 struct frame_unwind arm_m_exception_unwind
=
3056 default_frame_unwind_stop_reason
,
3057 arm_m_exception_this_id
,
3058 arm_m_exception_prev_register
,
3060 arm_m_exception_unwind_sniffer
3064 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3066 struct arm_prologue_cache
*cache
;
3068 if (*this_cache
== NULL
)
3069 *this_cache
= arm_make_prologue_cache (this_frame
);
3070 cache
= (struct arm_prologue_cache
*) *this_cache
;
3072 return cache
->prev_sp
- cache
->framesize
;
3075 struct frame_base arm_normal_base
= {
3076 &arm_prologue_unwind
,
3077 arm_normal_frame_base
,
3078 arm_normal_frame_base
,
3079 arm_normal_frame_base
3082 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3083 dummy frame. The frame ID's base needs to match the TOS value
3084 saved by save_dummy_frame_tos() and returned from
3085 arm_push_dummy_call, and the PC needs to match the dummy frame's
3088 static struct frame_id
3089 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3091 return frame_id_build (get_frame_register_unsigned (this_frame
,
3093 get_frame_pc (this_frame
));
3096 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3097 be used to construct the previous frame's ID, after looking up the
3098 containing function). */
3101 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3104 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3105 return arm_addr_bits_remove (gdbarch
, pc
);
3109 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3111 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3114 static struct value
*
3115 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3118 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3120 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3125 /* The PC is normally copied from the return column, which
3126 describes saves of LR. However, that version may have an
3127 extra bit set to indicate Thumb state. The bit is not
3129 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3130 return frame_unwind_got_constant (this_frame
, regnum
,
3131 arm_addr_bits_remove (gdbarch
, lr
));
3134 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3135 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3136 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3137 if (IS_THUMB_ADDR (lr
))
3141 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3144 internal_error (__FILE__
, __LINE__
,
3145 _("Unexpected register %d"), regnum
);
3150 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3151 struct dwarf2_frame_state_reg
*reg
,
3152 struct frame_info
*this_frame
)
3158 reg
->how
= DWARF2_FRAME_REG_FN
;
3159 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3162 reg
->how
= DWARF2_FRAME_REG_CFA
;
3167 /* Implement the stack_frame_destroyed_p gdbarch method. */
3170 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3172 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3173 unsigned int insn
, insn2
;
3174 int found_return
= 0, found_stack_adjust
= 0;
3175 CORE_ADDR func_start
, func_end
;
3179 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3182 /* The epilogue is a sequence of instructions along the following lines:
3184 - add stack frame size to SP or FP
3185 - [if frame pointer used] restore SP from FP
3186 - restore registers from SP [may include PC]
3187 - a return-type instruction [if PC wasn't already restored]
3189 In a first pass, we scan forward from the current PC and verify the
3190 instructions we find as compatible with this sequence, ending in a
3193 However, this is not sufficient to distinguish indirect function calls
3194 within a function from indirect tail calls in the epilogue in some cases.
3195 Therefore, if we didn't already find any SP-changing instruction during
3196 forward scan, we add a backward scanning heuristic to ensure we actually
3197 are in the epilogue. */
3200 while (scan_pc
< func_end
&& !found_return
)
3202 if (target_read_memory (scan_pc
, buf
, 2))
3206 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3208 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3210 else if (insn
== 0x46f7) /* mov pc, lr */
3212 else if (thumb_instruction_restores_sp (insn
))
3214 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3217 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3219 if (target_read_memory (scan_pc
, buf
, 2))
3223 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3225 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3227 if (insn2
& 0x8000) /* <registers> include PC. */
3230 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3231 && (insn2
& 0x0fff) == 0x0b04)
3233 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3236 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3237 && (insn2
& 0x0e00) == 0x0a00)
3249 /* Since any instruction in the epilogue sequence, with the possible
3250 exception of return itself, updates the stack pointer, we need to
3251 scan backwards for at most one instruction. Try either a 16-bit or
3252 a 32-bit instruction. This is just a heuristic, so we do not worry
3253 too much about false positives. */
3255 if (pc
- 4 < func_start
)
3257 if (target_read_memory (pc
- 4, buf
, 4))
3260 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3261 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3263 if (thumb_instruction_restores_sp (insn2
))
3264 found_stack_adjust
= 1;
3265 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3266 found_stack_adjust
= 1;
3267 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3268 && (insn2
& 0x0fff) == 0x0b04)
3269 found_stack_adjust
= 1;
3270 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3271 && (insn2
& 0x0e00) == 0x0a00)
3272 found_stack_adjust
= 1;
3274 return found_stack_adjust
;
3278 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3280 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3283 CORE_ADDR func_start
, func_end
;
3285 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3288 /* We are in the epilogue if the previous instruction was a stack
3289 adjustment and the next instruction is a possible return (bx, mov
3290 pc, or pop). We could have to scan backwards to find the stack
3291 adjustment, or forwards to find the return, but this is a decent
3292 approximation. First scan forwards. */
3295 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3296 if (bits (insn
, 28, 31) != INST_NV
)
3298 if ((insn
& 0x0ffffff0) == 0x012fff10)
3301 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3304 else if ((insn
& 0x0fff0000) == 0x08bd0000
3305 && (insn
& 0x0000c000) != 0)
3306 /* POP (LDMIA), including PC or LR. */
3313 /* Scan backwards. This is just a heuristic, so do not worry about
3314 false positives from mode changes. */
3316 if (pc
< func_start
+ 4)
3319 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3320 if (arm_instruction_restores_sp (insn
))
3326 /* Implement the stack_frame_destroyed_p gdbarch method. */
3329 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3331 if (arm_pc_is_thumb (gdbarch
, pc
))
3332 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3334 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3337 /* When arguments must be pushed onto the stack, they go on in reverse
3338 order. The code below implements a FILO (stack) to do this. */
3343 struct stack_item
*prev
;
3347 static struct stack_item
*
3348 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3350 struct stack_item
*si
;
3351 si
= XNEW (struct stack_item
);
3352 si
->data
= (gdb_byte
*) xmalloc (len
);
3355 memcpy (si
->data
, contents
, len
);
3359 static struct stack_item
*
3360 pop_stack_item (struct stack_item
*si
)
3362 struct stack_item
*dead
= si
;
3370 /* Return the alignment (in bytes) of the given type. */
3373 arm_type_align (struct type
*t
)
3379 t
= check_typedef (t
);
3380 switch (TYPE_CODE (t
))
3383 /* Should never happen. */
3384 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3388 case TYPE_CODE_ENUM
:
3392 case TYPE_CODE_RANGE
:
3394 case TYPE_CODE_CHAR
:
3395 case TYPE_CODE_BOOL
:
3396 return TYPE_LENGTH (t
);
3398 case TYPE_CODE_ARRAY
:
3399 if (TYPE_VECTOR (t
))
3401 /* Use the natural alignment for vector types (the same for
3402 scalar type), but the maximum alignment is 64-bit. */
3403 if (TYPE_LENGTH (t
) > 8)
3406 return TYPE_LENGTH (t
);
3409 return arm_type_align (TYPE_TARGET_TYPE (t
));
3410 case TYPE_CODE_COMPLEX
:
3411 return arm_type_align (TYPE_TARGET_TYPE (t
));
3413 case TYPE_CODE_STRUCT
:
3414 case TYPE_CODE_UNION
:
3416 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3418 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3426 /* Possible base types for a candidate for passing and returning in
3429 enum arm_vfp_cprc_base_type
3438 /* The length of one element of base type B. */
3441 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3445 case VFP_CPRC_SINGLE
:
3447 case VFP_CPRC_DOUBLE
:
3449 case VFP_CPRC_VEC64
:
3451 case VFP_CPRC_VEC128
:
3454 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3459 /* The character ('s', 'd' or 'q') for the type of VFP register used
3460 for passing base type B. */
3463 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3467 case VFP_CPRC_SINGLE
:
3469 case VFP_CPRC_DOUBLE
:
3471 case VFP_CPRC_VEC64
:
3473 case VFP_CPRC_VEC128
:
3476 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3481 /* Determine whether T may be part of a candidate for passing and
3482 returning in VFP registers, ignoring the limit on the total number
3483 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3484 classification of the first valid component found; if it is not
3485 VFP_CPRC_UNKNOWN, all components must have the same classification
3486 as *BASE_TYPE. If it is found that T contains a type not permitted
3487 for passing and returning in VFP registers, a type differently
3488 classified from *BASE_TYPE, or two types differently classified
3489 from each other, return -1, otherwise return the total number of
3490 base-type elements found (possibly 0 in an empty structure or
3491 array). Vector types are not currently supported, matching the
3492 generic AAPCS support. */
3495 arm_vfp_cprc_sub_candidate (struct type
*t
,
3496 enum arm_vfp_cprc_base_type
*base_type
)
3498 t
= check_typedef (t
);
3499 switch (TYPE_CODE (t
))
3502 switch (TYPE_LENGTH (t
))
3505 if (*base_type
== VFP_CPRC_UNKNOWN
)
3506 *base_type
= VFP_CPRC_SINGLE
;
3507 else if (*base_type
!= VFP_CPRC_SINGLE
)
3512 if (*base_type
== VFP_CPRC_UNKNOWN
)
3513 *base_type
= VFP_CPRC_DOUBLE
;
3514 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3523 case TYPE_CODE_COMPLEX
:
3524 /* Arguments of complex T where T is one of the types float or
3525 double get treated as if they are implemented as:
3534 switch (TYPE_LENGTH (t
))
3537 if (*base_type
== VFP_CPRC_UNKNOWN
)
3538 *base_type
= VFP_CPRC_SINGLE
;
3539 else if (*base_type
!= VFP_CPRC_SINGLE
)
3544 if (*base_type
== VFP_CPRC_UNKNOWN
)
3545 *base_type
= VFP_CPRC_DOUBLE
;
3546 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3555 case TYPE_CODE_ARRAY
:
3557 if (TYPE_VECTOR (t
))
3559 /* A 64-bit or 128-bit containerized vector type are VFP
3561 switch (TYPE_LENGTH (t
))
3564 if (*base_type
== VFP_CPRC_UNKNOWN
)
3565 *base_type
= VFP_CPRC_VEC64
;
3568 if (*base_type
== VFP_CPRC_UNKNOWN
)
3569 *base_type
= VFP_CPRC_VEC128
;
3580 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3584 if (TYPE_LENGTH (t
) == 0)
3586 gdb_assert (count
== 0);
3589 else if (count
== 0)
3591 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3592 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3593 return TYPE_LENGTH (t
) / unitlen
;
3598 case TYPE_CODE_STRUCT
:
3603 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3607 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3608 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3610 if (sub_count
== -1)
3614 if (TYPE_LENGTH (t
) == 0)
3616 gdb_assert (count
== 0);
3619 else if (count
== 0)
3621 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3622 if (TYPE_LENGTH (t
) != unitlen
* count
)
3627 case TYPE_CODE_UNION
:
3632 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3634 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3636 if (sub_count
== -1)
3638 count
= (count
> sub_count
? count
: sub_count
);
3640 if (TYPE_LENGTH (t
) == 0)
3642 gdb_assert (count
== 0);
3645 else if (count
== 0)
3647 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3648 if (TYPE_LENGTH (t
) != unitlen
* count
)
3660 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3661 if passed to or returned from a non-variadic function with the VFP
3662 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3663 *BASE_TYPE to the base type for T and *COUNT to the number of
3664 elements of that base type before returning. */
3667 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3670 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3671 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3672 if (c
<= 0 || c
> 4)
3679 /* Return 1 if the VFP ABI should be used for passing arguments to and
3680 returning values from a function of type FUNC_TYPE, 0
3684 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3686 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3687 /* Variadic functions always use the base ABI. Assume that functions
3688 without debug info are not variadic. */
3689 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3691 /* The VFP ABI is only supported as a variant of AAPCS. */
3692 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3694 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3697 /* We currently only support passing parameters in integer registers, which
3698 conforms with GCC's default model, and VFP argument passing following
3699 the VFP variant of AAPCS. Several other variants exist and
3700 we should probably support some of them based on the selected ABI. */
3703 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3704 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3705 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3706 CORE_ADDR struct_addr
)
3708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3712 struct stack_item
*si
= NULL
;
3715 unsigned vfp_regs_free
= (1 << 16) - 1;
3717 /* Determine the type of this function and whether the VFP ABI
3719 ftype
= check_typedef (value_type (function
));
3720 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3721 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3722 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3724 /* Set the return address. For the ARM, the return breakpoint is
3725 always at BP_ADDR. */
3726 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3728 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3730 /* Walk through the list of args and determine how large a temporary
3731 stack is required. Need to take care here as structs may be
3732 passed on the stack, and we have to push them. */
3735 argreg
= ARM_A1_REGNUM
;
3738 /* The struct_return pointer occupies the first parameter
3739 passing register. */
3743 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3744 gdbarch_register_name (gdbarch
, argreg
),
3745 paddress (gdbarch
, struct_addr
));
3746 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3750 for (argnum
= 0; argnum
< nargs
; argnum
++)
3753 struct type
*arg_type
;
3754 struct type
*target_type
;
3755 enum type_code typecode
;
3756 const bfd_byte
*val
;
3758 enum arm_vfp_cprc_base_type vfp_base_type
;
3760 int may_use_core_reg
= 1;
3762 arg_type
= check_typedef (value_type (args
[argnum
]));
3763 len
= TYPE_LENGTH (arg_type
);
3764 target_type
= TYPE_TARGET_TYPE (arg_type
);
3765 typecode
= TYPE_CODE (arg_type
);
3766 val
= value_contents (args
[argnum
]);
3768 align
= arm_type_align (arg_type
);
3769 /* Round alignment up to a whole number of words. */
3770 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3771 /* Different ABIs have different maximum alignments. */
3772 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3774 /* The APCS ABI only requires word alignment. */
3775 align
= INT_REGISTER_SIZE
;
3779 /* The AAPCS requires at most doubleword alignment. */
3780 if (align
> INT_REGISTER_SIZE
* 2)
3781 align
= INT_REGISTER_SIZE
* 2;
3785 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3793 /* Because this is a CPRC it cannot go in a core register or
3794 cause a core register to be skipped for alignment.
3795 Either it goes in VFP registers and the rest of this loop
3796 iteration is skipped for this argument, or it goes on the
3797 stack (and the stack alignment code is correct for this
3799 may_use_core_reg
= 0;
3801 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3802 shift
= unit_length
/ 4;
3803 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3804 for (regno
= 0; regno
< 16; regno
+= shift
)
3805 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3814 vfp_regs_free
&= ~(mask
<< regno
);
3815 reg_scaled
= regno
/ shift
;
3816 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3817 for (i
= 0; i
< vfp_base_count
; i
++)
3821 if (reg_char
== 'q')
3822 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3823 val
+ i
* unit_length
);
3826 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3827 reg_char
, reg_scaled
+ i
);
3828 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3830 regcache_cooked_write (regcache
, regnum
,
3831 val
+ i
* unit_length
);
3838 /* This CPRC could not go in VFP registers, so all VFP
3839 registers are now marked as used. */
3844 /* Push stack padding for dowubleword alignment. */
3845 if (nstack
& (align
- 1))
3847 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3848 nstack
+= INT_REGISTER_SIZE
;
3851 /* Doubleword aligned quantities must go in even register pairs. */
3852 if (may_use_core_reg
3853 && argreg
<= ARM_LAST_ARG_REGNUM
3854 && align
> INT_REGISTER_SIZE
3858 /* If the argument is a pointer to a function, and it is a
3859 Thumb function, create a LOCAL copy of the value and set
3860 the THUMB bit in it. */
3861 if (TYPE_CODE_PTR
== typecode
3862 && target_type
!= NULL
3863 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3865 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3866 if (arm_pc_is_thumb (gdbarch
, regval
))
3868 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3869 store_unsigned_integer (copy
, len
, byte_order
,
3870 MAKE_THUMB_ADDR (regval
));
3875 /* Copy the argument to general registers or the stack in
3876 register-sized pieces. Large arguments are split between
3877 registers and stack. */
3880 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3882 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3884 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3886 /* The argument is being passed in a general purpose
3888 if (byte_order
== BFD_ENDIAN_BIG
)
3889 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3891 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3893 gdbarch_register_name
3895 phex (regval
, INT_REGISTER_SIZE
));
3896 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3901 gdb_byte buf
[INT_REGISTER_SIZE
];
3903 memset (buf
, 0, sizeof (buf
));
3904 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3906 /* Push the arguments onto the stack. */
3908 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3910 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3911 nstack
+= INT_REGISTER_SIZE
;
3918 /* If we have an odd number of words to push, then decrement the stack
3919 by one word now, so first stack argument will be dword aligned. */
3926 write_memory (sp
, si
->data
, si
->len
);
3927 si
= pop_stack_item (si
);
3930 /* Finally, update teh SP register. */
3931 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3937 /* Always align the frame to an 8-byte boundary. This is required on
3938 some platforms and harmless on the rest. */
3941 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3943 /* Align the stack to eight bytes. */
3944 return sp
& ~ (CORE_ADDR
) 7;
3948 print_fpu_flags (struct ui_file
*file
, int flags
)
3950 if (flags
& (1 << 0))
3951 fputs_filtered ("IVO ", file
);
3952 if (flags
& (1 << 1))
3953 fputs_filtered ("DVZ ", file
);
3954 if (flags
& (1 << 2))
3955 fputs_filtered ("OFL ", file
);
3956 if (flags
& (1 << 3))
3957 fputs_filtered ("UFL ", file
);
3958 if (flags
& (1 << 4))
3959 fputs_filtered ("INX ", file
);
3960 fputc_filtered ('\n', file
);
3963 /* Print interesting information about the floating point processor
3964 (if present) or emulator. */
3966 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3967 struct frame_info
*frame
, const char *args
)
3969 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3972 type
= (status
>> 24) & 127;
3973 if (status
& (1 << 31))
3974 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3976 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3977 /* i18n: [floating point unit] mask */
3978 fputs_filtered (_("mask: "), file
);
3979 print_fpu_flags (file
, status
>> 16);
3980 /* i18n: [floating point unit] flags */
3981 fputs_filtered (_("flags: "), file
);
3982 print_fpu_flags (file
, status
);
3985 /* Construct the ARM extended floating point type. */
3986 static struct type
*
3987 arm_ext_type (struct gdbarch
*gdbarch
)
3989 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3991 if (!tdep
->arm_ext_type
)
3993 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3994 floatformats_arm_ext
);
3996 return tdep
->arm_ext_type
;
3999 static struct type
*
4000 arm_neon_double_type (struct gdbarch
*gdbarch
)
4002 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4004 if (tdep
->neon_double_type
== NULL
)
4006 struct type
*t
, *elem
;
4008 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4010 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4011 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4012 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4013 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4014 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4015 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4016 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4017 append_composite_type_field (t
, "u64", elem
);
4018 elem
= builtin_type (gdbarch
)->builtin_float
;
4019 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4020 elem
= builtin_type (gdbarch
)->builtin_double
;
4021 append_composite_type_field (t
, "f64", elem
);
4023 TYPE_VECTOR (t
) = 1;
4024 TYPE_NAME (t
) = "neon_d";
4025 tdep
->neon_double_type
= t
;
4028 return tdep
->neon_double_type
;
4031 /* FIXME: The vector types are not correctly ordered on big-endian
4032 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4033 bits of d0 - regardless of what unit size is being held in d0. So
4034 the offset of the first uint8 in d0 is 7, but the offset of the
4035 first float is 4. This code works as-is for little-endian
4038 static struct type
*
4039 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4041 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4043 if (tdep
->neon_quad_type
== NULL
)
4045 struct type
*t
, *elem
;
4047 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4049 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4050 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4051 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4052 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4053 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4054 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4055 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4056 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4057 elem
= builtin_type (gdbarch
)->builtin_float
;
4058 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4059 elem
= builtin_type (gdbarch
)->builtin_double
;
4060 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4062 TYPE_VECTOR (t
) = 1;
4063 TYPE_NAME (t
) = "neon_q";
4064 tdep
->neon_quad_type
= t
;
4067 return tdep
->neon_quad_type
;
4070 /* Return the GDB type object for the "standard" data type of data in
4073 static struct type
*
4074 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4076 int num_regs
= gdbarch_num_regs (gdbarch
);
4078 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4079 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4080 return builtin_type (gdbarch
)->builtin_float
;
4082 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4083 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4084 return arm_neon_quad_type (gdbarch
);
4086 /* If the target description has register information, we are only
4087 in this function so that we can override the types of
4088 double-precision registers for NEON. */
4089 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4091 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4093 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4094 && TYPE_CODE (t
) == TYPE_CODE_FLT
4095 && gdbarch_tdep (gdbarch
)->have_neon
)
4096 return arm_neon_double_type (gdbarch
);
4101 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4103 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4104 return builtin_type (gdbarch
)->builtin_void
;
4106 return arm_ext_type (gdbarch
);
4108 else if (regnum
== ARM_SP_REGNUM
)
4109 return builtin_type (gdbarch
)->builtin_data_ptr
;
4110 else if (regnum
== ARM_PC_REGNUM
)
4111 return builtin_type (gdbarch
)->builtin_func_ptr
;
4112 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4113 /* These registers are only supported on targets which supply
4114 an XML description. */
4115 return builtin_type (gdbarch
)->builtin_int0
;
4117 return builtin_type (gdbarch
)->builtin_uint32
;
4120 /* Map a DWARF register REGNUM onto the appropriate GDB register
4124 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4126 /* Core integer regs. */
4127 if (reg
>= 0 && reg
<= 15)
4130 /* Legacy FPA encoding. These were once used in a way which
4131 overlapped with VFP register numbering, so their use is
4132 discouraged, but GDB doesn't support the ARM toolchain
4133 which used them for VFP. */
4134 if (reg
>= 16 && reg
<= 23)
4135 return ARM_F0_REGNUM
+ reg
- 16;
4137 /* New assignments for the FPA registers. */
4138 if (reg
>= 96 && reg
<= 103)
4139 return ARM_F0_REGNUM
+ reg
- 96;
4141 /* WMMX register assignments. */
4142 if (reg
>= 104 && reg
<= 111)
4143 return ARM_WCGR0_REGNUM
+ reg
- 104;
4145 if (reg
>= 112 && reg
<= 127)
4146 return ARM_WR0_REGNUM
+ reg
- 112;
4148 if (reg
>= 192 && reg
<= 199)
4149 return ARM_WC0_REGNUM
+ reg
- 192;
4151 /* VFP v2 registers. A double precision value is actually
4152 in d1 rather than s2, but the ABI only defines numbering
4153 for the single precision registers. This will "just work"
4154 in GDB for little endian targets (we'll read eight bytes,
4155 starting in s0 and then progressing to s1), but will be
4156 reversed on big endian targets with VFP. This won't
4157 be a problem for the new Neon quad registers; you're supposed
4158 to use DW_OP_piece for those. */
4159 if (reg
>= 64 && reg
<= 95)
4163 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4164 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4168 /* VFP v3 / Neon registers. This range is also used for VFP v2
4169 registers, except that it now describes d0 instead of s0. */
4170 if (reg
>= 256 && reg
<= 287)
4174 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4175 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4182 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4184 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4187 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4189 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4190 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4192 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4193 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4195 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4196 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4198 if (reg
< NUM_GREGS
)
4199 return SIM_ARM_R0_REGNUM
+ reg
;
4202 if (reg
< NUM_FREGS
)
4203 return SIM_ARM_FP0_REGNUM
+ reg
;
4206 if (reg
< NUM_SREGS
)
4207 return SIM_ARM_FPS_REGNUM
+ reg
;
4210 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4213 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4214 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4215 It is thought that this is is the floating-point register format on
4216 little-endian systems. */
4219 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4220 void *dbl
, int endianess
)
4224 if (endianess
== BFD_ENDIAN_BIG
)
4225 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4227 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4229 floatformat_from_doublest (fmt
, &d
, dbl
);
4233 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4238 floatformat_to_doublest (fmt
, ptr
, &d
);
4239 if (endianess
== BFD_ENDIAN_BIG
)
4240 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4242 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4246 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4247 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4248 NULL if an error occurs. BUF is freed. */
4251 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4252 int old_len
, int new_len
)
4255 int bytes_to_read
= new_len
- old_len
;
4257 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4258 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4260 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4268 /* An IT block is at most the 2-byte IT instruction followed by
4269 four 4-byte instructions. The furthest back we must search to
4270 find an IT block that affects the current instruction is thus
4271 2 + 3 * 4 == 14 bytes. */
4272 #define MAX_IT_BLOCK_PREFIX 14
4274 /* Use a quick scan if there are more than this many bytes of
4276 #define IT_SCAN_THRESHOLD 32
4278 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4279 A breakpoint in an IT block may not be hit, depending on the
4282 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4286 CORE_ADDR boundary
, func_start
;
4288 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4289 int i
, any
, last_it
, last_it_count
;
4291 /* If we are using BKPT breakpoints, none of this is necessary. */
4292 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4295 /* ARM mode does not have this problem. */
4296 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4299 /* We are setting a breakpoint in Thumb code that could potentially
4300 contain an IT block. The first step is to find how much Thumb
4301 code there is; we do not need to read outside of known Thumb
4303 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4305 /* Thumb-2 code must have mapping symbols to have a chance. */
4308 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4310 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4311 && func_start
> boundary
)
4312 boundary
= func_start
;
4314 /* Search for a candidate IT instruction. We have to do some fancy
4315 footwork to distinguish a real IT instruction from the second
4316 half of a 32-bit instruction, but there is no need for that if
4317 there's no candidate. */
4318 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4320 /* No room for an IT instruction. */
4323 buf
= (gdb_byte
*) xmalloc (buf_len
);
4324 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4327 for (i
= 0; i
< buf_len
; i
+= 2)
4329 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4330 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4343 /* OK, the code bytes before this instruction contain at least one
4344 halfword which resembles an IT instruction. We know that it's
4345 Thumb code, but there are still two possibilities. Either the
4346 halfword really is an IT instruction, or it is the second half of
4347 a 32-bit Thumb instruction. The only way we can tell is to
4348 scan forwards from a known instruction boundary. */
4349 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4353 /* There's a lot of code before this instruction. Start with an
4354 optimistic search; it's easy to recognize halfwords that can
4355 not be the start of a 32-bit instruction, and use that to
4356 lock on to the instruction boundaries. */
4357 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4360 buf_len
= IT_SCAN_THRESHOLD
;
4363 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4365 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4366 if (thumb_insn_size (inst1
) == 2)
4373 /* At this point, if DEFINITE, BUF[I] is the first place we
4374 are sure that we know the instruction boundaries, and it is far
4375 enough from BPADDR that we could not miss an IT instruction
4376 affecting BPADDR. If ! DEFINITE, give up - start from a
4380 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4384 buf_len
= bpaddr
- boundary
;
4390 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4393 buf_len
= bpaddr
- boundary
;
4397 /* Scan forwards. Find the last IT instruction before BPADDR. */
4402 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4404 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4409 else if (inst1
& 0x0002)
4411 else if (inst1
& 0x0004)
4416 i
+= thumb_insn_size (inst1
);
4422 /* There wasn't really an IT instruction after all. */
4425 if (last_it_count
< 1)
4426 /* It was too far away. */
4429 /* This really is a trouble spot. Move the breakpoint to the IT
4431 return bpaddr
- buf_len
+ last_it
;
4434 /* ARM displaced stepping support.
4436 Generally ARM displaced stepping works as follows:
4438 1. When an instruction is to be single-stepped, it is first decoded by
4439 arm_process_displaced_insn. Depending on the type of instruction, it is
4440 then copied to a scratch location, possibly in a modified form. The
4441 copy_* set of functions performs such modification, as necessary. A
4442 breakpoint is placed after the modified instruction in the scratch space
4443 to return control to GDB. Note in particular that instructions which
4444 modify the PC will no longer do so after modification.
4446 2. The instruction is single-stepped, by setting the PC to the scratch
4447 location address, and resuming. Control returns to GDB when the
4450 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4451 function used for the current instruction. This function's job is to
4452 put the CPU/memory state back to what it would have been if the
4453 instruction had been executed unmodified in its original location. */
4455 /* NOP instruction (mov r0, r0). */
4456 #define ARM_NOP 0xe1a00000
4457 #define THUMB_NOP 0x4600
4459 /* Helper for register reads for displaced stepping. In particular, this
4460 returns the PC as it would be seen by the instruction at its original
4464 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4468 CORE_ADDR from
= dsc
->insn_addr
;
4470 if (regno
== ARM_PC_REGNUM
)
4472 /* Compute pipeline offset:
4473 - When executing an ARM instruction, PC reads as the address of the
4474 current instruction plus 8.
4475 - When executing a Thumb instruction, PC reads as the address of the
4476 current instruction plus 4. */
4483 if (debug_displaced
)
4484 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4485 (unsigned long) from
);
4486 return (ULONGEST
) from
;
4490 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4491 if (debug_displaced
)
4492 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4493 regno
, (unsigned long) ret
);
4499 displaced_in_arm_mode (struct regcache
*regs
)
4502 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4504 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4506 return (ps
& t_bit
) == 0;
4509 /* Write to the PC as from a branch instruction. */
4512 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4516 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4517 architecture versions < 6. */
4518 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4519 val
& ~(ULONGEST
) 0x3);
4521 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4522 val
& ~(ULONGEST
) 0x1);
4525 /* Write to the PC as from a branch-exchange instruction. */
4528 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4531 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4533 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4537 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4538 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4540 else if ((val
& 2) == 0)
4542 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4543 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4547 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4548 mode, align dest to 4 bytes). */
4549 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4550 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4551 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4555 /* Write to the PC as if from a load instruction. */
4558 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4561 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4562 bx_write_pc (regs
, val
);
4564 branch_write_pc (regs
, dsc
, val
);
4567 /* Write to the PC as if from an ALU instruction. */
4570 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4573 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4574 bx_write_pc (regs
, val
);
4576 branch_write_pc (regs
, dsc
, val
);
4579 /* Helper for writing to registers for displaced stepping. Writing to the PC
4580 has a varying effects depending on the instruction which does the write:
4581 this is controlled by the WRITE_PC argument. */
4584 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4585 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4587 if (regno
== ARM_PC_REGNUM
)
4589 if (debug_displaced
)
4590 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4591 (unsigned long) val
);
4594 case BRANCH_WRITE_PC
:
4595 branch_write_pc (regs
, dsc
, val
);
4599 bx_write_pc (regs
, val
);
4603 load_write_pc (regs
, dsc
, val
);
4607 alu_write_pc (regs
, dsc
, val
);
4610 case CANNOT_WRITE_PC
:
4611 warning (_("Instruction wrote to PC in an unexpected way when "
4612 "single-stepping"));
4616 internal_error (__FILE__
, __LINE__
,
4617 _("Invalid argument to displaced_write_reg"));
4620 dsc
->wrote_to_pc
= 1;
4624 if (debug_displaced
)
4625 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4626 regno
, (unsigned long) val
);
4627 regcache_cooked_write_unsigned (regs
, regno
, val
);
4631 /* This function is used to concisely determine if an instruction INSN
4632 references PC. Register fields of interest in INSN should have the
4633 corresponding fields of BITMASK set to 0b1111. The function
4634 returns return 1 if any of these fields in INSN reference the PC
4635 (also 0b1111, r15), else it returns 0. */
4638 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4640 uint32_t lowbit
= 1;
4642 while (bitmask
!= 0)
4646 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4652 mask
= lowbit
* 0xf;
4654 if ((insn
& mask
) == mask
)
4663 /* The simplest copy function. Many instructions have the same effect no
4664 matter what address they are executed at: in those cases, use this. */
4667 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4668 const char *iname
, struct displaced_step_closure
*dsc
)
4670 if (debug_displaced
)
4671 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4672 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4675 dsc
->modinsn
[0] = insn
;
4681 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4682 uint16_t insn2
, const char *iname
,
4683 struct displaced_step_closure
*dsc
)
4685 if (debug_displaced
)
4686 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4687 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4690 dsc
->modinsn
[0] = insn1
;
4691 dsc
->modinsn
[1] = insn2
;
4697 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4700 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4702 struct displaced_step_closure
*dsc
)
4704 if (debug_displaced
)
4705 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4706 "opcode/class '%s' unmodified\n", insn
,
4709 dsc
->modinsn
[0] = insn
;
4714 /* Preload instructions with immediate offset. */
4717 cleanup_preload (struct gdbarch
*gdbarch
,
4718 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4720 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4721 if (!dsc
->u
.preload
.immed
)
4722 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4726 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4727 struct displaced_step_closure
*dsc
, unsigned int rn
)
4730 /* Preload instructions:
4732 {pli/pld} [rn, #+/-imm]
4734 {pli/pld} [r0, #+/-imm]. */
4736 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4737 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4738 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4739 dsc
->u
.preload
.immed
= 1;
4741 dsc
->cleanup
= &cleanup_preload
;
4745 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4746 struct displaced_step_closure
*dsc
)
4748 unsigned int rn
= bits (insn
, 16, 19);
4750 if (!insn_references_pc (insn
, 0x000f0000ul
))
4751 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4753 if (debug_displaced
)
4754 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4755 (unsigned long) insn
);
4757 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4759 install_preload (gdbarch
, regs
, dsc
, rn
);
4765 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4766 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4768 unsigned int rn
= bits (insn1
, 0, 3);
4769 unsigned int u_bit
= bit (insn1
, 7);
4770 int imm12
= bits (insn2
, 0, 11);
4773 if (rn
!= ARM_PC_REGNUM
)
4774 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4776 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4777 PLD (literal) Encoding T1. */
4778 if (debug_displaced
)
4779 fprintf_unfiltered (gdb_stdlog
,
4780 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4781 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4787 /* Rewrite instruction {pli/pld} PC imm12 into:
4788 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4792 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4794 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4795 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4797 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4799 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4800 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4801 dsc
->u
.preload
.immed
= 0;
4803 /* {pli/pld} [r0, r1] */
4804 dsc
->modinsn
[0] = insn1
& 0xfff0;
4805 dsc
->modinsn
[1] = 0xf001;
4808 dsc
->cleanup
= &cleanup_preload
;
4812 /* Preload instructions with register offset. */
4815 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4816 struct displaced_step_closure
*dsc
, unsigned int rn
,
4819 ULONGEST rn_val
, rm_val
;
4821 /* Preload register-offset instructions:
4823 {pli/pld} [rn, rm {, shift}]
4825 {pli/pld} [r0, r1 {, shift}]. */
4827 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4828 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4829 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4830 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4831 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4832 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4833 dsc
->u
.preload
.immed
= 0;
4835 dsc
->cleanup
= &cleanup_preload
;
4839 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4840 struct regcache
*regs
,
4841 struct displaced_step_closure
*dsc
)
4843 unsigned int rn
= bits (insn
, 16, 19);
4844 unsigned int rm
= bits (insn
, 0, 3);
4847 if (!insn_references_pc (insn
, 0x000f000ful
))
4848 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4850 if (debug_displaced
)
4851 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4852 (unsigned long) insn
);
4854 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4856 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4860 /* Copy/cleanup coprocessor load and store instructions. */
4863 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4864 struct regcache
*regs
,
4865 struct displaced_step_closure
*dsc
)
4867 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4869 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4871 if (dsc
->u
.ldst
.writeback
)
4872 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4876 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4877 struct displaced_step_closure
*dsc
,
4878 int writeback
, unsigned int rn
)
4882 /* Coprocessor load/store instructions:
4884 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4886 {stc/stc2} [r0, #+/-imm].
4888 ldc/ldc2 are handled identically. */
4890 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4891 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4892 /* PC should be 4-byte aligned. */
4893 rn_val
= rn_val
& 0xfffffffc;
4894 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4896 dsc
->u
.ldst
.writeback
= writeback
;
4897 dsc
->u
.ldst
.rn
= rn
;
4899 dsc
->cleanup
= &cleanup_copro_load_store
;
4903 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4904 struct regcache
*regs
,
4905 struct displaced_step_closure
*dsc
)
4907 unsigned int rn
= bits (insn
, 16, 19);
4909 if (!insn_references_pc (insn
, 0x000f0000ul
))
4910 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4912 if (debug_displaced
)
4913 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4914 "load/store insn %.8lx\n", (unsigned long) insn
);
4916 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4918 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4924 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4925 uint16_t insn2
, struct regcache
*regs
,
4926 struct displaced_step_closure
*dsc
)
4928 unsigned int rn
= bits (insn1
, 0, 3);
4930 if (rn
!= ARM_PC_REGNUM
)
4931 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4932 "copro load/store", dsc
);
4934 if (debug_displaced
)
4935 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4936 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4938 dsc
->modinsn
[0] = insn1
& 0xfff0;
4939 dsc
->modinsn
[1] = insn2
;
4942 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4943 doesn't support writeback, so pass 0. */
4944 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4949 /* Clean up branch instructions (actually perform the branch, by setting
4953 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4954 struct displaced_step_closure
*dsc
)
4956 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4957 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4958 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4959 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4964 if (dsc
->u
.branch
.link
)
4966 /* The value of LR should be the next insn of current one. In order
4967 not to confuse logic hanlding later insn `bx lr', if current insn mode
4968 is Thumb, the bit 0 of LR value should be set to 1. */
4969 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4972 next_insn_addr
|= 0x1;
4974 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4978 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4981 /* Copy B/BL/BLX instructions with immediate destinations. */
4984 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4985 struct displaced_step_closure
*dsc
,
4986 unsigned int cond
, int exchange
, int link
, long offset
)
4988 /* Implement "BL<cond> <label>" as:
4990 Preparation: cond <- instruction condition
4991 Insn: mov r0, r0 (nop)
4992 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4994 B<cond> similar, but don't set r14 in cleanup. */
4996 dsc
->u
.branch
.cond
= cond
;
4997 dsc
->u
.branch
.link
= link
;
4998 dsc
->u
.branch
.exchange
= exchange
;
5000 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
5001 if (link
&& exchange
)
5002 /* For BLX, offset is computed from the Align (PC, 4). */
5003 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5006 dsc
->u
.branch
.dest
+= 4 + offset
;
5008 dsc
->u
.branch
.dest
+= 8 + offset
;
5010 dsc
->cleanup
= &cleanup_branch
;
5013 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5014 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5016 unsigned int cond
= bits (insn
, 28, 31);
5017 int exchange
= (cond
== 0xf);
5018 int link
= exchange
|| bit (insn
, 24);
5021 if (debug_displaced
)
5022 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5023 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5024 (unsigned long) insn
);
5026 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5027 then arrange the switch into Thumb mode. */
5028 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5030 offset
= bits (insn
, 0, 23) << 2;
5032 if (bit (offset
, 25))
5033 offset
= offset
| ~0x3ffffff;
5035 dsc
->modinsn
[0] = ARM_NOP
;
5037 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5042 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5043 uint16_t insn2
, struct regcache
*regs
,
5044 struct displaced_step_closure
*dsc
)
5046 int link
= bit (insn2
, 14);
5047 int exchange
= link
&& !bit (insn2
, 12);
5050 int j1
= bit (insn2
, 13);
5051 int j2
= bit (insn2
, 11);
5052 int s
= sbits (insn1
, 10, 10);
5053 int i1
= !(j1
^ bit (insn1
, 10));
5054 int i2
= !(j2
^ bit (insn1
, 10));
5056 if (!link
&& !exchange
) /* B */
5058 offset
= (bits (insn2
, 0, 10) << 1);
5059 if (bit (insn2
, 12)) /* Encoding T4 */
5061 offset
|= (bits (insn1
, 0, 9) << 12)
5067 else /* Encoding T3 */
5069 offset
|= (bits (insn1
, 0, 5) << 12)
5073 cond
= bits (insn1
, 6, 9);
5078 offset
= (bits (insn1
, 0, 9) << 12);
5079 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5080 offset
|= exchange
?
5081 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5084 if (debug_displaced
)
5085 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5086 "%.4x %.4x with offset %.8lx\n",
5087 link
? (exchange
) ? "blx" : "bl" : "b",
5088 insn1
, insn2
, offset
);
5090 dsc
->modinsn
[0] = THUMB_NOP
;
5092 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5096 /* Copy B Thumb instructions. */
5098 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5099 struct displaced_step_closure
*dsc
)
5101 unsigned int cond
= 0;
5103 unsigned short bit_12_15
= bits (insn
, 12, 15);
5104 CORE_ADDR from
= dsc
->insn_addr
;
5106 if (bit_12_15
== 0xd)
5108 /* offset = SignExtend (imm8:0, 32) */
5109 offset
= sbits ((insn
<< 1), 0, 8);
5110 cond
= bits (insn
, 8, 11);
5112 else if (bit_12_15
== 0xe) /* Encoding T2 */
5114 offset
= sbits ((insn
<< 1), 0, 11);
5118 if (debug_displaced
)
5119 fprintf_unfiltered (gdb_stdlog
,
5120 "displaced: copying b immediate insn %.4x "
5121 "with offset %d\n", insn
, offset
);
5123 dsc
->u
.branch
.cond
= cond
;
5124 dsc
->u
.branch
.link
= 0;
5125 dsc
->u
.branch
.exchange
= 0;
5126 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5128 dsc
->modinsn
[0] = THUMB_NOP
;
5130 dsc
->cleanup
= &cleanup_branch
;
5135 /* Copy BX/BLX with register-specified destinations. */
5138 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5139 struct displaced_step_closure
*dsc
, int link
,
5140 unsigned int cond
, unsigned int rm
)
5142 /* Implement {BX,BLX}<cond> <reg>" as:
5144 Preparation: cond <- instruction condition
5145 Insn: mov r0, r0 (nop)
5146 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5148 Don't set r14 in cleanup for BX. */
5150 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5152 dsc
->u
.branch
.cond
= cond
;
5153 dsc
->u
.branch
.link
= link
;
5155 dsc
->u
.branch
.exchange
= 1;
5157 dsc
->cleanup
= &cleanup_branch
;
5161 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5162 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5164 unsigned int cond
= bits (insn
, 28, 31);
5167 int link
= bit (insn
, 5);
5168 unsigned int rm
= bits (insn
, 0, 3);
5170 if (debug_displaced
)
5171 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5172 (unsigned long) insn
);
5174 dsc
->modinsn
[0] = ARM_NOP
;
5176 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5181 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5182 struct regcache
*regs
,
5183 struct displaced_step_closure
*dsc
)
5185 int link
= bit (insn
, 7);
5186 unsigned int rm
= bits (insn
, 3, 6);
5188 if (debug_displaced
)
5189 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5190 (unsigned short) insn
);
5192 dsc
->modinsn
[0] = THUMB_NOP
;
5194 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5200 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5203 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5204 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5206 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5207 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5208 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5209 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5213 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5214 struct displaced_step_closure
*dsc
)
5216 unsigned int rn
= bits (insn
, 16, 19);
5217 unsigned int rd
= bits (insn
, 12, 15);
5218 unsigned int op
= bits (insn
, 21, 24);
5219 int is_mov
= (op
== 0xd);
5220 ULONGEST rd_val
, rn_val
;
5222 if (!insn_references_pc (insn
, 0x000ff000ul
))
5223 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5225 if (debug_displaced
)
5226 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5227 "%.8lx\n", is_mov
? "move" : "ALU",
5228 (unsigned long) insn
);
5230 /* Instruction is of form:
5232 <op><cond> rd, [rn,] #imm
5236 Preparation: tmp1, tmp2 <- r0, r1;
5238 Insn: <op><cond> r0, r1, #imm
5239 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5242 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5243 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5244 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5245 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5246 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5247 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5251 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5253 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5255 dsc
->cleanup
= &cleanup_alu_imm
;
5261 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5262 uint16_t insn2
, struct regcache
*regs
,
5263 struct displaced_step_closure
*dsc
)
5265 unsigned int op
= bits (insn1
, 5, 8);
5266 unsigned int rn
, rm
, rd
;
5267 ULONGEST rd_val
, rn_val
;
5269 rn
= bits (insn1
, 0, 3); /* Rn */
5270 rm
= bits (insn2
, 0, 3); /* Rm */
5271 rd
= bits (insn2
, 8, 11); /* Rd */
5273 /* This routine is only called for instruction MOV. */
5274 gdb_assert (op
== 0x2 && rn
== 0xf);
5276 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5277 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5279 if (debug_displaced
)
5280 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5281 "ALU", insn1
, insn2
);
5283 /* Instruction is of form:
5285 <op><cond> rd, [rn,] #imm
5289 Preparation: tmp1, tmp2 <- r0, r1;
5291 Insn: <op><cond> r0, r1, #imm
5292 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5295 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5296 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5297 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5298 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5299 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5300 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5303 dsc
->modinsn
[0] = insn1
;
5304 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5307 dsc
->cleanup
= &cleanup_alu_imm
;
5312 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5315 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5316 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5321 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5323 for (i
= 0; i
< 3; i
++)
5324 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5326 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5330 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5331 struct displaced_step_closure
*dsc
,
5332 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5334 ULONGEST rd_val
, rn_val
, rm_val
;
5336 /* Instruction is of form:
5338 <op><cond> rd, [rn,] rm [, <shift>]
5342 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5343 r0, r1, r2 <- rd, rn, rm
5344 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5345 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5348 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5349 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5350 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5351 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5352 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5353 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5354 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5355 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5356 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5359 dsc
->cleanup
= &cleanup_alu_reg
;
5363 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5364 struct displaced_step_closure
*dsc
)
5366 unsigned int op
= bits (insn
, 21, 24);
5367 int is_mov
= (op
== 0xd);
5369 if (!insn_references_pc (insn
, 0x000ff00ful
))
5370 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5372 if (debug_displaced
)
5373 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5374 is_mov
? "move" : "ALU", (unsigned long) insn
);
5377 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5379 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5381 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5387 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5388 struct regcache
*regs
,
5389 struct displaced_step_closure
*dsc
)
5393 rm
= bits (insn
, 3, 6);
5394 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5396 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5397 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5399 if (debug_displaced
)
5400 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5401 (unsigned short) insn
);
5403 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5405 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5410 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5413 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5414 struct regcache
*regs
,
5415 struct displaced_step_closure
*dsc
)
5417 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5420 for (i
= 0; i
< 4; i
++)
5421 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5423 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5427 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5428 struct displaced_step_closure
*dsc
,
5429 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5433 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5435 /* Instruction is of form:
5437 <op><cond> rd, [rn,] rm, <shift> rs
5441 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5442 r0, r1, r2, r3 <- rd, rn, rm, rs
5443 Insn: <op><cond> r0, r1, r2, <shift> r3
5445 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5449 for (i
= 0; i
< 4; i
++)
5450 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5452 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5453 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5454 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5455 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5456 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5457 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5458 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5459 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5461 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5465 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5466 struct regcache
*regs
,
5467 struct displaced_step_closure
*dsc
)
5469 unsigned int op
= bits (insn
, 21, 24);
5470 int is_mov
= (op
== 0xd);
5471 unsigned int rd
, rn
, rm
, rs
;
5473 if (!insn_references_pc (insn
, 0x000fff0ful
))
5474 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5476 if (debug_displaced
)
5477 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5478 "%.8lx\n", is_mov
? "move" : "ALU",
5479 (unsigned long) insn
);
5481 rn
= bits (insn
, 16, 19);
5482 rm
= bits (insn
, 0, 3);
5483 rs
= bits (insn
, 8, 11);
5484 rd
= bits (insn
, 12, 15);
5487 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5489 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5491 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5496 /* Clean up load instructions. */
5499 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5500 struct displaced_step_closure
*dsc
)
5502 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5504 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5505 if (dsc
->u
.ldst
.xfersize
== 8)
5506 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5507 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5509 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5510 if (dsc
->u
.ldst
.xfersize
> 4)
5511 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5512 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5513 if (!dsc
->u
.ldst
.immed
)
5514 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5516 /* Handle register writeback. */
5517 if (dsc
->u
.ldst
.writeback
)
5518 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5519 /* Put result in right place. */
5520 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5521 if (dsc
->u
.ldst
.xfersize
== 8)
5522 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5525 /* Clean up store instructions. */
5528 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5529 struct displaced_step_closure
*dsc
)
5531 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5533 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5534 if (dsc
->u
.ldst
.xfersize
> 4)
5535 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5536 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5537 if (!dsc
->u
.ldst
.immed
)
5538 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5539 if (!dsc
->u
.ldst
.restore_r4
)
5540 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5543 if (dsc
->u
.ldst
.writeback
)
5544 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5547 /* Copy "extra" load/store instructions. These are halfword/doubleword
5548 transfers, which have a different encoding to byte/word transfers. */
5551 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5552 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5554 unsigned int op1
= bits (insn
, 20, 24);
5555 unsigned int op2
= bits (insn
, 5, 6);
5556 unsigned int rt
= bits (insn
, 12, 15);
5557 unsigned int rn
= bits (insn
, 16, 19);
5558 unsigned int rm
= bits (insn
, 0, 3);
5559 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5560 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5561 int immed
= (op1
& 0x4) != 0;
5563 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5565 if (!insn_references_pc (insn
, 0x000ff00ful
))
5566 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5568 if (debug_displaced
)
5569 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5570 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5571 (unsigned long) insn
);
5573 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5576 internal_error (__FILE__
, __LINE__
,
5577 _("copy_extra_ld_st: instruction decode error"));
5579 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5580 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5581 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5583 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5585 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5586 if (bytesize
[opcode
] == 8)
5587 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5588 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5590 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5592 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5593 if (bytesize
[opcode
] == 8)
5594 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5595 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5597 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5600 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5601 dsc
->u
.ldst
.rn
= rn
;
5602 dsc
->u
.ldst
.immed
= immed
;
5603 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5604 dsc
->u
.ldst
.restore_r4
= 0;
5607 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5609 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5610 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5612 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5614 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5615 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5617 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5622 /* Copy byte/half word/word loads and stores. */
5625 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5626 struct displaced_step_closure
*dsc
, int load
,
5627 int immed
, int writeback
, int size
, int usermode
,
5628 int rt
, int rm
, int rn
)
5630 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5632 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5633 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5635 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5637 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5639 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5640 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5642 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5644 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5645 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5647 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5649 dsc
->u
.ldst
.xfersize
= size
;
5650 dsc
->u
.ldst
.rn
= rn
;
5651 dsc
->u
.ldst
.immed
= immed
;
5652 dsc
->u
.ldst
.writeback
= writeback
;
5654 /* To write PC we can do:
5656 Before this sequence of instructions:
5657 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5658 r2 is the Rn value got from dispalced_read_reg.
5660 Insn1: push {pc} Write address of STR instruction + offset on stack
5661 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5662 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5663 = addr(Insn1) + offset - addr(Insn3) - 8
5665 Insn4: add r4, r4, #8 r4 = offset - 8
5666 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5668 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5670 Otherwise we don't know what value to write for PC, since the offset is
5671 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5672 of this can be found in Section "Saving from r15" in
5673 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5675 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5680 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5681 uint16_t insn2
, struct regcache
*regs
,
5682 struct displaced_step_closure
*dsc
, int size
)
5684 unsigned int u_bit
= bit (insn1
, 7);
5685 unsigned int rt
= bits (insn2
, 12, 15);
5686 int imm12
= bits (insn2
, 0, 11);
5689 if (debug_displaced
)
5690 fprintf_unfiltered (gdb_stdlog
,
5691 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5692 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5698 /* Rewrite instruction LDR Rt imm12 into:
5700 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5704 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5707 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5708 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5709 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5711 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5713 pc_val
= pc_val
& 0xfffffffc;
5715 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5716 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5720 dsc
->u
.ldst
.xfersize
= size
;
5721 dsc
->u
.ldst
.immed
= 0;
5722 dsc
->u
.ldst
.writeback
= 0;
5723 dsc
->u
.ldst
.restore_r4
= 0;
5725 /* LDR R0, R2, R3 */
5726 dsc
->modinsn
[0] = 0xf852;
5727 dsc
->modinsn
[1] = 0x3;
5730 dsc
->cleanup
= &cleanup_load
;
5736 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5737 uint16_t insn2
, struct regcache
*regs
,
5738 struct displaced_step_closure
*dsc
,
5739 int writeback
, int immed
)
5741 unsigned int rt
= bits (insn2
, 12, 15);
5742 unsigned int rn
= bits (insn1
, 0, 3);
5743 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5744 /* In LDR (register), there is also a register Rm, which is not allowed to
5745 be PC, so we don't have to check it. */
5747 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5748 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5751 if (debug_displaced
)
5752 fprintf_unfiltered (gdb_stdlog
,
5753 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5754 rt
, rn
, insn1
, insn2
);
5756 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5759 dsc
->u
.ldst
.restore_r4
= 0;
5762 /* ldr[b]<cond> rt, [rn, #imm], etc.
5764 ldr[b]<cond> r0, [r2, #imm]. */
5766 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5767 dsc
->modinsn
[1] = insn2
& 0x0fff;
5770 /* ldr[b]<cond> rt, [rn, rm], etc.
5772 ldr[b]<cond> r0, [r2, r3]. */
5774 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5775 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5785 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5786 struct regcache
*regs
,
5787 struct displaced_step_closure
*dsc
,
5788 int load
, int size
, int usermode
)
5790 int immed
= !bit (insn
, 25);
5791 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5792 unsigned int rt
= bits (insn
, 12, 15);
5793 unsigned int rn
= bits (insn
, 16, 19);
5794 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5796 if (!insn_references_pc (insn
, 0x000ff00ful
))
5797 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5799 if (debug_displaced
)
5800 fprintf_unfiltered (gdb_stdlog
,
5801 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5802 load
? (size
== 1 ? "ldrb" : "ldr")
5803 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5805 (unsigned long) insn
);
5807 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5808 usermode
, rt
, rm
, rn
);
5810 if (load
|| rt
!= ARM_PC_REGNUM
)
5812 dsc
->u
.ldst
.restore_r4
= 0;
5815 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5817 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5818 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5820 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5822 {ldr,str}[b]<cond> r0, [r2, r3]. */
5823 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5827 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5828 dsc
->u
.ldst
.restore_r4
= 1;
5829 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5830 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5831 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5832 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5833 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5837 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5839 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5844 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5849 /* Cleanup LDM instructions with fully-populated register list. This is an
5850 unfortunate corner case: it's impossible to implement correctly by modifying
5851 the instruction. The issue is as follows: we have an instruction,
5855 which we must rewrite to avoid loading PC. A possible solution would be to
5856 do the load in two halves, something like (with suitable cleanup
5860 ldm[id][ab] r8!, {r0-r7}
5862 ldm[id][ab] r8, {r7-r14}
5865 but at present there's no suitable place for <temp>, since the scratch space
5866 is overwritten before the cleanup routine is called. For now, we simply
5867 emulate the instruction. */
5870 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5871 struct displaced_step_closure
*dsc
)
5873 int inc
= dsc
->u
.block
.increment
;
5874 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5875 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5876 uint32_t regmask
= dsc
->u
.block
.regmask
;
5877 int regno
= inc
? 0 : 15;
5878 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5879 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5880 && (regmask
& 0x8000) != 0;
5881 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5882 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5888 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5889 sensible we can do here. Complain loudly. */
5890 if (exception_return
)
5891 error (_("Cannot single-step exception return"));
5893 /* We don't handle any stores here for now. */
5894 gdb_assert (dsc
->u
.block
.load
!= 0);
5896 if (debug_displaced
)
5897 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5898 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5899 dsc
->u
.block
.increment
? "inc" : "dec",
5900 dsc
->u
.block
.before
? "before" : "after");
5907 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5910 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5913 xfer_addr
+= bump_before
;
5915 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5916 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5918 xfer_addr
+= bump_after
;
5920 regmask
&= ~(1 << regno
);
5923 if (dsc
->u
.block
.writeback
)
5924 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5928 /* Clean up an STM which included the PC in the register list. */
5931 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5932 struct displaced_step_closure
*dsc
)
5934 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5935 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5936 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5937 CORE_ADDR stm_insn_addr
;
5940 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5942 /* If condition code fails, there's nothing else to do. */
5943 if (!store_executed
)
5946 if (dsc
->u
.block
.increment
)
5948 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5950 if (dsc
->u
.block
.before
)
5955 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5957 if (dsc
->u
.block
.before
)
5961 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5962 stm_insn_addr
= dsc
->scratch_base
;
5963 offset
= pc_val
- stm_insn_addr
;
5965 if (debug_displaced
)
5966 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5967 "STM instruction\n", offset
);
5969 /* Rewrite the stored PC to the proper value for the non-displaced original
5971 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5972 dsc
->insn_addr
+ offset
);
5975 /* Clean up an LDM which includes the PC in the register list. We clumped all
5976 the registers in the transferred list into a contiguous range r0...rX (to
5977 avoid loading PC directly and losing control of the debugged program), so we
5978 must undo that here. */
5981 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5982 struct regcache
*regs
,
5983 struct displaced_step_closure
*dsc
)
5985 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5986 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5987 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5988 unsigned int regs_loaded
= bitcount (mask
);
5989 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5991 /* The method employed here will fail if the register list is fully populated
5992 (we need to avoid loading PC directly). */
5993 gdb_assert (num_to_shuffle
< 16);
5998 clobbered
= (1 << num_to_shuffle
) - 1;
6000 while (num_to_shuffle
> 0)
6002 if ((mask
& (1 << write_reg
)) != 0)
6004 unsigned int read_reg
= num_to_shuffle
- 1;
6006 if (read_reg
!= write_reg
)
6008 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6009 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6010 if (debug_displaced
)
6011 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6012 "loaded register r%d to r%d\n"), read_reg
,
6015 else if (debug_displaced
)
6016 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6017 "r%d already in the right place\n"),
6020 clobbered
&= ~(1 << write_reg
);
6028 /* Restore any registers we scribbled over. */
6029 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6031 if ((clobbered
& (1 << write_reg
)) != 0)
6033 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6035 if (debug_displaced
)
6036 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6037 "clobbered register r%d\n"), write_reg
);
6038 clobbered
&= ~(1 << write_reg
);
6042 /* Perform register writeback manually. */
6043 if (dsc
->u
.block
.writeback
)
6045 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6047 if (dsc
->u
.block
.increment
)
6048 new_rn_val
+= regs_loaded
* 4;
6050 new_rn_val
-= regs_loaded
* 4;
6052 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6057 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6058 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6061 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6062 struct regcache
*regs
,
6063 struct displaced_step_closure
*dsc
)
6065 int load
= bit (insn
, 20);
6066 int user
= bit (insn
, 22);
6067 int increment
= bit (insn
, 23);
6068 int before
= bit (insn
, 24);
6069 int writeback
= bit (insn
, 21);
6070 int rn
= bits (insn
, 16, 19);
6072 /* Block transfers which don't mention PC can be run directly
6074 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6075 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6077 if (rn
== ARM_PC_REGNUM
)
6079 warning (_("displaced: Unpredictable LDM or STM with "
6080 "base register r15"));
6081 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6084 if (debug_displaced
)
6085 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6086 "%.8lx\n", (unsigned long) insn
);
6088 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6089 dsc
->u
.block
.rn
= rn
;
6091 dsc
->u
.block
.load
= load
;
6092 dsc
->u
.block
.user
= user
;
6093 dsc
->u
.block
.increment
= increment
;
6094 dsc
->u
.block
.before
= before
;
6095 dsc
->u
.block
.writeback
= writeback
;
6096 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6098 dsc
->u
.block
.regmask
= insn
& 0xffff;
6102 if ((insn
& 0xffff) == 0xffff)
6104 /* LDM with a fully-populated register list. This case is
6105 particularly tricky. Implement for now by fully emulating the
6106 instruction (which might not behave perfectly in all cases, but
6107 these instructions should be rare enough for that not to matter
6109 dsc
->modinsn
[0] = ARM_NOP
;
6111 dsc
->cleanup
= &cleanup_block_load_all
;
6115 /* LDM of a list of registers which includes PC. Implement by
6116 rewriting the list of registers to be transferred into a
6117 contiguous chunk r0...rX before doing the transfer, then shuffling
6118 registers into the correct places in the cleanup routine. */
6119 unsigned int regmask
= insn
& 0xffff;
6120 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6123 for (i
= 0; i
< num_in_list
; i
++)
6124 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6126 /* Writeback makes things complicated. We need to avoid clobbering
6127 the base register with one of the registers in our modified
6128 register list, but just using a different register can't work in
6131 ldm r14!, {r0-r13,pc}
6133 which would need to be rewritten as:
6137 but that can't work, because there's no free register for N.
6139 Solve this by turning off the writeback bit, and emulating
6140 writeback manually in the cleanup routine. */
6145 new_regmask
= (1 << num_in_list
) - 1;
6147 if (debug_displaced
)
6148 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6149 "{..., pc}: original reg list %.4x, modified "
6150 "list %.4x\n"), rn
, writeback
? "!" : "",
6151 (int) insn
& 0xffff, new_regmask
);
6153 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6155 dsc
->cleanup
= &cleanup_block_load_pc
;
6160 /* STM of a list of registers which includes PC. Run the instruction
6161 as-is, but out of line: this will store the wrong value for the PC,
6162 so we must manually fix up the memory in the cleanup routine.
6163 Doing things this way has the advantage that we can auto-detect
6164 the offset of the PC write (which is architecture-dependent) in
6165 the cleanup routine. */
6166 dsc
->modinsn
[0] = insn
;
6168 dsc
->cleanup
= &cleanup_block_store_pc
;
6175 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6176 struct regcache
*regs
,
6177 struct displaced_step_closure
*dsc
)
6179 int rn
= bits (insn1
, 0, 3);
6180 int load
= bit (insn1
, 4);
6181 int writeback
= bit (insn1
, 5);
6183 /* Block transfers which don't mention PC can be run directly
6185 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6186 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6188 if (rn
== ARM_PC_REGNUM
)
6190 warning (_("displaced: Unpredictable LDM or STM with "
6191 "base register r15"));
6192 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6193 "unpredictable ldm/stm", dsc
);
6196 if (debug_displaced
)
6197 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6198 "%.4x%.4x\n", insn1
, insn2
);
6200 /* Clear bit 13, since it should be always zero. */
6201 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6202 dsc
->u
.block
.rn
= rn
;
6204 dsc
->u
.block
.load
= load
;
6205 dsc
->u
.block
.user
= 0;
6206 dsc
->u
.block
.increment
= bit (insn1
, 7);
6207 dsc
->u
.block
.before
= bit (insn1
, 8);
6208 dsc
->u
.block
.writeback
= writeback
;
6209 dsc
->u
.block
.cond
= INST_AL
;
6210 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6214 if (dsc
->u
.block
.regmask
== 0xffff)
6216 /* This branch is impossible to happen. */
6221 unsigned int regmask
= dsc
->u
.block
.regmask
;
6222 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6225 for (i
= 0; i
< num_in_list
; i
++)
6226 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6231 new_regmask
= (1 << num_in_list
) - 1;
6233 if (debug_displaced
)
6234 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6235 "{..., pc}: original reg list %.4x, modified "
6236 "list %.4x\n"), rn
, writeback
? "!" : "",
6237 (int) dsc
->u
.block
.regmask
, new_regmask
);
6239 dsc
->modinsn
[0] = insn1
;
6240 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6243 dsc
->cleanup
= &cleanup_block_load_pc
;
6248 dsc
->modinsn
[0] = insn1
;
6249 dsc
->modinsn
[1] = insn2
;
6251 dsc
->cleanup
= &cleanup_block_store_pc
;
6256 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6257 This is used to avoid a dependency on BFD's bfd_endian enum. */
6260 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6263 return read_memory_unsigned_integer (memaddr
, len
,
6264 (enum bfd_endian
) byte_order
);
6267 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6270 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6273 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6276 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6279 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6284 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6287 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6289 return arm_is_thumb (self
->regcache
);
6292 /* single_step() is called just before we want to resume the inferior,
6293 if we want to single-step it but there is no hardware or kernel
6294 single-step support. We find the target of the coming instructions
6295 and breakpoint them. */
6298 arm_software_single_step (struct regcache
*regcache
)
6300 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6301 struct arm_get_next_pcs next_pcs_ctx
;
6304 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6305 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6307 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6308 &arm_get_next_pcs_ops
,
6309 gdbarch_byte_order (gdbarch
),
6310 gdbarch_byte_order_for_code (gdbarch
),
6314 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6316 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6318 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
6319 VEC_replace (CORE_ADDR
, next_pcs
, i
, pc
);
6322 discard_cleanups (old_chain
);
6327 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6328 for Linux, where some SVC instructions must be treated specially. */
6331 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6332 struct displaced_step_closure
*dsc
)
6334 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6336 if (debug_displaced
)
6337 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6338 "%.8lx\n", (unsigned long) resume_addr
);
6340 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6344 /* Common copy routine for svc instruciton. */
6347 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6348 struct displaced_step_closure
*dsc
)
6350 /* Preparation: none.
6351 Insn: unmodified svc.
6352 Cleanup: pc <- insn_addr + insn_size. */
6354 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6356 dsc
->wrote_to_pc
= 1;
6358 /* Allow OS-specific code to override SVC handling. */
6359 if (dsc
->u
.svc
.copy_svc_os
)
6360 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6363 dsc
->cleanup
= &cleanup_svc
;
6369 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6370 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6373 if (debug_displaced
)
6374 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6375 (unsigned long) insn
);
6377 dsc
->modinsn
[0] = insn
;
6379 return install_svc (gdbarch
, regs
, dsc
);
6383 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6384 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6387 if (debug_displaced
)
6388 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6391 dsc
->modinsn
[0] = insn
;
6393 return install_svc (gdbarch
, regs
, dsc
);
6396 /* Copy undefined instructions. */
6399 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6400 struct displaced_step_closure
*dsc
)
6402 if (debug_displaced
)
6403 fprintf_unfiltered (gdb_stdlog
,
6404 "displaced: copying undefined insn %.8lx\n",
6405 (unsigned long) insn
);
6407 dsc
->modinsn
[0] = insn
;
6413 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6414 struct displaced_step_closure
*dsc
)
6417 if (debug_displaced
)
6418 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6419 "%.4x %.4x\n", (unsigned short) insn1
,
6420 (unsigned short) insn2
);
6422 dsc
->modinsn
[0] = insn1
;
6423 dsc
->modinsn
[1] = insn2
;
6429 /* Copy unpredictable instructions. */
6432 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6433 struct displaced_step_closure
*dsc
)
6435 if (debug_displaced
)
6436 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6437 "%.8lx\n", (unsigned long) insn
);
6439 dsc
->modinsn
[0] = insn
;
6444 /* The decode_* functions are instruction decoding helpers. They mostly follow
6445 the presentation in the ARM ARM. */
6448 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6449 struct regcache
*regs
,
6450 struct displaced_step_closure
*dsc
)
6452 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6453 unsigned int rn
= bits (insn
, 16, 19);
6455 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6456 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6457 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6458 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6459 else if ((op1
& 0x60) == 0x20)
6460 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6461 else if ((op1
& 0x71) == 0x40)
6462 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6464 else if ((op1
& 0x77) == 0x41)
6465 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6466 else if ((op1
& 0x77) == 0x45)
6467 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6468 else if ((op1
& 0x77) == 0x51)
6471 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6473 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6475 else if ((op1
& 0x77) == 0x55)
6476 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6477 else if (op1
== 0x57)
6480 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6481 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6482 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6483 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6484 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6486 else if ((op1
& 0x63) == 0x43)
6487 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6488 else if ((op2
& 0x1) == 0x0)
6489 switch (op1
& ~0x80)
6492 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6494 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6495 case 0x71: case 0x75:
6497 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6498 case 0x63: case 0x67: case 0x73: case 0x77:
6499 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6501 return arm_copy_undef (gdbarch
, insn
, dsc
);
6504 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6508 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6509 struct regcache
*regs
,
6510 struct displaced_step_closure
*dsc
)
6512 if (bit (insn
, 27) == 0)
6513 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6514 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6515 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6518 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6521 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6523 case 0x4: case 0x5: case 0x6: case 0x7:
6524 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6527 switch ((insn
& 0xe00000) >> 21)
6529 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6531 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6534 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6537 return arm_copy_undef (gdbarch
, insn
, dsc
);
6542 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6543 switch ((insn
& 0xe00000) >> 21)
6546 /* ldc/ldc2 imm (undefined for rn == pc). */
6547 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6548 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6551 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6553 case 0x4: case 0x5: case 0x6: case 0x7:
6554 /* ldc/ldc2 lit (undefined for rn != pc). */
6555 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6556 : arm_copy_undef (gdbarch
, insn
, dsc
);
6559 return arm_copy_undef (gdbarch
, insn
, dsc
);
6564 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6567 if (bits (insn
, 16, 19) == 0xf)
6569 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6571 return arm_copy_undef (gdbarch
, insn
, dsc
);
6575 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6577 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6581 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6583 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6586 return arm_copy_undef (gdbarch
, insn
, dsc
);
6590 /* Decode miscellaneous instructions in dp/misc encoding space. */
6593 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6594 struct regcache
*regs
,
6595 struct displaced_step_closure
*dsc
)
6597 unsigned int op2
= bits (insn
, 4, 6);
6598 unsigned int op
= bits (insn
, 21, 22);
6603 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6606 if (op
== 0x1) /* bx. */
6607 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6609 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6611 return arm_copy_undef (gdbarch
, insn
, dsc
);
6615 /* Not really supported. */
6616 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6618 return arm_copy_undef (gdbarch
, insn
, dsc
);
6622 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6623 regs
, dsc
); /* blx register. */
6625 return arm_copy_undef (gdbarch
, insn
, dsc
);
6628 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6632 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6634 /* Not really supported. */
6635 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6638 return arm_copy_undef (gdbarch
, insn
, dsc
);
6643 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6644 struct regcache
*regs
,
6645 struct displaced_step_closure
*dsc
)
6648 switch (bits (insn
, 20, 24))
6651 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6654 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6656 case 0x12: case 0x16:
6657 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6660 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6664 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6666 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6667 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6668 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6669 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6670 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6671 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6672 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6673 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6674 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6675 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6676 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6677 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6678 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6679 /* 2nd arg means "unprivileged". */
6680 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6684 /* Should be unreachable. */
6689 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6690 struct regcache
*regs
,
6691 struct displaced_step_closure
*dsc
)
6693 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6694 uint32_t op1
= bits (insn
, 20, 24);
6696 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6697 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6698 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6699 else if ((!a
&& (op1
& 0x17) == 0x02)
6700 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6701 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6702 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6703 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6704 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6705 else if ((!a
&& (op1
& 0x17) == 0x03)
6706 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6707 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6708 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6709 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6710 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6711 else if ((!a
&& (op1
& 0x17) == 0x06)
6712 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6713 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6714 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6715 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6716 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6717 else if ((!a
&& (op1
& 0x17) == 0x07)
6718 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6719 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6721 /* Should be unreachable. */
6726 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6727 struct displaced_step_closure
*dsc
)
6729 switch (bits (insn
, 20, 24))
6731 case 0x00: case 0x01: case 0x02: case 0x03:
6732 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6734 case 0x04: case 0x05: case 0x06: case 0x07:
6735 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6737 case 0x08: case 0x09: case 0x0a: case 0x0b:
6738 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6739 return arm_copy_unmodified (gdbarch
, insn
,
6740 "decode/pack/unpack/saturate/reverse", dsc
);
6743 if (bits (insn
, 5, 7) == 0) /* op2. */
6745 if (bits (insn
, 12, 15) == 0xf)
6746 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6748 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6751 return arm_copy_undef (gdbarch
, insn
, dsc
);
6753 case 0x1a: case 0x1b:
6754 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6755 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6757 return arm_copy_undef (gdbarch
, insn
, dsc
);
6759 case 0x1c: case 0x1d:
6760 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6762 if (bits (insn
, 0, 3) == 0xf)
6763 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6765 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6768 return arm_copy_undef (gdbarch
, insn
, dsc
);
6770 case 0x1e: case 0x1f:
6771 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6772 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6774 return arm_copy_undef (gdbarch
, insn
, dsc
);
6777 /* Should be unreachable. */
6782 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6783 struct regcache
*regs
,
6784 struct displaced_step_closure
*dsc
)
6787 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6789 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6793 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6794 struct regcache
*regs
,
6795 struct displaced_step_closure
*dsc
)
6797 unsigned int opcode
= bits (insn
, 20, 24);
6801 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6802 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6804 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6805 case 0x12: case 0x16:
6806 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6808 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6809 case 0x13: case 0x17:
6810 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6812 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6813 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6814 /* Note: no writeback for these instructions. Bit 25 will always be
6815 zero though (via caller), so the following works OK. */
6816 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6819 /* Should be unreachable. */
6823 /* Decode shifted register instructions. */
6826 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6827 uint16_t insn2
, struct regcache
*regs
,
6828 struct displaced_step_closure
*dsc
)
6830 /* PC is only allowed to be used in instruction MOV. */
6832 unsigned int op
= bits (insn1
, 5, 8);
6833 unsigned int rn
= bits (insn1
, 0, 3);
6835 if (op
== 0x2 && rn
== 0xf) /* MOV */
6836 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6838 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6839 "dp (shift reg)", dsc
);
6843 /* Decode extension register load/store. Exactly the same as
6844 arm_decode_ext_reg_ld_st. */
6847 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6848 uint16_t insn2
, struct regcache
*regs
,
6849 struct displaced_step_closure
*dsc
)
6851 unsigned int opcode
= bits (insn1
, 4, 8);
6855 case 0x04: case 0x05:
6856 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6857 "vfp/neon vmov", dsc
);
6859 case 0x08: case 0x0c: /* 01x00 */
6860 case 0x0a: case 0x0e: /* 01x10 */
6861 case 0x12: case 0x16: /* 10x10 */
6862 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6863 "vfp/neon vstm/vpush", dsc
);
6865 case 0x09: case 0x0d: /* 01x01 */
6866 case 0x0b: case 0x0f: /* 01x11 */
6867 case 0x13: case 0x17: /* 10x11 */
6868 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6869 "vfp/neon vldm/vpop", dsc
);
6871 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6872 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6874 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6875 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6878 /* Should be unreachable. */
6883 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6884 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6886 unsigned int op1
= bits (insn
, 20, 25);
6887 int op
= bit (insn
, 4);
6888 unsigned int coproc
= bits (insn
, 8, 11);
6890 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6891 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6892 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6893 && (coproc
& 0xe) != 0xa)
6895 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6896 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6897 && (coproc
& 0xe) != 0xa)
6898 /* ldc/ldc2 imm/lit. */
6899 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6900 else if ((op1
& 0x3e) == 0x00)
6901 return arm_copy_undef (gdbarch
, insn
, dsc
);
6902 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6903 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6904 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6905 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6906 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6907 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6908 else if ((op1
& 0x30) == 0x20 && !op
)
6910 if ((coproc
& 0xe) == 0xa)
6911 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6913 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6915 else if ((op1
& 0x30) == 0x20 && op
)
6916 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6917 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6918 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6919 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6920 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6921 else if ((op1
& 0x30) == 0x30)
6922 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6924 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6928 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6929 uint16_t insn2
, struct regcache
*regs
,
6930 struct displaced_step_closure
*dsc
)
6932 unsigned int coproc
= bits (insn2
, 8, 11);
6933 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6934 unsigned int bit_9
= bit (insn1
, 9);
6935 unsigned int bit_4
= bit (insn1
, 4);
6940 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6941 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6943 else if (bit_5_8
== 0) /* UNDEFINED. */
6944 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6947 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6948 if ((coproc
& 0xe) == 0xa)
6949 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6951 else /* coproc is not 101x. */
6953 if (bit_4
== 0) /* STC/STC2. */
6954 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6956 else /* LDC/LDC2 {literal, immeidate}. */
6957 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6963 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6969 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6970 struct displaced_step_closure
*dsc
, int rd
)
6976 Preparation: Rd <- PC
6982 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6983 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6987 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6988 struct displaced_step_closure
*dsc
,
6989 int rd
, unsigned int imm
)
6992 /* Encoding T2: ADDS Rd, #imm */
6993 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6995 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7001 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7002 struct regcache
*regs
,
7003 struct displaced_step_closure
*dsc
)
7005 unsigned int rd
= bits (insn
, 8, 10);
7006 unsigned int imm8
= bits (insn
, 0, 7);
7008 if (debug_displaced
)
7009 fprintf_unfiltered (gdb_stdlog
,
7010 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7013 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7017 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7018 uint16_t insn2
, struct regcache
*regs
,
7019 struct displaced_step_closure
*dsc
)
7021 unsigned int rd
= bits (insn2
, 8, 11);
7022 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7023 extract raw immediate encoding rather than computing immediate. When
7024 generating ADD or SUB instruction, we can simply perform OR operation to
7025 set immediate into ADD. */
7026 unsigned int imm_3_8
= insn2
& 0x70ff;
7027 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7029 if (debug_displaced
)
7030 fprintf_unfiltered (gdb_stdlog
,
7031 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7032 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7034 if (bit (insn1
, 7)) /* Encoding T2 */
7036 /* Encoding T3: SUB Rd, Rd, #imm */
7037 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7038 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7040 else /* Encoding T3 */
7042 /* Encoding T3: ADD Rd, Rd, #imm */
7043 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7044 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7048 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7054 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7055 struct regcache
*regs
,
7056 struct displaced_step_closure
*dsc
)
7058 unsigned int rt
= bits (insn1
, 8, 10);
7060 int imm8
= (bits (insn1
, 0, 7) << 2);
7066 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7068 Insn: LDR R0, [R2, R3];
7069 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7071 if (debug_displaced
)
7072 fprintf_unfiltered (gdb_stdlog
,
7073 "displaced: copying thumb ldr r%d [pc #%d]\n"
7076 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7077 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7078 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7079 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7080 /* The assembler calculates the required value of the offset from the
7081 Align(PC,4) value of this instruction to the label. */
7082 pc
= pc
& 0xfffffffc;
7084 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7085 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7088 dsc
->u
.ldst
.xfersize
= 4;
7090 dsc
->u
.ldst
.immed
= 0;
7091 dsc
->u
.ldst
.writeback
= 0;
7092 dsc
->u
.ldst
.restore_r4
= 0;
7094 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7096 dsc
->cleanup
= &cleanup_load
;
7101 /* Copy Thumb cbnz/cbz insruction. */
7104 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7105 struct regcache
*regs
,
7106 struct displaced_step_closure
*dsc
)
7108 int non_zero
= bit (insn1
, 11);
7109 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7110 CORE_ADDR from
= dsc
->insn_addr
;
7111 int rn
= bits (insn1
, 0, 2);
7112 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7114 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7115 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7116 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7117 condition is false, let it be, cleanup_branch will do nothing. */
7118 if (dsc
->u
.branch
.cond
)
7120 dsc
->u
.branch
.cond
= INST_AL
;
7121 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7124 dsc
->u
.branch
.dest
= from
+ 2;
7126 dsc
->u
.branch
.link
= 0;
7127 dsc
->u
.branch
.exchange
= 0;
7129 if (debug_displaced
)
7130 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7131 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7132 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7134 dsc
->modinsn
[0] = THUMB_NOP
;
7136 dsc
->cleanup
= &cleanup_branch
;
7140 /* Copy Table Branch Byte/Halfword */
7142 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7143 uint16_t insn2
, struct regcache
*regs
,
7144 struct displaced_step_closure
*dsc
)
7146 ULONGEST rn_val
, rm_val
;
7147 int is_tbh
= bit (insn2
, 4);
7148 CORE_ADDR halfwords
= 0;
7149 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7151 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7152 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7158 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7159 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7165 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7166 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7169 if (debug_displaced
)
7170 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7171 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7172 (unsigned int) rn_val
, (unsigned int) rm_val
,
7173 (unsigned int) halfwords
);
7175 dsc
->u
.branch
.cond
= INST_AL
;
7176 dsc
->u
.branch
.link
= 0;
7177 dsc
->u
.branch
.exchange
= 0;
7178 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7180 dsc
->cleanup
= &cleanup_branch
;
7186 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7187 struct displaced_step_closure
*dsc
)
7190 int val
= displaced_read_reg (regs
, dsc
, 7);
7191 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7194 val
= displaced_read_reg (regs
, dsc
, 8);
7195 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7198 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7203 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7204 struct regcache
*regs
,
7205 struct displaced_step_closure
*dsc
)
7207 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7209 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7212 (1) register list is full, that is, r0-r7 are used.
7213 Prepare: tmp[0] <- r8
7215 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7216 MOV r8, r7; Move value of r7 to r8;
7217 POP {r7}; Store PC value into r7.
7219 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7221 (2) register list is not full, supposing there are N registers in
7222 register list (except PC, 0 <= N <= 7).
7223 Prepare: for each i, 0 - N, tmp[i] <- ri.
7225 POP {r0, r1, ...., rN};
7227 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7228 from tmp[] properly.
7230 if (debug_displaced
)
7231 fprintf_unfiltered (gdb_stdlog
,
7232 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7233 dsc
->u
.block
.regmask
, insn1
);
7235 if (dsc
->u
.block
.regmask
== 0xff)
7237 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7239 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7240 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7241 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7244 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7248 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7250 unsigned int new_regmask
;
7252 for (i
= 0; i
< num_in_list
+ 1; i
++)
7253 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7255 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7257 if (debug_displaced
)
7258 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7259 "{..., pc}: original reg list %.4x,"
7260 " modified list %.4x\n"),
7261 (int) dsc
->u
.block
.regmask
, new_regmask
);
7263 dsc
->u
.block
.regmask
|= 0x8000;
7264 dsc
->u
.block
.writeback
= 0;
7265 dsc
->u
.block
.cond
= INST_AL
;
7267 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7269 dsc
->cleanup
= &cleanup_block_load_pc
;
7276 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7277 struct regcache
*regs
,
7278 struct displaced_step_closure
*dsc
)
7280 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7281 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7284 /* 16-bit thumb instructions. */
7285 switch (op_bit_12_15
)
7287 /* Shift (imme), add, subtract, move and compare. */
7288 case 0: case 1: case 2: case 3:
7289 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7290 "shift/add/sub/mov/cmp",
7294 switch (op_bit_10_11
)
7296 case 0: /* Data-processing */
7297 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7301 case 1: /* Special data instructions and branch and exchange. */
7303 unsigned short op
= bits (insn1
, 7, 9);
7304 if (op
== 6 || op
== 7) /* BX or BLX */
7305 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7306 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7307 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7309 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7313 default: /* LDR (literal) */
7314 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7317 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7318 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7321 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7322 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7323 else /* Generate SP-relative address */
7324 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7326 case 11: /* Misc 16-bit instructions */
7328 switch (bits (insn1
, 8, 11))
7330 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7331 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7333 case 12: case 13: /* POP */
7334 if (bit (insn1
, 8)) /* PC is in register list. */
7335 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7337 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7339 case 15: /* If-Then, and hints */
7340 if (bits (insn1
, 0, 3))
7341 /* If-Then makes up to four following instructions conditional.
7342 IT instruction itself is not conditional, so handle it as a
7343 common unmodified instruction. */
7344 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7347 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7350 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7355 if (op_bit_10_11
< 2) /* Store multiple registers */
7356 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7357 else /* Load multiple registers */
7358 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7360 case 13: /* Conditional branch and supervisor call */
7361 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7362 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7364 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7366 case 14: /* Unconditional branch */
7367 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7374 internal_error (__FILE__
, __LINE__
,
7375 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7379 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7380 uint16_t insn1
, uint16_t insn2
,
7381 struct regcache
*regs
,
7382 struct displaced_step_closure
*dsc
)
7384 int rt
= bits (insn2
, 12, 15);
7385 int rn
= bits (insn1
, 0, 3);
7386 int op1
= bits (insn1
, 7, 8);
7388 switch (bits (insn1
, 5, 6))
7390 case 0: /* Load byte and memory hints */
7391 if (rt
== 0xf) /* PLD/PLI */
7394 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7395 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7397 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7402 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7403 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7406 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7407 "ldrb{reg, immediate}/ldrbt",
7412 case 1: /* Load halfword and memory hints. */
7413 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7414 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7415 "pld/unalloc memhint", dsc
);
7419 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7422 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7426 case 2: /* Load word */
7428 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7431 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7432 else if (op1
== 0x1) /* Encoding T3 */
7433 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7435 else /* op1 == 0x0 */
7437 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7438 /* LDR (immediate) */
7439 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7440 dsc
, bit (insn2
, 8), 1);
7441 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7442 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7445 /* LDR (register) */
7446 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7452 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7459 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7460 uint16_t insn2
, struct regcache
*regs
,
7461 struct displaced_step_closure
*dsc
)
7464 unsigned short op
= bit (insn2
, 15);
7465 unsigned int op1
= bits (insn1
, 11, 12);
7471 switch (bits (insn1
, 9, 10))
7476 /* Load/store {dual, execlusive}, table branch. */
7477 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7478 && bits (insn2
, 5, 7) == 0)
7479 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7482 /* PC is not allowed to use in load/store {dual, exclusive}
7484 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7485 "load/store dual/ex", dsc
);
7487 else /* load/store multiple */
7489 switch (bits (insn1
, 7, 8))
7491 case 0: case 3: /* SRS, RFE */
7492 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7495 case 1: case 2: /* LDM/STM/PUSH/POP */
7496 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7503 /* Data-processing (shift register). */
7504 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7507 default: /* Coprocessor instructions. */
7508 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7513 case 2: /* op1 = 2 */
7514 if (op
) /* Branch and misc control. */
7516 if (bit (insn2
, 14) /* BLX/BL */
7517 || bit (insn2
, 12) /* Unconditional branch */
7518 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7519 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7521 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7526 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7528 int op
= bits (insn1
, 4, 8);
7529 int rn
= bits (insn1
, 0, 3);
7530 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7531 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7534 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7537 else /* Data processing (modified immeidate) */
7538 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7542 case 3: /* op1 = 3 */
7543 switch (bits (insn1
, 9, 10))
7547 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7549 else /* NEON Load/Store and Store single data item */
7550 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7551 "neon elt/struct load/store",
7554 case 1: /* op1 = 3, bits (9, 10) == 1 */
7555 switch (bits (insn1
, 7, 8))
7557 case 0: case 1: /* Data processing (register) */
7558 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7561 case 2: /* Multiply and absolute difference */
7562 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7563 "mul/mua/diff", dsc
);
7565 case 3: /* Long multiply and divide */
7566 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7571 default: /* Coprocessor instructions */
7572 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7581 internal_error (__FILE__
, __LINE__
,
7582 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7587 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7588 struct regcache
*regs
,
7589 struct displaced_step_closure
*dsc
)
7591 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7593 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7595 if (debug_displaced
)
7596 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7597 "at %.8lx\n", insn1
, (unsigned long) from
);
7600 dsc
->insn_size
= thumb_insn_size (insn1
);
7601 if (thumb_insn_size (insn1
) == 4)
7604 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7605 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7608 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7612 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7613 CORE_ADDR to
, struct regcache
*regs
,
7614 struct displaced_step_closure
*dsc
)
7617 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7620 /* Most displaced instructions use a 1-instruction scratch space, so set this
7621 here and override below if/when necessary. */
7623 dsc
->insn_addr
= from
;
7624 dsc
->scratch_base
= to
;
7625 dsc
->cleanup
= NULL
;
7626 dsc
->wrote_to_pc
= 0;
7628 if (!displaced_in_arm_mode (regs
))
7629 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7633 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7634 if (debug_displaced
)
7635 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7636 "at %.8lx\n", (unsigned long) insn
,
7637 (unsigned long) from
);
7639 if ((insn
& 0xf0000000) == 0xf0000000)
7640 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7641 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7643 case 0x0: case 0x1: case 0x2: case 0x3:
7644 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7647 case 0x4: case 0x5: case 0x6:
7648 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7652 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7655 case 0x8: case 0x9: case 0xa: case 0xb:
7656 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7659 case 0xc: case 0xd: case 0xe: case 0xf:
7660 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7665 internal_error (__FILE__
, __LINE__
,
7666 _("arm_process_displaced_insn: Instruction decode error"));
7669 /* Actually set up the scratch space for a displaced instruction. */
7672 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7673 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7675 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7676 unsigned int i
, len
, offset
;
7677 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7678 int size
= dsc
->is_thumb
? 2 : 4;
7679 const gdb_byte
*bkp_insn
;
7682 /* Poke modified instruction(s). */
7683 for (i
= 0; i
< dsc
->numinsns
; i
++)
7685 if (debug_displaced
)
7687 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7689 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7692 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7693 (unsigned short)dsc
->modinsn
[i
]);
7695 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7696 (unsigned long) to
+ offset
);
7699 write_memory_unsigned_integer (to
+ offset
, size
,
7700 byte_order_for_code
,
7705 /* Choose the correct breakpoint instruction. */
7708 bkp_insn
= tdep
->thumb_breakpoint
;
7709 len
= tdep
->thumb_breakpoint_size
;
7713 bkp_insn
= tdep
->arm_breakpoint
;
7714 len
= tdep
->arm_breakpoint_size
;
7717 /* Put breakpoint afterwards. */
7718 write_memory (to
+ offset
, bkp_insn
, len
);
7720 if (debug_displaced
)
7721 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7722 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7725 /* Entry point for cleaning things up after a displaced instruction has been
7729 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7730 struct displaced_step_closure
*dsc
,
7731 CORE_ADDR from
, CORE_ADDR to
,
7732 struct regcache
*regs
)
7735 dsc
->cleanup (gdbarch
, regs
, dsc
);
7737 if (!dsc
->wrote_to_pc
)
7738 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7739 dsc
->insn_addr
+ dsc
->insn_size
);
7743 #include "bfd-in2.h"
7744 #include "libcoff.h"
7747 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7749 gdb_disassembler
*di
7750 = static_cast<gdb_disassembler
*>(info
->application_data
);
7751 struct gdbarch
*gdbarch
= di
->arch ();
7753 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7755 static asymbol
*asym
;
7756 static combined_entry_type ce
;
7757 static struct coff_symbol_struct csym
;
7758 static struct bfd fake_bfd
;
7759 static bfd_target fake_target
;
7761 if (csym
.native
== NULL
)
7763 /* Create a fake symbol vector containing a Thumb symbol.
7764 This is solely so that the code in print_insn_little_arm()
7765 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7766 the presence of a Thumb symbol and switch to decoding
7767 Thumb instructions. */
7769 fake_target
.flavour
= bfd_target_coff_flavour
;
7770 fake_bfd
.xvec
= &fake_target
;
7771 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7773 csym
.symbol
.the_bfd
= &fake_bfd
;
7774 csym
.symbol
.name
= "fake";
7775 asym
= (asymbol
*) & csym
;
7778 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7779 info
->symbols
= &asym
;
7782 info
->symbols
= NULL
;
7784 if (info
->endian
== BFD_ENDIAN_BIG
)
7785 return print_insn_big_arm (memaddr
, info
);
7787 return print_insn_little_arm (memaddr
, info
);
7790 /* The following define instruction sequences that will cause ARM
7791 cpu's to take an undefined instruction trap. These are used to
7792 signal a breakpoint to GDB.
7794 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7795 modes. A different instruction is required for each mode. The ARM
7796 cpu's can also be big or little endian. Thus four different
7797 instructions are needed to support all cases.
7799 Note: ARMv4 defines several new instructions that will take the
7800 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7801 not in fact add the new instructions. The new undefined
7802 instructions in ARMv4 are all instructions that had no defined
7803 behaviour in earlier chips. There is no guarantee that they will
7804 raise an exception, but may be treated as NOP's. In practice, it
7805 may only safe to rely on instructions matching:
7807 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7808 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7809 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7811 Even this may only true if the condition predicate is true. The
7812 following use a condition predicate of ALWAYS so it is always TRUE.
7814 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7815 and NetBSD all use a software interrupt rather than an undefined
7816 instruction to force a trap. This can be handled by by the
7817 abi-specific code during establishment of the gdbarch vector. */
7819 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7820 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7821 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7822 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7824 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7825 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7826 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7827 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7829 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7832 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7834 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7835 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7837 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7839 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7841 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7842 check whether we are replacing a 32-bit instruction. */
7843 if (tdep
->thumb2_breakpoint
!= NULL
)
7847 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7849 unsigned short inst1
;
7851 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7852 if (thumb_insn_size (inst1
) == 4)
7853 return ARM_BP_KIND_THUMB2
;
7857 return ARM_BP_KIND_THUMB
;
7860 return ARM_BP_KIND_ARM
;
7864 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7866 static const gdb_byte
*
7867 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7869 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7873 case ARM_BP_KIND_ARM
:
7874 *size
= tdep
->arm_breakpoint_size
;
7875 return tdep
->arm_breakpoint
;
7876 case ARM_BP_KIND_THUMB
:
7877 *size
= tdep
->thumb_breakpoint_size
;
7878 return tdep
->thumb_breakpoint
;
7879 case ARM_BP_KIND_THUMB2
:
7880 *size
= tdep
->thumb2_breakpoint_size
;
7881 return tdep
->thumb2_breakpoint
;
7883 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7887 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7890 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7891 struct regcache
*regcache
,
7896 /* Check the memory pointed by PC is readable. */
7897 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7899 struct arm_get_next_pcs next_pcs_ctx
;
7902 VEC (CORE_ADDR
) *next_pcs
= NULL
;
7903 struct cleanup
*old_chain
7904 = make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
7906 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7907 &arm_get_next_pcs_ops
,
7908 gdbarch_byte_order (gdbarch
),
7909 gdbarch_byte_order_for_code (gdbarch
),
7913 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7915 /* If MEMADDR is the next instruction of current pc, do the
7916 software single step computation, and get the thumb mode by
7917 the destination address. */
7918 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
7920 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7922 do_cleanups (old_chain
);
7924 if (IS_THUMB_ADDR (pc
))
7926 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7927 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7930 return ARM_BP_KIND_ARM
;
7934 do_cleanups (old_chain
);
7937 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7940 /* Extract from an array REGBUF containing the (raw) register state a
7941 function return value of type TYPE, and copy that, in virtual
7942 format, into VALBUF. */
7945 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7948 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7949 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7951 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7953 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7957 /* The value is in register F0 in internal format. We need to
7958 extract the raw value and then convert it to the desired
7960 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7962 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7963 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7964 valbuf
, gdbarch_byte_order (gdbarch
));
7968 case ARM_FLOAT_SOFT_FPA
:
7969 case ARM_FLOAT_SOFT_VFP
:
7970 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7971 not using the VFP ABI code. */
7973 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7974 if (TYPE_LENGTH (type
) > 4)
7975 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7976 valbuf
+ INT_REGISTER_SIZE
);
7980 internal_error (__FILE__
, __LINE__
,
7981 _("arm_extract_return_value: "
7982 "Floating point model not supported"));
7986 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7987 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7988 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7989 || TYPE_CODE (type
) == TYPE_CODE_PTR
7990 || TYPE_CODE (type
) == TYPE_CODE_REF
7991 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7993 /* If the type is a plain integer, then the access is
7994 straight-forward. Otherwise we have to play around a bit
7996 int len
= TYPE_LENGTH (type
);
7997 int regno
= ARM_A1_REGNUM
;
8002 /* By using store_unsigned_integer we avoid having to do
8003 anything special for small big-endian values. */
8004 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8005 store_unsigned_integer (valbuf
,
8006 (len
> INT_REGISTER_SIZE
8007 ? INT_REGISTER_SIZE
: len
),
8009 len
-= INT_REGISTER_SIZE
;
8010 valbuf
+= INT_REGISTER_SIZE
;
8015 /* For a structure or union the behaviour is as if the value had
8016 been stored to word-aligned memory and then loaded into
8017 registers with 32-bit load instruction(s). */
8018 int len
= TYPE_LENGTH (type
);
8019 int regno
= ARM_A1_REGNUM
;
8020 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8024 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8025 memcpy (valbuf
, tmpbuf
,
8026 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8027 len
-= INT_REGISTER_SIZE
;
8028 valbuf
+= INT_REGISTER_SIZE
;
8034 /* Will a function return an aggregate type in memory or in a
8035 register? Return 0 if an aggregate type can be returned in a
8036 register, 1 if it must be returned in memory. */
8039 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8041 enum type_code code
;
8043 type
= check_typedef (type
);
8045 /* Simple, non-aggregate types (ie not including vectors and
8046 complex) are always returned in a register (or registers). */
8047 code
= TYPE_CODE (type
);
8048 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8049 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8052 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
8054 /* Vector values should be returned using ARM registers if they
8055 are not over 16 bytes. */
8056 return (TYPE_LENGTH (type
) > 16);
8059 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8061 /* The AAPCS says all aggregates not larger than a word are returned
8063 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
8072 /* All aggregate types that won't fit in a register must be returned
8074 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8077 /* In the ARM ABI, "integer" like aggregate types are returned in
8078 registers. For an aggregate type to be integer like, its size
8079 must be less than or equal to INT_REGISTER_SIZE and the
8080 offset of each addressable subfield must be zero. Note that bit
8081 fields are not addressable, and all addressable subfields of
8082 unions always start at offset zero.
8084 This function is based on the behaviour of GCC 2.95.1.
8085 See: gcc/arm.c: arm_return_in_memory() for details.
8087 Note: All versions of GCC before GCC 2.95.2 do not set up the
8088 parameters correctly for a function returning the following
8089 structure: struct { float f;}; This should be returned in memory,
8090 not a register. Richard Earnshaw sent me a patch, but I do not
8091 know of any way to detect if a function like the above has been
8092 compiled with the correct calling convention. */
8094 /* Assume all other aggregate types can be returned in a register.
8095 Run a check for structures, unions and arrays. */
8098 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8101 /* Need to check if this struct/union is "integer" like. For
8102 this to be true, its size must be less than or equal to
8103 INT_REGISTER_SIZE and the offset of each addressable
8104 subfield must be zero. Note that bit fields are not
8105 addressable, and unions always start at offset zero. If any
8106 of the subfields is a floating point type, the struct/union
8107 cannot be an integer type. */
8109 /* For each field in the object, check:
8110 1) Is it FP? --> yes, nRc = 1;
8111 2) Is it addressable (bitpos != 0) and
8112 not packed (bitsize == 0)?
8116 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8118 enum type_code field_type_code
;
8121 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8124 /* Is it a floating point type field? */
8125 if (field_type_code
== TYPE_CODE_FLT
)
8131 /* If bitpos != 0, then we have to care about it. */
8132 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8134 /* Bitfields are not addressable. If the field bitsize is
8135 zero, then the field is not packed. Hence it cannot be
8136 a bitfield or any other packed type. */
8137 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8150 /* Write into appropriate registers a function return value of type
8151 TYPE, given in virtual format. */
8154 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8155 const gdb_byte
*valbuf
)
8157 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8158 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8160 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8162 gdb_byte buf
[MAX_REGISTER_SIZE
];
8164 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8168 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8169 gdbarch_byte_order (gdbarch
));
8170 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8173 case ARM_FLOAT_SOFT_FPA
:
8174 case ARM_FLOAT_SOFT_VFP
:
8175 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8176 not using the VFP ABI code. */
8178 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8179 if (TYPE_LENGTH (type
) > 4)
8180 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8181 valbuf
+ INT_REGISTER_SIZE
);
8185 internal_error (__FILE__
, __LINE__
,
8186 _("arm_store_return_value: Floating "
8187 "point model not supported"));
8191 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8192 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8193 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8194 || TYPE_CODE (type
) == TYPE_CODE_PTR
8195 || TYPE_CODE (type
) == TYPE_CODE_REF
8196 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8198 if (TYPE_LENGTH (type
) <= 4)
8200 /* Values of one word or less are zero/sign-extended and
8202 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8203 LONGEST val
= unpack_long (type
, valbuf
);
8205 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8206 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8210 /* Integral values greater than one word are stored in consecutive
8211 registers starting with r0. This will always be a multiple of
8212 the regiser size. */
8213 int len
= TYPE_LENGTH (type
);
8214 int regno
= ARM_A1_REGNUM
;
8218 regcache_cooked_write (regs
, regno
++, valbuf
);
8219 len
-= INT_REGISTER_SIZE
;
8220 valbuf
+= INT_REGISTER_SIZE
;
8226 /* For a structure or union the behaviour is as if the value had
8227 been stored to word-aligned memory and then loaded into
8228 registers with 32-bit load instruction(s). */
8229 int len
= TYPE_LENGTH (type
);
8230 int regno
= ARM_A1_REGNUM
;
8231 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8235 memcpy (tmpbuf
, valbuf
,
8236 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8237 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8238 len
-= INT_REGISTER_SIZE
;
8239 valbuf
+= INT_REGISTER_SIZE
;
8245 /* Handle function return values. */
8247 static enum return_value_convention
8248 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8249 struct type
*valtype
, struct regcache
*regcache
,
8250 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8252 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8253 struct type
*func_type
= function
? value_type (function
) : NULL
;
8254 enum arm_vfp_cprc_base_type vfp_base_type
;
8257 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8258 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8260 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8261 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8263 for (i
= 0; i
< vfp_base_count
; i
++)
8265 if (reg_char
== 'q')
8268 arm_neon_quad_write (gdbarch
, regcache
, i
,
8269 writebuf
+ i
* unit_length
);
8272 arm_neon_quad_read (gdbarch
, regcache
, i
,
8273 readbuf
+ i
* unit_length
);
8280 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8281 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8284 regcache_cooked_write (regcache
, regnum
,
8285 writebuf
+ i
* unit_length
);
8287 regcache_cooked_read (regcache
, regnum
,
8288 readbuf
+ i
* unit_length
);
8291 return RETURN_VALUE_REGISTER_CONVENTION
;
8294 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8295 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8296 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8298 if (tdep
->struct_return
== pcc_struct_return
8299 || arm_return_in_memory (gdbarch
, valtype
))
8300 return RETURN_VALUE_STRUCT_CONVENTION
;
8302 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8304 if (arm_return_in_memory (gdbarch
, valtype
))
8305 return RETURN_VALUE_STRUCT_CONVENTION
;
8309 arm_store_return_value (valtype
, regcache
, writebuf
);
8312 arm_extract_return_value (valtype
, regcache
, readbuf
);
8314 return RETURN_VALUE_REGISTER_CONVENTION
;
8319 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8321 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8322 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8323 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8325 gdb_byte buf
[INT_REGISTER_SIZE
];
8327 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8329 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8333 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8337 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8338 return the target PC. Otherwise return 0. */
8341 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8345 CORE_ADDR start_addr
;
8347 /* Find the starting address and name of the function containing the PC. */
8348 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8350 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8352 start_addr
= arm_skip_bx_reg (frame
, pc
);
8353 if (start_addr
!= 0)
8359 /* If PC is in a Thumb call or return stub, return the address of the
8360 target PC, which is in a register. The thunk functions are called
8361 _call_via_xx, where x is the register name. The possible names
8362 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8363 functions, named __ARM_call_via_r[0-7]. */
8364 if (startswith (name
, "_call_via_")
8365 || startswith (name
, "__ARM_call_via_"))
8367 /* Use the name suffix to determine which register contains the
8369 static char *table
[15] =
8370 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8371 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8374 int offset
= strlen (name
) - 2;
8376 for (regno
= 0; regno
<= 14; regno
++)
8377 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8378 return get_frame_register_unsigned (frame
, regno
);
8381 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8382 non-interworking calls to foo. We could decode the stubs
8383 to find the target but it's easier to use the symbol table. */
8384 namelen
= strlen (name
);
8385 if (name
[0] == '_' && name
[1] == '_'
8386 && ((namelen
> 2 + strlen ("_from_thumb")
8387 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8388 || (namelen
> 2 + strlen ("_from_arm")
8389 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8392 int target_len
= namelen
- 2;
8393 struct bound_minimal_symbol minsym
;
8394 struct objfile
*objfile
;
8395 struct obj_section
*sec
;
8397 if (name
[namelen
- 1] == 'b')
8398 target_len
-= strlen ("_from_thumb");
8400 target_len
-= strlen ("_from_arm");
8402 target_name
= (char *) alloca (target_len
+ 1);
8403 memcpy (target_name
, name
+ 2, target_len
);
8404 target_name
[target_len
] = '\0';
8406 sec
= find_pc_section (pc
);
8407 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8408 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8409 if (minsym
.minsym
!= NULL
)
8410 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8415 return 0; /* not a stub */
8419 set_arm_command (char *args
, int from_tty
)
8421 printf_unfiltered (_("\
8422 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8423 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8427 show_arm_command (char *args
, int from_tty
)
8429 cmd_show_list (showarmcmdlist
, from_tty
, "");
8433 arm_update_current_architecture (void)
8435 struct gdbarch_info info
;
8437 /* If the current architecture is not ARM, we have nothing to do. */
8438 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8441 /* Update the architecture. */
8442 gdbarch_info_init (&info
);
8444 if (!gdbarch_update_p (info
))
8445 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8449 set_fp_model_sfunc (char *args
, int from_tty
,
8450 struct cmd_list_element
*c
)
8454 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8455 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8457 arm_fp_model
= (enum arm_float_model
) fp_model
;
8461 if (fp_model
== ARM_FLOAT_LAST
)
8462 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8465 arm_update_current_architecture ();
8469 show_fp_model (struct ui_file
*file
, int from_tty
,
8470 struct cmd_list_element
*c
, const char *value
)
8472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8474 if (arm_fp_model
== ARM_FLOAT_AUTO
8475 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8476 fprintf_filtered (file
, _("\
8477 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8478 fp_model_strings
[tdep
->fp_model
]);
8480 fprintf_filtered (file
, _("\
8481 The current ARM floating point model is \"%s\".\n"),
8482 fp_model_strings
[arm_fp_model
]);
8486 arm_set_abi (char *args
, int from_tty
,
8487 struct cmd_list_element
*c
)
8491 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8492 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8494 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8498 if (arm_abi
== ARM_ABI_LAST
)
8499 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8502 arm_update_current_architecture ();
8506 arm_show_abi (struct ui_file
*file
, int from_tty
,
8507 struct cmd_list_element
*c
, const char *value
)
8509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8511 if (arm_abi_global
== ARM_ABI_AUTO
8512 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8513 fprintf_filtered (file
, _("\
8514 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8515 arm_abi_strings
[tdep
->arm_abi
]);
8517 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8522 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8523 struct cmd_list_element
*c
, const char *value
)
8525 fprintf_filtered (file
,
8526 _("The current execution mode assumed "
8527 "(when symbols are unavailable) is \"%s\".\n"),
8528 arm_fallback_mode_string
);
8532 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8533 struct cmd_list_element
*c
, const char *value
)
8535 fprintf_filtered (file
,
8536 _("The current execution mode assumed "
8537 "(even when symbols are available) is \"%s\".\n"),
8538 arm_force_mode_string
);
8541 /* If the user changes the register disassembly style used for info
8542 register and other commands, we have to also switch the style used
8543 in opcodes for disassembly output. This function is run in the "set
8544 arm disassembly" command, and does that. */
8547 set_disassembly_style_sfunc (char *args
, int from_tty
,
8548 struct cmd_list_element
*c
)
8550 /* Convert the short style name into the long style name (eg, reg-names-*)
8551 before calling the generic set_disassembler_options() function. */
8552 std::string long_name
= std::string ("reg-names-") + disassembly_style
;
8553 set_disassembler_options (&long_name
[0]);
8557 show_disassembly_style_sfunc (struct ui_file
*file
, int from_tty
,
8558 struct cmd_list_element
*c
, const char *value
)
8560 struct gdbarch
*gdbarch
= get_current_arch ();
8561 char *options
= get_disassembler_options (gdbarch
);
8562 const char *style
= "";
8566 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
8567 if (CONST_STRNEQ (opt
, "reg-names-"))
8569 style
= &opt
[strlen ("reg-names-")];
8570 len
= strcspn (style
, ",");
8573 fprintf_unfiltered (file
, "The disassembly style is \"%.*s\".\n", len
, style
);
8576 /* Return the ARM register name corresponding to register I. */
8578 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8580 const int num_regs
= gdbarch_num_regs (gdbarch
);
8582 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8583 && i
>= num_regs
&& i
< num_regs
+ 32)
8585 static const char *const vfp_pseudo_names
[] = {
8586 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8587 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8588 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8589 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8592 return vfp_pseudo_names
[i
- num_regs
];
8595 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8596 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8598 static const char *const neon_pseudo_names
[] = {
8599 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8600 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8603 return neon_pseudo_names
[i
- num_regs
- 32];
8606 if (i
>= ARRAY_SIZE (arm_register_names
))
8607 /* These registers are only supported on targets which supply
8608 an XML description. */
8611 return arm_register_names
[i
];
8614 /* Test whether the coff symbol specific value corresponds to a Thumb
8618 coff_sym_is_thumb (int val
)
8620 return (val
== C_THUMBEXT
8621 || val
== C_THUMBSTAT
8622 || val
== C_THUMBEXTFUNC
8623 || val
== C_THUMBSTATFUNC
8624 || val
== C_THUMBLABEL
);
8627 /* arm_coff_make_msymbol_special()
8628 arm_elf_make_msymbol_special()
8630 These functions test whether the COFF or ELF symbol corresponds to
8631 an address in thumb code, and set a "special" bit in a minimal
8632 symbol to indicate that it does. */
8635 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8637 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8639 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8640 == ST_BRANCH_TO_THUMB
)
8641 MSYMBOL_SET_SPECIAL (msym
);
8645 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8647 if (coff_sym_is_thumb (val
))
8648 MSYMBOL_SET_SPECIAL (msym
);
8652 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8654 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8657 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8658 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8662 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8665 const char *name
= bfd_asymbol_name (sym
);
8666 struct arm_per_objfile
*data
;
8667 VEC(arm_mapping_symbol_s
) **map_p
;
8668 struct arm_mapping_symbol new_map_sym
;
8670 gdb_assert (name
[0] == '$');
8671 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8674 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8675 arm_objfile_data_key
);
8678 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8679 struct arm_per_objfile
);
8680 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8681 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8682 objfile
->obfd
->section_count
,
8683 VEC(arm_mapping_symbol_s
) *);
8685 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8687 new_map_sym
.value
= sym
->value
;
8688 new_map_sym
.type
= name
[1];
8690 /* Assume that most mapping symbols appear in order of increasing
8691 value. If they were randomly distributed, it would be faster to
8692 always push here and then sort at first use. */
8693 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8695 struct arm_mapping_symbol
*prev_map_sym
;
8697 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8698 if (prev_map_sym
->value
>= sym
->value
)
8701 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8702 arm_compare_mapping_symbols
);
8703 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8708 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8712 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8714 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8715 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8717 /* If necessary, set the T bit. */
8720 ULONGEST val
, t_bit
;
8721 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8722 t_bit
= arm_psr_thumb_bit (gdbarch
);
8723 if (arm_pc_is_thumb (gdbarch
, pc
))
8724 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8727 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8732 /* Read the contents of a NEON quad register, by reading from two
8733 double registers. This is used to implement the quad pseudo
8734 registers, and for argument passing in case the quad registers are
8735 missing; vectors are passed in quad registers when using the VFP
8736 ABI, even if a NEON unit is not present. REGNUM is the index of
8737 the quad register, in [0, 15]. */
8739 static enum register_status
8740 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8741 int regnum
, gdb_byte
*buf
)
8744 gdb_byte reg_buf
[8];
8745 int offset
, double_regnum
;
8746 enum register_status status
;
8748 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8749 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8752 /* d0 is always the least significant half of q0. */
8753 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8758 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8759 if (status
!= REG_VALID
)
8761 memcpy (buf
+ offset
, reg_buf
, 8);
8763 offset
= 8 - offset
;
8764 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8765 if (status
!= REG_VALID
)
8767 memcpy (buf
+ offset
, reg_buf
, 8);
8772 static enum register_status
8773 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8774 int regnum
, gdb_byte
*buf
)
8776 const int num_regs
= gdbarch_num_regs (gdbarch
);
8778 gdb_byte reg_buf
[8];
8779 int offset
, double_regnum
;
8781 gdb_assert (regnum
>= num_regs
);
8784 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8785 /* Quad-precision register. */
8786 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8789 enum register_status status
;
8791 /* Single-precision register. */
8792 gdb_assert (regnum
< 32);
8794 /* s0 is always the least significant half of d0. */
8795 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8796 offset
= (regnum
& 1) ? 0 : 4;
8798 offset
= (regnum
& 1) ? 4 : 0;
8800 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8801 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8804 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8805 if (status
== REG_VALID
)
8806 memcpy (buf
, reg_buf
+ offset
, 4);
8811 /* Store the contents of BUF to a NEON quad register, by writing to
8812 two double registers. This is used to implement the quad pseudo
8813 registers, and for argument passing in case the quad registers are
8814 missing; vectors are passed in quad registers when using the VFP
8815 ABI, even if a NEON unit is not present. REGNUM is the index
8816 of the quad register, in [0, 15]. */
8819 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8820 int regnum
, const gdb_byte
*buf
)
8823 int offset
, double_regnum
;
8825 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8826 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8829 /* d0 is always the least significant half of q0. */
8830 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8835 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8836 offset
= 8 - offset
;
8837 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8841 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8842 int regnum
, const gdb_byte
*buf
)
8844 const int num_regs
= gdbarch_num_regs (gdbarch
);
8846 gdb_byte reg_buf
[8];
8847 int offset
, double_regnum
;
8849 gdb_assert (regnum
>= num_regs
);
8852 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8853 /* Quad-precision register. */
8854 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8857 /* Single-precision register. */
8858 gdb_assert (regnum
< 32);
8860 /* s0 is always the least significant half of d0. */
8861 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8862 offset
= (regnum
& 1) ? 0 : 4;
8864 offset
= (regnum
& 1) ? 4 : 0;
8866 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8867 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8870 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8871 memcpy (reg_buf
+ offset
, buf
, 4);
8872 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8876 static struct value
*
8877 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8879 const int *reg_p
= (const int *) baton
;
8880 return value_of_register (*reg_p
, frame
);
8883 static enum gdb_osabi
8884 arm_elf_osabi_sniffer (bfd
*abfd
)
8886 unsigned int elfosabi
;
8887 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8889 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8891 if (elfosabi
== ELFOSABI_ARM
)
8892 /* GNU tools use this value. Check note sections in this case,
8894 bfd_map_over_sections (abfd
,
8895 generic_elf_osabi_sniff_abi_tag_sections
,
8898 /* Anything else will be handled by the generic ELF sniffer. */
8903 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8904 struct reggroup
*group
)
8906 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8907 this, FPS register belongs to save_regroup, restore_reggroup, and
8908 all_reggroup, of course. */
8909 if (regnum
== ARM_FPS_REGNUM
)
8910 return (group
== float_reggroup
8911 || group
== save_reggroup
8912 || group
== restore_reggroup
8913 || group
== all_reggroup
);
8915 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8919 /* For backward-compatibility we allow two 'g' packet lengths with
8920 the remote protocol depending on whether FPA registers are
8921 supplied. M-profile targets do not have FPA registers, but some
8922 stubs already exist in the wild which use a 'g' packet which
8923 supplies them albeit with dummy values. The packet format which
8924 includes FPA registers should be considered deprecated for
8925 M-profile targets. */
8928 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8930 if (gdbarch_tdep (gdbarch
)->is_m
)
8932 /* If we know from the executable this is an M-profile target,
8933 cater for remote targets whose register set layout is the
8934 same as the FPA layout. */
8935 register_remote_g_packet_guess (gdbarch
,
8936 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8937 (16 * INT_REGISTER_SIZE
)
8938 + (8 * FP_REGISTER_SIZE
)
8939 + (2 * INT_REGISTER_SIZE
),
8940 tdesc_arm_with_m_fpa_layout
);
8942 /* The regular M-profile layout. */
8943 register_remote_g_packet_guess (gdbarch
,
8944 /* r0-r12,sp,lr,pc; xpsr */
8945 (16 * INT_REGISTER_SIZE
)
8946 + INT_REGISTER_SIZE
,
8949 /* M-profile plus M4F VFP. */
8950 register_remote_g_packet_guess (gdbarch
,
8951 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8952 (16 * INT_REGISTER_SIZE
)
8953 + (16 * VFP_REGISTER_SIZE
)
8954 + (2 * INT_REGISTER_SIZE
),
8955 tdesc_arm_with_m_vfp_d16
);
8958 /* Otherwise we don't have a useful guess. */
8961 /* Implement the code_of_frame_writable gdbarch method. */
8964 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8966 if (gdbarch_tdep (gdbarch
)->is_m
8967 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8969 /* M-profile exception frames return to some magic PCs, where
8970 isn't writable at all. */
8978 /* Initialize the current architecture based on INFO. If possible,
8979 re-use an architecture from ARCHES, which is a list of
8980 architectures already created during this debugging session.
8982 Called e.g. at program startup, when reading a core file, and when
8983 reading a binary file. */
8985 static struct gdbarch
*
8986 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8988 struct gdbarch_tdep
*tdep
;
8989 struct gdbarch
*gdbarch
;
8990 struct gdbarch_list
*best_arch
;
8991 enum arm_abi_kind arm_abi
= arm_abi_global
;
8992 enum arm_float_model fp_model
= arm_fp_model
;
8993 struct tdesc_arch_data
*tdesc_data
= NULL
;
8995 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8996 int have_wmmx_registers
= 0;
8998 int have_fpa_registers
= 1;
8999 const struct target_desc
*tdesc
= info
.target_desc
;
9001 /* If we have an object to base this architecture on, try to determine
9004 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9006 int ei_osabi
, e_flags
;
9008 switch (bfd_get_flavour (info
.abfd
))
9010 case bfd_target_coff_flavour
:
9011 /* Assume it's an old APCS-style ABI. */
9013 arm_abi
= ARM_ABI_APCS
;
9016 case bfd_target_elf_flavour
:
9017 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9018 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9020 if (ei_osabi
== ELFOSABI_ARM
)
9022 /* GNU tools used to use this value, but do not for EABI
9023 objects. There's nowhere to tag an EABI version
9024 anyway, so assume APCS. */
9025 arm_abi
= ARM_ABI_APCS
;
9027 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9029 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9030 int attr_arch
, attr_profile
;
9034 case EF_ARM_EABI_UNKNOWN
:
9035 /* Assume GNU tools. */
9036 arm_abi
= ARM_ABI_APCS
;
9039 case EF_ARM_EABI_VER4
:
9040 case EF_ARM_EABI_VER5
:
9041 arm_abi
= ARM_ABI_AAPCS
;
9042 /* EABI binaries default to VFP float ordering.
9043 They may also contain build attributes that can
9044 be used to identify if the VFP argument-passing
9046 if (fp_model
== ARM_FLOAT_AUTO
)
9049 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9053 case AEABI_VFP_args_base
:
9054 /* "The user intended FP parameter/result
9055 passing to conform to AAPCS, base
9057 fp_model
= ARM_FLOAT_SOFT_VFP
;
9059 case AEABI_VFP_args_vfp
:
9060 /* "The user intended FP parameter/result
9061 passing to conform to AAPCS, VFP
9063 fp_model
= ARM_FLOAT_VFP
;
9065 case AEABI_VFP_args_toolchain
:
9066 /* "The user intended FP parameter/result
9067 passing to conform to tool chain-specific
9068 conventions" - we don't know any such
9069 conventions, so leave it as "auto". */
9071 case AEABI_VFP_args_compatible
:
9072 /* "Code is compatible with both the base
9073 and VFP variants; the user did not permit
9074 non-variadic functions to pass FP
9075 parameters/results" - leave it as
9079 /* Attribute value not mentioned in the
9080 November 2012 ABI, so leave it as
9085 fp_model
= ARM_FLOAT_SOFT_VFP
;
9091 /* Leave it as "auto". */
9092 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9097 /* Detect M-profile programs. This only works if the
9098 executable file includes build attributes; GCC does
9099 copy them to the executable, but e.g. RealView does
9101 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9103 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9105 Tag_CPU_arch_profile
);
9106 /* GCC specifies the profile for v6-M; RealView only
9107 specifies the profile for architectures starting with
9108 V7 (as opposed to architectures with a tag
9109 numerically greater than TAG_CPU_ARCH_V7). */
9110 if (!tdesc_has_registers (tdesc
)
9111 && (attr_arch
== TAG_CPU_ARCH_V6_M
9112 || attr_arch
== TAG_CPU_ARCH_V6S_M
9113 || attr_profile
== 'M'))
9118 if (fp_model
== ARM_FLOAT_AUTO
)
9120 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9122 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9125 /* Leave it as "auto". Strictly speaking this case
9126 means FPA, but almost nobody uses that now, and
9127 many toolchains fail to set the appropriate bits
9128 for the floating-point model they use. */
9130 case EF_ARM_SOFT_FLOAT
:
9131 fp_model
= ARM_FLOAT_SOFT_FPA
;
9133 case EF_ARM_VFP_FLOAT
:
9134 fp_model
= ARM_FLOAT_VFP
;
9136 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9137 fp_model
= ARM_FLOAT_SOFT_VFP
;
9142 if (e_flags
& EF_ARM_BE8
)
9143 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9148 /* Leave it as "auto". */
9153 /* Check any target description for validity. */
9154 if (tdesc_has_registers (tdesc
))
9156 /* For most registers we require GDB's default names; but also allow
9157 the numeric names for sp / lr / pc, as a convenience. */
9158 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9159 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9160 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9162 const struct tdesc_feature
*feature
;
9165 feature
= tdesc_find_feature (tdesc
,
9166 "org.gnu.gdb.arm.core");
9167 if (feature
== NULL
)
9169 feature
= tdesc_find_feature (tdesc
,
9170 "org.gnu.gdb.arm.m-profile");
9171 if (feature
== NULL
)
9177 tdesc_data
= tdesc_data_alloc ();
9180 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9181 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9182 arm_register_names
[i
]);
9183 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9186 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9189 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9193 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9194 ARM_PS_REGNUM
, "xpsr");
9196 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9197 ARM_PS_REGNUM
, "cpsr");
9201 tdesc_data_cleanup (tdesc_data
);
9205 feature
= tdesc_find_feature (tdesc
,
9206 "org.gnu.gdb.arm.fpa");
9207 if (feature
!= NULL
)
9210 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9211 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9212 arm_register_names
[i
]);
9215 tdesc_data_cleanup (tdesc_data
);
9220 have_fpa_registers
= 0;
9222 feature
= tdesc_find_feature (tdesc
,
9223 "org.gnu.gdb.xscale.iwmmxt");
9224 if (feature
!= NULL
)
9226 static const char *const iwmmxt_names
[] = {
9227 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9228 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9229 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9230 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9234 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9236 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9237 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9239 /* Check for the control registers, but do not fail if they
9241 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9242 tdesc_numbered_register (feature
, tdesc_data
, i
,
9243 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9245 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9247 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9248 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9252 tdesc_data_cleanup (tdesc_data
);
9256 have_wmmx_registers
= 1;
9259 /* If we have a VFP unit, check whether the single precision registers
9260 are present. If not, then we will synthesize them as pseudo
9262 feature
= tdesc_find_feature (tdesc
,
9263 "org.gnu.gdb.arm.vfp");
9264 if (feature
!= NULL
)
9266 static const char *const vfp_double_names
[] = {
9267 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9268 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9269 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9270 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9273 /* Require the double precision registers. There must be either
9276 for (i
= 0; i
< 32; i
++)
9278 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9280 vfp_double_names
[i
]);
9284 if (!valid_p
&& i
== 16)
9287 /* Also require FPSCR. */
9288 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9289 ARM_FPSCR_REGNUM
, "fpscr");
9292 tdesc_data_cleanup (tdesc_data
);
9296 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9297 have_vfp_pseudos
= 1;
9299 vfp_register_count
= i
;
9301 /* If we have VFP, also check for NEON. The architecture allows
9302 NEON without VFP (integer vector operations only), but GDB
9303 does not support that. */
9304 feature
= tdesc_find_feature (tdesc
,
9305 "org.gnu.gdb.arm.neon");
9306 if (feature
!= NULL
)
9308 /* NEON requires 32 double-precision registers. */
9311 tdesc_data_cleanup (tdesc_data
);
9315 /* If there are quad registers defined by the stub, use
9316 their type; otherwise (normally) provide them with
9317 the default type. */
9318 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9319 have_neon_pseudos
= 1;
9326 /* If there is already a candidate, use it. */
9327 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9329 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9331 if (arm_abi
!= ARM_ABI_AUTO
9332 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9335 if (fp_model
!= ARM_FLOAT_AUTO
9336 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9339 /* There are various other properties in tdep that we do not
9340 need to check here: those derived from a target description,
9341 since gdbarches with a different target description are
9342 automatically disqualified. */
9344 /* Do check is_m, though, since it might come from the binary. */
9345 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9348 /* Found a match. */
9352 if (best_arch
!= NULL
)
9354 if (tdesc_data
!= NULL
)
9355 tdesc_data_cleanup (tdesc_data
);
9356 return best_arch
->gdbarch
;
9359 tdep
= XCNEW (struct gdbarch_tdep
);
9360 gdbarch
= gdbarch_alloc (&info
, tdep
);
9362 /* Record additional information about the architecture we are defining.
9363 These are gdbarch discriminators, like the OSABI. */
9364 tdep
->arm_abi
= arm_abi
;
9365 tdep
->fp_model
= fp_model
;
9367 tdep
->have_fpa_registers
= have_fpa_registers
;
9368 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9369 gdb_assert (vfp_register_count
== 0
9370 || vfp_register_count
== 16
9371 || vfp_register_count
== 32);
9372 tdep
->vfp_register_count
= vfp_register_count
;
9373 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9374 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9375 tdep
->have_neon
= have_neon
;
9377 arm_register_g_packet_guesses (gdbarch
);
9380 switch (info
.byte_order_for_code
)
9382 case BFD_ENDIAN_BIG
:
9383 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9384 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9385 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9386 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9390 case BFD_ENDIAN_LITTLE
:
9391 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9392 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9393 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9394 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9399 internal_error (__FILE__
, __LINE__
,
9400 _("arm_gdbarch_init: bad byte order for float format"));
9403 /* On ARM targets char defaults to unsigned. */
9404 set_gdbarch_char_signed (gdbarch
, 0);
9406 /* Note: for displaced stepping, this includes the breakpoint, and one word
9407 of additional scratch space. This setting isn't used for anything beside
9408 displaced stepping at present. */
9409 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9411 /* This should be low enough for everything. */
9412 tdep
->lowest_pc
= 0x20;
9413 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9415 /* The default, for both APCS and AAPCS, is to return small
9416 structures in registers. */
9417 tdep
->struct_return
= reg_struct_return
;
9419 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9420 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9423 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9425 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9427 /* Frame handling. */
9428 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9429 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9430 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9432 frame_base_set_default (gdbarch
, &arm_normal_base
);
9434 /* Address manipulation. */
9435 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9437 /* Advance PC across function entry code. */
9438 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9440 /* Detect whether PC is at a point where the stack has been destroyed. */
9441 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9443 /* Skip trampolines. */
9444 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9446 /* The stack grows downward. */
9447 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9449 /* Breakpoint manipulation. */
9450 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
9451 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
9452 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9453 arm_breakpoint_kind_from_current_state
);
9455 /* Information about registers, etc. */
9456 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9457 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9458 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9459 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9460 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9462 /* This "info float" is FPA-specific. Use the generic version if we
9464 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9465 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9467 /* Internal <-> external register number maps. */
9468 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9469 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9471 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9473 /* Returning results. */
9474 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9477 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9479 /* Minsymbol frobbing. */
9480 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9481 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9482 arm_coff_make_msymbol_special
);
9483 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9485 /* Thumb-2 IT block support. */
9486 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9487 arm_adjust_breakpoint_address
);
9489 /* Virtual tables. */
9490 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9492 /* Hook in the ABI-specific overrides, if they have been registered. */
9493 gdbarch_init_osabi (info
, gdbarch
);
9495 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9497 /* Add some default predicates. */
9499 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9500 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9501 dwarf2_append_unwinders (gdbarch
);
9502 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9503 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9504 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9506 /* Now we have tuned the configuration, set a few final things,
9507 based on what the OS ABI has told us. */
9509 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9510 binaries are always marked. */
9511 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9512 tdep
->arm_abi
= ARM_ABI_APCS
;
9514 /* Watchpoints are not steppable. */
9515 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9517 /* We used to default to FPA for generic ARM, but almost nobody
9518 uses that now, and we now provide a way for the user to force
9519 the model. So default to the most useful variant. */
9520 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9521 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9523 if (tdep
->jb_pc
>= 0)
9524 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9526 /* Floating point sizes and format. */
9527 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9528 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9530 set_gdbarch_double_format
9531 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9532 set_gdbarch_long_double_format
9533 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9537 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9538 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9541 if (have_vfp_pseudos
)
9543 /* NOTE: These are the only pseudo registers used by
9544 the ARM target at the moment. If more are added, a
9545 little more care in numbering will be needed. */
9547 int num_pseudos
= 32;
9548 if (have_neon_pseudos
)
9550 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9551 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9552 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9557 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9559 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9561 /* Override tdesc_register_type to adjust the types of VFP
9562 registers for NEON. */
9563 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9566 /* Add standard register aliases. We add aliases even for those
9567 nanes which are used by the current architecture - it's simpler,
9568 and does no harm, since nothing ever lists user registers. */
9569 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9570 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9571 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9573 set_gdbarch_disassembler_options (gdbarch
, &arm_disassembler_options
);
9574 set_gdbarch_valid_disassembler_options (gdbarch
, disassembler_options_arm ());
9580 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9582 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9587 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9588 (unsigned long) tdep
->lowest_pc
);
9593 static void arm_record_test (void);
9596 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9599 _initialize_arm_tdep (void)
9602 const char *setname
;
9603 const char *setdesc
;
9605 char regdesc
[1024], *rdptr
= regdesc
;
9606 size_t rest
= sizeof (regdesc
);
9608 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9610 arm_objfile_data_key
9611 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9613 /* Add ourselves to objfile event chain. */
9614 observer_attach_new_objfile (arm_exidx_new_objfile
);
9616 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9618 /* Register an ELF OS ABI sniffer for ARM binaries. */
9619 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9620 bfd_target_elf_flavour
,
9621 arm_elf_osabi_sniffer
);
9623 /* Initialize the standard target descriptions. */
9624 initialize_tdesc_arm_with_m ();
9625 initialize_tdesc_arm_with_m_fpa_layout ();
9626 initialize_tdesc_arm_with_m_vfp_d16 ();
9627 initialize_tdesc_arm_with_iwmmxt ();
9628 initialize_tdesc_arm_with_vfpv2 ();
9629 initialize_tdesc_arm_with_vfpv3 ();
9630 initialize_tdesc_arm_with_neon ();
9632 /* Add root prefix command for all "set arm"/"show arm" commands. */
9633 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9634 _("Various ARM-specific commands."),
9635 &setarmcmdlist
, "set arm ", 0, &setlist
);
9637 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9638 _("Various ARM-specific commands."),
9639 &showarmcmdlist
, "show arm ", 0, &showlist
);
9642 arm_disassembler_options
= xstrdup ("reg-names-std");
9643 const disasm_options_t
*disasm_options
= disassembler_options_arm ();
9644 int num_disassembly_styles
= 0;
9645 for (i
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9646 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9647 num_disassembly_styles
++;
9649 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
9650 valid_disassembly_styles
= XNEWVEC (const char *,
9651 num_disassembly_styles
+ 1);
9652 for (i
= j
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9653 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9655 size_t offset
= strlen ("reg-names-");
9656 const char *style
= disasm_options
->name
[i
];
9657 valid_disassembly_styles
[j
++] = &style
[offset
];
9658 length
= snprintf (rdptr
, rest
, "%s - %s\n", &style
[offset
],
9659 disasm_options
->description
[i
]);
9663 /* Mark the end of valid options. */
9664 valid_disassembly_styles
[num_disassembly_styles
] = NULL
;
9666 /* Create the help text. */
9667 std::string helptext
= string_printf ("%s%s%s",
9668 _("The valid values are:\n"),
9670 _("The default is \"std\"."));
9672 add_setshow_enum_cmd("disassembler", no_class
,
9673 valid_disassembly_styles
, &disassembly_style
,
9674 _("Set the disassembly style."),
9675 _("Show the disassembly style."),
9677 set_disassembly_style_sfunc
,
9678 show_disassembly_style_sfunc
,
9679 &setarmcmdlist
, &showarmcmdlist
);
9681 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9682 _("Set usage of ARM 32-bit mode."),
9683 _("Show usage of ARM 32-bit mode."),
9684 _("When off, a 26-bit PC will be used."),
9686 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9688 &setarmcmdlist
, &showarmcmdlist
);
9690 /* Add a command to allow the user to force the FPU model. */
9691 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9692 _("Set the floating point type."),
9693 _("Show the floating point type."),
9694 _("auto - Determine the FP typefrom the OS-ABI.\n\
9695 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9696 fpa - FPA co-processor (GCC compiled).\n\
9697 softvfp - Software FP with pure-endian doubles.\n\
9698 vfp - VFP co-processor."),
9699 set_fp_model_sfunc
, show_fp_model
,
9700 &setarmcmdlist
, &showarmcmdlist
);
9702 /* Add a command to allow the user to force the ABI. */
9703 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9706 NULL
, arm_set_abi
, arm_show_abi
,
9707 &setarmcmdlist
, &showarmcmdlist
);
9709 /* Add two commands to allow the user to force the assumed
9711 add_setshow_enum_cmd ("fallback-mode", class_support
,
9712 arm_mode_strings
, &arm_fallback_mode_string
,
9713 _("Set the mode assumed when symbols are unavailable."),
9714 _("Show the mode assumed when symbols are unavailable."),
9715 NULL
, NULL
, arm_show_fallback_mode
,
9716 &setarmcmdlist
, &showarmcmdlist
);
9717 add_setshow_enum_cmd ("force-mode", class_support
,
9718 arm_mode_strings
, &arm_force_mode_string
,
9719 _("Set the mode assumed even when symbols are available."),
9720 _("Show the mode assumed even when symbols are available."),
9721 NULL
, NULL
, arm_show_force_mode
,
9722 &setarmcmdlist
, &showarmcmdlist
);
9724 /* Debugging flag. */
9725 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9726 _("Set ARM debugging."),
9727 _("Show ARM debugging."),
9728 _("When on, arm-specific debugging is enabled."),
9730 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9731 &setdebuglist
, &showdebuglist
);
9734 register_self_test (selftests::arm_record_test
);
9739 /* ARM-reversible process record data structures. */
9741 #define ARM_INSN_SIZE_BYTES 4
9742 #define THUMB_INSN_SIZE_BYTES 2
9743 #define THUMB2_INSN_SIZE_BYTES 4
9746 /* Position of the bit within a 32-bit ARM instruction
9747 that defines whether the instruction is a load or store. */
9748 #define INSN_S_L_BIT_NUM 20
9750 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9753 unsigned int reg_len = LENGTH; \
9756 REGS = XNEWVEC (uint32_t, reg_len); \
9757 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9762 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9765 unsigned int mem_len = LENGTH; \
9768 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9769 memcpy(&MEMS->len, &RECORD_BUF[0], \
9770 sizeof(struct arm_mem_r) * LENGTH); \
9775 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9776 #define INSN_RECORDED(ARM_RECORD) \
9777 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9779 /* ARM memory record structure. */
9782 uint32_t len
; /* Record length. */
9783 uint32_t addr
; /* Memory address. */
9786 /* ARM instruction record contains opcode of current insn
9787 and execution state (before entry to decode_insn()),
9788 contains list of to-be-modified registers and
9789 memory blocks (on return from decode_insn()). */
9791 typedef struct insn_decode_record_t
9793 struct gdbarch
*gdbarch
;
9794 struct regcache
*regcache
;
9795 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9796 uint32_t arm_insn
; /* Should accommodate thumb. */
9797 uint32_t cond
; /* Condition code. */
9798 uint32_t opcode
; /* Insn opcode. */
9799 uint32_t decode
; /* Insn decode bits. */
9800 uint32_t mem_rec_count
; /* No of mem records. */
9801 uint32_t reg_rec_count
; /* No of reg records. */
9802 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9803 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9804 } insn_decode_record
;
9807 /* Checks ARM SBZ and SBO mandatory fields. */
9810 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9812 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9831 enum arm_record_result
9833 ARM_RECORD_SUCCESS
= 0,
9834 ARM_RECORD_FAILURE
= 1
9841 } arm_record_strx_t
;
9852 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9853 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9856 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9857 ULONGEST u_regval
[2]= {0};
9859 uint32_t reg_src1
= 0, reg_src2
= 0;
9860 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9862 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9863 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9865 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9867 /* 1) Handle misc store, immediate offset. */
9868 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9869 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9870 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9871 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9873 if (ARM_PC_REGNUM
== reg_src1
)
9875 /* If R15 was used as Rn, hence current PC+8. */
9876 u_regval
[0] = u_regval
[0] + 8;
9878 offset_8
= (immed_high
<< 4) | immed_low
;
9879 /* Calculate target store address. */
9880 if (14 == arm_insn_r
->opcode
)
9882 tgt_mem_addr
= u_regval
[0] + offset_8
;
9886 tgt_mem_addr
= u_regval
[0] - offset_8
;
9888 if (ARM_RECORD_STRH
== str_type
)
9890 record_buf_mem
[0] = 2;
9891 record_buf_mem
[1] = tgt_mem_addr
;
9892 arm_insn_r
->mem_rec_count
= 1;
9894 else if (ARM_RECORD_STRD
== str_type
)
9896 record_buf_mem
[0] = 4;
9897 record_buf_mem
[1] = tgt_mem_addr
;
9898 record_buf_mem
[2] = 4;
9899 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9900 arm_insn_r
->mem_rec_count
= 2;
9903 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9905 /* 2) Store, register offset. */
9907 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9909 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9910 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9911 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9914 /* If R15 was used as Rn, hence current PC+8. */
9915 u_regval
[0] = u_regval
[0] + 8;
9917 /* Calculate target store address, Rn +/- Rm, register offset. */
9918 if (12 == arm_insn_r
->opcode
)
9920 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9924 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9926 if (ARM_RECORD_STRH
== str_type
)
9928 record_buf_mem
[0] = 2;
9929 record_buf_mem
[1] = tgt_mem_addr
;
9930 arm_insn_r
->mem_rec_count
= 1;
9932 else if (ARM_RECORD_STRD
== str_type
)
9934 record_buf_mem
[0] = 4;
9935 record_buf_mem
[1] = tgt_mem_addr
;
9936 record_buf_mem
[2] = 4;
9937 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9938 arm_insn_r
->mem_rec_count
= 2;
9941 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9942 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9944 /* 3) Store, immediate pre-indexed. */
9945 /* 5) Store, immediate post-indexed. */
9946 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9947 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9948 offset_8
= (immed_high
<< 4) | immed_low
;
9949 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9950 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9951 /* Calculate target store address, Rn +/- Rm, register offset. */
9952 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9954 tgt_mem_addr
= u_regval
[0] + offset_8
;
9958 tgt_mem_addr
= u_regval
[0] - offset_8
;
9960 if (ARM_RECORD_STRH
== str_type
)
9962 record_buf_mem
[0] = 2;
9963 record_buf_mem
[1] = tgt_mem_addr
;
9964 arm_insn_r
->mem_rec_count
= 1;
9966 else if (ARM_RECORD_STRD
== str_type
)
9968 record_buf_mem
[0] = 4;
9969 record_buf_mem
[1] = tgt_mem_addr
;
9970 record_buf_mem
[2] = 4;
9971 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9972 arm_insn_r
->mem_rec_count
= 2;
9974 /* Record Rn also as it changes. */
9975 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9976 arm_insn_r
->reg_rec_count
= 1;
9978 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9979 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9981 /* 4) Store, register pre-indexed. */
9982 /* 6) Store, register post -indexed. */
9983 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9984 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9985 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9986 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9987 /* Calculate target store address, Rn +/- Rm, register offset. */
9988 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9990 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9994 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9996 if (ARM_RECORD_STRH
== str_type
)
9998 record_buf_mem
[0] = 2;
9999 record_buf_mem
[1] = tgt_mem_addr
;
10000 arm_insn_r
->mem_rec_count
= 1;
10002 else if (ARM_RECORD_STRD
== str_type
)
10004 record_buf_mem
[0] = 4;
10005 record_buf_mem
[1] = tgt_mem_addr
;
10006 record_buf_mem
[2] = 4;
10007 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10008 arm_insn_r
->mem_rec_count
= 2;
10010 /* Record Rn also as it changes. */
10011 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10012 arm_insn_r
->reg_rec_count
= 1;
10017 /* Handling ARM extension space insns. */
10020 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10022 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10023 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10024 uint32_t record_buf
[8], record_buf_mem
[8];
10025 uint32_t reg_src1
= 0;
10026 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10027 ULONGEST u_regval
= 0;
10029 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10030 /* Handle unconditional insn extension space. */
10032 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10033 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10034 if (arm_insn_r
->cond
)
10036 /* PLD has no affect on architectural state, it just affects
10038 if (5 == ((opcode1
& 0xE0) >> 5))
10041 record_buf
[0] = ARM_PS_REGNUM
;
10042 record_buf
[1] = ARM_LR_REGNUM
;
10043 arm_insn_r
->reg_rec_count
= 2;
10045 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10049 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10050 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10053 /* Undefined instruction on ARM V5; need to handle if later
10054 versions define it. */
10057 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10058 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10059 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10061 /* Handle arithmetic insn extension space. */
10062 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10063 && !INSN_RECORDED(arm_insn_r
))
10065 /* Handle MLA(S) and MUL(S). */
10066 if (0 <= insn_op1
&& 3 >= insn_op1
)
10068 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10069 record_buf
[1] = ARM_PS_REGNUM
;
10070 arm_insn_r
->reg_rec_count
= 2;
10072 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10074 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10075 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10076 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10077 record_buf
[2] = ARM_PS_REGNUM
;
10078 arm_insn_r
->reg_rec_count
= 3;
10082 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10083 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10084 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10086 /* Handle control insn extension space. */
10088 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10089 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10091 if (!bit (arm_insn_r
->arm_insn
,25))
10093 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10095 if ((0 == insn_op1
) || (2 == insn_op1
))
10098 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10099 arm_insn_r
->reg_rec_count
= 1;
10101 else if (1 == insn_op1
)
10103 /* CSPR is going to be changed. */
10104 record_buf
[0] = ARM_PS_REGNUM
;
10105 arm_insn_r
->reg_rec_count
= 1;
10107 else if (3 == insn_op1
)
10109 /* SPSR is going to be changed. */
10110 /* We need to get SPSR value, which is yet to be done. */
10114 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10119 record_buf
[0] = ARM_PS_REGNUM
;
10120 arm_insn_r
->reg_rec_count
= 1;
10122 else if (3 == insn_op1
)
10125 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10126 arm_insn_r
->reg_rec_count
= 1;
10129 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10132 record_buf
[0] = ARM_PS_REGNUM
;
10133 record_buf
[1] = ARM_LR_REGNUM
;
10134 arm_insn_r
->reg_rec_count
= 2;
10136 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10138 /* QADD, QSUB, QDADD, QDSUB */
10139 record_buf
[0] = ARM_PS_REGNUM
;
10140 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10141 arm_insn_r
->reg_rec_count
= 2;
10143 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10146 record_buf
[0] = ARM_PS_REGNUM
;
10147 record_buf
[1] = ARM_LR_REGNUM
;
10148 arm_insn_r
->reg_rec_count
= 2;
10150 /* Save SPSR also;how? */
10153 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10154 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10155 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10156 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10159 if (0 == insn_op1
|| 1 == insn_op1
)
10161 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10162 /* We dont do optimization for SMULW<y> where we
10164 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10165 record_buf
[1] = ARM_PS_REGNUM
;
10166 arm_insn_r
->reg_rec_count
= 2;
10168 else if (2 == insn_op1
)
10171 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10172 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10173 arm_insn_r
->reg_rec_count
= 2;
10175 else if (3 == insn_op1
)
10178 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10179 arm_insn_r
->reg_rec_count
= 1;
10185 /* MSR : immediate form. */
10188 /* CSPR is going to be changed. */
10189 record_buf
[0] = ARM_PS_REGNUM
;
10190 arm_insn_r
->reg_rec_count
= 1;
10192 else if (3 == insn_op1
)
10194 /* SPSR is going to be changed. */
10195 /* we need to get SPSR value, which is yet to be done */
10201 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10202 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10203 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10205 /* Handle load/store insn extension space. */
10207 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10208 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10209 && !INSN_RECORDED(arm_insn_r
))
10214 /* These insn, changes register and memory as well. */
10215 /* SWP or SWPB insn. */
10216 /* Get memory address given by Rn. */
10217 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10218 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10219 /* SWP insn ?, swaps word. */
10220 if (8 == arm_insn_r
->opcode
)
10222 record_buf_mem
[0] = 4;
10226 /* SWPB insn, swaps only byte. */
10227 record_buf_mem
[0] = 1;
10229 record_buf_mem
[1] = u_regval
;
10230 arm_insn_r
->mem_rec_count
= 1;
10231 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10232 arm_insn_r
->reg_rec_count
= 1;
10234 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10237 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10240 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10243 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10244 record_buf
[1] = record_buf
[0] + 1;
10245 arm_insn_r
->reg_rec_count
= 2;
10247 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10250 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10253 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10255 /* LDRH, LDRSB, LDRSH. */
10256 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10257 arm_insn_r
->reg_rec_count
= 1;
10262 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10263 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10264 && !INSN_RECORDED(arm_insn_r
))
10267 /* Handle coprocessor insn extension space. */
10270 /* To be done for ARMv5 and later; as of now we return -1. */
10274 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10275 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10280 /* Handling opcode 000 insns. */
10283 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10285 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10286 uint32_t record_buf
[8], record_buf_mem
[8];
10287 ULONGEST u_regval
[2] = {0};
10289 uint32_t reg_src1
= 0, reg_dest
= 0;
10290 uint32_t opcode1
= 0;
10292 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10293 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10294 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10296 /* Data processing insn /multiply insn. */
10297 if (9 == arm_insn_r
->decode
10298 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10299 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10301 /* Handle multiply instructions. */
10302 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10303 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10305 /* Handle MLA and MUL. */
10306 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10307 record_buf
[1] = ARM_PS_REGNUM
;
10308 arm_insn_r
->reg_rec_count
= 2;
10310 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10312 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10313 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10314 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10315 record_buf
[2] = ARM_PS_REGNUM
;
10316 arm_insn_r
->reg_rec_count
= 3;
10319 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10320 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10322 /* Handle misc load insns, as 20th bit (L = 1). */
10323 /* LDR insn has a capability to do branching, if
10324 MOV LR, PC is precceded by LDR insn having Rn as R15
10325 in that case, it emulates branch and link insn, and hence we
10326 need to save CSPR and PC as well. I am not sure this is right
10327 place; as opcode = 010 LDR insn make this happen, if R15 was
10329 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10330 if (15 != reg_dest
)
10332 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10333 arm_insn_r
->reg_rec_count
= 1;
10337 record_buf
[0] = reg_dest
;
10338 record_buf
[1] = ARM_PS_REGNUM
;
10339 arm_insn_r
->reg_rec_count
= 2;
10342 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10343 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10344 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10345 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10347 /* Handle MSR insn. */
10348 if (9 == arm_insn_r
->opcode
)
10350 /* CSPR is going to be changed. */
10351 record_buf
[0] = ARM_PS_REGNUM
;
10352 arm_insn_r
->reg_rec_count
= 1;
10356 /* SPSR is going to be changed. */
10357 /* How to read SPSR value? */
10361 else if (9 == arm_insn_r
->decode
10362 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10363 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10365 /* Handling SWP, SWPB. */
10366 /* These insn, changes register and memory as well. */
10367 /* SWP or SWPB insn. */
10369 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10370 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10371 /* SWP insn ?, swaps word. */
10372 if (8 == arm_insn_r
->opcode
)
10374 record_buf_mem
[0] = 4;
10378 /* SWPB insn, swaps only byte. */
10379 record_buf_mem
[0] = 1;
10381 record_buf_mem
[1] = u_regval
[0];
10382 arm_insn_r
->mem_rec_count
= 1;
10383 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10384 arm_insn_r
->reg_rec_count
= 1;
10386 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10387 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10389 /* Handle BLX, branch and link/exchange. */
10390 if (9 == arm_insn_r
->opcode
)
10392 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10393 and R14 stores the return address. */
10394 record_buf
[0] = ARM_PS_REGNUM
;
10395 record_buf
[1] = ARM_LR_REGNUM
;
10396 arm_insn_r
->reg_rec_count
= 2;
10399 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10401 /* Handle enhanced software breakpoint insn, BKPT. */
10402 /* CPSR is changed to be executed in ARM state, disabling normal
10403 interrupts, entering abort mode. */
10404 /* According to high vector configuration PC is set. */
10405 /* user hit breakpoint and type reverse, in
10406 that case, we need to go back with previous CPSR and
10407 Program Counter. */
10408 record_buf
[0] = ARM_PS_REGNUM
;
10409 record_buf
[1] = ARM_LR_REGNUM
;
10410 arm_insn_r
->reg_rec_count
= 2;
10412 /* Save SPSR also; how? */
10415 else if (11 == arm_insn_r
->decode
10416 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10418 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10420 /* Handle str(x) insn */
10421 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10424 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10425 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10427 /* Handle BX, branch and link/exchange. */
10428 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10429 record_buf
[0] = ARM_PS_REGNUM
;
10430 arm_insn_r
->reg_rec_count
= 1;
10432 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10433 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10434 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10436 /* Count leading zeros: CLZ. */
10437 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10438 arm_insn_r
->reg_rec_count
= 1;
10440 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10441 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10442 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10443 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10446 /* Handle MRS insn. */
10447 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10448 arm_insn_r
->reg_rec_count
= 1;
10450 else if (arm_insn_r
->opcode
<= 15)
10452 /* Normal data processing insns. */
10453 /* Out of 11 shifter operands mode, all the insn modifies destination
10454 register, which is specified by 13-16 decode. */
10455 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10456 record_buf
[1] = ARM_PS_REGNUM
;
10457 arm_insn_r
->reg_rec_count
= 2;
10464 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10465 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10469 /* Handling opcode 001 insns. */
10472 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10474 uint32_t record_buf
[8], record_buf_mem
[8];
10476 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10477 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10479 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10480 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10481 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10484 /* Handle MSR insn. */
10485 if (9 == arm_insn_r
->opcode
)
10487 /* CSPR is going to be changed. */
10488 record_buf
[0] = ARM_PS_REGNUM
;
10489 arm_insn_r
->reg_rec_count
= 1;
10493 /* SPSR is going to be changed. */
10496 else if (arm_insn_r
->opcode
<= 15)
10498 /* Normal data processing insns. */
10499 /* Out of 11 shifter operands mode, all the insn modifies destination
10500 register, which is specified by 13-16 decode. */
10501 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10502 record_buf
[1] = ARM_PS_REGNUM
;
10503 arm_insn_r
->reg_rec_count
= 2;
10510 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10511 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10516 arm_record_media (insn_decode_record
*arm_insn_r
)
10518 uint32_t record_buf
[8];
10520 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10523 /* Parallel addition and subtraction, signed */
10525 /* Parallel addition and subtraction, unsigned */
10528 /* Packing, unpacking, saturation and reversal */
10530 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10532 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10538 /* Signed multiplies */
10540 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10541 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10543 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10545 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10546 else if (op1
== 0x4)
10547 record_buf
[arm_insn_r
->reg_rec_count
++]
10548 = bits (arm_insn_r
->arm_insn
, 12, 15);
10554 if (bit (arm_insn_r
->arm_insn
, 21)
10555 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10558 record_buf
[arm_insn_r
->reg_rec_count
++]
10559 = bits (arm_insn_r
->arm_insn
, 12, 15);
10561 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10562 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10564 /* USAD8 and USADA8 */
10565 record_buf
[arm_insn_r
->reg_rec_count
++]
10566 = bits (arm_insn_r
->arm_insn
, 16, 19);
10573 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10574 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10576 /* Permanently UNDEFINED */
10581 /* BFC, BFI and UBFX */
10582 record_buf
[arm_insn_r
->reg_rec_count
++]
10583 = bits (arm_insn_r
->arm_insn
, 12, 15);
10592 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10597 /* Handle ARM mode instructions with opcode 010. */
10600 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10602 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10604 uint32_t reg_base
, reg_dest
;
10605 uint32_t offset_12
, tgt_mem_addr
;
10606 uint32_t record_buf
[8], record_buf_mem
[8];
10607 unsigned char wback
;
10610 /* Calculate wback. */
10611 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10612 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10614 arm_insn_r
->reg_rec_count
= 0;
10615 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10617 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10619 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10622 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10623 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10625 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10626 preceeds a LDR instruction having R15 as reg_base, it
10627 emulates a branch and link instruction, and hence we need to save
10628 CPSR and PC as well. */
10629 if (ARM_PC_REGNUM
== reg_dest
)
10630 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10632 /* If wback is true, also save the base register, which is going to be
10635 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10639 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10641 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10642 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10644 /* Handle bit U. */
10645 if (bit (arm_insn_r
->arm_insn
, 23))
10647 /* U == 1: Add the offset. */
10648 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10652 /* U == 0: subtract the offset. */
10653 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10656 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10658 if (bit (arm_insn_r
->arm_insn
, 22))
10660 /* STRB and STRBT: 1 byte. */
10661 record_buf_mem
[0] = 1;
10665 /* STR and STRT: 4 bytes. */
10666 record_buf_mem
[0] = 4;
10669 /* Handle bit P. */
10670 if (bit (arm_insn_r
->arm_insn
, 24))
10671 record_buf_mem
[1] = tgt_mem_addr
;
10673 record_buf_mem
[1] = (uint32_t) u_regval
;
10675 arm_insn_r
->mem_rec_count
= 1;
10677 /* If wback is true, also save the base register, which is going to be
10680 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10683 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10684 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10688 /* Handling opcode 011 insns. */
10691 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10693 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10695 uint32_t shift_imm
= 0;
10696 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10697 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10698 uint32_t record_buf
[8], record_buf_mem
[8];
10701 ULONGEST u_regval
[2];
10703 if (bit (arm_insn_r
->arm_insn
, 4))
10704 return arm_record_media (arm_insn_r
);
10706 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10707 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10709 /* Handle enhanced store insns and LDRD DSP insn,
10710 order begins according to addressing modes for store insns
10714 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10716 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10717 /* LDR insn has a capability to do branching, if
10718 MOV LR, PC is precedded by LDR insn having Rn as R15
10719 in that case, it emulates branch and link insn, and hence we
10720 need to save CSPR and PC as well. */
10721 if (15 != reg_dest
)
10723 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10724 arm_insn_r
->reg_rec_count
= 1;
10728 record_buf
[0] = reg_dest
;
10729 record_buf
[1] = ARM_PS_REGNUM
;
10730 arm_insn_r
->reg_rec_count
= 2;
10735 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10737 /* Store insn, register offset and register pre-indexed,
10738 register post-indexed. */
10740 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10742 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10743 regcache_raw_read_unsigned (reg_cache
, reg_src1
10745 regcache_raw_read_unsigned (reg_cache
, reg_src2
10747 if (15 == reg_src2
)
10749 /* If R15 was used as Rn, hence current PC+8. */
10750 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10751 u_regval
[0] = u_regval
[0] + 8;
10753 /* Calculate target store address, Rn +/- Rm, register offset. */
10755 if (bit (arm_insn_r
->arm_insn
, 23))
10757 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10761 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10764 switch (arm_insn_r
->opcode
)
10778 record_buf_mem
[0] = 4;
10793 record_buf_mem
[0] = 1;
10797 gdb_assert_not_reached ("no decoding pattern found");
10800 record_buf_mem
[1] = tgt_mem_addr
;
10801 arm_insn_r
->mem_rec_count
= 1;
10803 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10804 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10805 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10806 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10807 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10808 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10811 /* Rn is going to be changed in pre-indexed mode and
10812 post-indexed mode as well. */
10813 record_buf
[0] = reg_src2
;
10814 arm_insn_r
->reg_rec_count
= 1;
10819 /* Store insn, scaled register offset; scaled pre-indexed. */
10820 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10822 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10824 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10825 /* Get shift_imm. */
10826 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10827 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10828 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10829 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10830 /* Offset_12 used as shift. */
10834 /* Offset_12 used as index. */
10835 offset_12
= u_regval
[0] << shift_imm
;
10839 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10845 if (bit (u_regval
[0], 31))
10847 offset_12
= 0xFFFFFFFF;
10856 /* This is arithmetic shift. */
10857 offset_12
= s_word
>> shift_imm
;
10864 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10866 /* Get C flag value and shift it by 31. */
10867 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10868 | (u_regval
[0]) >> 1);
10872 offset_12
= (u_regval
[0] >> shift_imm
) \
10874 (sizeof(uint32_t) - shift_imm
));
10879 gdb_assert_not_reached ("no decoding pattern found");
10883 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10885 if (bit (arm_insn_r
->arm_insn
, 23))
10887 tgt_mem_addr
= u_regval
[1] + offset_12
;
10891 tgt_mem_addr
= u_regval
[1] - offset_12
;
10894 switch (arm_insn_r
->opcode
)
10908 record_buf_mem
[0] = 4;
10923 record_buf_mem
[0] = 1;
10927 gdb_assert_not_reached ("no decoding pattern found");
10930 record_buf_mem
[1] = tgt_mem_addr
;
10931 arm_insn_r
->mem_rec_count
= 1;
10933 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10934 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10935 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10936 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10937 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10938 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10941 /* Rn is going to be changed in register scaled pre-indexed
10942 mode,and scaled post indexed mode. */
10943 record_buf
[0] = reg_src2
;
10944 arm_insn_r
->reg_rec_count
= 1;
10949 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10950 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10954 /* Handle ARM mode instructions with opcode 100. */
10957 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10959 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10960 uint32_t register_count
= 0, register_bits
;
10961 uint32_t reg_base
, addr_mode
;
10962 uint32_t record_buf
[24], record_buf_mem
[48];
10966 /* Fetch the list of registers. */
10967 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10968 arm_insn_r
->reg_rec_count
= 0;
10970 /* Fetch the base register that contains the address we are loading data
10972 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10974 /* Calculate wback. */
10975 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10977 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10979 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10981 /* Find out which registers are going to be loaded from memory. */
10982 while (register_bits
)
10984 if (register_bits
& 0x00000001)
10985 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10986 register_bits
= register_bits
>> 1;
10991 /* If wback is true, also save the base register, which is going to be
10994 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10996 /* Save the CPSR register. */
10997 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11001 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11003 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11005 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11007 /* Find out how many registers are going to be stored to memory. */
11008 while (register_bits
)
11010 if (register_bits
& 0x00000001)
11012 register_bits
= register_bits
>> 1;
11017 /* STMDA (STMED): Decrement after. */
11019 record_buf_mem
[1] = (uint32_t) u_regval
11020 - register_count
* INT_REGISTER_SIZE
+ 4;
11022 /* STM (STMIA, STMEA): Increment after. */
11024 record_buf_mem
[1] = (uint32_t) u_regval
;
11026 /* STMDB (STMFD): Decrement before. */
11028 record_buf_mem
[1] = (uint32_t) u_regval
11029 - register_count
* INT_REGISTER_SIZE
;
11031 /* STMIB (STMFA): Increment before. */
11033 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11036 gdb_assert_not_reached ("no decoding pattern found");
11040 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11041 arm_insn_r
->mem_rec_count
= 1;
11043 /* If wback is true, also save the base register, which is going to be
11046 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11049 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11050 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11054 /* Handling opcode 101 insns. */
11057 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11059 uint32_t record_buf
[8];
11061 /* Handle B, BL, BLX(1) insns. */
11062 /* B simply branches so we do nothing here. */
11063 /* Note: BLX(1) doesnt fall here but instead it falls into
11064 extension space. */
11065 if (bit (arm_insn_r
->arm_insn
, 24))
11067 record_buf
[0] = ARM_LR_REGNUM
;
11068 arm_insn_r
->reg_rec_count
= 1;
11071 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11077 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11079 printf_unfiltered (_("Process record does not support instruction "
11080 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11081 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11086 /* Record handler for vector data transfer instructions. */
11089 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11091 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11092 uint32_t record_buf
[4];
11094 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11095 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11096 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11097 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11098 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11100 /* Handle VMOV instruction. */
11101 if (bit_l
&& bit_c
)
11103 record_buf
[0] = reg_t
;
11104 arm_insn_r
->reg_rec_count
= 1;
11106 else if (bit_l
&& !bit_c
)
11108 /* Handle VMOV instruction. */
11109 if (bits_a
== 0x00)
11111 record_buf
[0] = reg_t
;
11112 arm_insn_r
->reg_rec_count
= 1;
11114 /* Handle VMRS instruction. */
11115 else if (bits_a
== 0x07)
11118 reg_t
= ARM_PS_REGNUM
;
11120 record_buf
[0] = reg_t
;
11121 arm_insn_r
->reg_rec_count
= 1;
11124 else if (!bit_l
&& !bit_c
)
11126 /* Handle VMOV instruction. */
11127 if (bits_a
== 0x00)
11129 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11131 arm_insn_r
->reg_rec_count
= 1;
11133 /* Handle VMSR instruction. */
11134 else if (bits_a
== 0x07)
11136 record_buf
[0] = ARM_FPSCR_REGNUM
;
11137 arm_insn_r
->reg_rec_count
= 1;
11140 else if (!bit_l
&& bit_c
)
11142 /* Handle VMOV instruction. */
11143 if (!(bits_a
& 0x04))
11145 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11147 arm_insn_r
->reg_rec_count
= 1;
11149 /* Handle VDUP instruction. */
11152 if (bit (arm_insn_r
->arm_insn
, 21))
11154 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11155 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11156 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11157 arm_insn_r
->reg_rec_count
= 2;
11161 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11162 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11163 arm_insn_r
->reg_rec_count
= 1;
11168 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11172 /* Record handler for extension register load/store instructions. */
11175 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11177 uint32_t opcode
, single_reg
;
11178 uint8_t op_vldm_vstm
;
11179 uint32_t record_buf
[8], record_buf_mem
[128];
11180 ULONGEST u_regval
= 0;
11182 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11184 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11185 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11186 op_vldm_vstm
= opcode
& 0x1b;
11188 /* Handle VMOV instructions. */
11189 if ((opcode
& 0x1e) == 0x04)
11191 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11193 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11194 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11195 arm_insn_r
->reg_rec_count
= 2;
11199 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11200 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11204 /* The first S register number m is REG_M:M (M is bit 5),
11205 the corresponding D register number is REG_M:M / 2, which
11207 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11208 /* The second S register number is REG_M:M + 1, the
11209 corresponding D register number is (REG_M:M + 1) / 2.
11210 IOW, if bit M is 1, the first and second S registers
11211 are mapped to different D registers, otherwise, they are
11212 in the same D register. */
11215 record_buf
[arm_insn_r
->reg_rec_count
++]
11216 = ARM_D0_REGNUM
+ reg_m
+ 1;
11221 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11222 arm_insn_r
->reg_rec_count
= 1;
11226 /* Handle VSTM and VPUSH instructions. */
11227 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11228 || op_vldm_vstm
== 0x12)
11230 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11231 uint32_t memory_index
= 0;
11233 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11234 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11235 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11236 imm_off32
= imm_off8
<< 2;
11237 memory_count
= imm_off8
;
11239 if (bit (arm_insn_r
->arm_insn
, 23))
11240 start_address
= u_regval
;
11242 start_address
= u_regval
- imm_off32
;
11244 if (bit (arm_insn_r
->arm_insn
, 21))
11246 record_buf
[0] = reg_rn
;
11247 arm_insn_r
->reg_rec_count
= 1;
11250 while (memory_count
> 0)
11254 record_buf_mem
[memory_index
] = 4;
11255 record_buf_mem
[memory_index
+ 1] = start_address
;
11256 start_address
= start_address
+ 4;
11257 memory_index
= memory_index
+ 2;
11261 record_buf_mem
[memory_index
] = 4;
11262 record_buf_mem
[memory_index
+ 1] = start_address
;
11263 record_buf_mem
[memory_index
+ 2] = 4;
11264 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11265 start_address
= start_address
+ 8;
11266 memory_index
= memory_index
+ 4;
11270 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11272 /* Handle VLDM instructions. */
11273 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11274 || op_vldm_vstm
== 0x13)
11276 uint32_t reg_count
, reg_vd
;
11277 uint32_t reg_index
= 0;
11278 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11280 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11281 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11283 /* REG_VD is the first D register number. If the instruction
11284 loads memory to S registers (SINGLE_REG is TRUE), the register
11285 number is (REG_VD << 1 | bit D), so the corresponding D
11286 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11288 reg_vd
= reg_vd
| (bit_d
<< 4);
11290 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11291 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11293 /* If the instruction loads memory to D register, REG_COUNT should
11294 be divided by 2, according to the ARM Architecture Reference
11295 Manual. If the instruction loads memory to S register, divide by
11296 2 as well because two S registers are mapped to D register. */
11297 reg_count
= reg_count
/ 2;
11298 if (single_reg
&& bit_d
)
11300 /* Increase the register count if S register list starts from
11301 an odd number (bit d is one). */
11305 while (reg_count
> 0)
11307 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11310 arm_insn_r
->reg_rec_count
= reg_index
;
11312 /* VSTR Vector store register. */
11313 else if ((opcode
& 0x13) == 0x10)
11315 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11316 uint32_t memory_index
= 0;
11318 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11319 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11320 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11321 imm_off32
= imm_off8
<< 2;
11323 if (bit (arm_insn_r
->arm_insn
, 23))
11324 start_address
= u_regval
+ imm_off32
;
11326 start_address
= u_regval
- imm_off32
;
11330 record_buf_mem
[memory_index
] = 4;
11331 record_buf_mem
[memory_index
+ 1] = start_address
;
11332 arm_insn_r
->mem_rec_count
= 1;
11336 record_buf_mem
[memory_index
] = 4;
11337 record_buf_mem
[memory_index
+ 1] = start_address
;
11338 record_buf_mem
[memory_index
+ 2] = 4;
11339 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11340 arm_insn_r
->mem_rec_count
= 2;
11343 /* VLDR Vector load register. */
11344 else if ((opcode
& 0x13) == 0x11)
11346 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11350 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11351 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11355 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11356 /* Record register D rather than pseudo register S. */
11357 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11359 arm_insn_r
->reg_rec_count
= 1;
11362 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11363 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11367 /* Record handler for arm/thumb mode VFP data processing instructions. */
11370 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11372 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11373 uint32_t record_buf
[4];
11374 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11375 enum insn_types curr_insn_type
= INSN_INV
;
11377 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11378 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11379 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11380 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11381 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11382 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11383 opc1
= opc1
& 0x04;
11385 /* Handle VMLA, VMLS. */
11388 if (bit (arm_insn_r
->arm_insn
, 10))
11390 if (bit (arm_insn_r
->arm_insn
, 6))
11391 curr_insn_type
= INSN_T0
;
11393 curr_insn_type
= INSN_T1
;
11398 curr_insn_type
= INSN_T1
;
11400 curr_insn_type
= INSN_T2
;
11403 /* Handle VNMLA, VNMLS, VNMUL. */
11404 else if (opc1
== 0x01)
11407 curr_insn_type
= INSN_T1
;
11409 curr_insn_type
= INSN_T2
;
11412 else if (opc1
== 0x02 && !(opc3
& 0x01))
11414 if (bit (arm_insn_r
->arm_insn
, 10))
11416 if (bit (arm_insn_r
->arm_insn
, 6))
11417 curr_insn_type
= INSN_T0
;
11419 curr_insn_type
= INSN_T1
;
11424 curr_insn_type
= INSN_T1
;
11426 curr_insn_type
= INSN_T2
;
11429 /* Handle VADD, VSUB. */
11430 else if (opc1
== 0x03)
11432 if (!bit (arm_insn_r
->arm_insn
, 9))
11434 if (bit (arm_insn_r
->arm_insn
, 6))
11435 curr_insn_type
= INSN_T0
;
11437 curr_insn_type
= INSN_T1
;
11442 curr_insn_type
= INSN_T1
;
11444 curr_insn_type
= INSN_T2
;
11448 else if (opc1
== 0x0b)
11451 curr_insn_type
= INSN_T1
;
11453 curr_insn_type
= INSN_T2
;
11455 /* Handle all other vfp data processing instructions. */
11456 else if (opc1
== 0x0b)
11459 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11461 if (bit (arm_insn_r
->arm_insn
, 4))
11463 if (bit (arm_insn_r
->arm_insn
, 6))
11464 curr_insn_type
= INSN_T0
;
11466 curr_insn_type
= INSN_T1
;
11471 curr_insn_type
= INSN_T1
;
11473 curr_insn_type
= INSN_T2
;
11476 /* Handle VNEG and VABS. */
11477 else if ((opc2
== 0x01 && opc3
== 0x01)
11478 || (opc2
== 0x00 && opc3
== 0x03))
11480 if (!bit (arm_insn_r
->arm_insn
, 11))
11482 if (bit (arm_insn_r
->arm_insn
, 6))
11483 curr_insn_type
= INSN_T0
;
11485 curr_insn_type
= INSN_T1
;
11490 curr_insn_type
= INSN_T1
;
11492 curr_insn_type
= INSN_T2
;
11495 /* Handle VSQRT. */
11496 else if (opc2
== 0x01 && opc3
== 0x03)
11499 curr_insn_type
= INSN_T1
;
11501 curr_insn_type
= INSN_T2
;
11504 else if (opc2
== 0x07 && opc3
== 0x03)
11507 curr_insn_type
= INSN_T1
;
11509 curr_insn_type
= INSN_T2
;
11511 else if (opc3
& 0x01)
11514 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11516 if (!bit (arm_insn_r
->arm_insn
, 18))
11517 curr_insn_type
= INSN_T2
;
11521 curr_insn_type
= INSN_T1
;
11523 curr_insn_type
= INSN_T2
;
11527 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11530 curr_insn_type
= INSN_T1
;
11532 curr_insn_type
= INSN_T2
;
11534 /* Handle VCVTB, VCVTT. */
11535 else if ((opc2
& 0x0e) == 0x02)
11536 curr_insn_type
= INSN_T2
;
11537 /* Handle VCMP, VCMPE. */
11538 else if ((opc2
& 0x0e) == 0x04)
11539 curr_insn_type
= INSN_T3
;
11543 switch (curr_insn_type
)
11546 reg_vd
= reg_vd
| (bit_d
<< 4);
11547 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11548 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11549 arm_insn_r
->reg_rec_count
= 2;
11553 reg_vd
= reg_vd
| (bit_d
<< 4);
11554 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11555 arm_insn_r
->reg_rec_count
= 1;
11559 reg_vd
= (reg_vd
<< 1) | bit_d
;
11560 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11561 arm_insn_r
->reg_rec_count
= 1;
11565 record_buf
[0] = ARM_FPSCR_REGNUM
;
11566 arm_insn_r
->reg_rec_count
= 1;
11570 gdb_assert_not_reached ("no decoding pattern found");
11574 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11578 /* Handling opcode 110 insns. */
11581 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11583 uint32_t op1
, op1_ebit
, coproc
;
11585 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11586 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11587 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11589 if ((coproc
& 0x0e) == 0x0a)
11591 /* Handle extension register ld/st instructions. */
11593 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11595 /* 64-bit transfers between arm core and extension registers. */
11596 if ((op1
& 0x3e) == 0x04)
11597 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11601 /* Handle coprocessor ld/st instructions. */
11606 return arm_record_unsupported_insn (arm_insn_r
);
11609 return arm_record_unsupported_insn (arm_insn_r
);
11612 /* Move to coprocessor from two arm core registers. */
11614 return arm_record_unsupported_insn (arm_insn_r
);
11616 /* Move to two arm core registers from coprocessor. */
11621 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11622 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11623 arm_insn_r
->reg_rec_count
= 2;
11625 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11629 return arm_record_unsupported_insn (arm_insn_r
);
11632 /* Handling opcode 111 insns. */
11635 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11637 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11638 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11639 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11641 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11642 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11643 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11644 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11645 op
= bit (arm_insn_r
->arm_insn
, 4);
11647 /* Handle arm SWI/SVC system call instructions. */
11650 if (tdep
->arm_syscall_record
!= NULL
)
11652 ULONGEST svc_operand
, svc_number
;
11654 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11656 if (svc_operand
) /* OABI. */
11657 svc_number
= svc_operand
- 0x900000;
11659 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11661 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11665 printf_unfiltered (_("no syscall record support\n"));
11670 if ((coproc
& 0x0e) == 0x0a)
11672 /* VFP data-processing instructions. */
11673 if (!op1_sbit
&& !op
)
11674 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11676 /* Advanced SIMD, VFP instructions. */
11677 if (!op1_sbit
&& op
)
11678 return arm_record_vdata_transfer_insn (arm_insn_r
);
11682 /* Coprocessor data operations. */
11683 if (!op1_sbit
&& !op
)
11684 return arm_record_unsupported_insn (arm_insn_r
);
11686 /* Move to Coprocessor from ARM core register. */
11687 if (!op1_sbit
&& !op1_ebit
&& op
)
11688 return arm_record_unsupported_insn (arm_insn_r
);
11690 /* Move to arm core register from coprocessor. */
11691 if (!op1_sbit
&& op1_ebit
&& op
)
11693 uint32_t record_buf
[1];
11695 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11696 if (record_buf
[0] == 15)
11697 record_buf
[0] = ARM_PS_REGNUM
;
11699 arm_insn_r
->reg_rec_count
= 1;
11700 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11706 return arm_record_unsupported_insn (arm_insn_r
);
11709 /* Handling opcode 000 insns. */
11712 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11714 uint32_t record_buf
[8];
11715 uint32_t reg_src1
= 0;
11717 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11719 record_buf
[0] = ARM_PS_REGNUM
;
11720 record_buf
[1] = reg_src1
;
11721 thumb_insn_r
->reg_rec_count
= 2;
11723 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11729 /* Handling opcode 001 insns. */
11732 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11734 uint32_t record_buf
[8];
11735 uint32_t reg_src1
= 0;
11737 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11739 record_buf
[0] = ARM_PS_REGNUM
;
11740 record_buf
[1] = reg_src1
;
11741 thumb_insn_r
->reg_rec_count
= 2;
11743 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11748 /* Handling opcode 010 insns. */
11751 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11753 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11754 uint32_t record_buf
[8], record_buf_mem
[8];
11756 uint32_t reg_src1
= 0, reg_src2
= 0;
11757 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11759 ULONGEST u_regval
[2] = {0};
11761 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11763 if (bit (thumb_insn_r
->arm_insn
, 12))
11765 /* Handle load/store register offset. */
11766 uint32_t opB
= bits (thumb_insn_r
->arm_insn
, 9, 11);
11768 if (opB
>= 4 && opB
<= 7)
11770 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11771 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11772 record_buf
[0] = reg_src1
;
11773 thumb_insn_r
->reg_rec_count
= 1;
11775 else if (opB
>= 0 && opB
<= 2)
11777 /* STR(2), STRB(2), STRH(2) . */
11778 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11779 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11780 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11781 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11783 record_buf_mem
[0] = 4; /* STR (2). */
11785 record_buf_mem
[0] = 1; /* STRB (2). */
11787 record_buf_mem
[0] = 2; /* STRH (2). */
11788 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11789 thumb_insn_r
->mem_rec_count
= 1;
11792 else if (bit (thumb_insn_r
->arm_insn
, 11))
11794 /* Handle load from literal pool. */
11796 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11797 record_buf
[0] = reg_src1
;
11798 thumb_insn_r
->reg_rec_count
= 1;
11802 /* Special data instructions and branch and exchange */
11803 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11804 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11805 if ((3 == opcode2
) && (!opcode3
))
11807 /* Branch with exchange. */
11808 record_buf
[0] = ARM_PS_REGNUM
;
11809 thumb_insn_r
->reg_rec_count
= 1;
11813 /* Format 8; special data processing insns. */
11814 record_buf
[0] = ARM_PS_REGNUM
;
11815 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11816 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11817 thumb_insn_r
->reg_rec_count
= 2;
11822 /* Format 5; data processing insns. */
11823 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11824 if (bit (thumb_insn_r
->arm_insn
, 7))
11826 reg_src1
= reg_src1
+ 8;
11828 record_buf
[0] = ARM_PS_REGNUM
;
11829 record_buf
[1] = reg_src1
;
11830 thumb_insn_r
->reg_rec_count
= 2;
11833 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11834 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11840 /* Handling opcode 001 insns. */
11843 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11845 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11846 uint32_t record_buf
[8], record_buf_mem
[8];
11848 uint32_t reg_src1
= 0;
11849 uint32_t opcode
= 0, immed_5
= 0;
11851 ULONGEST u_regval
= 0;
11853 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11858 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11859 record_buf
[0] = reg_src1
;
11860 thumb_insn_r
->reg_rec_count
= 1;
11865 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11866 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11867 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11868 record_buf_mem
[0] = 4;
11869 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11870 thumb_insn_r
->mem_rec_count
= 1;
11873 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11874 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11880 /* Handling opcode 100 insns. */
11883 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11885 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11886 uint32_t record_buf
[8], record_buf_mem
[8];
11888 uint32_t reg_src1
= 0;
11889 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11891 ULONGEST u_regval
= 0;
11893 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11898 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11899 record_buf
[0] = reg_src1
;
11900 thumb_insn_r
->reg_rec_count
= 1;
11902 else if (1 == opcode
)
11905 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11906 record_buf
[0] = reg_src1
;
11907 thumb_insn_r
->reg_rec_count
= 1;
11909 else if (2 == opcode
)
11912 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11913 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11914 record_buf_mem
[0] = 4;
11915 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11916 thumb_insn_r
->mem_rec_count
= 1;
11918 else if (0 == opcode
)
11921 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11922 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11923 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11924 record_buf_mem
[0] = 2;
11925 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11926 thumb_insn_r
->mem_rec_count
= 1;
11929 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11930 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11936 /* Handling opcode 101 insns. */
11939 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11941 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11943 uint32_t opcode
= 0;
11944 uint32_t register_bits
= 0, register_count
= 0;
11945 uint32_t index
= 0, start_address
= 0;
11946 uint32_t record_buf
[24], record_buf_mem
[48];
11949 ULONGEST u_regval
= 0;
11951 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11953 if (opcode
== 0 || opcode
== 1)
11955 /* ADR and ADD (SP plus immediate) */
11957 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11958 record_buf
[0] = reg_src1
;
11959 thumb_insn_r
->reg_rec_count
= 1;
11963 /* Miscellaneous 16-bit instructions */
11964 uint32_t opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 11);
11969 /* SETEND and CPS */
11972 /* ADD/SUB (SP plus immediate) */
11973 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11974 record_buf
[0] = ARM_SP_REGNUM
;
11975 thumb_insn_r
->reg_rec_count
= 1;
11977 case 1: /* fall through */
11978 case 3: /* fall through */
11979 case 9: /* fall through */
11985 /* SXTH, SXTB, UXTH, UXTB */
11986 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
11987 thumb_insn_r
->reg_rec_count
= 1;
11989 case 4: /* fall through */
11992 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11993 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11994 while (register_bits
)
11996 if (register_bits
& 0x00000001)
11998 register_bits
= register_bits
>> 1;
12000 start_address
= u_regval
- \
12001 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12002 thumb_insn_r
->mem_rec_count
= register_count
;
12003 while (register_count
)
12005 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12006 record_buf_mem
[(register_count
* 2) - 2] = 4;
12007 start_address
= start_address
+ 4;
12010 record_buf
[0] = ARM_SP_REGNUM
;
12011 thumb_insn_r
->reg_rec_count
= 1;
12014 /* REV, REV16, REVSH */
12017 case 12: /* fall through */
12020 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12021 while (register_bits
)
12023 if (register_bits
& 0x00000001)
12024 record_buf
[index
++] = register_count
;
12025 register_bits
= register_bits
>> 1;
12028 record_buf
[index
++] = ARM_PS_REGNUM
;
12029 record_buf
[index
++] = ARM_SP_REGNUM
;
12030 thumb_insn_r
->reg_rec_count
= index
;
12034 /* Handle enhanced software breakpoint insn, BKPT. */
12035 /* CPSR is changed to be executed in ARM state, disabling normal
12036 interrupts, entering abort mode. */
12037 /* According to high vector configuration PC is set. */
12038 /* User hits breakpoint and type reverse, in that case, we need to go back with
12039 previous CPSR and Program Counter. */
12040 record_buf
[0] = ARM_PS_REGNUM
;
12041 record_buf
[1] = ARM_LR_REGNUM
;
12042 thumb_insn_r
->reg_rec_count
= 2;
12043 /* We need to save SPSR value, which is not yet done. */
12044 printf_unfiltered (_("Process record does not support instruction "
12045 "0x%0x at address %s.\n"),
12046 thumb_insn_r
->arm_insn
,
12047 paddress (thumb_insn_r
->gdbarch
,
12048 thumb_insn_r
->this_addr
));
12052 /* If-Then, and hints */
12059 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12060 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12066 /* Handling opcode 110 insns. */
12069 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12072 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12074 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12075 uint32_t reg_src1
= 0;
12076 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12077 uint32_t index
= 0, start_address
= 0;
12078 uint32_t record_buf
[24], record_buf_mem
[48];
12080 ULONGEST u_regval
= 0;
12082 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12083 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12089 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12091 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12092 while (register_bits
)
12094 if (register_bits
& 0x00000001)
12095 record_buf
[index
++] = register_count
;
12096 register_bits
= register_bits
>> 1;
12099 record_buf
[index
++] = reg_src1
;
12100 thumb_insn_r
->reg_rec_count
= index
;
12102 else if (0 == opcode2
)
12104 /* It handles both STMIA. */
12105 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12107 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12108 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12109 while (register_bits
)
12111 if (register_bits
& 0x00000001)
12113 register_bits
= register_bits
>> 1;
12115 start_address
= u_regval
;
12116 thumb_insn_r
->mem_rec_count
= register_count
;
12117 while (register_count
)
12119 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12120 record_buf_mem
[(register_count
* 2) - 2] = 4;
12121 start_address
= start_address
+ 4;
12125 else if (0x1F == opcode1
)
12127 /* Handle arm syscall insn. */
12128 if (tdep
->arm_syscall_record
!= NULL
)
12130 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12131 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12135 printf_unfiltered (_("no syscall record support\n"));
12140 /* B (1), conditional branch is automatically taken care in process_record,
12141 as PC is saved there. */
12143 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12144 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12150 /* Handling opcode 111 insns. */
12153 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12155 uint32_t record_buf
[8];
12156 uint32_t bits_h
= 0;
12158 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12160 if (2 == bits_h
|| 3 == bits_h
)
12163 record_buf
[0] = ARM_LR_REGNUM
;
12164 thumb_insn_r
->reg_rec_count
= 1;
12166 else if (1 == bits_h
)
12169 record_buf
[0] = ARM_PS_REGNUM
;
12170 record_buf
[1] = ARM_LR_REGNUM
;
12171 thumb_insn_r
->reg_rec_count
= 2;
12174 /* B(2) is automatically taken care in process_record, as PC is
12177 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12182 /* Handler for thumb2 load/store multiple instructions. */
12185 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12187 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12189 uint32_t reg_rn
, op
;
12190 uint32_t register_bits
= 0, register_count
= 0;
12191 uint32_t index
= 0, start_address
= 0;
12192 uint32_t record_buf
[24], record_buf_mem
[48];
12194 ULONGEST u_regval
= 0;
12196 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12197 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12199 if (0 == op
|| 3 == op
)
12201 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12203 /* Handle RFE instruction. */
12204 record_buf
[0] = ARM_PS_REGNUM
;
12205 thumb2_insn_r
->reg_rec_count
= 1;
12209 /* Handle SRS instruction after reading banked SP. */
12210 return arm_record_unsupported_insn (thumb2_insn_r
);
12213 else if (1 == op
|| 2 == op
)
12215 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12217 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12218 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12219 while (register_bits
)
12221 if (register_bits
& 0x00000001)
12222 record_buf
[index
++] = register_count
;
12225 register_bits
= register_bits
>> 1;
12227 record_buf
[index
++] = reg_rn
;
12228 record_buf
[index
++] = ARM_PS_REGNUM
;
12229 thumb2_insn_r
->reg_rec_count
= index
;
12233 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12234 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12235 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12236 while (register_bits
)
12238 if (register_bits
& 0x00000001)
12241 register_bits
= register_bits
>> 1;
12246 /* Start address calculation for LDMDB/LDMEA. */
12247 start_address
= u_regval
;
12251 /* Start address calculation for LDMDB/LDMEA. */
12252 start_address
= u_regval
- register_count
* 4;
12255 thumb2_insn_r
->mem_rec_count
= register_count
;
12256 while (register_count
)
12258 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12259 record_buf_mem
[register_count
* 2 - 2] = 4;
12260 start_address
= start_address
+ 4;
12263 record_buf
[0] = reg_rn
;
12264 record_buf
[1] = ARM_PS_REGNUM
;
12265 thumb2_insn_r
->reg_rec_count
= 2;
12269 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12271 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12273 return ARM_RECORD_SUCCESS
;
12276 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12280 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12282 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12284 uint32_t reg_rd
, reg_rn
, offset_imm
;
12285 uint32_t reg_dest1
, reg_dest2
;
12286 uint32_t address
, offset_addr
;
12287 uint32_t record_buf
[8], record_buf_mem
[8];
12288 uint32_t op1
, op2
, op3
;
12290 ULONGEST u_regval
[2];
12292 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12293 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12294 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12296 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12298 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12300 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12301 record_buf
[0] = reg_dest1
;
12302 record_buf
[1] = ARM_PS_REGNUM
;
12303 thumb2_insn_r
->reg_rec_count
= 2;
12306 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12308 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12309 record_buf
[2] = reg_dest2
;
12310 thumb2_insn_r
->reg_rec_count
= 3;
12315 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12316 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12318 if (0 == op1
&& 0 == op2
)
12320 /* Handle STREX. */
12321 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12322 address
= u_regval
[0] + (offset_imm
* 4);
12323 record_buf_mem
[0] = 4;
12324 record_buf_mem
[1] = address
;
12325 thumb2_insn_r
->mem_rec_count
= 1;
12326 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12327 record_buf
[0] = reg_rd
;
12328 thumb2_insn_r
->reg_rec_count
= 1;
12330 else if (1 == op1
&& 0 == op2
)
12332 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12333 record_buf
[0] = reg_rd
;
12334 thumb2_insn_r
->reg_rec_count
= 1;
12335 address
= u_regval
[0];
12336 record_buf_mem
[1] = address
;
12340 /* Handle STREXB. */
12341 record_buf_mem
[0] = 1;
12342 thumb2_insn_r
->mem_rec_count
= 1;
12346 /* Handle STREXH. */
12347 record_buf_mem
[0] = 2 ;
12348 thumb2_insn_r
->mem_rec_count
= 1;
12352 /* Handle STREXD. */
12353 address
= u_regval
[0];
12354 record_buf_mem
[0] = 4;
12355 record_buf_mem
[2] = 4;
12356 record_buf_mem
[3] = address
+ 4;
12357 thumb2_insn_r
->mem_rec_count
= 2;
12362 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12364 if (bit (thumb2_insn_r
->arm_insn
, 24))
12366 if (bit (thumb2_insn_r
->arm_insn
, 23))
12367 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12369 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12371 address
= offset_addr
;
12374 address
= u_regval
[0];
12376 record_buf_mem
[0] = 4;
12377 record_buf_mem
[1] = address
;
12378 record_buf_mem
[2] = 4;
12379 record_buf_mem
[3] = address
+ 4;
12380 thumb2_insn_r
->mem_rec_count
= 2;
12381 record_buf
[0] = reg_rn
;
12382 thumb2_insn_r
->reg_rec_count
= 1;
12386 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12388 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12390 return ARM_RECORD_SUCCESS
;
12393 /* Handler for thumb2 data processing (shift register and modified immediate)
12397 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12399 uint32_t reg_rd
, op
;
12400 uint32_t record_buf
[8];
12402 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12403 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12405 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12407 record_buf
[0] = ARM_PS_REGNUM
;
12408 thumb2_insn_r
->reg_rec_count
= 1;
12412 record_buf
[0] = reg_rd
;
12413 record_buf
[1] = ARM_PS_REGNUM
;
12414 thumb2_insn_r
->reg_rec_count
= 2;
12417 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12419 return ARM_RECORD_SUCCESS
;
12422 /* Generic handler for thumb2 instructions which effect destination and PS
12426 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12429 uint32_t record_buf
[8];
12431 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12433 record_buf
[0] = reg_rd
;
12434 record_buf
[1] = ARM_PS_REGNUM
;
12435 thumb2_insn_r
->reg_rec_count
= 2;
12437 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12439 return ARM_RECORD_SUCCESS
;
12442 /* Handler for thumb2 branch and miscellaneous control instructions. */
12445 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12447 uint32_t op
, op1
, op2
;
12448 uint32_t record_buf
[8];
12450 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12451 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12452 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12454 /* Handle MSR insn. */
12455 if (!(op1
& 0x2) && 0x38 == op
)
12459 /* CPSR is going to be changed. */
12460 record_buf
[0] = ARM_PS_REGNUM
;
12461 thumb2_insn_r
->reg_rec_count
= 1;
12465 arm_record_unsupported_insn(thumb2_insn_r
);
12469 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12472 record_buf
[0] = ARM_PS_REGNUM
;
12473 record_buf
[1] = ARM_LR_REGNUM
;
12474 thumb2_insn_r
->reg_rec_count
= 2;
12477 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12479 return ARM_RECORD_SUCCESS
;
12482 /* Handler for thumb2 store single data item instructions. */
12485 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12487 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12489 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12490 uint32_t address
, offset_addr
;
12491 uint32_t record_buf
[8], record_buf_mem
[8];
12494 ULONGEST u_regval
[2];
12496 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12497 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12498 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12499 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12501 if (bit (thumb2_insn_r
->arm_insn
, 23))
12504 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12505 offset_addr
= u_regval
[0] + offset_imm
;
12506 address
= offset_addr
;
12511 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12513 /* Handle STRB (register). */
12514 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12515 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12516 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12517 offset_addr
= u_regval
[1] << shift_imm
;
12518 address
= u_regval
[0] + offset_addr
;
12522 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12523 if (bit (thumb2_insn_r
->arm_insn
, 10))
12525 if (bit (thumb2_insn_r
->arm_insn
, 9))
12526 offset_addr
= u_regval
[0] + offset_imm
;
12528 offset_addr
= u_regval
[0] - offset_imm
;
12530 address
= offset_addr
;
12533 address
= u_regval
[0];
12539 /* Store byte instructions. */
12542 record_buf_mem
[0] = 1;
12544 /* Store half word instructions. */
12547 record_buf_mem
[0] = 2;
12549 /* Store word instructions. */
12552 record_buf_mem
[0] = 4;
12556 gdb_assert_not_reached ("no decoding pattern found");
12560 record_buf_mem
[1] = address
;
12561 thumb2_insn_r
->mem_rec_count
= 1;
12562 record_buf
[0] = reg_rn
;
12563 thumb2_insn_r
->reg_rec_count
= 1;
12565 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12567 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12569 return ARM_RECORD_SUCCESS
;
12572 /* Handler for thumb2 load memory hints instructions. */
12575 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12577 uint32_t record_buf
[8];
12578 uint32_t reg_rt
, reg_rn
;
12580 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12581 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12583 if (ARM_PC_REGNUM
!= reg_rt
)
12585 record_buf
[0] = reg_rt
;
12586 record_buf
[1] = reg_rn
;
12587 record_buf
[2] = ARM_PS_REGNUM
;
12588 thumb2_insn_r
->reg_rec_count
= 3;
12590 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12592 return ARM_RECORD_SUCCESS
;
12595 return ARM_RECORD_FAILURE
;
12598 /* Handler for thumb2 load word instructions. */
12601 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12603 uint32_t record_buf
[8];
12605 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12606 record_buf
[1] = ARM_PS_REGNUM
;
12607 thumb2_insn_r
->reg_rec_count
= 2;
12609 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12611 return ARM_RECORD_SUCCESS
;
12614 /* Handler for thumb2 long multiply, long multiply accumulate, and
12615 divide instructions. */
12618 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12620 uint32_t opcode1
= 0, opcode2
= 0;
12621 uint32_t record_buf
[8];
12623 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12624 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12626 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12628 /* Handle SMULL, UMULL, SMULAL. */
12629 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12630 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12631 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12632 record_buf
[2] = ARM_PS_REGNUM
;
12633 thumb2_insn_r
->reg_rec_count
= 3;
12635 else if (1 == opcode1
|| 3 == opcode2
)
12637 /* Handle SDIV and UDIV. */
12638 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12639 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12640 record_buf
[2] = ARM_PS_REGNUM
;
12641 thumb2_insn_r
->reg_rec_count
= 3;
12644 return ARM_RECORD_FAILURE
;
12646 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12648 return ARM_RECORD_SUCCESS
;
12651 /* Record handler for thumb32 coprocessor instructions. */
12654 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12656 if (bit (thumb2_insn_r
->arm_insn
, 25))
12657 return arm_record_coproc_data_proc (thumb2_insn_r
);
12659 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12662 /* Record handler for advance SIMD structure load/store instructions. */
12665 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12667 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12668 uint32_t l_bit
, a_bit
, b_bits
;
12669 uint32_t record_buf
[128], record_buf_mem
[128];
12670 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12671 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12674 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12675 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12676 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12677 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12678 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12679 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12680 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12681 f_elem
= 8 / f_ebytes
;
12685 ULONGEST u_regval
= 0;
12686 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12687 address
= u_regval
;
12692 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12694 if (b_bits
== 0x07)
12696 else if (b_bits
== 0x0a)
12698 else if (b_bits
== 0x06)
12700 else if (b_bits
== 0x02)
12705 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12707 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12709 record_buf_mem
[index_m
++] = f_ebytes
;
12710 record_buf_mem
[index_m
++] = address
;
12711 address
= address
+ f_ebytes
;
12712 thumb2_insn_r
->mem_rec_count
+= 1;
12717 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12719 if (b_bits
== 0x09 || b_bits
== 0x08)
12721 else if (b_bits
== 0x03)
12726 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12727 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12729 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12731 record_buf_mem
[index_m
++] = f_ebytes
;
12732 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12733 thumb2_insn_r
->mem_rec_count
+= 1;
12735 address
= address
+ (2 * f_ebytes
);
12739 else if ((b_bits
& 0x0e) == 0x04)
12741 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12743 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12745 record_buf_mem
[index_m
++] = f_ebytes
;
12746 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12747 thumb2_insn_r
->mem_rec_count
+= 1;
12749 address
= address
+ (3 * f_ebytes
);
12753 else if (!(b_bits
& 0x0e))
12755 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12757 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12759 record_buf_mem
[index_m
++] = f_ebytes
;
12760 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12761 thumb2_insn_r
->mem_rec_count
+= 1;
12763 address
= address
+ (4 * f_ebytes
);
12769 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12771 if (bft_size
== 0x00)
12773 else if (bft_size
== 0x01)
12775 else if (bft_size
== 0x02)
12781 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12782 thumb2_insn_r
->mem_rec_count
= 1;
12784 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12785 thumb2_insn_r
->mem_rec_count
= 2;
12787 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12788 thumb2_insn_r
->mem_rec_count
= 3;
12790 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12791 thumb2_insn_r
->mem_rec_count
= 4;
12793 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12795 record_buf_mem
[index_m
] = f_ebytes
;
12796 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12805 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12806 thumb2_insn_r
->reg_rec_count
= 1;
12808 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12809 thumb2_insn_r
->reg_rec_count
= 2;
12811 else if ((b_bits
& 0x0e) == 0x04)
12812 thumb2_insn_r
->reg_rec_count
= 3;
12814 else if (!(b_bits
& 0x0e))
12815 thumb2_insn_r
->reg_rec_count
= 4;
12820 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12821 thumb2_insn_r
->reg_rec_count
= 1;
12823 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12824 thumb2_insn_r
->reg_rec_count
= 2;
12826 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12827 thumb2_insn_r
->reg_rec_count
= 3;
12829 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12830 thumb2_insn_r
->reg_rec_count
= 4;
12832 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12833 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12837 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12839 record_buf
[index_r
] = reg_rn
;
12840 thumb2_insn_r
->reg_rec_count
+= 1;
12843 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12845 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12850 /* Decodes thumb2 instruction type and invokes its record handler. */
12852 static unsigned int
12853 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12855 uint32_t op
, op1
, op2
;
12857 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12858 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12859 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12863 if (!(op2
& 0x64 ))
12865 /* Load/store multiple instruction. */
12866 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12868 else if ((op2
& 0x64) == 0x4)
12870 /* Load/store (dual/exclusive) and table branch instruction. */
12871 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12873 else if ((op2
& 0x60) == 0x20)
12875 /* Data-processing (shifted register). */
12876 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12878 else if (op2
& 0x40)
12880 /* Co-processor instructions. */
12881 return thumb2_record_coproc_insn (thumb2_insn_r
);
12884 else if (op1
== 0x02)
12888 /* Branches and miscellaneous control instructions. */
12889 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12891 else if (op2
& 0x20)
12893 /* Data-processing (plain binary immediate) instruction. */
12894 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12898 /* Data-processing (modified immediate). */
12899 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12902 else if (op1
== 0x03)
12904 if (!(op2
& 0x71 ))
12906 /* Store single data item. */
12907 return thumb2_record_str_single_data (thumb2_insn_r
);
12909 else if (!((op2
& 0x71) ^ 0x10))
12911 /* Advanced SIMD or structure load/store instructions. */
12912 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12914 else if (!((op2
& 0x67) ^ 0x01))
12916 /* Load byte, memory hints instruction. */
12917 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12919 else if (!((op2
& 0x67) ^ 0x03))
12921 /* Load halfword, memory hints instruction. */
12922 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12924 else if (!((op2
& 0x67) ^ 0x05))
12926 /* Load word instruction. */
12927 return thumb2_record_ld_word (thumb2_insn_r
);
12929 else if (!((op2
& 0x70) ^ 0x20))
12931 /* Data-processing (register) instruction. */
12932 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12934 else if (!((op2
& 0x78) ^ 0x30))
12936 /* Multiply, multiply accumulate, abs diff instruction. */
12937 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12939 else if (!((op2
& 0x78) ^ 0x38))
12941 /* Long multiply, long multiply accumulate, and divide. */
12942 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12944 else if (op2
& 0x40)
12946 /* Co-processor instructions. */
12947 return thumb2_record_coproc_insn (thumb2_insn_r
);
12954 /* Abstract memory reader. */
12956 class abstract_memory_reader
12959 /* Read LEN bytes of target memory at address MEMADDR, placing the
12960 results in GDB's memory at BUF. Return true on success. */
12962 virtual bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) = 0;
12965 /* Instruction reader from real target. */
12967 class instruction_reader
: public abstract_memory_reader
12970 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
)
12972 if (target_read_memory (memaddr
, buf
, len
))
12979 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12980 and positive val on fauilure. */
12983 extract_arm_insn (abstract_memory_reader
& reader
,
12984 insn_decode_record
*insn_record
, uint32_t insn_size
)
12986 gdb_byte buf
[insn_size
];
12988 memset (&buf
[0], 0, insn_size
);
12990 if (!reader
.read (insn_record
->this_addr
, buf
, insn_size
))
12992 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12994 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12998 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13000 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13004 decode_insn (abstract_memory_reader
&reader
, insn_decode_record
*arm_record
,
13005 record_type_t record_type
, uint32_t insn_size
)
13008 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
13010 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13012 arm_record_data_proc_misc_ld_str
, /* 000. */
13013 arm_record_data_proc_imm
, /* 001. */
13014 arm_record_ld_st_imm_offset
, /* 010. */
13015 arm_record_ld_st_reg_offset
, /* 011. */
13016 arm_record_ld_st_multiple
, /* 100. */
13017 arm_record_b_bl
, /* 101. */
13018 arm_record_asimd_vfp_coproc
, /* 110. */
13019 arm_record_coproc_data_proc
/* 111. */
13022 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
13024 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13026 thumb_record_shift_add_sub
, /* 000. */
13027 thumb_record_add_sub_cmp_mov
, /* 001. */
13028 thumb_record_ld_st_reg_offset
, /* 010. */
13029 thumb_record_ld_st_imm_offset
, /* 011. */
13030 thumb_record_ld_st_stack
, /* 100. */
13031 thumb_record_misc
, /* 101. */
13032 thumb_record_ldm_stm_swi
, /* 110. */
13033 thumb_record_branch
/* 111. */
13036 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13037 uint32_t insn_id
= 0;
13039 if (extract_arm_insn (reader
, arm_record
, insn_size
))
13043 printf_unfiltered (_("Process record: error reading memory at "
13044 "addr %s len = %d.\n"),
13045 paddress (arm_record
->gdbarch
,
13046 arm_record
->this_addr
), insn_size
);
13050 else if (ARM_RECORD
== record_type
)
13052 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13053 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13055 if (arm_record
->cond
== 0xf)
13056 ret
= arm_record_extension_space (arm_record
);
13059 /* If this insn has fallen into extension space
13060 then we need not decode it anymore. */
13061 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13063 if (ret
!= ARM_RECORD_SUCCESS
)
13065 arm_record_unsupported_insn (arm_record
);
13069 else if (THUMB_RECORD
== record_type
)
13071 /* As thumb does not have condition codes, we set negative. */
13072 arm_record
->cond
= -1;
13073 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13074 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13075 if (ret
!= ARM_RECORD_SUCCESS
)
13077 arm_record_unsupported_insn (arm_record
);
13081 else if (THUMB2_RECORD
== record_type
)
13083 /* As thumb does not have condition codes, we set negative. */
13084 arm_record
->cond
= -1;
13086 /* Swap first half of 32bit thumb instruction with second half. */
13087 arm_record
->arm_insn
13088 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13090 ret
= thumb2_record_decode_insn_handler (arm_record
);
13092 if (ret
!= ARM_RECORD_SUCCESS
)
13094 arm_record_unsupported_insn (arm_record
);
13100 /* Throw assertion. */
13101 gdb_assert_not_reached ("not a valid instruction, could not decode");
13108 namespace selftests
{
13110 /* Provide both 16-bit and 32-bit thumb instructions. */
13112 class instruction_reader_thumb
: public abstract_memory_reader
13115 template<size_t SIZE
>
13116 instruction_reader_thumb (enum bfd_endian endian
,
13117 const uint16_t (&insns
)[SIZE
])
13118 : m_endian (endian
), m_insns (insns
), m_insns_size (SIZE
)
13121 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
)
13123 SELF_CHECK (len
== 4 || len
== 2);
13124 SELF_CHECK (memaddr
% 2 == 0);
13125 SELF_CHECK ((memaddr
/ 2) < m_insns_size
);
13127 store_unsigned_integer (buf
, 2, m_endian
, m_insns
[memaddr
/ 2]);
13130 store_unsigned_integer (&buf
[2], 2, m_endian
,
13131 m_insns
[memaddr
/ 2 + 1]);
13137 enum bfd_endian m_endian
;
13138 const uint16_t *m_insns
;
13139 size_t m_insns_size
;
13143 arm_record_test (void)
13145 struct gdbarch_info info
;
13146 gdbarch_info_init (&info
);
13147 info
.bfd_arch_info
= bfd_scan_arch ("arm");
13149 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
13151 SELF_CHECK (gdbarch
!= NULL
);
13153 /* 16-bit Thumb instructions. */
13155 insn_decode_record arm_record
;
13157 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13158 arm_record
.gdbarch
= gdbarch
;
13160 static const uint16_t insns
[] = {
13161 /* db b2 uxtb r3, r3 */
13163 /* cd 58 ldr r5, [r1, r3] */
13167 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13168 instruction_reader_thumb
reader (endian
, insns
);
13169 int ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13170 THUMB_INSN_SIZE_BYTES
);
13172 SELF_CHECK (ret
== 0);
13173 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13174 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13175 SELF_CHECK (arm_record
.arm_regs
[0] == 3);
13177 arm_record
.this_addr
+= 2;
13178 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13179 THUMB_INSN_SIZE_BYTES
);
13181 SELF_CHECK (ret
== 0);
13182 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13183 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13184 SELF_CHECK (arm_record
.arm_regs
[0] == 5);
13187 /* 32-bit Thumb-2 instructions. */
13189 insn_decode_record arm_record
;
13191 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13192 arm_record
.gdbarch
= gdbarch
;
13194 static const uint16_t insns
[] = {
13195 /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
13199 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13200 instruction_reader_thumb
reader (endian
, insns
);
13201 int ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13202 THUMB2_INSN_SIZE_BYTES
);
13204 SELF_CHECK (ret
== 0);
13205 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13206 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13207 SELF_CHECK (arm_record
.arm_regs
[0] == 7);
13210 } // namespace selftests
13211 #endif /* GDB_SELF_TEST */
13213 /* Cleans up local record registers and memory allocations. */
13216 deallocate_reg_mem (insn_decode_record
*record
)
13218 xfree (record
->arm_regs
);
13219 xfree (record
->arm_mems
);
13223 /* Parse the current instruction and record the values of the registers and
13224 memory that will be changed in current instruction to record_arch_list".
13225 Return -1 if something is wrong. */
13228 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13229 CORE_ADDR insn_addr
)
13232 uint32_t no_of_rec
= 0;
13233 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13234 ULONGEST t_bit
= 0, insn_id
= 0;
13236 ULONGEST u_regval
= 0;
13238 insn_decode_record arm_record
;
13240 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13241 arm_record
.regcache
= regcache
;
13242 arm_record
.this_addr
= insn_addr
;
13243 arm_record
.gdbarch
= gdbarch
;
13246 if (record_debug
> 1)
13248 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13250 paddress (gdbarch
, arm_record
.this_addr
));
13253 instruction_reader reader
;
13254 if (extract_arm_insn (reader
, &arm_record
, 2))
13258 printf_unfiltered (_("Process record: error reading memory at "
13259 "addr %s len = %d.\n"),
13260 paddress (arm_record
.gdbarch
,
13261 arm_record
.this_addr
), 2);
13266 /* Check the insn, whether it is thumb or arm one. */
13268 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13269 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13272 if (!(u_regval
& t_bit
))
13274 /* We are decoding arm insn. */
13275 ret
= decode_insn (reader
, &arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13279 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13280 /* is it thumb2 insn? */
13281 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13283 ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13284 THUMB2_INSN_SIZE_BYTES
);
13288 /* We are decoding thumb insn. */
13289 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13290 THUMB_INSN_SIZE_BYTES
);
13296 /* Record registers. */
13297 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13298 if (arm_record
.arm_regs
)
13300 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13302 if (record_full_arch_list_add_reg
13303 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13307 /* Record memories. */
13308 if (arm_record
.arm_mems
)
13310 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13312 if (record_full_arch_list_add_mem
13313 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13314 arm_record
.arm_mems
[no_of_rec
].len
))
13319 if (record_full_arch_list_add_end ())
13324 deallocate_reg_mem (&arm_record
);