1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
39 #include "gdb/sim-arm.h"
42 #include "coff/internal.h"
45 #include "gdb_assert.h"
49 /* Each OS has a different mechanism for accessing the various
50 registers stored in the sigcontext structure.
52 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
53 function pointer) which may be used to determine the addresses
54 of the various saved registers in the sigcontext structure.
56 For the ARM target, there are three parameters to this function.
57 The first is the pc value of the frame under consideration, the
58 second the stack pointer of this frame, and the last is the
59 register number to fetch.
61 If the tm.h file does not define this macro, then it's assumed that
62 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
65 When it comes time to multi-arching this code, see the identically
66 named machinery in ia64-tdep.c for an example of how it could be
67 done. It should not be necessary to modify the code below where
68 this macro is used. */
70 #ifdef SIGCONTEXT_REGISTER_ADDRESS
71 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
72 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
75 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
76 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
79 /* Macros for setting and testing a bit in a minimal symbol that marks
80 it as Thumb function. The MSB of the minimal symbol's "info" field
81 is used for this purpose. This field is already being used to store
82 the symbol size, so the assumption is that the symbol size cannot
85 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
86 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
87 MSYMBOL_SIZE Returns the size of the minimal symbol,
88 i.e. the "info" field with the "special" bit
91 #define MSYMBOL_SET_SPECIAL(msym) \
92 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
95 #define MSYMBOL_IS_SPECIAL(msym) \
96 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
98 #define MSYMBOL_SIZE(msym) \
99 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
101 /* Number of different reg name sets (options). */
102 static int num_flavor_options
;
104 /* We have more registers than the disassembler as gdb can print the value
105 of special registers as well.
106 The general register names are overwritten by whatever is being used by
107 the disassembler at the moment. We also adjust the case of cpsr and fps. */
109 /* Initial value: Register names used in ARM's ISA documentation. */
110 static char * arm_register_name_strings
[] =
111 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
112 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
113 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
114 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
115 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
116 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
117 "fps", "cpsr" }; /* 24 25 */
118 static char **arm_register_names
= arm_register_name_strings
;
120 /* Valid register name flavors. */
121 static const char **valid_flavors
;
123 /* Disassembly flavor to use. Default to "std" register names. */
124 static const char *disassembly_flavor
;
125 /* Index to that option in the opcodes table. */
126 static int current_option
;
128 /* This is used to keep the bfd arch_info in sync with the disassembly
130 static void set_disassembly_flavor_sfunc(char *, int,
131 struct cmd_list_element
*);
132 static void set_disassembly_flavor (void);
134 static void convert_from_extended (void *ptr
, void *dbl
);
136 /* Define other aspects of the stack frame. We keep the offsets of
137 all saved registers, 'cause we need 'em a lot! We also keep the
138 current size of the stack frame, and the offset of the frame
139 pointer from the stack pointer (for frameless functions, and when
140 we're still in the prologue of a function with a frame). */
142 struct frame_extra_info
149 /* Addresses for calling Thumb functions have the bit 0 set.
150 Here are some macros to test, set, or clear bit 0 of addresses. */
151 #define IS_THUMB_ADDR(addr) ((addr) & 1)
152 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
153 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
156 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
158 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
161 /* Set to true if the 32-bit mode is in use. */
165 /* Flag set by arm_fix_call_dummy that tells whether the target
166 function is a Thumb function. This flag is checked by
167 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
168 its use in valops.c) to pass the function address as an additional
171 static int target_is_thumb
;
173 /* Flag set by arm_fix_call_dummy that tells whether the calling
174 function is a Thumb function. This flag is checked by
175 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
177 static int caller_is_thumb
;
179 /* Determine if the program counter specified in MEMADDR is in a Thumb
183 arm_pc_is_thumb (CORE_ADDR memaddr
)
185 struct minimal_symbol
*sym
;
187 /* If bit 0 of the address is set, assume this is a Thumb address. */
188 if (IS_THUMB_ADDR (memaddr
))
191 /* Thumb functions have a "special" bit set in minimal symbols. */
192 sym
= lookup_minimal_symbol_by_pc (memaddr
);
195 return (MSYMBOL_IS_SPECIAL (sym
));
203 /* Determine if the program counter specified in MEMADDR is in a call
204 dummy being called from a Thumb function. */
207 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
209 CORE_ADDR sp
= read_sp ();
211 /* FIXME: Until we switch for the new call dummy macros, this heuristic
212 is the best we can do. We are trying to determine if the pc is on
213 the stack, which (hopefully) will only happen in a call dummy.
214 We hope the current stack pointer is not so far alway from the dummy
215 frame location (true if we have not pushed large data structures or
216 gone too many levels deep) and that our 1024 is not enough to consider
217 code regions as part of the stack (true for most practical purposes). */
218 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
219 return caller_is_thumb
;
224 /* Remove useless bits from addresses in a running program. */
226 arm_addr_bits_remove (CORE_ADDR val
)
229 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
231 return (val
& 0x03fffffc);
234 /* When reading symbols, we need to zap the low bit of the address,
235 which may be set to 1 for Thumb functions. */
237 arm_smash_text_address (CORE_ADDR val
)
242 /* Immediately after a function call, return the saved pc. Can't
243 always go through the frames for this because on some machines the
244 new frame is not set up until the new function executes some
248 arm_saved_pc_after_call (struct frame_info
*frame
)
250 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
253 /* Determine whether the function invocation represented by FI has a
254 frame on the stack associated with it. If it does return zero,
255 otherwise return 1. */
258 arm_frameless_function_invocation (struct frame_info
*fi
)
260 CORE_ADDR func_start
, after_prologue
;
263 /* Sometimes we have functions that do a little setup (like saving the
264 vN registers with the stmdb instruction, but DO NOT set up a frame.
265 The symbol table will report this as a prologue. However, it is
266 important not to try to parse these partial frames as frames, or we
267 will get really confused.
269 So I will demand 3 instructions between the start & end of the
270 prologue before I call it a real prologue, i.e. at least
275 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
276 after_prologue
= SKIP_PROLOGUE (func_start
);
278 /* There are some frameless functions whose first two instructions
279 follow the standard APCS form, in which case after_prologue will
280 be func_start + 8. */
282 frameless
= (after_prologue
< func_start
+ 12);
286 /* The address of the arguments in the frame. */
288 arm_frame_args_address (struct frame_info
*fi
)
293 /* The address of the local variables in the frame. */
295 arm_frame_locals_address (struct frame_info
*fi
)
300 /* The number of arguments being passed in the frame. */
302 arm_frame_num_args (struct frame_info
*fi
)
304 /* We have no way of knowing. */
308 /* A typical Thumb prologue looks like this:
312 Sometimes the latter instruction may be replaced by:
320 or, on tpcs, like this:
327 There is always one instruction of three classes:
332 When we have found at least one of each class we are done with the prolog.
333 Note that the "sub sp, #NN" before the push does not count.
337 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
339 CORE_ADDR current_pc
;
341 bit 0 - push { rlist }
342 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
343 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
347 for (current_pc
= pc
;
348 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
351 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
353 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
355 findmask
|= 1; /* push found */
357 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
360 if ((findmask
& 1) == 0) /* before push ? */
363 findmask
|= 4; /* add/sub sp found */
365 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
367 findmask
|= 2; /* setting of r7 found */
369 else if (insn
== 0x466f) /* mov r7, sp */
371 findmask
|= 2; /* setting of r7 found */
373 else if (findmask
== (4+2+1))
375 /* We have found one of each type of prologue instruction */
379 /* Something in the prolog that we don't care about or some
380 instruction from outside the prolog scheduled here for
388 /* Advance the PC across any function entry prologue instructions to
389 reach some "real" code.
391 The APCS (ARM Procedure Call Standard) defines the following
395 [stmfd sp!, {a1,a2,a3,a4}]
396 stmfd sp!, {...,fp,ip,lr,pc}
397 [stfe f7, [sp, #-12]!]
398 [stfe f6, [sp, #-12]!]
399 [stfe f5, [sp, #-12]!]
400 [stfe f4, [sp, #-12]!]
401 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
404 arm_skip_prologue (CORE_ADDR pc
)
408 CORE_ADDR func_addr
, func_end
= 0;
410 struct symtab_and_line sal
;
412 /* If we're in a dummy frame, don't even try to skip the prologue. */
413 if (USE_GENERIC_DUMMY_FRAMES
414 && PC_IN_CALL_DUMMY (pc
, 0, 0))
417 /* See what the symbol table says. */
419 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
423 /* Found a function. */
424 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
425 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
427 /* Don't use this trick for assembly source files. */
428 sal
= find_pc_line (func_addr
, 0);
429 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
434 /* Check if this is Thumb code. */
435 if (arm_pc_is_thumb (pc
))
436 return thumb_skip_prologue (pc
, func_end
);
438 /* Can't find the prologue end in the symbol table, try it the hard way
439 by disassembling the instructions. */
441 /* Like arm_scan_prologue, stop no later than pc + 64. */
442 if (func_end
== 0 || func_end
> pc
+ 64)
445 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
447 inst
= read_memory_integer (skip_pc
, 4);
449 /* "mov ip, sp" is no longer a required part of the prologue. */
450 if (inst
== 0xe1a0c00d) /* mov ip, sp */
453 /* Some prologues begin with "str lr, [sp, #-4]!". */
454 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
457 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
460 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
463 /* Any insns after this point may float into the code, if it makes
464 for better instruction scheduling, so we skip them only if we
465 find them, but still consider the function to be frame-ful. */
467 /* We may have either one sfmfd instruction here, or several stfe
468 insns, depending on the version of floating point code we
470 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
473 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
476 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
479 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
482 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
483 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
484 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
487 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
488 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
489 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
492 /* Un-recognized instruction; stop scanning. */
496 return skip_pc
; /* End of prologue */
500 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
501 This function decodes a Thumb function prologue to determine:
502 1) the size of the stack frame
503 2) which registers are saved on it
504 3) the offsets of saved regs
505 4) the offset from the stack pointer to the frame pointer
506 This information is stored in the "extra" fields of the frame_info.
508 A typical Thumb function prologue would create this stack frame
509 (offsets relative to FP)
510 old SP -> 24 stack parameters
513 R7 -> 0 local variables (16 bytes)
514 SP -> -12 additional stack space (12 bytes)
515 The frame size would thus be 36 bytes, and the frame offset would be
516 12 bytes. The frame register is R7.
518 The comments for thumb_skip_prolog() describe the algorithm we use
519 to detect the end of the prolog. */
523 thumb_scan_prologue (struct frame_info
*fi
)
525 CORE_ADDR prologue_start
;
526 CORE_ADDR prologue_end
;
527 CORE_ADDR current_pc
;
528 /* Which register has been copied to register n? */
531 bit 0 - push { rlist }
532 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
533 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
538 /* Don't try to scan dummy frames. */
539 if (USE_GENERIC_DUMMY_FRAMES
541 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
544 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
546 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
548 if (sal
.line
== 0) /* no line info, use current PC */
549 prologue_end
= fi
->pc
;
550 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
551 prologue_end
= sal
.end
; /* (probably means no prologue) */
554 /* We're in the boondocks: allow for
555 16 pushes, an add, and "mv fp,sp". */
556 prologue_end
= prologue_start
+ 40;
558 prologue_end
= min (prologue_end
, fi
->pc
);
560 /* Initialize the saved register map. When register H is copied to
561 register L, we will put H in saved_reg[L]. */
562 for (i
= 0; i
< 16; i
++)
565 /* Search the prologue looking for instructions that set up the
566 frame pointer, adjust the stack pointer, and save registers.
567 Do this until all basic prolog instructions are found. */
569 fi
->extra_info
->framesize
= 0;
570 for (current_pc
= prologue_start
;
571 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
578 insn
= read_memory_unsigned_integer (current_pc
, 2);
580 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
583 findmask
|= 1; /* push found */
584 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
585 whether to save LR (R14). */
586 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
588 /* Calculate offsets of saved R0-R7 and LR. */
589 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
590 if (mask
& (1 << regno
))
592 fi
->extra_info
->framesize
+= 4;
593 fi
->saved_regs
[saved_reg
[regno
]] =
594 -(fi
->extra_info
->framesize
);
595 /* Reset saved register map. */
596 saved_reg
[regno
] = regno
;
599 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
602 if ((findmask
& 1) == 0) /* before push? */
605 findmask
|= 4; /* add/sub sp found */
607 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
608 if (insn
& 0x80) /* is it signed? (==subtracting) */
610 fi
->extra_info
->frameoffset
+= offset
;
613 fi
->extra_info
->framesize
-= offset
;
615 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
617 findmask
|= 2; /* setting of r7 found */
618 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
619 /* get scaled offset */
620 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
622 else if (insn
== 0x466f) /* mov r7, sp */
624 findmask
|= 2; /* setting of r7 found */
625 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
626 fi
->extra_info
->frameoffset
= 0;
627 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
629 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
631 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
632 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
633 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
636 /* Something in the prolog that we don't care about or some
637 instruction from outside the prolog scheduled here for
643 /* Check if prologue for this frame's PC has already been scanned. If
644 it has, copy the relevant information about that prologue and
645 return non-zero. Otherwise do not copy anything and return zero.
647 The information saved in the cache includes:
648 * the frame register number;
649 * the size of the stack frame;
650 * the offsets of saved regs (relative to the old SP); and
651 * the offset from the stack pointer to the frame pointer
653 The cache contains only one entry, since this is adequate for the
654 typical sequence of prologue scan requests we get. When performing
655 a backtrace, GDB will usually ask to scan the same function twice
656 in a row (once to get the frame chain, and once to fill in the
657 extra frame information). */
659 static struct frame_info prologue_cache
;
662 check_prologue_cache (struct frame_info
*fi
)
666 if (fi
->pc
== prologue_cache
.pc
)
668 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
669 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
670 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
671 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
672 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
680 /* Copy the prologue information from fi to the prologue cache. */
683 save_prologue_cache (struct frame_info
*fi
)
687 prologue_cache
.pc
= fi
->pc
;
688 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
689 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
690 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
692 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
693 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
697 /* This function decodes an ARM function prologue to determine:
698 1) the size of the stack frame
699 2) which registers are saved on it
700 3) the offsets of saved regs
701 4) the offset from the stack pointer to the frame pointer
702 This information is stored in the "extra" fields of the frame_info.
704 There are two basic forms for the ARM prologue. The fixed argument
705 function call will look like:
708 stmfd sp!, {fp, ip, lr, pc}
712 Which would create this stack frame (offsets relative to FP):
713 IP -> 4 (caller's stack)
714 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
715 -4 LR (return address in caller)
716 -8 IP (copy of caller's SP)
718 SP -> -28 Local variables
720 The frame size would thus be 32 bytes, and the frame offset would be
721 28 bytes. The stmfd call can also save any of the vN registers it
722 plans to use, which increases the frame size accordingly.
724 Note: The stored PC is 8 off of the STMFD instruction that stored it
725 because the ARM Store instructions always store PC + 8 when you read
728 A variable argument function call will look like:
731 stmfd sp!, {a1, a2, a3, a4}
732 stmfd sp!, {fp, ip, lr, pc}
735 Which would create this stack frame (offsets relative to FP):
736 IP -> 20 (caller's stack)
741 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
742 -4 LR (return address in caller)
743 -8 IP (copy of caller's SP)
745 SP -> -28 Local variables
747 The frame size would thus be 48 bytes, and the frame offset would be
750 There is another potential complication, which is that the optimizer
751 will try to separate the store of fp in the "stmfd" instruction from
752 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
753 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
755 Also, note, the original version of the ARM toolchain claimed that there
758 instruction at the end of the prologue. I have never seen GCC produce
759 this, and the ARM docs don't mention it. We still test for it below in
765 arm_scan_prologue (struct frame_info
*fi
)
767 int regno
, sp_offset
, fp_offset
;
768 LONGEST return_value
;
769 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
771 /* Check if this function is already in the cache of frame information. */
772 if (check_prologue_cache (fi
))
775 /* Assume there is no frame until proven otherwise. */
776 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
777 fi
->extra_info
->framesize
= 0;
778 fi
->extra_info
->frameoffset
= 0;
780 /* Check for Thumb prologue. */
781 if (arm_pc_is_thumb (fi
->pc
))
783 thumb_scan_prologue (fi
);
784 save_prologue_cache (fi
);
788 /* Find the function prologue. If we can't find the function in
789 the symbol table, peek in the stack frame to find the PC. */
790 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
792 /* One way to find the end of the prologue (which works well
793 for unoptimized code) is to do the following:
795 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
798 prologue_end = fi->pc;
799 else if (sal.end < prologue_end)
800 prologue_end = sal.end;
802 This mechanism is very accurate so long as the optimizer
803 doesn't move any instructions from the function body into the
804 prologue. If this happens, sal.end will be the last
805 instruction in the first hunk of prologue code just before
806 the first instruction that the scheduler has moved from
807 the body to the prologue.
809 In order to make sure that we scan all of the prologue
810 instructions, we use a slightly less accurate mechanism which
811 may scan more than necessary. To help compensate for this
812 lack of accuracy, the prologue scanning loop below contains
813 several clauses which'll cause the loop to terminate early if
814 an implausible prologue instruction is encountered.
820 is a suitable endpoint since it accounts for the largest
821 possible prologue plus up to five instructions inserted by
824 if (prologue_end
> prologue_start
+ 64)
826 prologue_end
= prologue_start
+ 64; /* See above. */
831 /* Get address of the stmfd in the prologue of the callee;
832 the saved PC is the address of the stmfd + 8. */
833 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
837 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
838 prologue_end
= prologue_start
+ 64; /* See above. */
842 /* Now search the prologue looking for instructions that set up the
843 frame pointer, adjust the stack pointer, and save registers.
845 Be careful, however, and if it doesn't look like a prologue,
846 don't try to scan it. If, for instance, a frameless function
847 begins with stmfd sp!, then we will tell ourselves there is
848 a frame, which will confuse stack traceback, as well as "finish"
849 and other operations that rely on a knowledge of the stack
852 In the APCS, the prologue should start with "mov ip, sp" so
853 if we don't see this as the first insn, we will stop.
855 [Note: This doesn't seem to be true any longer, so it's now an
856 optional part of the prologue. - Kevin Buettner, 2001-11-20]
858 [Note further: The "mov ip,sp" only seems to be missing in
859 frameless functions at optimization level "-O2" or above,
860 in which case it is often (but not always) replaced by
861 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
863 sp_offset
= fp_offset
= 0;
865 for (current_pc
= prologue_start
;
866 current_pc
< prologue_end
;
869 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
871 if (insn
== 0xe1a0c00d) /* mov ip, sp */
875 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
877 /* Function is frameless: extra_info defaults OK? */
880 else if ((insn
& 0xffff0000) == 0xe92d0000)
881 /* stmfd sp!, {..., fp, ip, lr, pc}
883 stmfd sp!, {a1, a2, a3, a4} */
885 int mask
= insn
& 0xffff;
887 /* Calculate offsets of saved registers. */
888 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
889 if (mask
& (1 << regno
))
892 fi
->saved_regs
[regno
] = sp_offset
;
895 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
896 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
897 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
899 /* No need to add this to saved_regs -- it's just an arg reg. */
902 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
903 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
904 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
906 /* No need to add this to saved_regs -- it's just an arg reg. */
909 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
911 unsigned imm
= insn
& 0xff; /* immediate value */
912 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
913 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
915 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
917 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
919 unsigned imm
= insn
& 0xff; /* immediate value */
920 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
921 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
924 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
927 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
928 fi
->saved_regs
[regno
] = sp_offset
;
930 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
933 unsigned int fp_start_reg
, fp_bound_reg
;
935 if ((insn
& 0x800) == 0x800) /* N0 is set */
937 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
944 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
950 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
951 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
952 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
955 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
958 else if ((insn
& 0xf0000000) != 0xe0000000)
959 break; /* Condition not true, exit early */
960 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
961 break; /* Don't scan past a block load */
963 /* The optimizer might shove anything into the prologue,
964 so we just skip what we don't recognize. */
968 /* The frame size is just the negative of the offset (from the
969 original SP) of the last thing thing we pushed on the stack.
970 The frame offset is [new FP] - [new SP]. */
971 fi
->extra_info
->framesize
= -sp_offset
;
972 if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
)
973 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
975 fi
->extra_info
->frameoffset
= 0;
977 save_prologue_cache (fi
);
980 /* Find REGNUM on the stack. Otherwise, it's in an active register.
981 One thing we might want to do here is to check REGNUM against the
982 clobber mask, and somehow flag it as invalid if it isn't saved on
983 the stack somewhere. This would provide a graceful failure mode
984 when trying to get the value of caller-saves registers for an inner
988 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
990 /* NOTE: cagney/2002-05-03: This function really shouldn't be
991 needed. Instead the (still being written) register unwind
992 function could be called directly. */
993 for (; fi
; fi
= fi
->next
)
995 if (USE_GENERIC_DUMMY_FRAMES
996 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
998 return deprecated_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1000 else if (fi
->saved_regs
[regnum
] != 0)
1002 /* NOTE: cagney/2002-05-03: This would normally need to
1003 handle ARM_SP_REGNUM as a special case as, according to
1004 the frame.h comments, saved_regs[SP_REGNUM] contains the
1005 SP value not its address. It appears that the ARM isn't
1006 doing this though. */
1007 return read_memory_integer (fi
->saved_regs
[regnum
],
1008 REGISTER_RAW_SIZE (regnum
));
1011 return read_register (regnum
);
1013 /* Function: frame_chain Given a GDB frame, determine the address of
1014 the calling function's frame. This will be used to create a new
1015 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1016 will be called for the new frame. For ARM, we save the frame size
1017 when we initialize the frame_info. */
1020 arm_frame_chain (struct frame_info
*fi
)
1022 CORE_ADDR caller_pc
;
1023 int framereg
= fi
->extra_info
->framereg
;
1025 if (USE_GENERIC_DUMMY_FRAMES
1026 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1027 /* A generic call dummy's frame is the same as caller's. */
1030 if (fi
->pc
< LOWEST_PC
)
1033 /* If the caller is the startup code, we're at the end of the chain. */
1034 caller_pc
= FRAME_SAVED_PC (fi
);
1036 /* If the caller is Thumb and the caller is ARM, or vice versa,
1037 the frame register of the caller is different from ours.
1038 So we must scan the prologue of the caller to determine its
1039 frame register number. */
1040 /* XXX Fixme, we should try to do this without creating a temporary
1042 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1044 struct frame_info caller_fi
;
1045 struct cleanup
*old_chain
;
1047 /* Create a temporary frame suitable for scanning the caller's
1049 memset (&caller_fi
, 0, sizeof (caller_fi
));
1050 caller_fi
.extra_info
= (struct frame_extra_info
*)
1051 xcalloc (1, sizeof (struct frame_extra_info
));
1052 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1053 caller_fi
.saved_regs
= (CORE_ADDR
*)
1054 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1055 make_cleanup (xfree
, caller_fi
.saved_regs
);
1057 /* Now, scan the prologue and obtain the frame register. */
1058 caller_fi
.pc
= caller_pc
;
1059 arm_scan_prologue (&caller_fi
);
1060 framereg
= caller_fi
.extra_info
->framereg
;
1062 /* Deallocate the storage associated with the temporary frame
1064 do_cleanups (old_chain
);
1067 /* If the caller used a frame register, return its value.
1068 Otherwise, return the caller's stack pointer. */
1069 if (framereg
== ARM_FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1070 return arm_find_callers_reg (fi
, framereg
);
1072 return fi
->frame
+ fi
->extra_info
->framesize
;
1075 /* This function actually figures out the frame address for a given pc
1076 and sp. This is tricky because we sometimes don't use an explicit
1077 frame pointer, and the previous stack pointer isn't necessarily
1078 recorded on the stack. The only reliable way to get this info is
1079 to examine the prologue. FROMLEAF is a little confusing, it means
1080 this is the next frame up the chain AFTER a frameless function. If
1081 this is true, then the frame value for this frame is still in the
1085 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1090 if (fi
->saved_regs
== NULL
)
1091 frame_saved_regs_zalloc (fi
);
1093 fi
->extra_info
= (struct frame_extra_info
*)
1094 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1096 fi
->extra_info
->framesize
= 0;
1097 fi
->extra_info
->frameoffset
= 0;
1098 fi
->extra_info
->framereg
= 0;
1101 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1103 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1105 /* Compute stack pointer for this frame. We use this value for both
1106 the sigtramp and call dummy cases. */
1109 else if (USE_GENERIC_DUMMY_FRAMES
1110 && PC_IN_CALL_DUMMY (fi
->next
->pc
, 0, 0))
1111 /* For generic dummy frames, pull the value direct from the frame.
1112 Having an unwind function to do this would be nice. */
1113 sp
= deprecated_read_register_dummy (fi
->next
->pc
, fi
->next
->frame
,
1116 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1117 + fi
->next
->extra_info
->framesize
);
1119 /* Determine whether or not we're in a sigtramp frame.
1120 Unfortunately, it isn't sufficient to test
1121 fi->signal_handler_caller because this value is sometimes set
1122 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1123 fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we
1124 need to use the sigcontext addresses for the saved registers.
1126 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1127 against the name of the function, the code below will have to be
1128 changed to first fetch the name of the function and then pass
1129 this name to PC_IN_SIGTRAMP. */
1131 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1132 && (fi
->signal_handler_caller
|| PC_IN_SIGTRAMP (fi
->pc
, (char *)0)))
1134 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1135 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1137 /* FIXME: What about thumb mode? */
1138 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
1140 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1141 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1142 fi
->extra_info
->framesize
= 0;
1143 fi
->extra_info
->frameoffset
= 0;
1146 else if (!USE_GENERIC_DUMMY_FRAMES
1147 && PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1150 CORE_ADDR callers_sp
;
1152 /* Set rp point at the high end of the saved registers. */
1153 rp
= fi
->frame
- REGISTER_SIZE
;
1155 /* Fill in addresses of saved registers. */
1156 fi
->saved_regs
[ARM_PS_REGNUM
] = rp
;
1157 rp
-= REGISTER_RAW_SIZE (ARM_PS_REGNUM
);
1158 for (reg
= ARM_PC_REGNUM
; reg
>= 0; reg
--)
1160 fi
->saved_regs
[reg
] = rp
;
1161 rp
-= REGISTER_RAW_SIZE (reg
);
1164 callers_sp
= read_memory_integer (fi
->saved_regs
[ARM_SP_REGNUM
],
1165 REGISTER_RAW_SIZE (ARM_SP_REGNUM
));
1166 if (arm_pc_is_thumb (fi
->pc
))
1167 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
1169 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
1170 fi
->extra_info
->framesize
= callers_sp
- sp
;
1171 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1175 arm_scan_prologue (fi
);
1178 /* This is the innermost frame? */
1179 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1180 else if (USE_GENERIC_DUMMY_FRAMES
1181 && PC_IN_CALL_DUMMY (fi
->next
->pc
, 0, 0))
1182 /* Next inner most frame is a dummy, just grab its frame.
1183 Dummy frames always have the same FP as their caller. */
1184 fi
->frame
= fi
->next
->frame
;
1185 else if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
1186 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1188 /* not the innermost frame */
1189 /* If we have an FP, the callee saved it. */
1190 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1192 read_memory_integer (fi
->next
1193 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1195 /* If we were called by a frameless fn. then our frame is
1196 still in the frame pointer register on the board... */
1197 fi
->frame
= read_fp ();
1200 /* Calculate actual addresses of saved registers using offsets
1201 determined by arm_scan_prologue. */
1202 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1203 if (fi
->saved_regs
[reg
] != 0)
1204 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1205 - fi
->extra_info
->frameoffset
);
1210 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1211 is saved in the stack anywhere, otherwise we get it from the
1214 The old definition of this function was a macro:
1215 #define FRAME_SAVED_PC(FRAME) \
1216 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1219 arm_frame_saved_pc (struct frame_info
*fi
)
1221 /* If a dummy frame, pull the PC out of the frame's register buffer. */
1222 if (USE_GENERIC_DUMMY_FRAMES
1223 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1224 return deprecated_read_register_dummy (fi
->pc
, fi
->frame
, ARM_PC_REGNUM
);
1226 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1229 return read_memory_integer (fi
->saved_regs
[ARM_PC_REGNUM
],
1230 REGISTER_RAW_SIZE (ARM_PC_REGNUM
));
1234 CORE_ADDR pc
= arm_find_callers_reg (fi
, ARM_LR_REGNUM
);
1235 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1239 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1240 Examine the Program Status Register to decide which state we're in. */
1245 if (read_register (ARM_PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1246 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1248 return read_register (ARM_FP_REGNUM
); /* R11 if ARM */
1251 /* Store into a struct frame_saved_regs the addresses of the saved
1252 registers of frame described by FRAME_INFO. This includes special
1253 registers such as PC and FP saved in special ways in the stack
1254 frame. SP is even more special: the address we return for it IS
1255 the sp for the next frame. */
1258 arm_frame_init_saved_regs (struct frame_info
*fip
)
1261 if (fip
->saved_regs
)
1264 arm_init_extra_frame_info (0, fip
);
1267 /* Set the return address for a generic dummy frame. ARM uses the
1271 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1273 write_register (ARM_LR_REGNUM
, CALL_DUMMY_ADDRESS ());
1277 /* Push an empty stack frame, to record the current PC, etc. */
1280 arm_push_dummy_frame (void)
1282 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1283 CORE_ADDR sp
= old_sp
;
1284 CORE_ADDR fp
, prologue_start
;
1287 /* Push the two dummy prologue instructions in reverse order,
1288 so that they'll be in the correct low-to-high order in memory. */
1289 /* sub fp, ip, #4 */
1290 sp
= push_word (sp
, 0xe24cb004);
1291 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1292 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1294 /* Push a pointer to the dummy prologue + 12, because when stm
1295 instruction stores the PC, it stores the address of the stm
1296 instruction itself plus 12. */
1297 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1299 /* Push the processor status. */
1300 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1302 /* Push all 16 registers starting with r15. */
1303 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1304 sp
= push_word (sp
, read_register (regnum
));
1306 /* Update fp (for both Thumb and ARM) and sp. */
1307 write_register (ARM_FP_REGNUM
, fp
);
1308 write_register (THUMB_FP_REGNUM
, fp
);
1309 write_register (ARM_SP_REGNUM
, sp
);
1312 /* CALL_DUMMY_WORDS:
1313 This sequence of words is the instructions
1319 Note this is 12 bytes. */
1321 static LONGEST arm_call_dummy_words
[] =
1323 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1326 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1327 breakpoint to the proper address in the call dummy, so that
1328 `finish' after a stop in a call dummy works.
1330 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1331 optimal solution, but the call to arm_fix_call_dummy is immediately
1332 followed by a call to run_stack_dummy, which is the only function
1333 where call_dummy_breakpoint_offset is actually used. */
1337 arm_set_call_dummy_breakpoint_offset (void)
1339 if (caller_is_thumb
)
1340 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1342 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1345 /* Fix up the call dummy, based on whether the processor is currently
1346 in Thumb or ARM mode, and whether the target function is Thumb or
1347 ARM. There are three different situations requiring three
1350 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1351 been copied into the dummy parameter to this function.
1352 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1353 "mov pc,r4" instruction patched to be a "bx r4" instead.
1354 * Thumb calling anything: uses the Thumb dummy defined below, which
1355 works for calling both ARM and Thumb functions.
1357 All three call dummies expect to receive the target function
1358 address in R4, with the low bit set if it's a Thumb function. */
1361 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1362 struct value
**args
, struct type
*type
, int gcc_p
)
1364 static short thumb_dummy
[4] =
1366 0xf000, 0xf801, /* bl label */
1367 0xdf18, /* swi 24 */
1368 0x4720, /* label: bx r4 */
1370 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1372 /* Set flag indicating whether the current PC is in a Thumb function. */
1373 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1374 arm_set_call_dummy_breakpoint_offset ();
1376 /* If the target function is Thumb, set the low bit of the function
1377 address. And if the CPU is currently in ARM mode, patch the
1378 second instruction of call dummy to use a BX instruction to
1379 switch to Thumb mode. */
1380 target_is_thumb
= arm_pc_is_thumb (fun
);
1381 if (target_is_thumb
)
1384 if (!caller_is_thumb
)
1385 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1388 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1389 instead of the ARM one that's already been copied. This will
1390 work for both Thumb and ARM target functions. */
1391 if (caller_is_thumb
)
1395 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1397 for (i
= 0; i
< len
; i
++)
1399 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1400 p
+= sizeof (thumb_dummy
[0]);
1404 /* Put the target address in r4; the call dummy will copy this to
1406 write_register (4, fun
);
1411 This function does not support passing parameters using the FPA
1412 variant of the APCS. It passes any floating point arguments in the
1413 general registers and/or on the stack. */
1416 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1417 int struct_return
, CORE_ADDR struct_addr
)
1425 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1427 /* Walk through the list of args and determine how large a temporary
1428 stack is required. Need to take care here as structs may be
1429 passed on the stack, and we have to to push them. On the second
1430 pass, do the store. */
1433 for (second_pass
= 0; second_pass
< 2; second_pass
++)
1435 /* Compute the FP using the information computed during the
1441 argreg
= ARM_A1_REGNUM
;
1444 /* The struct_return pointer occupies the first parameter
1445 passing register. */
1451 fprintf_unfiltered (gdb_stdlog
,
1452 "struct return in %s = 0x%s\n",
1453 REGISTER_NAME (argreg
),
1454 paddr (struct_addr
));
1455 write_register (argreg
, struct_addr
);
1460 for (argnum
= 0; argnum
< nargs
; argnum
++)
1463 struct type
*arg_type
;
1464 struct type
*target_type
;
1465 enum type_code typecode
;
1468 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1469 len
= TYPE_LENGTH (arg_type
);
1470 target_type
= TYPE_TARGET_TYPE (arg_type
);
1471 typecode
= TYPE_CODE (arg_type
);
1472 val
= VALUE_CONTENTS (args
[argnum
]);
1474 /* If the argument is a pointer to a function, and it is a
1475 Thumb function, create a LOCAL copy of the value and set
1476 the THUMB bit in it. */
1478 && TYPE_CODE_PTR
== typecode
1479 && target_type
!= NULL
1480 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1482 CORE_ADDR regval
= extract_address (val
, len
);
1483 if (arm_pc_is_thumb (regval
))
1486 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1490 /* Copy the argument to general registers or the stack in
1491 register-sized pieces. Large arguments are split between
1492 registers and stack. */
1495 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1497 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1499 /* The argument is being passed in a general purpose
1503 CORE_ADDR regval
= extract_address (val
,
1506 fprintf_unfiltered (gdb_stdlog
,
1507 "arg %d in %s = 0x%s\n",
1509 REGISTER_NAME (argreg
),
1510 phex (regval
, REGISTER_SIZE
));
1511 write_register (argreg
, regval
);
1519 /* Push the arguments onto the stack. */
1521 fprintf_unfiltered (gdb_stdlog
,
1522 "arg %d @ 0x%s + %d\n",
1523 argnum
, paddr (fp
), nstack
);
1524 write_memory (fp
+ nstack
, val
, REGISTER_SIZE
);
1526 nstack
+= REGISTER_SIZE
;
1536 /* Return the botom of the argument list (pointed to by fp). */
1540 /* Pop the current frame. So long as the frame info has been
1541 initialized properly (see arm_init_extra_frame_info), this code
1542 works for dummy frames as well as regular frames. I.e, there's no
1543 need to have a special case for dummy frames. */
1545 arm_pop_frame (void)
1548 struct frame_info
*frame
= get_current_frame ();
1549 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1550 + frame
->extra_info
->framesize
);
1552 if (USE_GENERIC_DUMMY_FRAMES
1553 && PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1555 generic_pop_dummy_frame ();
1556 flush_cached_frames ();
1560 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1561 if (frame
->saved_regs
[regnum
] != 0)
1562 write_register (regnum
,
1563 read_memory_integer (frame
->saved_regs
[regnum
],
1564 REGISTER_RAW_SIZE (regnum
)));
1566 write_register (ARM_PC_REGNUM
, FRAME_SAVED_PC (frame
));
1567 write_register (ARM_SP_REGNUM
, old_SP
);
1569 flush_cached_frames ();
1573 print_fpu_flags (int flags
)
1575 if (flags
& (1 << 0))
1576 fputs ("IVO ", stdout
);
1577 if (flags
& (1 << 1))
1578 fputs ("DVZ ", stdout
);
1579 if (flags
& (1 << 2))
1580 fputs ("OFL ", stdout
);
1581 if (flags
& (1 << 3))
1582 fputs ("UFL ", stdout
);
1583 if (flags
& (1 << 4))
1584 fputs ("INX ", stdout
);
1588 /* Print interesting information about the floating point processor
1589 (if present) or emulator. */
1591 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1592 struct frame_info
*frame
, const char *args
)
1594 register unsigned long status
= read_register (ARM_FPS_REGNUM
);
1597 type
= (status
>> 24) & 127;
1598 printf ("%s FPU type %d\n",
1599 (status
& (1 << 31)) ? "Hardware" : "Software",
1601 fputs ("mask: ", stdout
);
1602 print_fpu_flags (status
>> 16);
1603 fputs ("flags: ", stdout
);
1604 print_fpu_flags (status
);
1607 /* Return the GDB type object for the "standard" data type of data in
1610 static struct type
*
1611 arm_register_type (int regnum
)
1613 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1615 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1616 return builtin_type_arm_ext_big
;
1618 return builtin_type_arm_ext_littlebyte_bigword
;
1621 return builtin_type_int32
;
1624 /* Index within `registers' of the first byte of the space for
1628 arm_register_byte (int regnum
)
1630 if (regnum
< ARM_F0_REGNUM
)
1631 return regnum
* INT_REGISTER_RAW_SIZE
;
1632 else if (regnum
< ARM_PS_REGNUM
)
1633 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1634 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1636 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1637 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1638 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1641 /* Number of bytes of storage in the actual machine representation for
1642 register N. All registers are 4 bytes, except fp0 - fp7, which are
1643 12 bytes in length. */
1646 arm_register_raw_size (int regnum
)
1648 if (regnum
< ARM_F0_REGNUM
)
1649 return INT_REGISTER_RAW_SIZE
;
1650 else if (regnum
< ARM_FPS_REGNUM
)
1651 return FP_REGISTER_RAW_SIZE
;
1653 return STATUS_REGISTER_SIZE
;
1656 /* Number of bytes of storage in a program's representation
1659 arm_register_virtual_size (int regnum
)
1661 if (regnum
< ARM_F0_REGNUM
)
1662 return INT_REGISTER_VIRTUAL_SIZE
;
1663 else if (regnum
< ARM_FPS_REGNUM
)
1664 return FP_REGISTER_VIRTUAL_SIZE
;
1666 return STATUS_REGISTER_SIZE
;
1669 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1671 arm_register_sim_regno (int regnum
)
1674 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1676 if (reg
< NUM_GREGS
)
1677 return SIM_ARM_R0_REGNUM
+ reg
;
1680 if (reg
< NUM_FREGS
)
1681 return SIM_ARM_FP0_REGNUM
+ reg
;
1684 if (reg
< NUM_SREGS
)
1685 return SIM_ARM_FPS_REGNUM
+ reg
;
1688 internal_error (__FILE__
, __LINE__
, "Bad REGNUM %d", regnum
);
1691 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1692 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1693 It is thought that this is is the floating-point register format on
1694 little-endian systems. */
1697 convert_from_extended (void *ptr
, void *dbl
)
1700 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1701 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1703 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1705 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1709 convert_to_extended (void *dbl
, void *ptr
)
1712 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1713 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1714 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1716 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1721 condition_true (unsigned long cond
, unsigned long status_reg
)
1723 if (cond
== INST_AL
|| cond
== INST_NV
)
1729 return ((status_reg
& FLAG_Z
) != 0);
1731 return ((status_reg
& FLAG_Z
) == 0);
1733 return ((status_reg
& FLAG_C
) != 0);
1735 return ((status_reg
& FLAG_C
) == 0);
1737 return ((status_reg
& FLAG_N
) != 0);
1739 return ((status_reg
& FLAG_N
) == 0);
1741 return ((status_reg
& FLAG_V
) != 0);
1743 return ((status_reg
& FLAG_V
) == 0);
1745 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1747 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1749 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1751 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1753 return (((status_reg
& FLAG_Z
) == 0) &&
1754 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1756 return (((status_reg
& FLAG_Z
) != 0) ||
1757 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1762 /* Support routines for single stepping. Calculate the next PC value. */
1763 #define submask(x) ((1L << ((x) + 1)) - 1)
1764 #define bit(obj,st) (((obj) >> (st)) & 1)
1765 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1766 #define sbits(obj,st,fn) \
1767 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1768 #define BranchDest(addr,instr) \
1769 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1772 static unsigned long
1773 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1774 unsigned long status_reg
)
1776 unsigned long res
, shift
;
1777 int rm
= bits (inst
, 0, 3);
1778 unsigned long shifttype
= bits (inst
, 5, 6);
1782 int rs
= bits (inst
, 8, 11);
1783 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1786 shift
= bits (inst
, 7, 11);
1789 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1790 + (bit (inst
, 4) ? 12 : 8))
1791 : read_register (rm
));
1796 res
= shift
>= 32 ? 0 : res
<< shift
;
1800 res
= shift
>= 32 ? 0 : res
>> shift
;
1806 res
= ((res
& 0x80000000L
)
1807 ? ~((~res
) >> shift
) : res
>> shift
);
1810 case 3: /* ROR/RRX */
1813 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1815 res
= (res
>> shift
) | (res
<< (32 - shift
));
1819 return res
& 0xffffffff;
1822 /* Return number of 1-bits in VAL. */
1825 bitcount (unsigned long val
)
1828 for (nbits
= 0; val
!= 0; nbits
++)
1829 val
&= val
- 1; /* delete rightmost 1-bit in val */
1834 thumb_get_next_pc (CORE_ADDR pc
)
1836 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1837 unsigned short inst1
= read_memory_integer (pc
, 2);
1838 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1839 unsigned long offset
;
1841 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1845 /* Fetch the saved PC from the stack. It's stored above
1846 all of the other registers. */
1847 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1848 sp
= read_register (ARM_SP_REGNUM
);
1849 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1850 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1852 error ("Infinite loop detected");
1854 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1856 unsigned long status
= read_register (ARM_PS_REGNUM
);
1857 unsigned long cond
= bits (inst1
, 8, 11);
1858 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1859 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1861 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1863 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1865 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1867 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1868 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1869 nextpc
= pc_val
+ offset
;
1876 arm_get_next_pc (CORE_ADDR pc
)
1878 unsigned long pc_val
;
1879 unsigned long this_instr
;
1880 unsigned long status
;
1883 if (arm_pc_is_thumb (pc
))
1884 return thumb_get_next_pc (pc
);
1886 pc_val
= (unsigned long) pc
;
1887 this_instr
= read_memory_integer (pc
, 4);
1888 status
= read_register (ARM_PS_REGNUM
);
1889 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1891 if (condition_true (bits (this_instr
, 28, 31), status
))
1893 switch (bits (this_instr
, 24, 27))
1896 case 0x1: /* data processing */
1900 unsigned long operand1
, operand2
, result
= 0;
1904 if (bits (this_instr
, 12, 15) != 15)
1907 if (bits (this_instr
, 22, 25) == 0
1908 && bits (this_instr
, 4, 7) == 9) /* multiply */
1909 error ("Illegal update to pc in instruction");
1911 /* Multiply into PC */
1912 c
= (status
& FLAG_C
) ? 1 : 0;
1913 rn
= bits (this_instr
, 16, 19);
1914 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1916 if (bit (this_instr
, 25))
1918 unsigned long immval
= bits (this_instr
, 0, 7);
1919 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1920 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1923 else /* operand 2 is a shifted register */
1924 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1926 switch (bits (this_instr
, 21, 24))
1929 result
= operand1
& operand2
;
1933 result
= operand1
^ operand2
;
1937 result
= operand1
- operand2
;
1941 result
= operand2
- operand1
;
1945 result
= operand1
+ operand2
;
1949 result
= operand1
+ operand2
+ c
;
1953 result
= operand1
- operand2
+ c
;
1957 result
= operand2
- operand1
+ c
;
1963 case 0xb: /* tst, teq, cmp, cmn */
1964 result
= (unsigned long) nextpc
;
1968 result
= operand1
| operand2
;
1972 /* Always step into a function. */
1977 result
= operand1
& ~operand2
;
1984 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1987 error ("Infinite loop detected");
1992 case 0x5: /* data transfer */
1995 if (bit (this_instr
, 20))
1998 if (bits (this_instr
, 12, 15) == 15)
2004 if (bit (this_instr
, 22))
2005 error ("Illegal update to pc in instruction");
2007 /* byte write to PC */
2008 rn
= bits (this_instr
, 16, 19);
2009 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
2010 if (bit (this_instr
, 24))
2013 int c
= (status
& FLAG_C
) ? 1 : 0;
2014 unsigned long offset
=
2015 (bit (this_instr
, 25)
2016 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
2017 : bits (this_instr
, 0, 11));
2019 if (bit (this_instr
, 23))
2024 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2027 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2030 error ("Infinite loop detected");
2036 case 0x9: /* block transfer */
2037 if (bit (this_instr
, 20))
2040 if (bit (this_instr
, 15))
2045 if (bit (this_instr
, 23))
2048 unsigned long reglist
= bits (this_instr
, 0, 14);
2049 offset
= bitcount (reglist
) * 4;
2050 if (bit (this_instr
, 24)) /* pre */
2053 else if (bit (this_instr
, 24))
2057 unsigned long rn_val
=
2058 read_register (bits (this_instr
, 16, 19));
2060 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2064 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2066 error ("Infinite loop detected");
2071 case 0xb: /* branch & link */
2072 case 0xa: /* branch */
2074 nextpc
= BranchDest (pc
, this_instr
);
2076 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2078 error ("Infinite loop detected");
2084 case 0xe: /* coproc ops */
2089 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2097 /* single_step() is called just before we want to resume the inferior,
2098 if we want to single-step it but there is no hardware or kernel
2099 single-step support. We find the target of the coming instruction
2102 single_step() is also called just after the inferior stops. If we
2103 had set up a simulated single-step, we undo our damage. */
2106 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2108 static int next_pc
; /* State between setting and unsetting. */
2109 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2113 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2114 target_insert_breakpoint (next_pc
, break_mem
);
2117 target_remove_breakpoint (next_pc
, break_mem
);
2120 #include "bfd-in2.h"
2121 #include "libcoff.h"
2124 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2126 if (arm_pc_is_thumb (memaddr
))
2128 static asymbol
*asym
;
2129 static combined_entry_type ce
;
2130 static struct coff_symbol_struct csym
;
2131 static struct _bfd fake_bfd
;
2132 static bfd_target fake_target
;
2134 if (csym
.native
== NULL
)
2136 /* Create a fake symbol vector containing a Thumb symbol.
2137 This is solely so that the code in print_insn_little_arm()
2138 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2139 the presence of a Thumb symbol and switch to decoding
2140 Thumb instructions. */
2142 fake_target
.flavour
= bfd_target_coff_flavour
;
2143 fake_bfd
.xvec
= &fake_target
;
2144 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2146 csym
.symbol
.the_bfd
= &fake_bfd
;
2147 csym
.symbol
.name
= "fake";
2148 asym
= (asymbol
*) & csym
;
2151 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2152 info
->symbols
= &asym
;
2155 info
->symbols
= NULL
;
2157 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2158 return print_insn_big_arm (memaddr
, info
);
2160 return print_insn_little_arm (memaddr
, info
);
2163 /* The following define instruction sequences that will cause ARM
2164 cpu's to take an undefined instruction trap. These are used to
2165 signal a breakpoint to GDB.
2167 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2168 modes. A different instruction is required for each mode. The ARM
2169 cpu's can also be big or little endian. Thus four different
2170 instructions are needed to support all cases.
2172 Note: ARMv4 defines several new instructions that will take the
2173 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2174 not in fact add the new instructions. The new undefined
2175 instructions in ARMv4 are all instructions that had no defined
2176 behaviour in earlier chips. There is no guarantee that they will
2177 raise an exception, but may be treated as NOP's. In practice, it
2178 may only safe to rely on instructions matching:
2180 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2181 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2182 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2184 Even this may only true if the condition predicate is true. The
2185 following use a condition predicate of ALWAYS so it is always TRUE.
2187 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2188 and NetBSD all use a software interrupt rather than an undefined
2189 instruction to force a trap. This can be handled by by the
2190 abi-specific code during establishment of the gdbarch vector. */
2193 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2194 override these definitions. */
2195 #ifndef ARM_LE_BREAKPOINT
2196 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2198 #ifndef ARM_BE_BREAKPOINT
2199 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2201 #ifndef THUMB_LE_BREAKPOINT
2202 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2204 #ifndef THUMB_BE_BREAKPOINT
2205 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2208 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2209 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2210 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2211 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2213 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2214 the program counter value to determine whether a 16-bit or 32-bit
2215 breakpoint should be used. It returns a pointer to a string of
2216 bytes that encode a breakpoint instruction, stores the length of
2217 the string to *lenptr, and adjusts the program counter (if
2218 necessary) to point to the actual memory location where the
2219 breakpoint should be inserted. */
2221 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2222 breakpoints and storing their handles instread of what was in
2223 memory. It is nice that this is the same size as a handle -
2224 otherwise remote-rdp will have to change. */
2226 static const unsigned char *
2227 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2229 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2231 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2233 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2234 *lenptr
= tdep
->thumb_breakpoint_size
;
2235 return tdep
->thumb_breakpoint
;
2239 *lenptr
= tdep
->arm_breakpoint_size
;
2240 return tdep
->arm_breakpoint
;
2244 /* Extract from an array REGBUF containing the (raw) register state a
2245 function return value of type TYPE, and copy that, in virtual
2246 format, into VALBUF. */
2249 arm_extract_return_value (struct type
*type
,
2250 char regbuf
[REGISTER_BYTES
],
2253 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2255 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2257 switch (tdep
->fp_model
)
2260 convert_from_extended (®buf
[REGISTER_BYTE (ARM_F0_REGNUM
)],
2264 case ARM_FLOAT_SOFT
:
2265 case ARM_FLOAT_SOFT_VFP
:
2266 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2267 TYPE_LENGTH (type
));
2272 (__FILE__
, __LINE__
,
2273 "arm_extract_return_value: Floating point model not supported");
2278 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2279 TYPE_LENGTH (type
));
2282 /* Extract from an array REGBUF containing the (raw) register state
2283 the address in which a function should return its structure value. */
2286 arm_extract_struct_value_address (struct regcache
*regcache
)
2290 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2294 /* Will a function return an aggregate type in memory or in a
2295 register? Return 0 if an aggregate type can be returned in a
2296 register, 1 if it must be returned in memory. */
2299 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2302 register enum type_code code
;
2304 /* In the ARM ABI, "integer" like aggregate types are returned in
2305 registers. For an aggregate type to be integer like, its size
2306 must be less than or equal to REGISTER_SIZE and the offset of
2307 each addressable subfield must be zero. Note that bit fields are
2308 not addressable, and all addressable subfields of unions always
2309 start at offset zero.
2311 This function is based on the behaviour of GCC 2.95.1.
2312 See: gcc/arm.c: arm_return_in_memory() for details.
2314 Note: All versions of GCC before GCC 2.95.2 do not set up the
2315 parameters correctly for a function returning the following
2316 structure: struct { float f;}; This should be returned in memory,
2317 not a register. Richard Earnshaw sent me a patch, but I do not
2318 know of any way to detect if a function like the above has been
2319 compiled with the correct calling convention. */
2321 /* All aggregate types that won't fit in a register must be returned
2323 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
2328 /* The only aggregate types that can be returned in a register are
2329 structs and unions. Arrays must be returned in memory. */
2330 code
= TYPE_CODE (type
);
2331 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2336 /* Assume all other aggregate types can be returned in a register.
2337 Run a check for structures, unions and arrays. */
2340 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2343 /* Need to check if this struct/union is "integer" like. For
2344 this to be true, its size must be less than or equal to
2345 REGISTER_SIZE and the offset of each addressable subfield
2346 must be zero. Note that bit fields are not addressable, and
2347 unions always start at offset zero. If any of the subfields
2348 is a floating point type, the struct/union cannot be an
2351 /* For each field in the object, check:
2352 1) Is it FP? --> yes, nRc = 1;
2353 2) Is it addressable (bitpos != 0) and
2354 not packed (bitsize == 0)?
2358 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2360 enum type_code field_type_code
;
2361 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2363 /* Is it a floating point type field? */
2364 if (field_type_code
== TYPE_CODE_FLT
)
2370 /* If bitpos != 0, then we have to care about it. */
2371 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2373 /* Bitfields are not addressable. If the field bitsize is
2374 zero, then the field is not packed. Hence it cannot be
2375 a bitfield or any other packed type. */
2376 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2388 /* Write into appropriate registers a function return value of type
2389 TYPE, given in virtual format. */
2392 arm_store_return_value (struct type
*type
, char *valbuf
)
2394 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2397 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2399 switch (tdep
->fp_model
)
2403 convert_to_extended (valbuf
, buf
);
2404 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM
), buf
,
2405 FP_REGISTER_RAW_SIZE
);
2408 case ARM_FLOAT_SOFT
:
2409 case ARM_FLOAT_SOFT_VFP
:
2410 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2415 (__FILE__
, __LINE__
,
2416 "arm_store_return_value: Floating point model not supported");
2421 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2424 /* Store the address of the place in which to copy the structure the
2425 subroutine will return. This is called from call_function. */
2428 arm_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2430 write_register (ARM_A1_REGNUM
, addr
);
2434 arm_get_longjmp_target (CORE_ADDR
*pc
)
2437 char buf
[INT_REGISTER_RAW_SIZE
];
2438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2440 jb_addr
= read_register (ARM_A1_REGNUM
);
2442 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2443 INT_REGISTER_RAW_SIZE
))
2446 *pc
= extract_address (buf
, INT_REGISTER_RAW_SIZE
);
2450 /* Return non-zero if the PC is inside a thumb call thunk. */
2453 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2455 CORE_ADDR start_addr
;
2457 /* Find the starting address of the function containing the PC. If
2458 the caller didn't give us a name, look it up at the same time. */
2459 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2463 return strncmp (name
, "_call_via_r", 11) == 0;
2466 /* If PC is in a Thumb call or return stub, return the address of the
2467 target PC, which is in a register. The thunk functions are called
2468 _called_via_xx, where x is the register name. The possible names
2469 are r0-r9, sl, fp, ip, sp, and lr. */
2472 arm_skip_stub (CORE_ADDR pc
)
2475 CORE_ADDR start_addr
;
2477 /* Find the starting address and name of the function containing the PC. */
2478 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2481 /* Call thunks always start with "_call_via_". */
2482 if (strncmp (name
, "_call_via_", 10) == 0)
2484 /* Use the name suffix to determine which register contains the
2486 static char *table
[15] =
2487 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2488 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2492 for (regno
= 0; regno
<= 14; regno
++)
2493 if (strcmp (&name
[10], table
[regno
]) == 0)
2494 return read_register (regno
);
2497 return 0; /* not a stub */
2500 /* If the user changes the register disassembly flavor used for info
2501 register and other commands, we have to also switch the flavor used
2502 in opcodes for disassembly output. This function is run in the set
2503 disassembly_flavor command, and does that. */
2506 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2507 struct cmd_list_element
*c
)
2509 set_disassembly_flavor ();
2512 /* Return the ARM register name corresponding to register I. */
2514 arm_register_name (int i
)
2516 return arm_register_names
[i
];
2520 set_disassembly_flavor (void)
2522 const char *setname
, *setdesc
, **regnames
;
2525 /* Find the flavor that the user wants in the opcodes table. */
2527 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2528 while ((disassembly_flavor
!= setname
)
2529 && (current
< num_flavor_options
))
2530 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2531 current_option
= current
;
2533 /* Fill our copy. */
2534 for (j
= 0; j
< numregs
; j
++)
2535 arm_register_names
[j
] = (char *) regnames
[j
];
2538 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2540 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2541 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2545 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2546 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2549 /* Synchronize the disassembler. */
2550 set_arm_regname_option (current
);
2553 /* arm_othernames implements the "othernames" command. This is kind
2554 of hacky, and I prefer the set-show disassembly-flavor which is
2555 also used for the x86 gdb. I will keep this around, however, in
2556 case anyone is actually using it. */
2559 arm_othernames (char *names
, int n
)
2561 /* Circle through the various flavors. */
2562 current_option
= (current_option
+ 1) % num_flavor_options
;
2564 disassembly_flavor
= valid_flavors
[current_option
];
2565 set_disassembly_flavor ();
2568 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2569 for ARM linux targets using the struct offsets defined in <link.h>.
2570 Note, however, that link.h is not actually referred to in this file.
2571 Instead, the relevant structs offsets were obtained from examining
2572 link.h. (We can't refer to link.h from this file because the host
2573 system won't necessarily have it, or if it does, the structs which
2574 it defines will refer to the host system, not the target). */
2576 struct link_map_offsets
*
2577 arm_linux_svr4_fetch_link_map_offsets (void)
2579 static struct link_map_offsets lmo
;
2580 static struct link_map_offsets
*lmp
= 0;
2586 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2589 lmo
.r_map_offset
= 4;
2592 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2595 lmo
.l_addr_offset
= 0;
2596 lmo
.l_addr_size
= 4;
2598 lmo
.l_name_offset
= 4;
2599 lmo
.l_name_size
= 4;
2601 lmo
.l_next_offset
= 12;
2602 lmo
.l_next_size
= 4;
2604 lmo
.l_prev_offset
= 16;
2605 lmo
.l_prev_size
= 4;
2611 /* Test whether the coff symbol specific value corresponds to a Thumb
2615 coff_sym_is_thumb (int val
)
2617 return (val
== C_THUMBEXT
||
2618 val
== C_THUMBSTAT
||
2619 val
== C_THUMBEXTFUNC
||
2620 val
== C_THUMBSTATFUNC
||
2621 val
== C_THUMBLABEL
);
2624 /* arm_coff_make_msymbol_special()
2625 arm_elf_make_msymbol_special()
2627 These functions test whether the COFF or ELF symbol corresponds to
2628 an address in thumb code, and set a "special" bit in a minimal
2629 symbol to indicate that it does. */
2632 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2634 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2636 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2638 MSYMBOL_SET_SPECIAL (msym
);
2642 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2644 if (coff_sym_is_thumb (val
))
2645 MSYMBOL_SET_SPECIAL (msym
);
2649 static enum gdb_osabi
2650 arm_elf_osabi_sniffer (bfd
*abfd
)
2652 unsigned int elfosabi
, eflags
;
2653 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2655 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2660 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2661 file are conforming to the base specification for that machine
2662 (there are no OS-specific extensions). In order to determine the
2663 real OS in use we must look for OS notes that have been added. */
2664 bfd_map_over_sections (abfd
,
2665 generic_elf_osabi_sniff_abi_tag_sections
,
2667 if (osabi
== GDB_OSABI_UNKNOWN
)
2669 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2670 field for more information. */
2671 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2674 case EF_ARM_EABI_VER1
:
2675 osabi
= GDB_OSABI_ARM_EABI_V1
;
2678 case EF_ARM_EABI_VER2
:
2679 osabi
= GDB_OSABI_ARM_EABI_V2
;
2682 case EF_ARM_EABI_UNKNOWN
:
2683 /* Assume GNU tools. */
2684 osabi
= GDB_OSABI_ARM_APCS
;
2688 internal_error (__FILE__
, __LINE__
,
2689 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2690 "version 0x%x", eflags
);
2696 /* GNU tools use this value. Check note sections in this case,
2698 bfd_map_over_sections (abfd
,
2699 generic_elf_osabi_sniff_abi_tag_sections
,
2701 if (osabi
== GDB_OSABI_UNKNOWN
)
2703 /* Assume APCS ABI. */
2704 osabi
= GDB_OSABI_ARM_APCS
;
2708 case ELFOSABI_FREEBSD
:
2709 osabi
= GDB_OSABI_FREEBSD_ELF
;
2712 case ELFOSABI_NETBSD
:
2713 osabi
= GDB_OSABI_NETBSD_ELF
;
2716 case ELFOSABI_LINUX
:
2717 osabi
= GDB_OSABI_LINUX
;
2725 /* Initialize the current architecture based on INFO. If possible,
2726 re-use an architecture from ARCHES, which is a list of
2727 architectures already created during this debugging session.
2729 Called e.g. at program startup, when reading a core file, and when
2730 reading a binary file. */
2732 static struct gdbarch
*
2733 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2735 struct gdbarch_tdep
*tdep
;
2736 struct gdbarch
*gdbarch
;
2737 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2739 /* Try to deterimine the ABI of the object we are loading. */
2741 if (info
.abfd
!= NULL
)
2743 osabi
= gdbarch_lookup_osabi (info
.abfd
);
2744 if (osabi
== GDB_OSABI_UNKNOWN
)
2746 switch (bfd_get_flavour (info
.abfd
))
2748 case bfd_target_aout_flavour
:
2749 /* Assume it's an old APCS-style ABI. */
2750 osabi
= GDB_OSABI_ARM_APCS
;
2753 case bfd_target_coff_flavour
:
2754 /* Assume it's an old APCS-style ABI. */
2756 osabi
= GDB_OSABI_ARM_APCS
;
2760 /* Leave it as "unknown". */
2765 /* Find a candidate among extant architectures. */
2766 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2768 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2770 /* Make sure the ABI selection matches. */
2771 tdep
= gdbarch_tdep (arches
->gdbarch
);
2772 if (tdep
&& tdep
->osabi
== osabi
)
2773 return arches
->gdbarch
;
2776 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2777 gdbarch
= gdbarch_alloc (&info
, tdep
);
2779 tdep
->osabi
= osabi
;
2781 /* This is the way it has always defaulted. */
2782 tdep
->fp_model
= ARM_FLOAT_FPA
;
2785 switch (info
.byte_order
)
2787 case BFD_ENDIAN_BIG
:
2788 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2789 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2790 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2791 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2795 case BFD_ENDIAN_LITTLE
:
2796 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2797 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2798 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2799 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2804 internal_error (__FILE__
, __LINE__
,
2805 "arm_gdbarch_init: bad byte order for float format");
2808 /* On ARM targets char defaults to unsigned. */
2809 set_gdbarch_char_signed (gdbarch
, 0);
2811 /* This should be low enough for everything. */
2812 tdep
->lowest_pc
= 0x20;
2813 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2815 #if OLD_STYLE_ARM_DUMMY_FRAMES
2816 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2817 specific (non-generic) dummy frame code. Might be useful if
2818 there appears to be a problem with the generic dummy frame
2819 mechanism that replaced it. */
2820 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2822 /* Call dummy code. */
2823 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2824 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2825 /* We have to give this a value now, even though we will re-set it
2826 during each call to arm_fix_call_dummy. */
2827 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8);
2828 set_gdbarch_call_dummy_p (gdbarch
, 1);
2829 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2831 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2832 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (arm_call_dummy_words
));
2833 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2834 set_gdbarch_call_dummy_length (gdbarch
, 0);
2836 set_gdbarch_fix_call_dummy (gdbarch
, arm_fix_call_dummy
);
2838 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2840 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
2841 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
2843 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2844 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
2846 set_gdbarch_call_dummy_p (gdbarch
, 1);
2847 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2849 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2850 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
2851 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2852 set_gdbarch_call_dummy_length (gdbarch
, 0);
2854 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
2855 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
2857 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
2858 set_gdbarch_push_return_address (gdbarch
, arm_push_return_address
);
2861 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2862 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2863 set_gdbarch_coerce_float_to_double (gdbarch
,
2864 standard_coerce_float_to_double
);
2866 /* Frame handling. */
2867 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2868 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2869 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2870 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2871 set_gdbarch_frameless_function_invocation
2872 (gdbarch
, arm_frameless_function_invocation
);
2873 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2874 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2875 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2876 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2877 set_gdbarch_frame_args_skip (gdbarch
, 0);
2878 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2879 #if OLD_STYLE_ARM_DUMMY_FRAMES
2880 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2881 specific (non-generic) dummy frame code. Might be useful if
2882 there appears to be a problem with the generic dummy frame
2883 mechanism that replaced it. */
2884 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2886 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
2888 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2890 /* Address manipulation. */
2891 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2892 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2894 /* Offset from address of function to start of its code. */
2895 set_gdbarch_function_start_offset (gdbarch
, 0);
2897 /* Advance PC across function entry code. */
2898 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2900 /* Get the PC when a frame might not be available. */
2901 set_gdbarch_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2903 /* The stack grows downward. */
2904 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2906 /* Breakpoint manipulation. */
2907 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2908 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2910 /* Information about registers, etc. */
2911 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2912 set_gdbarch_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2913 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2914 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2915 set_gdbarch_register_byte (gdbarch
, arm_register_byte
);
2916 set_gdbarch_register_bytes (gdbarch
,
2917 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2918 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2919 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2920 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2921 set_gdbarch_register_raw_size (gdbarch
, arm_register_raw_size
);
2922 set_gdbarch_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2923 set_gdbarch_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2924 set_gdbarch_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2925 set_gdbarch_register_virtual_type (gdbarch
, arm_register_type
);
2927 /* Internal <-> external register number maps. */
2928 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2930 /* Integer registers are 4 bytes. */
2931 set_gdbarch_register_size (gdbarch
, 4);
2932 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2934 /* Returning results. */
2935 set_gdbarch_deprecated_extract_return_value (gdbarch
, arm_extract_return_value
);
2936 set_gdbarch_deprecated_store_return_value (gdbarch
, arm_store_return_value
);
2937 set_gdbarch_store_struct_return (gdbarch
, arm_store_struct_return
);
2938 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2939 set_gdbarch_extract_struct_value_address (gdbarch
,
2940 arm_extract_struct_value_address
);
2942 /* Single stepping. */
2943 /* XXX For an RDI target we should ask the target if it can single-step. */
2944 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2946 /* Minsymbol frobbing. */
2947 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2948 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2949 arm_coff_make_msymbol_special
);
2951 /* Hook in the ABI-specific overrides, if they have been registered. */
2952 gdbarch_init_osabi (info
, gdbarch
, osabi
);
2954 /* Now we have tuned the configuration, set a few final things,
2955 based on what the OS ABI has told us. */
2957 if (tdep
->jb_pc
>= 0)
2958 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2960 /* Floating point sizes and format. */
2961 switch (info
.byte_order
)
2963 case BFD_ENDIAN_BIG
:
2964 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2965 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2966 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2970 case BFD_ENDIAN_LITTLE
:
2971 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2972 if (tdep
->fp_model
== ARM_FLOAT_VFP
2973 || tdep
->fp_model
== ARM_FLOAT_SOFT_VFP
)
2975 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2976 set_gdbarch_long_double_format (gdbarch
,
2977 &floatformat_ieee_double_little
);
2981 set_gdbarch_double_format
2982 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2983 set_gdbarch_long_double_format
2984 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2989 internal_error (__FILE__
, __LINE__
,
2990 "arm_gdbarch_init: bad byte order for float format");
2993 /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
2994 references the old architecture vector, not the one we are
2996 if (prologue_cache
.saved_regs
!= NULL
)
2997 xfree (prologue_cache
.saved_regs
);
2999 /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
3000 references the old architecture vector, not the one we are
3002 prologue_cache
.saved_regs
= (CORE_ADDR
*)
3003 xcalloc (1, (sizeof (CORE_ADDR
)
3004 * (gdbarch_num_regs (gdbarch
)
3005 + gdbarch_num_pseudo_regs (gdbarch
))));
3011 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3013 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3018 fprintf_unfiltered (file
, "arm_dump_tdep: OS ABI = %s\n",
3019 gdbarch_osabi_name (tdep
->osabi
));
3021 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
3022 (unsigned long) tdep
->lowest_pc
);
3026 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
3027 struct gdbarch
*gdbarch
)
3033 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
3034 struct gdbarch
*gdbarch
)
3040 arm_init_abi_apcs (struct gdbarch_info info
,
3041 struct gdbarch
*gdbarch
)
3047 _initialize_arm_tdep (void)
3049 struct ui_file
*stb
;
3051 struct cmd_list_element
*new_cmd
;
3052 const char *setname
;
3053 const char *setdesc
;
3054 const char **regnames
;
3056 static char *helptext
;
3059 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3061 /* Register an ELF OS ABI sniffer for ARM binaries. */
3062 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3063 bfd_target_elf_flavour
,
3064 arm_elf_osabi_sniffer
);
3066 /* Register some ABI variants for embedded systems. */
3067 gdbarch_register_osabi (bfd_arch_arm
, GDB_OSABI_ARM_EABI_V1
,
3068 arm_init_abi_eabi_v1
);
3069 gdbarch_register_osabi (bfd_arch_arm
, GDB_OSABI_ARM_EABI_V2
,
3070 arm_init_abi_eabi_v2
);
3071 gdbarch_register_osabi (bfd_arch_arm
, GDB_OSABI_ARM_APCS
,
3074 tm_print_insn
= gdb_print_insn_arm
;
3076 /* Get the number of possible sets of register names defined in opcodes. */
3077 num_flavor_options
= get_arm_regname_num_options ();
3079 /* Sync the opcode insn printer with our register viewer. */
3080 parse_arm_disassembler_option ("reg-names-std");
3082 /* Begin creating the help text. */
3083 stb
= mem_fileopen ();
3084 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
3085 The valid values are:\n");
3087 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3088 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
3089 for (i
= 0; i
< num_flavor_options
; i
++)
3091 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3092 valid_flavors
[i
] = setname
;
3093 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3095 /* Copy the default names (if found) and synchronize disassembler. */
3096 if (!strcmp (setname
, "std"))
3098 disassembly_flavor
= setname
;
3100 for (j
= 0; j
< numregs
; j
++)
3101 arm_register_names
[j
] = (char *) regnames
[j
];
3102 set_arm_regname_option (i
);
3105 /* Mark the end of valid options. */
3106 valid_flavors
[num_flavor_options
] = NULL
;
3108 /* Finish the creation of the help text. */
3109 fprintf_unfiltered (stb
, "The default is \"std\".");
3110 helptext
= ui_file_xstrdup (stb
, &length
);
3111 ui_file_delete (stb
);
3113 /* Add the disassembly-flavor command. */
3114 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3116 &disassembly_flavor
,
3119 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
3120 add_show_from_set (new_cmd
, &showlist
);
3122 /* ??? Maybe this should be a boolean. */
3123 add_show_from_set (add_set_cmd ("apcs32", no_class
,
3124 var_zinteger
, (char *) &arm_apcs_32
,
3125 "Set usage of ARM 32-bit mode.\n", &setlist
),
3128 /* Add the deprecated "othernames" command. */
3130 add_com ("othernames", class_obscure
, arm_othernames
,
3131 "Switch to the next set of register names.");
3133 /* Fill in the prologue_cache fields. */
3134 prologue_cache
.saved_regs
= NULL
;
3135 prologue_cache
.extra_info
= (struct frame_extra_info
*)
3136 xcalloc (1, sizeof (struct frame_extra_info
));
3138 /* Debugging flag. */
3139 add_show_from_set (add_set_cmd ("arm", class_maintenance
, var_zinteger
,
3140 &arm_debug
, "Set arm debugging.\n\
3141 When non-zero, arm specific debugging is enabled.", &setdebuglist
),