1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
48 #include "gdb/sim-arm.h"
51 #include "coff/internal.h"
54 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
69 #define MSYMBOL_IS_SPECIAL(msym) \
70 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
72 /* The list of available "set arm ..." and "show arm ..." commands. */
73 static struct cmd_list_element
*setarmcmdlist
= NULL
;
74 static struct cmd_list_element
*showarmcmdlist
= NULL
;
76 /* The type of floating-point to use. Keep this in sync with enum
77 arm_float_model, and the help string in _initialize_arm_tdep. */
78 static const char *fp_model_strings
[] =
88 /* A variable that can be configured by the user. */
89 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
90 static const char *current_fp_model
= "auto";
92 /* The ABI to use. Keep this in sync with arm_abi_kind. */
93 static const char *arm_abi_strings
[] =
101 /* A variable that can be configured by the user. */
102 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
103 static const char *arm_abi_string
= "auto";
105 /* Number of different reg name sets (options). */
106 static int num_disassembly_options
;
108 /* The standard register names, and all the valid aliases for them. */
113 } arm_register_aliases
[] = {
114 /* Basic register numbers. */
131 /* Synonyms (argument and variable registers). */
144 /* Other platform-specific names for r9. */
152 /* Names used by GCC (not listed in the ARM EABI). */
155 /* A special name from the older ATPCS. */
159 static const char *const arm_register_names
[] =
160 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
161 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
162 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
163 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
164 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
165 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
166 "fps", "cpsr" }; /* 24 25 */
168 /* Valid register name styles. */
169 static const char **valid_disassembly_styles
;
171 /* Disassembly style to use. Default to "std" register names. */
172 static const char *disassembly_style
;
174 /* This is used to keep the bfd arch_info in sync with the disassembly
176 static void set_disassembly_style_sfunc(char *, int,
177 struct cmd_list_element
*);
178 static void set_disassembly_style (void);
180 static void convert_from_extended (const struct floatformat
*, const void *,
182 static void convert_to_extended (const struct floatformat
*, void *,
185 struct arm_prologue_cache
187 /* The stack pointer at the time this frame was created; i.e. the
188 caller's stack pointer when this function was called. It is used
189 to identify this frame. */
192 /* The frame base for this frame is just prev_sp + frame offset -
193 frame size. FRAMESIZE is the size of this stack frame, and
194 FRAMEOFFSET if the initial offset from the stack pointer (this
195 frame's stack pointer, not PREV_SP) to the frame base. */
200 /* The register used to hold the frame pointer for this frame. */
203 /* Saved register offsets. */
204 struct trad_frame_saved_reg
*saved_regs
;
207 /* Addresses for calling Thumb functions have the bit 0 set.
208 Here are some macros to test, set, or clear bit 0 of addresses. */
209 #define IS_THUMB_ADDR(addr) ((addr) & 1)
210 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
211 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
213 /* Set to true if the 32-bit mode is in use. */
217 /* Determine if the program counter specified in MEMADDR is in a Thumb
221 arm_pc_is_thumb (CORE_ADDR memaddr
)
223 struct minimal_symbol
*sym
;
225 /* If bit 0 of the address is set, assume this is a Thumb address. */
226 if (IS_THUMB_ADDR (memaddr
))
229 /* Thumb functions have a "special" bit set in minimal symbols. */
230 sym
= lookup_minimal_symbol_by_pc (memaddr
);
233 return (MSYMBOL_IS_SPECIAL (sym
));
241 /* Remove useless bits from addresses in a running program. */
243 arm_addr_bits_remove (CORE_ADDR val
)
246 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
248 return (val
& 0x03fffffc);
251 /* When reading symbols, we need to zap the low bit of the address,
252 which may be set to 1 for Thumb functions. */
254 arm_smash_text_address (CORE_ADDR val
)
259 /* Analyze a Thumb prologue, looking for a recognizable stack frame
260 and frame pointer. Scan until we encounter a store that could
261 clobber the stack frame unexpectedly, or an unknown instruction. */
264 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
265 CORE_ADDR start
, CORE_ADDR limit
,
266 struct arm_prologue_cache
*cache
)
270 struct pv_area
*stack
;
271 struct cleanup
*back_to
;
274 for (i
= 0; i
< 16; i
++)
275 regs
[i
] = pv_register (i
, 0);
276 stack
= make_pv_area (ARM_SP_REGNUM
);
277 back_to
= make_cleanup_free_pv_area (stack
);
279 /* The call instruction saved PC in LR, and the current PC is not
280 interesting. Due to this file's conventions, we want the value
281 of LR at this function's entry, not at the call site, so we do
282 not record the save of the PC - when the ARM prologue analyzer
283 has also been converted to the pv mechanism, we could record the
284 save here and remove the hack in prev_register. */
285 regs
[ARM_PC_REGNUM
] = pv_unknown ();
287 while (start
< limit
)
291 insn
= read_memory_unsigned_integer (start
, 2);
293 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
299 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
300 whether to save LR (R14). */
301 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
303 /* Calculate offsets of saved R0-R7 and LR. */
304 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
305 if (mask
& (1 << regno
))
307 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
313 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
315 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
321 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
324 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
325 if (insn
& 0x80) /* Check for SUB. */
326 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
329 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
332 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
333 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
335 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
337 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
338 int src_reg
= (insn
& 0x78) >> 3;
339 regs
[dst_reg
] = regs
[src_reg
];
341 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
343 /* Handle stores to the stack. Normally pushes are used,
344 but with GCC -mtpcs-frame, there may be other stores
345 in the prologue to create the frame. */
346 int regno
= (insn
>> 8) & 0x7;
349 offset
= (insn
& 0xff) << 2;
350 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
352 if (pv_area_store_would_trash (stack
, addr
))
355 pv_area_store (stack
, addr
, 4, regs
[regno
]);
359 /* We don't know what this instruction is. We're finished
360 scanning. NOTE: Recognizing more safe-to-ignore
361 instructions here will improve support for optimized
371 do_cleanups (back_to
);
375 /* frameoffset is unused for this unwinder. */
376 cache
->frameoffset
= 0;
378 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
380 /* Frame pointer is fp. Frame size is constant. */
381 cache
->framereg
= ARM_FP_REGNUM
;
382 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
384 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
386 /* Frame pointer is r7. Frame size is constant. */
387 cache
->framereg
= THUMB_FP_REGNUM
;
388 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
390 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
392 /* Try the stack pointer... this is a bit desperate. */
393 cache
->framereg
= ARM_SP_REGNUM
;
394 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
398 /* We're just out of luck. We don't know where the frame is. */
399 cache
->framereg
= -1;
400 cache
->framesize
= 0;
403 for (i
= 0; i
< 16; i
++)
404 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
405 cache
->saved_regs
[i
].addr
= offset
;
407 do_cleanups (back_to
);
411 /* Advance the PC across any function entry prologue instructions to
412 reach some "real" code.
414 The APCS (ARM Procedure Call Standard) defines the following
418 [stmfd sp!, {a1,a2,a3,a4}]
419 stmfd sp!, {...,fp,ip,lr,pc}
420 [stfe f7, [sp, #-12]!]
421 [stfe f6, [sp, #-12]!]
422 [stfe f5, [sp, #-12]!]
423 [stfe f4, [sp, #-12]!]
424 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
427 arm_skip_prologue (CORE_ADDR pc
)
431 CORE_ADDR func_addr
, func_end
= 0;
433 struct symtab_and_line sal
;
435 /* If we're in a dummy frame, don't even try to skip the prologue. */
436 if (deprecated_pc_in_call_dummy (pc
))
439 /* See what the symbol table says. */
441 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
445 /* Found a function. */
446 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
447 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
449 /* Don't use this trick for assembly source files. */
450 sal
= find_pc_line (func_addr
, 0);
451 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
456 /* Can't find the prologue end in the symbol table, try it the hard way
457 by disassembling the instructions. */
459 /* Like arm_scan_prologue, stop no later than pc + 64. */
460 if (func_end
== 0 || func_end
> pc
+ 64)
463 /* Check if this is Thumb code. */
464 if (arm_pc_is_thumb (pc
))
465 return thumb_analyze_prologue (current_gdbarch
, pc
, func_end
, NULL
);
467 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
469 inst
= read_memory_unsigned_integer (skip_pc
, 4);
471 /* "mov ip, sp" is no longer a required part of the prologue. */
472 if (inst
== 0xe1a0c00d) /* mov ip, sp */
475 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
478 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
481 /* Some prologues begin with "str lr, [sp, #-4]!". */
482 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
485 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
488 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
491 /* Any insns after this point may float into the code, if it makes
492 for better instruction scheduling, so we skip them only if we
493 find them, but still consider the function to be frame-ful. */
495 /* We may have either one sfmfd instruction here, or several stfe
496 insns, depending on the version of floating point code we
498 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
501 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
504 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
507 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
510 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
511 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
512 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
515 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
516 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
517 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
520 /* Un-recognized instruction; stop scanning. */
524 return skip_pc
; /* End of prologue */
528 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
529 This function decodes a Thumb function prologue to determine:
530 1) the size of the stack frame
531 2) which registers are saved on it
532 3) the offsets of saved regs
533 4) the offset from the stack pointer to the frame pointer
535 A typical Thumb function prologue would create this stack frame
536 (offsets relative to FP)
537 old SP -> 24 stack parameters
540 R7 -> 0 local variables (16 bytes)
541 SP -> -12 additional stack space (12 bytes)
542 The frame size would thus be 36 bytes, and the frame offset would be
543 12 bytes. The frame register is R7.
545 The comments for thumb_skip_prolog() describe the algorithm we use
546 to detect the end of the prolog. */
550 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
552 CORE_ADDR prologue_start
;
553 CORE_ADDR prologue_end
;
554 CORE_ADDR current_pc
;
555 /* Which register has been copied to register n? */
558 bit 0 - push { rlist }
559 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
560 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
565 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
567 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
569 if (sal
.line
== 0) /* no line info, use current PC */
570 prologue_end
= prev_pc
;
571 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
572 prologue_end
= sal
.end
; /* (probably means no prologue) */
575 /* We're in the boondocks: we have no idea where the start of the
579 prologue_end
= min (prologue_end
, prev_pc
);
581 thumb_analyze_prologue (current_gdbarch
, prologue_start
, prologue_end
,
585 /* This function decodes an ARM function prologue to determine:
586 1) the size of the stack frame
587 2) which registers are saved on it
588 3) the offsets of saved regs
589 4) the offset from the stack pointer to the frame pointer
590 This information is stored in the "extra" fields of the frame_info.
592 There are two basic forms for the ARM prologue. The fixed argument
593 function call will look like:
596 stmfd sp!, {fp, ip, lr, pc}
600 Which would create this stack frame (offsets relative to FP):
601 IP -> 4 (caller's stack)
602 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
603 -4 LR (return address in caller)
604 -8 IP (copy of caller's SP)
606 SP -> -28 Local variables
608 The frame size would thus be 32 bytes, and the frame offset would be
609 28 bytes. The stmfd call can also save any of the vN registers it
610 plans to use, which increases the frame size accordingly.
612 Note: The stored PC is 8 off of the STMFD instruction that stored it
613 because the ARM Store instructions always store PC + 8 when you read
616 A variable argument function call will look like:
619 stmfd sp!, {a1, a2, a3, a4}
620 stmfd sp!, {fp, ip, lr, pc}
623 Which would create this stack frame (offsets relative to FP):
624 IP -> 20 (caller's stack)
629 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
630 -4 LR (return address in caller)
631 -8 IP (copy of caller's SP)
633 SP -> -28 Local variables
635 The frame size would thus be 48 bytes, and the frame offset would be
638 There is another potential complication, which is that the optimizer
639 will try to separate the store of fp in the "stmfd" instruction from
640 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
641 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
643 Also, note, the original version of the ARM toolchain claimed that there
646 instruction at the end of the prologue. I have never seen GCC produce
647 this, and the ARM docs don't mention it. We still test for it below in
653 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
655 int regno
, sp_offset
, fp_offset
, ip_offset
;
656 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
657 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
659 /* Assume there is no frame until proven otherwise. */
660 cache
->framereg
= ARM_SP_REGNUM
;
661 cache
->framesize
= 0;
662 cache
->frameoffset
= 0;
664 /* Check for Thumb prologue. */
665 if (arm_pc_is_thumb (prev_pc
))
667 thumb_scan_prologue (prev_pc
, cache
);
671 /* Find the function prologue. If we can't find the function in
672 the symbol table, peek in the stack frame to find the PC. */
673 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
675 /* One way to find the end of the prologue (which works well
676 for unoptimized code) is to do the following:
678 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
681 prologue_end = prev_pc;
682 else if (sal.end < prologue_end)
683 prologue_end = sal.end;
685 This mechanism is very accurate so long as the optimizer
686 doesn't move any instructions from the function body into the
687 prologue. If this happens, sal.end will be the last
688 instruction in the first hunk of prologue code just before
689 the first instruction that the scheduler has moved from
690 the body to the prologue.
692 In order to make sure that we scan all of the prologue
693 instructions, we use a slightly less accurate mechanism which
694 may scan more than necessary. To help compensate for this
695 lack of accuracy, the prologue scanning loop below contains
696 several clauses which'll cause the loop to terminate early if
697 an implausible prologue instruction is encountered.
703 is a suitable endpoint since it accounts for the largest
704 possible prologue plus up to five instructions inserted by
707 if (prologue_end
> prologue_start
+ 64)
709 prologue_end
= prologue_start
+ 64; /* See above. */
714 /* We have no symbol information. Our only option is to assume this
715 function has a standard stack frame and the normal frame register.
716 Then, we can find the value of our frame pointer on entrance to
717 the callee (or at the present moment if this is the innermost frame).
718 The value stored there should be the address of the stmfd + 8. */
720 LONGEST return_value
;
722 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
723 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
727 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
728 prologue_end
= prologue_start
+ 64; /* See above. */
732 if (prev_pc
< prologue_end
)
733 prologue_end
= prev_pc
;
735 /* Now search the prologue looking for instructions that set up the
736 frame pointer, adjust the stack pointer, and save registers.
738 Be careful, however, and if it doesn't look like a prologue,
739 don't try to scan it. If, for instance, a frameless function
740 begins with stmfd sp!, then we will tell ourselves there is
741 a frame, which will confuse stack traceback, as well as "finish"
742 and other operations that rely on a knowledge of the stack
745 In the APCS, the prologue should start with "mov ip, sp" so
746 if we don't see this as the first insn, we will stop.
748 [Note: This doesn't seem to be true any longer, so it's now an
749 optional part of the prologue. - Kevin Buettner, 2001-11-20]
751 [Note further: The "mov ip,sp" only seems to be missing in
752 frameless functions at optimization level "-O2" or above,
753 in which case it is often (but not always) replaced by
754 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
756 sp_offset
= fp_offset
= ip_offset
= 0;
758 for (current_pc
= prologue_start
;
759 current_pc
< prologue_end
;
762 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
764 if (insn
== 0xe1a0c00d) /* mov ip, sp */
769 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
771 unsigned imm
= insn
& 0xff; /* immediate value */
772 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
773 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
777 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
779 unsigned imm
= insn
& 0xff; /* immediate value */
780 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
781 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
785 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
788 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
791 else if ((insn
& 0xffff0000) == 0xe92d0000)
792 /* stmfd sp!, {..., fp, ip, lr, pc}
794 stmfd sp!, {a1, a2, a3, a4} */
796 int mask
= insn
& 0xffff;
798 /* Calculate offsets of saved registers. */
799 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
800 if (mask
& (1 << regno
))
803 cache
->saved_regs
[regno
].addr
= sp_offset
;
806 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
807 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
808 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
810 /* No need to add this to saved_regs -- it's just an arg reg. */
813 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
814 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
815 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
817 /* No need to add this to saved_regs -- it's just an arg reg. */
820 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
822 unsigned imm
= insn
& 0xff; /* immediate value */
823 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
824 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
825 fp_offset
= -imm
+ ip_offset
;
826 cache
->framereg
= ARM_FP_REGNUM
;
828 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
830 unsigned imm
= insn
& 0xff; /* immediate value */
831 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
832 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
835 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
836 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
839 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
840 cache
->saved_regs
[regno
].addr
= sp_offset
;
842 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
843 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
846 unsigned int fp_start_reg
, fp_bound_reg
;
848 if ((insn
& 0x800) == 0x800) /* N0 is set */
850 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
857 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
863 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
864 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
865 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
868 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
871 else if ((insn
& 0xf0000000) != 0xe0000000)
872 break; /* Condition not true, exit early */
873 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
874 break; /* Don't scan past a block load */
876 /* The optimizer might shove anything into the prologue,
877 so we just skip what we don't recognize. */
881 /* The frame size is just the negative of the offset (from the
882 original SP) of the last thing thing we pushed on the stack.
883 The frame offset is [new FP] - [new SP]. */
884 cache
->framesize
= -sp_offset
;
885 if (cache
->framereg
== ARM_FP_REGNUM
)
886 cache
->frameoffset
= fp_offset
- sp_offset
;
888 cache
->frameoffset
= 0;
891 static struct arm_prologue_cache
*
892 arm_make_prologue_cache (struct frame_info
*next_frame
)
895 struct arm_prologue_cache
*cache
;
896 CORE_ADDR unwound_fp
;
898 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
899 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
901 arm_scan_prologue (next_frame
, cache
);
903 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
907 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
909 /* Calculate actual addresses of saved registers using offsets
910 determined by arm_scan_prologue. */
911 for (reg
= 0; reg
< NUM_REGS
; reg
++)
912 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
913 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
918 /* Our frame ID for a normal frame is the current function's starting PC
919 and the caller's SP when we were called. */
922 arm_prologue_this_id (struct frame_info
*next_frame
,
924 struct frame_id
*this_id
)
926 struct arm_prologue_cache
*cache
;
930 if (*this_cache
== NULL
)
931 *this_cache
= arm_make_prologue_cache (next_frame
);
934 func
= frame_func_unwind (next_frame
);
936 /* This is meant to halt the backtrace at "_start". Make sure we
937 don't halt it at a generic dummy frame. */
938 if (func
<= LOWEST_PC
)
941 /* If we've hit a wall, stop. */
942 if (cache
->prev_sp
== 0)
945 id
= frame_id_build (cache
->prev_sp
, func
);
950 arm_prologue_prev_register (struct frame_info
*next_frame
,
954 enum lval_type
*lvalp
,
959 struct arm_prologue_cache
*cache
;
961 if (*this_cache
== NULL
)
962 *this_cache
= arm_make_prologue_cache (next_frame
);
965 /* If we are asked to unwind the PC, then we need to return the LR
966 instead. The saved value of PC points into this frame's
967 prologue, not the next frame's resume location. */
968 if (prev_regnum
== ARM_PC_REGNUM
)
969 prev_regnum
= ARM_LR_REGNUM
;
971 /* SP is generally not saved to the stack, but this frame is
972 identified by NEXT_FRAME's stack pointer at the time of the call.
973 The value was already reconstructed into PREV_SP. */
974 if (prev_regnum
== ARM_SP_REGNUM
)
978 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
982 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
983 optimized
, lvalp
, addrp
, realnump
, valuep
);
986 struct frame_unwind arm_prologue_unwind
= {
988 arm_prologue_this_id
,
989 arm_prologue_prev_register
992 static const struct frame_unwind
*
993 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
995 return &arm_prologue_unwind
;
998 static struct arm_prologue_cache
*
999 arm_make_stub_cache (struct frame_info
*next_frame
)
1002 struct arm_prologue_cache
*cache
;
1003 CORE_ADDR unwound_fp
;
1005 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1006 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1008 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1013 /* Our frame ID for a stub frame is the current SP and LR. */
1016 arm_stub_this_id (struct frame_info
*next_frame
,
1018 struct frame_id
*this_id
)
1020 struct arm_prologue_cache
*cache
;
1022 if (*this_cache
== NULL
)
1023 *this_cache
= arm_make_stub_cache (next_frame
);
1024 cache
= *this_cache
;
1026 *this_id
= frame_id_build (cache
->prev_sp
,
1027 frame_pc_unwind (next_frame
));
1030 struct frame_unwind arm_stub_unwind
= {
1033 arm_prologue_prev_register
1036 static const struct frame_unwind
*
1037 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1041 if (in_plt_section (frame_unwind_address_in_block (next_frame
), NULL
)
1042 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1043 return &arm_stub_unwind
;
1049 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1051 struct arm_prologue_cache
*cache
;
1053 if (*this_cache
== NULL
)
1054 *this_cache
= arm_make_prologue_cache (next_frame
);
1055 cache
= *this_cache
;
1057 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1060 struct frame_base arm_normal_base
= {
1061 &arm_prologue_unwind
,
1062 arm_normal_frame_base
,
1063 arm_normal_frame_base
,
1064 arm_normal_frame_base
1067 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1068 dummy frame. The frame ID's base needs to match the TOS value
1069 saved by save_dummy_frame_tos() and returned from
1070 arm_push_dummy_call, and the PC needs to match the dummy frame's
1073 static struct frame_id
1074 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1076 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1077 frame_pc_unwind (next_frame
));
1080 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1081 be used to construct the previous frame's ID, after looking up the
1082 containing function). */
1085 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1088 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1089 return arm_addr_bits_remove (pc
);
1093 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1095 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1098 /* When arguments must be pushed onto the stack, they go on in reverse
1099 order. The code below implements a FILO (stack) to do this. */
1104 struct stack_item
*prev
;
1108 static struct stack_item
*
1109 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1111 struct stack_item
*si
;
1112 si
= xmalloc (sizeof (struct stack_item
));
1113 si
->data
= xmalloc (len
);
1116 memcpy (si
->data
, contents
, len
);
1120 static struct stack_item
*
1121 pop_stack_item (struct stack_item
*si
)
1123 struct stack_item
*dead
= si
;
1131 /* Return the alignment (in bytes) of the given type. */
1134 arm_type_align (struct type
*t
)
1140 t
= check_typedef (t
);
1141 switch (TYPE_CODE (t
))
1144 /* Should never happen. */
1145 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1149 case TYPE_CODE_ENUM
:
1153 case TYPE_CODE_RANGE
:
1154 case TYPE_CODE_BITSTRING
:
1156 case TYPE_CODE_CHAR
:
1157 case TYPE_CODE_BOOL
:
1158 return TYPE_LENGTH (t
);
1160 case TYPE_CODE_ARRAY
:
1161 case TYPE_CODE_COMPLEX
:
1162 /* TODO: What about vector types? */
1163 return arm_type_align (TYPE_TARGET_TYPE (t
));
1165 case TYPE_CODE_STRUCT
:
1166 case TYPE_CODE_UNION
:
1168 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1170 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1178 /* We currently only support passing parameters in integer registers. This
1179 conforms with GCC's default model. Several other variants exist and
1180 we should probably support some of them based on the selected ABI. */
1183 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1184 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1185 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1186 CORE_ADDR struct_addr
)
1191 struct stack_item
*si
= NULL
;
1193 /* Set the return address. For the ARM, the return breakpoint is
1194 always at BP_ADDR. */
1195 /* XXX Fix for Thumb. */
1196 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1198 /* Walk through the list of args and determine how large a temporary
1199 stack is required. Need to take care here as structs may be
1200 passed on the stack, and we have to to push them. */
1203 argreg
= ARM_A1_REGNUM
;
1206 /* The struct_return pointer occupies the first parameter
1207 passing register. */
1211 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1212 REGISTER_NAME (argreg
), paddr (struct_addr
));
1213 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1217 for (argnum
= 0; argnum
< nargs
; argnum
++)
1220 struct type
*arg_type
;
1221 struct type
*target_type
;
1222 enum type_code typecode
;
1226 arg_type
= check_typedef (value_type (args
[argnum
]));
1227 len
= TYPE_LENGTH (arg_type
);
1228 target_type
= TYPE_TARGET_TYPE (arg_type
);
1229 typecode
= TYPE_CODE (arg_type
);
1230 val
= value_contents_writeable (args
[argnum
]);
1232 align
= arm_type_align (arg_type
);
1233 /* Round alignment up to a whole number of words. */
1234 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1235 /* Different ABIs have different maximum alignments. */
1236 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1238 /* The APCS ABI only requires word alignment. */
1239 align
= INT_REGISTER_SIZE
;
1243 /* The AAPCS requires at most doubleword alignment. */
1244 if (align
> INT_REGISTER_SIZE
* 2)
1245 align
= INT_REGISTER_SIZE
* 2;
1248 /* Push stack padding for dowubleword alignment. */
1249 if (nstack
& (align
- 1))
1251 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1252 nstack
+= INT_REGISTER_SIZE
;
1255 /* Doubleword aligned quantities must go in even register pairs. */
1256 if (argreg
<= ARM_LAST_ARG_REGNUM
1257 && align
> INT_REGISTER_SIZE
1261 /* If the argument is a pointer to a function, and it is a
1262 Thumb function, create a LOCAL copy of the value and set
1263 the THUMB bit in it. */
1264 if (TYPE_CODE_PTR
== typecode
1265 && target_type
!= NULL
1266 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1268 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1269 if (arm_pc_is_thumb (regval
))
1272 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1276 /* Copy the argument to general registers or the stack in
1277 register-sized pieces. Large arguments are split between
1278 registers and stack. */
1281 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1283 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1285 /* The argument is being passed in a general purpose
1287 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1289 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1290 argnum
, REGISTER_NAME (argreg
),
1291 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1292 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1297 /* Push the arguments onto the stack. */
1299 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1301 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1302 nstack
+= DEPRECATED_REGISTER_SIZE
;
1309 /* If we have an odd number of words to push, then decrement the stack
1310 by one word now, so first stack argument will be dword aligned. */
1317 write_memory (sp
, si
->data
, si
->len
);
1318 si
= pop_stack_item (si
);
1321 /* Finally, update teh SP register. */
1322 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1328 /* Always align the frame to an 8-byte boundary. This is required on
1329 some platforms and harmless on the rest. */
1332 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1334 /* Align the stack to eight bytes. */
1335 return sp
& ~ (CORE_ADDR
) 7;
1339 print_fpu_flags (int flags
)
1341 if (flags
& (1 << 0))
1342 fputs ("IVO ", stdout
);
1343 if (flags
& (1 << 1))
1344 fputs ("DVZ ", stdout
);
1345 if (flags
& (1 << 2))
1346 fputs ("OFL ", stdout
);
1347 if (flags
& (1 << 3))
1348 fputs ("UFL ", stdout
);
1349 if (flags
& (1 << 4))
1350 fputs ("INX ", stdout
);
1354 /* Print interesting information about the floating point processor
1355 (if present) or emulator. */
1357 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1358 struct frame_info
*frame
, const char *args
)
1360 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1363 type
= (status
>> 24) & 127;
1364 if (status
& (1 << 31))
1365 printf (_("Hardware FPU type %d\n"), type
);
1367 printf (_("Software FPU type %d\n"), type
);
1368 /* i18n: [floating point unit] mask */
1369 fputs (_("mask: "), stdout
);
1370 print_fpu_flags (status
>> 16);
1371 /* i18n: [floating point unit] flags */
1372 fputs (_("flags: "), stdout
);
1373 print_fpu_flags (status
);
1376 /* Return the GDB type object for the "standard" data type of data in
1379 static struct type
*
1380 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1382 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1383 return builtin_type_arm_ext
;
1384 else if (regnum
== ARM_SP_REGNUM
)
1385 return builtin_type_void_data_ptr
;
1386 else if (regnum
== ARM_PC_REGNUM
)
1387 return builtin_type_void_func_ptr
;
1388 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1389 /* These registers are only supported on targets which supply
1390 an XML description. */
1391 return builtin_type_int0
;
1393 return builtin_type_uint32
;
1396 /* Map a DWARF register REGNUM onto the appropriate GDB register
1400 arm_dwarf_reg_to_regnum (int reg
)
1402 /* Core integer regs. */
1403 if (reg
>= 0 && reg
<= 15)
1406 /* Legacy FPA encoding. These were once used in a way which
1407 overlapped with VFP register numbering, so their use is
1408 discouraged, but GDB doesn't support the ARM toolchain
1409 which used them for VFP. */
1410 if (reg
>= 16 && reg
<= 23)
1411 return ARM_F0_REGNUM
+ reg
- 16;
1413 /* New assignments for the FPA registers. */
1414 if (reg
>= 96 && reg
<= 103)
1415 return ARM_F0_REGNUM
+ reg
- 96;
1417 /* WMMX register assignments. */
1418 if (reg
>= 104 && reg
<= 111)
1419 return ARM_WCGR0_REGNUM
+ reg
- 104;
1421 if (reg
>= 112 && reg
<= 127)
1422 return ARM_WR0_REGNUM
+ reg
- 112;
1424 if (reg
>= 192 && reg
<= 199)
1425 return ARM_WC0_REGNUM
+ reg
- 192;
1430 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1432 arm_register_sim_regno (int regnum
)
1435 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1437 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1438 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1440 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1441 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1443 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1444 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1446 if (reg
< NUM_GREGS
)
1447 return SIM_ARM_R0_REGNUM
+ reg
;
1450 if (reg
< NUM_FREGS
)
1451 return SIM_ARM_FP0_REGNUM
+ reg
;
1454 if (reg
< NUM_SREGS
)
1455 return SIM_ARM_FPS_REGNUM
+ reg
;
1458 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1461 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1462 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1463 It is thought that this is is the floating-point register format on
1464 little-endian systems. */
1467 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1471 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1472 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1474 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1476 floatformat_from_doublest (fmt
, &d
, dbl
);
1480 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1483 floatformat_to_doublest (fmt
, ptr
, &d
);
1484 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1485 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1487 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1492 condition_true (unsigned long cond
, unsigned long status_reg
)
1494 if (cond
== INST_AL
|| cond
== INST_NV
)
1500 return ((status_reg
& FLAG_Z
) != 0);
1502 return ((status_reg
& FLAG_Z
) == 0);
1504 return ((status_reg
& FLAG_C
) != 0);
1506 return ((status_reg
& FLAG_C
) == 0);
1508 return ((status_reg
& FLAG_N
) != 0);
1510 return ((status_reg
& FLAG_N
) == 0);
1512 return ((status_reg
& FLAG_V
) != 0);
1514 return ((status_reg
& FLAG_V
) == 0);
1516 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1518 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1520 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1522 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1524 return (((status_reg
& FLAG_Z
) == 0) &&
1525 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1527 return (((status_reg
& FLAG_Z
) != 0) ||
1528 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1533 /* Support routines for single stepping. Calculate the next PC value. */
1534 #define submask(x) ((1L << ((x) + 1)) - 1)
1535 #define bit(obj,st) (((obj) >> (st)) & 1)
1536 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1537 #define sbits(obj,st,fn) \
1538 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1539 #define BranchDest(addr,instr) \
1540 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1543 static unsigned long
1544 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1545 unsigned long status_reg
)
1547 unsigned long res
, shift
;
1548 int rm
= bits (inst
, 0, 3);
1549 unsigned long shifttype
= bits (inst
, 5, 6);
1553 int rs
= bits (inst
, 8, 11);
1554 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1557 shift
= bits (inst
, 7, 11);
1560 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1561 + (bit (inst
, 4) ? 12 : 8))
1562 : read_register (rm
));
1567 res
= shift
>= 32 ? 0 : res
<< shift
;
1571 res
= shift
>= 32 ? 0 : res
>> shift
;
1577 res
= ((res
& 0x80000000L
)
1578 ? ~((~res
) >> shift
) : res
>> shift
);
1581 case 3: /* ROR/RRX */
1584 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1586 res
= (res
>> shift
) | (res
<< (32 - shift
));
1590 return res
& 0xffffffff;
1593 /* Return number of 1-bits in VAL. */
1596 bitcount (unsigned long val
)
1599 for (nbits
= 0; val
!= 0; nbits
++)
1600 val
&= val
- 1; /* delete rightmost 1-bit in val */
1605 thumb_get_next_pc (CORE_ADDR pc
)
1607 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1608 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1609 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1610 unsigned long offset
;
1612 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1616 /* Fetch the saved PC from the stack. It's stored above
1617 all of the other registers. */
1618 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1619 sp
= read_register (ARM_SP_REGNUM
);
1620 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1621 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1623 error (_("Infinite loop detected"));
1625 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1627 unsigned long status
= read_register (ARM_PS_REGNUM
);
1628 unsigned long cond
= bits (inst1
, 8, 11);
1629 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1630 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1632 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1634 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1636 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1638 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1639 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1640 nextpc
= pc_val
+ offset
;
1641 /* For BLX make sure to clear the low bits. */
1642 if (bits (inst2
, 11, 12) == 1)
1643 nextpc
= nextpc
& 0xfffffffc;
1645 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1647 if (bits (inst1
, 3, 6) == 0x0f)
1650 nextpc
= read_register (bits (inst1
, 3, 6));
1652 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1654 error (_("Infinite loop detected"));
1661 arm_get_next_pc (CORE_ADDR pc
)
1663 unsigned long pc_val
;
1664 unsigned long this_instr
;
1665 unsigned long status
;
1668 if (arm_pc_is_thumb (pc
))
1669 return thumb_get_next_pc (pc
);
1671 pc_val
= (unsigned long) pc
;
1672 this_instr
= read_memory_unsigned_integer (pc
, 4);
1673 status
= read_register (ARM_PS_REGNUM
);
1674 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1676 if (condition_true (bits (this_instr
, 28, 31), status
))
1678 switch (bits (this_instr
, 24, 27))
1681 case 0x1: /* data processing */
1685 unsigned long operand1
, operand2
, result
= 0;
1689 if (bits (this_instr
, 12, 15) != 15)
1692 if (bits (this_instr
, 22, 25) == 0
1693 && bits (this_instr
, 4, 7) == 9) /* multiply */
1694 error (_("Invalid update to pc in instruction"));
1696 /* BX <reg>, BLX <reg> */
1697 if (bits (this_instr
, 4, 27) == 0x12fff1
1698 || bits (this_instr
, 4, 27) == 0x12fff3)
1700 rn
= bits (this_instr
, 0, 3);
1701 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1702 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1705 error (_("Infinite loop detected"));
1710 /* Multiply into PC */
1711 c
= (status
& FLAG_C
) ? 1 : 0;
1712 rn
= bits (this_instr
, 16, 19);
1713 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1715 if (bit (this_instr
, 25))
1717 unsigned long immval
= bits (this_instr
, 0, 7);
1718 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1719 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1722 else /* operand 2 is a shifted register */
1723 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1725 switch (bits (this_instr
, 21, 24))
1728 result
= operand1
& operand2
;
1732 result
= operand1
^ operand2
;
1736 result
= operand1
- operand2
;
1740 result
= operand2
- operand1
;
1744 result
= operand1
+ operand2
;
1748 result
= operand1
+ operand2
+ c
;
1752 result
= operand1
- operand2
+ c
;
1756 result
= operand2
- operand1
+ c
;
1762 case 0xb: /* tst, teq, cmp, cmn */
1763 result
= (unsigned long) nextpc
;
1767 result
= operand1
| operand2
;
1771 /* Always step into a function. */
1776 result
= operand1
& ~operand2
;
1783 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1786 error (_("Infinite loop detected"));
1791 case 0x5: /* data transfer */
1794 if (bit (this_instr
, 20))
1797 if (bits (this_instr
, 12, 15) == 15)
1803 if (bit (this_instr
, 22))
1804 error (_("Invalid update to pc in instruction"));
1806 /* byte write to PC */
1807 rn
= bits (this_instr
, 16, 19);
1808 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1809 if (bit (this_instr
, 24))
1812 int c
= (status
& FLAG_C
) ? 1 : 0;
1813 unsigned long offset
=
1814 (bit (this_instr
, 25)
1815 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1816 : bits (this_instr
, 0, 11));
1818 if (bit (this_instr
, 23))
1823 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1826 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1829 error (_("Infinite loop detected"));
1835 case 0x9: /* block transfer */
1836 if (bit (this_instr
, 20))
1839 if (bit (this_instr
, 15))
1844 if (bit (this_instr
, 23))
1847 unsigned long reglist
= bits (this_instr
, 0, 14);
1848 offset
= bitcount (reglist
) * 4;
1849 if (bit (this_instr
, 24)) /* pre */
1852 else if (bit (this_instr
, 24))
1856 unsigned long rn_val
=
1857 read_register (bits (this_instr
, 16, 19));
1859 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1863 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1865 error (_("Infinite loop detected"));
1870 case 0xb: /* branch & link */
1871 case 0xa: /* branch */
1873 nextpc
= BranchDest (pc
, this_instr
);
1876 if (bits (this_instr
, 28, 31) == INST_NV
)
1877 nextpc
|= bit (this_instr
, 24) << 1;
1879 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1881 error (_("Infinite loop detected"));
1887 case 0xe: /* coproc ops */
1892 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1900 /* single_step() is called just before we want to resume the inferior,
1901 if we want to single-step it but there is no hardware or kernel
1902 single-step support. We find the target of the coming instruction
1905 single_step() is also called just after the inferior stops. If we
1906 had set up a simulated single-step, we undo our damage. */
1909 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1911 /* NOTE: This may insert the wrong breakpoint instruction when
1912 single-stepping over a mode-changing instruction, if the
1913 CPSR heuristics are used. */
1917 CORE_ADDR next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1919 insert_single_step_breakpoint (next_pc
);
1922 remove_single_step_breakpoints ();
1925 #include "bfd-in2.h"
1926 #include "libcoff.h"
1929 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1931 if (arm_pc_is_thumb (memaddr
))
1933 static asymbol
*asym
;
1934 static combined_entry_type ce
;
1935 static struct coff_symbol_struct csym
;
1936 static struct bfd fake_bfd
;
1937 static bfd_target fake_target
;
1939 if (csym
.native
== NULL
)
1941 /* Create a fake symbol vector containing a Thumb symbol.
1942 This is solely so that the code in print_insn_little_arm()
1943 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1944 the presence of a Thumb symbol and switch to decoding
1945 Thumb instructions. */
1947 fake_target
.flavour
= bfd_target_coff_flavour
;
1948 fake_bfd
.xvec
= &fake_target
;
1949 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1951 csym
.symbol
.the_bfd
= &fake_bfd
;
1952 csym
.symbol
.name
= "fake";
1953 asym
= (asymbol
*) & csym
;
1956 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1957 info
->symbols
= &asym
;
1960 info
->symbols
= NULL
;
1962 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1963 return print_insn_big_arm (memaddr
, info
);
1965 return print_insn_little_arm (memaddr
, info
);
1968 /* The following define instruction sequences that will cause ARM
1969 cpu's to take an undefined instruction trap. These are used to
1970 signal a breakpoint to GDB.
1972 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1973 modes. A different instruction is required for each mode. The ARM
1974 cpu's can also be big or little endian. Thus four different
1975 instructions are needed to support all cases.
1977 Note: ARMv4 defines several new instructions that will take the
1978 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1979 not in fact add the new instructions. The new undefined
1980 instructions in ARMv4 are all instructions that had no defined
1981 behaviour in earlier chips. There is no guarantee that they will
1982 raise an exception, but may be treated as NOP's. In practice, it
1983 may only safe to rely on instructions matching:
1985 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1986 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1987 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1989 Even this may only true if the condition predicate is true. The
1990 following use a condition predicate of ALWAYS so it is always TRUE.
1992 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1993 and NetBSD all use a software interrupt rather than an undefined
1994 instruction to force a trap. This can be handled by by the
1995 abi-specific code during establishment of the gdbarch vector. */
1998 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1999 override these definitions. */
2000 #ifndef ARM_LE_BREAKPOINT
2001 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2003 #ifndef ARM_BE_BREAKPOINT
2004 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2006 #ifndef THUMB_LE_BREAKPOINT
2007 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2009 #ifndef THUMB_BE_BREAKPOINT
2010 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2013 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2014 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2015 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2016 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2018 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2019 the program counter value to determine whether a 16-bit or 32-bit
2020 breakpoint should be used. It returns a pointer to a string of
2021 bytes that encode a breakpoint instruction, stores the length of
2022 the string to *lenptr, and adjusts the program counter (if
2023 necessary) to point to the actual memory location where the
2024 breakpoint should be inserted. */
2026 static const unsigned char *
2027 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2029 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2031 if (arm_pc_is_thumb (*pcptr
))
2033 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2034 *lenptr
= tdep
->thumb_breakpoint_size
;
2035 return tdep
->thumb_breakpoint
;
2039 *lenptr
= tdep
->arm_breakpoint_size
;
2040 return tdep
->arm_breakpoint
;
2044 /* Extract from an array REGBUF containing the (raw) register state a
2045 function return value of type TYPE, and copy that, in virtual
2046 format, into VALBUF. */
2049 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2052 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2054 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2058 /* The value is in register F0 in internal format. We need to
2059 extract the raw value and then convert it to the desired
2061 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2063 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2064 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2069 case ARM_FLOAT_SOFT_FPA
:
2070 case ARM_FLOAT_SOFT_VFP
:
2071 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2072 if (TYPE_LENGTH (type
) > 4)
2073 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2074 valbuf
+ INT_REGISTER_SIZE
);
2079 (__FILE__
, __LINE__
,
2080 _("arm_extract_return_value: Floating point model not supported"));
2084 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2085 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2086 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2087 || TYPE_CODE (type
) == TYPE_CODE_PTR
2088 || TYPE_CODE (type
) == TYPE_CODE_REF
2089 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2091 /* If the the type is a plain integer, then the access is
2092 straight-forward. Otherwise we have to play around a bit more. */
2093 int len
= TYPE_LENGTH (type
);
2094 int regno
= ARM_A1_REGNUM
;
2099 /* By using store_unsigned_integer we avoid having to do
2100 anything special for small big-endian values. */
2101 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2102 store_unsigned_integer (valbuf
,
2103 (len
> INT_REGISTER_SIZE
2104 ? INT_REGISTER_SIZE
: len
),
2106 len
-= INT_REGISTER_SIZE
;
2107 valbuf
+= INT_REGISTER_SIZE
;
2112 /* For a structure or union the behaviour is as if the value had
2113 been stored to word-aligned memory and then loaded into
2114 registers with 32-bit load instruction(s). */
2115 int len
= TYPE_LENGTH (type
);
2116 int regno
= ARM_A1_REGNUM
;
2117 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2121 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2122 memcpy (valbuf
, tmpbuf
,
2123 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2124 len
-= INT_REGISTER_SIZE
;
2125 valbuf
+= INT_REGISTER_SIZE
;
2131 /* Will a function return an aggregate type in memory or in a
2132 register? Return 0 if an aggregate type can be returned in a
2133 register, 1 if it must be returned in memory. */
2136 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2139 enum type_code code
;
2141 CHECK_TYPEDEF (type
);
2143 /* In the ARM ABI, "integer" like aggregate types are returned in
2144 registers. For an aggregate type to be integer like, its size
2145 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2146 offset of each addressable subfield must be zero. Note that bit
2147 fields are not addressable, and all addressable subfields of
2148 unions always start at offset zero.
2150 This function is based on the behaviour of GCC 2.95.1.
2151 See: gcc/arm.c: arm_return_in_memory() for details.
2153 Note: All versions of GCC before GCC 2.95.2 do not set up the
2154 parameters correctly for a function returning the following
2155 structure: struct { float f;}; This should be returned in memory,
2156 not a register. Richard Earnshaw sent me a patch, but I do not
2157 know of any way to detect if a function like the above has been
2158 compiled with the correct calling convention. */
2160 /* All aggregate types that won't fit in a register must be returned
2162 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2167 /* The AAPCS says all aggregates not larger than a word are returned
2169 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2172 /* The only aggregate types that can be returned in a register are
2173 structs and unions. Arrays must be returned in memory. */
2174 code
= TYPE_CODE (type
);
2175 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2180 /* Assume all other aggregate types can be returned in a register.
2181 Run a check for structures, unions and arrays. */
2184 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2187 /* Need to check if this struct/union is "integer" like. For
2188 this to be true, its size must be less than or equal to
2189 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2190 subfield must be zero. Note that bit fields are not
2191 addressable, and unions always start at offset zero. If any
2192 of the subfields is a floating point type, the struct/union
2193 cannot be an integer type. */
2195 /* For each field in the object, check:
2196 1) Is it FP? --> yes, nRc = 1;
2197 2) Is it addressable (bitpos != 0) and
2198 not packed (bitsize == 0)?
2202 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2204 enum type_code field_type_code
;
2205 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2207 /* Is it a floating point type field? */
2208 if (field_type_code
== TYPE_CODE_FLT
)
2214 /* If bitpos != 0, then we have to care about it. */
2215 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2217 /* Bitfields are not addressable. If the field bitsize is
2218 zero, then the field is not packed. Hence it cannot be
2219 a bitfield or any other packed type. */
2220 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2232 /* Write into appropriate registers a function return value of type
2233 TYPE, given in virtual format. */
2236 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2237 const gdb_byte
*valbuf
)
2239 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2241 char buf
[MAX_REGISTER_SIZE
];
2243 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2247 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2248 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2251 case ARM_FLOAT_SOFT_FPA
:
2252 case ARM_FLOAT_SOFT_VFP
:
2253 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2254 if (TYPE_LENGTH (type
) > 4)
2255 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2256 valbuf
+ INT_REGISTER_SIZE
);
2261 (__FILE__
, __LINE__
,
2262 _("arm_store_return_value: Floating point model not supported"));
2266 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2267 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2268 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2269 || TYPE_CODE (type
) == TYPE_CODE_PTR
2270 || TYPE_CODE (type
) == TYPE_CODE_REF
2271 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2273 if (TYPE_LENGTH (type
) <= 4)
2275 /* Values of one word or less are zero/sign-extended and
2277 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2278 LONGEST val
= unpack_long (type
, valbuf
);
2280 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2281 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2285 /* Integral values greater than one word are stored in consecutive
2286 registers starting with r0. This will always be a multiple of
2287 the regiser size. */
2288 int len
= TYPE_LENGTH (type
);
2289 int regno
= ARM_A1_REGNUM
;
2293 regcache_cooked_write (regs
, regno
++, valbuf
);
2294 len
-= INT_REGISTER_SIZE
;
2295 valbuf
+= INT_REGISTER_SIZE
;
2301 /* For a structure or union the behaviour is as if the value had
2302 been stored to word-aligned memory and then loaded into
2303 registers with 32-bit load instruction(s). */
2304 int len
= TYPE_LENGTH (type
);
2305 int regno
= ARM_A1_REGNUM
;
2306 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2310 memcpy (tmpbuf
, valbuf
,
2311 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2312 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2313 len
-= INT_REGISTER_SIZE
;
2314 valbuf
+= INT_REGISTER_SIZE
;
2320 /* Handle function return values. */
2322 static enum return_value_convention
2323 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2324 struct regcache
*regcache
, gdb_byte
*readbuf
,
2325 const gdb_byte
*writebuf
)
2327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2329 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2330 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2331 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2333 if (tdep
->struct_return
== pcc_struct_return
2334 || arm_return_in_memory (gdbarch
, valtype
))
2335 return RETURN_VALUE_STRUCT_CONVENTION
;
2339 arm_store_return_value (valtype
, regcache
, writebuf
);
2342 arm_extract_return_value (valtype
, regcache
, readbuf
);
2344 return RETURN_VALUE_REGISTER_CONVENTION
;
2349 arm_get_longjmp_target (CORE_ADDR
*pc
)
2352 char buf
[INT_REGISTER_SIZE
];
2353 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2355 jb_addr
= read_register (ARM_A1_REGNUM
);
2357 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2361 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2365 /* Return non-zero if the PC is inside a thumb call thunk. */
2368 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2370 CORE_ADDR start_addr
;
2372 /* Find the starting address of the function containing the PC. If
2373 the caller didn't give us a name, look it up at the same time. */
2374 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2378 return strncmp (name
, "_call_via_r", 11) == 0;
2381 /* If PC is in a Thumb call or return stub, return the address of the
2382 target PC, which is in a register. The thunk functions are called
2383 _called_via_xx, where x is the register name. The possible names
2384 are r0-r9, sl, fp, ip, sp, and lr. */
2387 arm_skip_stub (CORE_ADDR pc
)
2390 CORE_ADDR start_addr
;
2392 /* Find the starting address and name of the function containing the PC. */
2393 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2396 /* Call thunks always start with "_call_via_". */
2397 if (strncmp (name
, "_call_via_", 10) == 0)
2399 /* Use the name suffix to determine which register contains the
2401 static char *table
[15] =
2402 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2403 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2407 for (regno
= 0; regno
<= 14; regno
++)
2408 if (strcmp (&name
[10], table
[regno
]) == 0)
2409 return read_register (regno
);
2412 return 0; /* not a stub */
2416 set_arm_command (char *args
, int from_tty
)
2418 printf_unfiltered (_("\
2419 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2420 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2424 show_arm_command (char *args
, int from_tty
)
2426 cmd_show_list (showarmcmdlist
, from_tty
, "");
2430 arm_update_current_architecture (void)
2432 struct gdbarch_info info
;
2434 /* If the current architecture is not ARM, we have nothing to do. */
2435 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2438 /* Update the architecture. */
2439 gdbarch_info_init (&info
);
2441 if (!gdbarch_update_p (info
))
2442 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2446 set_fp_model_sfunc (char *args
, int from_tty
,
2447 struct cmd_list_element
*c
)
2449 enum arm_float_model fp_model
;
2451 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2452 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2454 arm_fp_model
= fp_model
;
2458 if (fp_model
== ARM_FLOAT_LAST
)
2459 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2462 arm_update_current_architecture ();
2466 show_fp_model (struct ui_file
*file
, int from_tty
,
2467 struct cmd_list_element
*c
, const char *value
)
2469 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2471 if (arm_fp_model
== ARM_FLOAT_AUTO
2472 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2473 fprintf_filtered (file
, _("\
2474 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2475 fp_model_strings
[tdep
->fp_model
]);
2477 fprintf_filtered (file
, _("\
2478 The current ARM floating point model is \"%s\".\n"),
2479 fp_model_strings
[arm_fp_model
]);
2483 arm_set_abi (char *args
, int from_tty
,
2484 struct cmd_list_element
*c
)
2486 enum arm_abi_kind arm_abi
;
2488 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2489 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2491 arm_abi_global
= arm_abi
;
2495 if (arm_abi
== ARM_ABI_LAST
)
2496 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2499 arm_update_current_architecture ();
2503 arm_show_abi (struct ui_file
*file
, int from_tty
,
2504 struct cmd_list_element
*c
, const char *value
)
2506 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2508 if (arm_abi_global
== ARM_ABI_AUTO
2509 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2510 fprintf_filtered (file
, _("\
2511 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2512 arm_abi_strings
[tdep
->arm_abi
]);
2514 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2518 /* If the user changes the register disassembly style used for info
2519 register and other commands, we have to also switch the style used
2520 in opcodes for disassembly output. This function is run in the "set
2521 arm disassembly" command, and does that. */
2524 set_disassembly_style_sfunc (char *args
, int from_tty
,
2525 struct cmd_list_element
*c
)
2527 set_disassembly_style ();
2530 /* Return the ARM register name corresponding to register I. */
2532 arm_register_name (int i
)
2534 if (i
>= ARRAY_SIZE (arm_register_names
))
2535 /* These registers are only supported on targets which supply
2536 an XML description. */
2539 return arm_register_names
[i
];
2543 set_disassembly_style (void)
2547 /* Find the style that the user wants. */
2548 for (current
= 0; current
< num_disassembly_options
; current
++)
2549 if (disassembly_style
== valid_disassembly_styles
[current
])
2551 gdb_assert (current
< num_disassembly_options
);
2553 /* Synchronize the disassembler. */
2554 set_arm_regname_option (current
);
2557 /* Test whether the coff symbol specific value corresponds to a Thumb
2561 coff_sym_is_thumb (int val
)
2563 return (val
== C_THUMBEXT
||
2564 val
== C_THUMBSTAT
||
2565 val
== C_THUMBEXTFUNC
||
2566 val
== C_THUMBSTATFUNC
||
2567 val
== C_THUMBLABEL
);
2570 /* arm_coff_make_msymbol_special()
2571 arm_elf_make_msymbol_special()
2573 These functions test whether the COFF or ELF symbol corresponds to
2574 an address in thumb code, and set a "special" bit in a minimal
2575 symbol to indicate that it does. */
2578 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2580 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2582 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2584 MSYMBOL_SET_SPECIAL (msym
);
2588 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2590 if (coff_sym_is_thumb (val
))
2591 MSYMBOL_SET_SPECIAL (msym
);
2595 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2597 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2599 /* If necessary, set the T bit. */
2602 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2603 if (arm_pc_is_thumb (pc
))
2604 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2606 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2610 static struct value
*
2611 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2613 const int *reg_p
= baton
;
2614 return value_of_register (*reg_p
, frame
);
2617 static enum gdb_osabi
2618 arm_elf_osabi_sniffer (bfd
*abfd
)
2620 unsigned int elfosabi
;
2621 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2623 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2625 if (elfosabi
== ELFOSABI_ARM
)
2626 /* GNU tools use this value. Check note sections in this case,
2628 bfd_map_over_sections (abfd
,
2629 generic_elf_osabi_sniff_abi_tag_sections
,
2632 /* Anything else will be handled by the generic ELF sniffer. */
2637 /* Initialize the current architecture based on INFO. If possible,
2638 re-use an architecture from ARCHES, which is a list of
2639 architectures already created during this debugging session.
2641 Called e.g. at program startup, when reading a core file, and when
2642 reading a binary file. */
2644 static struct gdbarch
*
2645 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2647 struct gdbarch_tdep
*tdep
;
2648 struct gdbarch
*gdbarch
;
2649 struct gdbarch_list
*best_arch
;
2650 enum arm_abi_kind arm_abi
= arm_abi_global
;
2651 enum arm_float_model fp_model
= arm_fp_model
;
2652 struct tdesc_arch_data
*tdesc_data
= NULL
;
2654 int have_fpa_registers
= 1;
2656 /* Check any target description for validity. */
2657 if (tdesc_has_registers (info
.target_desc
))
2659 /* For most registers we require GDB's default names; but also allow
2660 the numeric names for sp / lr / pc, as a convenience. */
2661 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2662 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2663 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2665 const struct tdesc_feature
*feature
;
2668 feature
= tdesc_find_feature (info
.target_desc
,
2669 "org.gnu.gdb.arm.core");
2670 if (feature
== NULL
)
2673 tdesc_data
= tdesc_data_alloc ();
2676 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2677 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2678 arm_register_names
[i
]);
2679 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2682 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2685 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2688 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2689 ARM_PS_REGNUM
, "cpsr");
2693 tdesc_data_cleanup (tdesc_data
);
2697 feature
= tdesc_find_feature (info
.target_desc
,
2698 "org.gnu.gdb.arm.fpa");
2699 if (feature
!= NULL
)
2702 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2703 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2704 arm_register_names
[i
]);
2707 tdesc_data_cleanup (tdesc_data
);
2712 have_fpa_registers
= 0;
2714 feature
= tdesc_find_feature (info
.target_desc
,
2715 "org.gnu.gdb.xscale.iwmmxt");
2716 if (feature
!= NULL
)
2718 static const char *const iwmmxt_names
[] = {
2719 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2720 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2721 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2722 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2726 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2728 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2729 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2731 /* Check for the control registers, but do not fail if they
2733 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2734 tdesc_numbered_register (feature
, tdesc_data
, i
,
2735 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2737 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2739 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2740 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2744 tdesc_data_cleanup (tdesc_data
);
2750 /* If we have an object to base this architecture on, try to determine
2753 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2755 int ei_osabi
, e_flags
;
2757 switch (bfd_get_flavour (info
.abfd
))
2759 case bfd_target_aout_flavour
:
2760 /* Assume it's an old APCS-style ABI. */
2761 arm_abi
= ARM_ABI_APCS
;
2764 case bfd_target_coff_flavour
:
2765 /* Assume it's an old APCS-style ABI. */
2767 arm_abi
= ARM_ABI_APCS
;
2770 case bfd_target_elf_flavour
:
2771 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2772 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2774 if (ei_osabi
== ELFOSABI_ARM
)
2776 /* GNU tools used to use this value, but do not for EABI
2777 objects. There's nowhere to tag an EABI version
2778 anyway, so assume APCS. */
2779 arm_abi
= ARM_ABI_APCS
;
2781 else if (ei_osabi
== ELFOSABI_NONE
)
2783 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2787 case EF_ARM_EABI_UNKNOWN
:
2788 /* Assume GNU tools. */
2789 arm_abi
= ARM_ABI_APCS
;
2792 case EF_ARM_EABI_VER4
:
2793 case EF_ARM_EABI_VER5
:
2794 arm_abi
= ARM_ABI_AAPCS
;
2795 /* EABI binaries default to VFP float ordering. */
2796 if (fp_model
== ARM_FLOAT_AUTO
)
2797 fp_model
= ARM_FLOAT_SOFT_VFP
;
2801 /* Leave it as "auto". */
2802 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2807 if (fp_model
== ARM_FLOAT_AUTO
)
2809 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2811 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
2814 /* Leave it as "auto". Strictly speaking this case
2815 means FPA, but almost nobody uses that now, and
2816 many toolchains fail to set the appropriate bits
2817 for the floating-point model they use. */
2819 case EF_ARM_SOFT_FLOAT
:
2820 fp_model
= ARM_FLOAT_SOFT_FPA
;
2822 case EF_ARM_VFP_FLOAT
:
2823 fp_model
= ARM_FLOAT_VFP
;
2825 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
2826 fp_model
= ARM_FLOAT_SOFT_VFP
;
2833 /* Leave it as "auto". */
2838 /* Now that we have inferred any architecture settings that we
2839 can, try to inherit from the last ARM ABI. */
2842 if (arm_abi
== ARM_ABI_AUTO
)
2843 arm_abi
= gdbarch_tdep (arches
->gdbarch
)->arm_abi
;
2845 if (fp_model
== ARM_FLOAT_AUTO
)
2846 fp_model
= gdbarch_tdep (arches
->gdbarch
)->fp_model
;
2850 /* There was no prior ARM architecture; fill in default values. */
2852 if (arm_abi
== ARM_ABI_AUTO
)
2853 arm_abi
= ARM_ABI_APCS
;
2855 /* We used to default to FPA for generic ARM, but almost nobody
2856 uses that now, and we now provide a way for the user to force
2857 the model. So default to the most useful variant. */
2858 if (fp_model
== ARM_FLOAT_AUTO
)
2859 fp_model
= ARM_FLOAT_SOFT_FPA
;
2862 /* If there is already a candidate, use it. */
2863 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2865 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2867 if (arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2870 if (fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2873 /* Found a match. */
2877 if (best_arch
!= NULL
)
2879 if (tdesc_data
!= NULL
)
2880 tdesc_data_cleanup (tdesc_data
);
2881 return best_arch
->gdbarch
;
2884 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2885 gdbarch
= gdbarch_alloc (&info
, tdep
);
2887 /* Record additional information about the architecture we are defining.
2888 These are gdbarch discriminators, like the OSABI. */
2889 tdep
->arm_abi
= arm_abi
;
2890 tdep
->fp_model
= fp_model
;
2891 tdep
->have_fpa_registers
= have_fpa_registers
;
2894 switch (info
.byte_order
)
2896 case BFD_ENDIAN_BIG
:
2897 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2898 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2899 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2900 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2904 case BFD_ENDIAN_LITTLE
:
2905 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2906 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2907 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2908 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2913 internal_error (__FILE__
, __LINE__
,
2914 _("arm_gdbarch_init: bad byte order for float format"));
2917 /* On ARM targets char defaults to unsigned. */
2918 set_gdbarch_char_signed (gdbarch
, 0);
2920 /* This should be low enough for everything. */
2921 tdep
->lowest_pc
= 0x20;
2922 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2924 /* The default, for both APCS and AAPCS, is to return small
2925 structures in registers. */
2926 tdep
->struct_return
= reg_struct_return
;
2928 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2929 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
2931 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2933 /* Frame handling. */
2934 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2935 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2936 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2938 frame_base_set_default (gdbarch
, &arm_normal_base
);
2940 /* Address manipulation. */
2941 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2942 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2944 /* Advance PC across function entry code. */
2945 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2947 /* The stack grows downward. */
2948 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2950 /* Breakpoint manipulation. */
2951 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2953 /* Information about registers, etc. */
2954 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2955 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2956 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2957 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
2958 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2960 /* This "info float" is FPA-specific. Use the generic version if we
2962 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2963 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2965 /* Internal <-> external register number maps. */
2966 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2967 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2968 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2970 /* Integer registers are 4 bytes. */
2971 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2972 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2974 /* Returning results. */
2975 set_gdbarch_return_value (gdbarch
, arm_return_value
);
2977 /* Single stepping. */
2978 /* XXX For an RDI target we should ask the target if it can single-step. */
2979 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2982 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2984 /* Minsymbol frobbing. */
2985 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2986 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2987 arm_coff_make_msymbol_special
);
2989 /* Virtual tables. */
2990 set_gdbarch_vbit_in_delta (gdbarch
, 1);
2992 /* Hook in the ABI-specific overrides, if they have been registered. */
2993 gdbarch_init_osabi (info
, gdbarch
);
2995 /* Add some default predicates. */
2996 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
2997 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2998 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
3000 /* Now we have tuned the configuration, set a few final things,
3001 based on what the OS ABI has told us. */
3003 if (tdep
->jb_pc
>= 0)
3004 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3006 /* Floating point sizes and format. */
3007 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3008 if (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
)
3010 set_gdbarch_double_format
3011 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3012 set_gdbarch_long_double_format
3013 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3017 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3018 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3022 tdesc_use_registers (gdbarch
, tdesc_data
);
3024 /* Add standard register aliases. We add aliases even for those
3025 nanes which are used by the current architecture - it's simpler,
3026 and does no harm, since nothing ever lists user registers. */
3027 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3028 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3029 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3035 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3037 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3042 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3043 (unsigned long) tdep
->lowest_pc
);
3046 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3049 _initialize_arm_tdep (void)
3051 struct ui_file
*stb
;
3053 struct cmd_list_element
*new_set
, *new_show
;
3054 const char *setname
;
3055 const char *setdesc
;
3056 const char *const *regnames
;
3058 static char *helptext
;
3059 char regdesc
[1024], *rdptr
= regdesc
;
3060 size_t rest
= sizeof (regdesc
);
3062 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3064 /* Register an ELF OS ABI sniffer for ARM binaries. */
3065 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3066 bfd_target_elf_flavour
,
3067 arm_elf_osabi_sniffer
);
3069 /* Get the number of possible sets of register names defined in opcodes. */
3070 num_disassembly_options
= get_arm_regname_num_options ();
3072 /* Add root prefix command for all "set arm"/"show arm" commands. */
3073 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3074 _("Various ARM-specific commands."),
3075 &setarmcmdlist
, "set arm ", 0, &setlist
);
3077 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3078 _("Various ARM-specific commands."),
3079 &showarmcmdlist
, "show arm ", 0, &showlist
);
3081 /* Sync the opcode insn printer with our register viewer. */
3082 parse_arm_disassembler_option ("reg-names-std");
3084 /* Initialize the array that will be passed to
3085 add_setshow_enum_cmd(). */
3086 valid_disassembly_styles
3087 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3088 for (i
= 0; i
< num_disassembly_options
; i
++)
3090 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3091 valid_disassembly_styles
[i
] = setname
;
3092 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3095 /* When we find the default names, tell the disassembler to use
3097 if (!strcmp (setname
, "std"))
3099 disassembly_style
= setname
;
3100 set_arm_regname_option (i
);
3103 /* Mark the end of valid options. */
3104 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3106 /* Create the help text. */
3107 stb
= mem_fileopen ();
3108 fprintf_unfiltered (stb
, "%s%s%s",
3109 _("The valid values are:\n"),
3111 _("The default is \"std\"."));
3112 helptext
= ui_file_xstrdup (stb
, &length
);
3113 ui_file_delete (stb
);
3115 add_setshow_enum_cmd("disassembler", no_class
,
3116 valid_disassembly_styles
, &disassembly_style
,
3117 _("Set the disassembly style."),
3118 _("Show the disassembly style."),
3120 set_disassembly_style_sfunc
,
3121 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3122 &setarmcmdlist
, &showarmcmdlist
);
3124 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3125 _("Set usage of ARM 32-bit mode."),
3126 _("Show usage of ARM 32-bit mode."),
3127 _("When off, a 26-bit PC will be used."),
3129 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3130 &setarmcmdlist
, &showarmcmdlist
);
3132 /* Add a command to allow the user to force the FPU model. */
3133 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3134 _("Set the floating point type."),
3135 _("Show the floating point type."),
3136 _("auto - Determine the FP typefrom the OS-ABI.\n\
3137 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3138 fpa - FPA co-processor (GCC compiled).\n\
3139 softvfp - Software FP with pure-endian doubles.\n\
3140 vfp - VFP co-processor."),
3141 set_fp_model_sfunc
, show_fp_model
,
3142 &setarmcmdlist
, &showarmcmdlist
);
3144 /* Add a command to allow the user to force the ABI. */
3145 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3148 NULL
, arm_set_abi
, arm_show_abi
,
3149 &setarmcmdlist
, &showarmcmdlist
);
3151 /* Debugging flag. */
3152 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3153 _("Set ARM debugging."),
3154 _("Show ARM debugging."),
3155 _("When on, arm-specific debugging is enabled."),
3157 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3158 &setdebuglist
, &showdebuglist
);