1 /* Target-dependent code for the Acorn Risc Machine (ARM).
2 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995-1999
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
32 The following macros are actually wrong. Neither arm nor thumb can
33 or should set the lsb on addr.
34 The thumb addresses are mod 2, so (addr & 2) would be a good heuristic
35 to use when checking for thumb (see arm_pc_is_thumb() below).
36 Unfortunately, something else depends on these (incorrect) macros, so
37 fixing them actually breaks gdb. I didn't have time to investigate. Z.R.
39 /* Thumb function addresses are odd (bit 0 is set). Here are some
40 macros to test, set, or clear bit 0 of addresses. */
41 #define IS_THUMB_ADDR(addr) ((addr) & 1)
42 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
43 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
45 /* Macros to round N up or down to the next A boundary; A must be
47 #define ROUND_DOWN(n,a) ((n) & ~((a) - 1))
48 #define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1))
50 static char *apcs_register_names
[] =
51 { "a1", "a2", "a3", "a4", /* 0 1 2 3 */
52 "v1", "v2", "v3", "v4", /* 4 5 6 7 */
53 "v5", "v6", "sl", "fp", /* 8 9 10 11 */
54 "ip", "sp", "lr", "pc", /* 12 13 14 15 */
55 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
56 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
57 "fps","ps" } /* 24 25 */;
59 /* These names are the ones which gcc emits, and
60 I find them less confusing. Toggle between them
61 using the `othernames' command. */
62 static char *additional_register_names
[] =
63 { "r0", "r1", "r2", "r3", /* 0 1 2 3 */
64 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
65 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
66 "r12", "r13", "r14", "pc", /* 12 13 14 15 */
67 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
68 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
69 "fps","ps" } /* 24 25 */;
71 /* By default use the APCS registers names */
73 char **arm_register_names
= apcs_register_names
;
74 /* This is the variable the is set with "set disassembly-flavor",
75 and its legitimate values. */
76 static char apcs_flavor
[] = "apcs";
77 static char r_prefix_flavor
[] = "r-prefix";
78 static char *valid_flavors
[] = {
83 static char *disassembly_flavor
= apcs_flavor
;
85 /* This is used to keep the bfd arch_info in sync with the disassembly flavor. */
86 static void set_disassembly_flavor_sfunc
PARAMS ((char *, int, \
87 struct cmd_list_element
*));
88 static void set_disassembly_flavor ();
90 /* Should call_function allocate stack space for a struct return? */
91 /* The system C compiler uses a similar structure return convention to gcc */
93 arm_use_struct_convention (gcc_p
, type
)
97 return (TYPE_LENGTH (type
) > 4);
101 arm_frame_chain_valid (chain
, thisframe
)
103 struct frame_info
*thisframe
;
105 #define LOWEST_PC 0x20 /* the first 0x20 bytes are the trap vectors. */
106 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
109 /* Set to true if the 32-bit mode is in use. */
113 /* Flag set by arm_fix_call_dummy that tells whether the target function
114 is a Thumb function. This flag is checked by arm_push_arguments.
115 FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to
116 pass the function address as an additional parameter. */
118 static int target_is_thumb
;
120 /* Flag set by arm_fix_call_dummy that tells whether the calling function
121 is a Thumb function. This flag is checked by arm_pc_is_thumb
122 and arm_call_dummy_breakpoint_offset. */
124 static int caller_is_thumb
;
126 /* Tell if the program counter value in MEMADDR is in a Thumb function. */
129 arm_pc_is_thumb (memaddr
)
132 struct minimal_symbol
*sym
;
135 /* If bit 0 of the address is set, assume this is a Thumb address. */
136 if (IS_THUMB_ADDR (memaddr
))
139 /* Thumb function have a "special" bit set in minimal symbols */
140 sym
= lookup_minimal_symbol_by_pc (memaddr
);
143 return (MSYMBOL_IS_SPECIAL (sym
));
149 /* Tell if the program counter value in MEMADDR is in a call dummy that
150 is being called from a Thumb function. */
153 arm_pc_is_thumb_dummy (memaddr
)
156 CORE_ADDR sp
= read_sp ();
158 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 64))
159 return caller_is_thumb
;
165 arm_addr_bits_remove (val
)
168 if (arm_pc_is_thumb (val
))
169 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
171 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
175 arm_saved_pc_after_call (frame
)
176 struct frame_info
*frame
;
178 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
182 arm_frameless_function_invocation (fi
)
183 struct frame_info
*fi
;
185 CORE_ADDR func_start
, after_prologue
;
188 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
189 after_prologue
= SKIP_PROLOGUE (func_start
);
191 /* There are some frameless functions whose first two instructions
192 follow the standard APCS form, in which case after_prologue
193 will be func_start + 8. */
195 frameless
= (after_prologue
< func_start
+ 12);
199 /* A typical Thumb prologue looks like this:
203 Sometimes the latter instruction may be replaced by:
208 thumb_skip_prologue (pc
)
211 CORE_ADDR current_pc
;
213 for (current_pc
= pc
; current_pc
< pc
+ 20; current_pc
+= 2)
215 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
217 if ((insn
& 0xfe00) != 0xb400 /* push {..., r7, lr} */
218 && (insn
& 0xff00) != 0xb000 /* add sp, #simm */
219 && (insn
& 0xff00) != 0xaf00 /* add r7, sp, #imm */
220 && insn
!= 0x466f /* mov r7, sp */
221 && (insn
& 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */
228 /* APCS (ARM procedure call standard) defines the following prologue:
231 [stmfd sp!, {a1,a2,a3,a4}]
232 stmfd sp!, {...,fp,ip,lr,pc}
233 [stfe f7, [sp, #-12]!]
234 [stfe f6, [sp, #-12]!]
235 [stfe f5, [sp, #-12]!]
236 [stfe f4, [sp, #-12]!]
237 sub fp, ip, #nn // nn == 20 or 4 depending on second ins
241 arm_skip_prologue (pc
)
246 CORE_ADDR func_addr
, func_end
;
247 struct symtab_and_line sal
;
249 /* See what the symbol table says. */
251 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
253 sal
= find_pc_line (func_addr
, 0);
254 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
258 /* Check if this is Thumb code. */
259 if (arm_pc_is_thumb (pc
))
260 return thumb_skip_prologue (pc
);
262 /* Can't find the prologue end in the symbol table, try it the hard way
263 by disassembling the instructions. */
265 inst
= read_memory_integer (skip_pc
, 4);
266 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
270 inst
= read_memory_integer (skip_pc
, 4);
271 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
274 inst
= read_memory_integer (skip_pc
, 4);
277 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
281 inst
= read_memory_integer (skip_pc
, 4);
283 /* Any insns after this point may float into the code, if it makes
284 for better instruction scheduling, so we skip them only if
285 we find them, but still consdier the function to be frame-ful */
287 /* We may have either one sfmfd instruction here, or several stfe insns,
288 depending on the version of floating point code we support. */
289 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
292 inst
= read_memory_integer (skip_pc
, 4);
296 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
299 inst
= read_memory_integer (skip_pc
, 4);
303 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
309 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
310 This function decodes a Thumb function prologue to determine:
311 1) the size of the stack frame
312 2) which registers are saved on it
313 3) the offsets of saved regs
314 4) the offset from the stack pointer to the frame pointer
315 This information is stored in the "extra" fields of the frame_info.
317 A typical Thumb function prologue might look like this:
321 Which would create this stack frame (offsets relative to FP)
322 old SP -> 24 stack parameters
325 R7 -> 0 local variables (16 bytes)
326 SP -> -12 additional stack space (12 bytes)
327 The frame size would thus be 36 bytes, and the frame offset would be
328 12 bytes. The frame register is R7. */
335 thumb_scan_prologue (fi
)
336 struct frame_info
*fi
;
338 CORE_ADDR prologue_start
;
339 CORE_ADDR prologue_end
;
340 CORE_ADDR current_pc
;
341 int saved_reg
[16]; /* which register has been copied to register n? */
344 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
346 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
348 if (sal
.line
== 0) /* no line info, use current PC */
349 prologue_end
= fi
->pc
;
350 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
351 prologue_end
= sal
.end
; /* (probably means no prologue) */
354 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
355 /* 16 pushes, an add, and "mv fp,sp" */
357 prologue_end
= min (prologue_end
, fi
->pc
);
359 /* Initialize the saved register map. When register H is copied to
360 register L, we will put H in saved_reg[L]. */
361 for (i
= 0; i
< 16; i
++)
364 /* Search the prologue looking for instructions that set up the
365 frame pointer, adjust the stack pointer, and save registers. */
368 for (current_pc
= prologue_start
; current_pc
< prologue_end
; current_pc
+= 2)
374 insn
= read_memory_unsigned_integer (current_pc
, 2);
376 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
378 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
379 whether to save LR (R14). */
380 int mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
382 /* Calculate offsets of saved R0-R7 and LR. */
383 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
384 if (mask
& (1 << regno
))
387 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
388 saved_reg
[regno
] = regno
; /* reset saved register map */
391 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm */
393 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
394 if (insn
& 0x80) /* is it signed? */
396 fi
->framesize
-= offset
;
398 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
400 fi
->framereg
= THUMB_FP_REGNUM
;
401 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
403 else if (insn
== 0x466f) /* mov r7, sp */
405 fi
->framereg
= THUMB_FP_REGNUM
;
407 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
409 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
411 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
412 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
413 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
416 break; /* anything else isn't prologue */
420 /* Function: check_prologue_cache
421 Check if prologue for this frame's PC has already been scanned.
422 If it has, copy the relevant information about that prologue and
423 return non-zero. Otherwise do not copy anything and return zero.
425 The information saved in the cache includes:
426 * the frame register number;
427 * the size of the stack frame;
428 * the offsets of saved regs (relative to the old SP); and
429 * the offset from the stack pointer to the frame pointer
431 The cache contains only one entry, since this is adequate
432 for the typical sequence of prologue scan requests we get.
433 When performing a backtrace, GDB will usually ask to scan
434 the same function twice in a row (once to get the frame chain,
435 and once to fill in the extra frame information).
438 static struct frame_info prologue_cache
;
441 check_prologue_cache (fi
)
442 struct frame_info
*fi
;
446 if (fi
->pc
== prologue_cache
.pc
)
448 fi
->framereg
= prologue_cache
.framereg
;
449 fi
->framesize
= prologue_cache
.framesize
;
450 fi
->frameoffset
= prologue_cache
.frameoffset
;
451 for (i
= 0; i
<= NUM_REGS
; i
++)
452 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
460 /* Function: save_prologue_cache
461 Copy the prologue information from fi to the prologue cache.
465 save_prologue_cache (fi
)
466 struct frame_info
*fi
;
470 prologue_cache
.pc
= fi
->pc
;
471 prologue_cache
.framereg
= fi
->framereg
;
472 prologue_cache
.framesize
= fi
->framesize
;
473 prologue_cache
.frameoffset
= fi
->frameoffset
;
475 for (i
= 0; i
<= NUM_REGS
; i
++)
476 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
480 /* Function: arm_scan_prologue
481 This function decodes an ARM function prologue to determine:
482 1) the size of the stack frame
483 2) which registers are saved on it
484 3) the offsets of saved regs
485 4) the offset from the stack pointer to the frame pointer
486 This information is stored in the "extra" fields of the frame_info.
488 There are two basic forms for the ARM prologue. The fixed argument
489 function call will look like:
492 stmfd sp!, {fp, ip, lr, pc}
496 Which would create this stack frame (offsets relative to FP):
497 IP -> 4 (caller's stack)
498 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
499 -4 LR (return address in caller)
500 -8 IP (copy of caller's SP)
502 SP -> -28 Local variables
504 The frame size would thus be 32 bytes, and the frame offset would be
505 28 bytes. The stmfd call can also save any of the vN registers it
506 plans to use, which increases the frame size accordingly.
508 Note: The stored PC is 8 off of the STMFD instruction that stored it
509 because the ARM Store instructions always store PC + 8 when you read
512 A variable argument function call will look like:
515 stmfd sp!, {a1, a2, a3, a4}
516 stmfd sp!, {fp, ip, lr, pc}
519 Which would create this stack frame (offsets relative to FP):
520 IP -> 20 (caller's stack)
525 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
526 -4 LR (return address in caller)
527 -8 IP (copy of caller's SP)
529 SP -> -28 Local variables
531 The frame size would thus be 48 bytes, and the frame offset would be
534 There is another potential complication, which is that the optimizer
535 will try to separate the store of fp in the "stmfd" instruction from
536 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
537 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
539 Also, note, the original version of the ARM toolchain claimed that there
542 instruction at the end of the prologue. I have never seen GCC produce
543 this, and the ARM docs don't mention it. We still test for it below in
549 arm_scan_prologue (fi
)
550 struct frame_info
*fi
;
552 int regno
, sp_offset
, fp_offset
;
553 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
555 /* Check if this function is already in the cache of frame information. */
556 if (check_prologue_cache (fi
))
559 /* Assume there is no frame until proven otherwise. */
560 fi
->framereg
= SP_REGNUM
;
564 /* Check for Thumb prologue. */
565 if (arm_pc_is_thumb (fi
->pc
))
567 thumb_scan_prologue (fi
);
568 save_prologue_cache (fi
);
572 /* Find the function prologue. If we can't find the function in
573 the symbol table, peek in the stack frame to find the PC. */
574 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
576 /* Assume the prologue is everything between the first instruction
577 in the function and the first source line. */
578 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
580 if (sal
.line
== 0) /* no line info, use current PC */
581 prologue_end
= fi
->pc
;
582 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
583 prologue_end
= sal
.end
; /* (probably means no prologue) */
587 /* Get address of the stmfd in the prologue of the callee; the saved
588 PC is the address of the stmfd + 8. */
589 prologue_start
= ADDR_BITS_REMOVE(read_memory_integer (fi
->frame
, 4))
591 prologue_end
= prologue_start
+ 64; /* This is all the insn's
592 that could be in the prologue,
593 plus room for 5 insn's inserted
597 /* Now search the prologue looking for instructions that set up the
598 frame pointer, adjust the stack pointer, and save registers.
600 Be careful, however, and if it doesn't look like a prologue,
601 don't try to scan it. If, for instance, a frameless function
602 begins with stmfd sp!, then we will tell ourselves there is
603 a frame, which will confuse stack traceback, as well ad"finish"
604 and other operations that rely on a knowledge of the stack
607 In the APCS, the prologue should start with "mov ip, sp" so
608 if we don't see this as the first insn, we will stop. */
610 sp_offset
= fp_offset
= 0;
612 if (read_memory_unsigned_integer (prologue_start
, 4)
613 == 0xe1a0c00d) /* mov ip, sp */
615 for (current_pc
= prologue_start
+4; current_pc
< prologue_end
;
618 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
620 if ((insn
& 0xffff0000) == 0xe92d0000)
621 /* stmfd sp!, {..., fp, ip, lr, pc}
623 stmfd sp!, {a1, a2, a3, a4} */
625 int mask
= insn
& 0xffff;
627 /* Calculate offsets of saved registers. */
628 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
629 if (mask
& (1 << regno
))
632 fi
->fsr
.regs
[regno
] = sp_offset
;
635 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
637 unsigned imm
= insn
& 0xff; /* immediate value */
638 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
639 imm
= (imm
>> rot
) | (imm
<< (32-rot
));
641 fi
->framereg
= FP_REGNUM
;
643 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
645 unsigned imm
= insn
& 0xff; /* immediate value */
646 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
647 imm
= (imm
>> rot
) | (imm
<< (32-rot
));
650 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
653 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
654 fi
->fsr
.regs
[regno
] = sp_offset
;
656 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
658 int n_saved_fp_regs
, i
;
659 unsigned int fp_start_reg
, fp_bound_reg
;
661 if ((insn
& 0x800) == 0x800) /* N0 is set */
663 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
670 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
676 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
677 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
678 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
681 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
685 continue; /* The optimizer might shove anything into the
686 prologue, so we just skip what we don't recognize. */
690 /* The frame size is just the negative of the offset (from the original SP)
691 of the last thing thing we pushed on the stack. The frame offset is
692 [new FP] - [new SP]. */
693 fi
->framesize
= -sp_offset
;
694 fi
->frameoffset
= fp_offset
- sp_offset
;
696 save_prologue_cache (fi
);
700 /* Function: find_callers_reg
701 Find REGNUM on the stack. Otherwise, it's in an active register. One thing
702 we might want to do here is to check REGNUM against the clobber mask, and
703 somehow flag it as invalid if it isn't saved on the stack somewhere. This
704 would provide a graceful failure mode when trying to get the value of
705 caller-saves registers for an inner frame. */
708 arm_find_callers_reg (fi
, regnum
)
709 struct frame_info
*fi
;
712 for (; fi
; fi
= fi
->next
)
714 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
715 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
716 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
719 if (fi
->fsr
.regs
[regnum
] != 0)
720 return read_memory_integer (fi
->fsr
.regs
[regnum
],
721 REGISTER_RAW_SIZE (regnum
));
722 return read_register (regnum
);
725 /* Function: frame_chain
726 Given a GDB frame, determine the address of the calling function's frame.
727 This will be used to create a new GDB frame struct, and then
728 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
729 For ARM, we save the frame size when we initialize the frame_info.
731 The original definition of this function was a macro in tm-arm.h:
732 { In the case of the ARM, the frame's nominal address is the FP value,
733 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
735 #define FRAME_CHAIN(thisframe) \
736 ((thisframe)->pc >= LOWEST_PC ? \
737 read_memory_integer ((thisframe)->frame - 12, 4) :\
747 struct frame_info
*fi
;
749 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
750 CORE_ADDR fn_start
, callers_pc
, fp
;
752 /* is this a dummy frame? */
753 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
754 return fi
->frame
; /* dummy frame same as caller's frame */
756 /* is caller-of-this a dummy frame? */
757 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
758 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
759 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
760 return fp
; /* dummy frame's frame may bear no relation to ours */
762 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
763 if (fn_start
== entry_point_address ())
764 return 0; /* in _start fn, don't chain further */
766 CORE_ADDR caller_pc
, fn_start
;
767 struct frame_info caller_fi
;
768 int framereg
= fi
->framereg
;
770 if (fi
->pc
< LOWEST_PC
)
773 /* If the caller is the startup code, we're at the end of the chain. */
774 caller_pc
= FRAME_SAVED_PC (fi
);
775 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
776 if (fn_start
== entry_point_address ())
779 /* If the caller is Thumb and the caller is ARM, or vice versa,
780 the frame register of the caller is different from ours.
781 So we must scan the prologue of the caller to determine its
782 frame register number. */
783 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
785 memset (&caller_fi
, 0, sizeof (caller_fi
));
786 caller_fi
.pc
= caller_pc
;
787 arm_scan_prologue (&caller_fi
);
788 framereg
= caller_fi
.framereg
;
791 /* If the caller used a frame register, return its value.
792 Otherwise, return the caller's stack pointer. */
793 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
794 return arm_find_callers_reg (fi
, framereg
);
796 return fi
->frame
+ fi
->framesize
;
799 /* Function: init_extra_frame_info
800 This function actually figures out the frame address for a given pc and
801 sp. This is tricky because we sometimes don't use an explicit
802 frame pointer, and the previous stack pointer isn't necessarily recorded
803 on the stack. The only reliable way to get this info is to
804 examine the prologue.
805 FROMLEAF is a little confusing, it means this is the next frame up
806 the chain AFTER a frameless function. If this is true, then the
807 frame value for this frame is still in the fp register. */
810 arm_init_extra_frame_info (fromleaf
, fi
)
812 struct frame_info
* fi
;
817 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
819 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
821 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
822 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
824 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
825 by assuming it's always FP. */
826 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
834 arm_scan_prologue (fi
);
837 /* this is the innermost frame? */
838 fi
->frame
= read_register (fi
->framereg
);
840 /* not the innermost frame */
841 /* If we have an FP, the callee saved it. */
842 if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
844 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
846 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
848 /* If we were called by a frameless fn. then our frame
849 is still in the frame pointer register on the
851 fi
->frame
= read_fp ();
854 /* Calculate actual addresses of saved registers using offsets determined
855 by arm_scan_prologue. */
856 for (reg
= 0; reg
< NUM_REGS
; reg
++)
857 if (fi
->fsr
.regs
[reg
] != 0)
858 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
863 /* Function: frame_saved_pc
864 Find the caller of this frame. We do this by seeing if LR_REGNUM is saved
865 in the stack anywhere, otherwise we get it from the registers.
867 The old definition of this function was a macro:
868 #define FRAME_SAVED_PC(FRAME) \
869 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4))
873 arm_frame_saved_pc (fi
)
874 struct frame_info
*fi
;
876 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
877 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
878 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
882 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
883 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
888 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
889 Examine the Program Status Register to decide which state we're in. */
892 arm_target_read_fp ()
894 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
895 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
897 return read_register (FP_REGNUM
); /* R11 if ARM */
901 /* Calculate the frame offsets of the saved registers (ARM version). */
903 arm_frame_find_saved_regs (fi
, regaddr
)
904 struct frame_info
*fi
;
905 struct frame_saved_regs
*regaddr
;
907 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
912 arm_push_dummy_frame ()
914 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
915 CORE_ADDR sp
= old_sp
;
916 CORE_ADDR fp
, prologue_start
;
919 /* Push the two dummy prologue instructions in reverse order,
920 so that they'll be in the correct low-to-high order in memory. */
922 sp
= push_word (sp
, 0xe24cb004);
923 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
924 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
926 /* push a pointer to the dummy prologue + 12, because when
927 stm instruction stores the PC, it stores the address of the stm
928 instruction itself plus 12. */
929 fp
= sp
= push_word (sp
, prologue_start
+ 12);
930 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
931 sp
= push_word (sp
, old_sp
);
932 sp
= push_word (sp
, read_register (FP_REGNUM
));
934 for (regnum
= 10; regnum
>= 0; regnum
--)
935 sp
= push_word (sp
, read_register (regnum
));
937 write_register (FP_REGNUM
, fp
);
938 write_register (THUMB_FP_REGNUM
, fp
);
939 write_register (SP_REGNUM
, sp
);
942 /* Fix up the call dummy, based on whether the processor is currently
943 in Thumb or ARM mode, and whether the target function is Thumb
944 or ARM. There are three different situations requiring three
947 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
948 been copied into the dummy parameter to this function.
949 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
950 "mov pc,r4" instruction patched to be a "bx r4" instead.
951 * Thumb calling anything: uses the Thumb dummy defined below, which
952 works for calling both ARM and Thumb functions.
954 All three call dummies expect to receive the target function address
955 in R4, with the low bit set if it's a Thumb function.
959 arm_fix_call_dummy (dummy
, pc
, fun
, nargs
, args
, type
, gcc_p
)
968 static short thumb_dummy
[4] =
970 0xf000, 0xf801, /* bl label */
972 0x4720, /* label: bx r4 */
974 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
976 /* Set flag indicating whether the current PC is in a Thumb function. */
977 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
979 /* If the target function is Thumb, set the low bit of the function address.
980 And if the CPU is currently in ARM mode, patch the second instruction
981 of call dummy to use a BX instruction to switch to Thumb mode. */
982 target_is_thumb
= arm_pc_is_thumb (fun
);
986 if (!caller_is_thumb
)
987 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
990 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
991 instead of the ARM one that's already been copied. This will
992 work for both Thumb and ARM target functions. */
997 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
999 for (i
= 0; i
< len
; i
++)
1001 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1002 p
+= sizeof (thumb_dummy
[0]);
1006 /* Put the target address in r4; the call dummy will copy this to the PC. */
1007 write_register (4, fun
);
1011 /* Return the offset in the call dummy of the instruction that needs
1012 to have a breakpoint placed on it. This is the offset of the 'swi 24'
1013 instruction, which is no longer actually used, but simply acts
1014 as a place-holder now.
1016 This implements the CALL_DUMMY_BREAK_OFFSET macro.
1020 arm_call_dummy_breakpoint_offset ()
1022 if (caller_is_thumb
)
1030 arm_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1035 CORE_ADDR struct_addr
;
1047 struct stack_arg
*stack_args
=
1048 (struct stack_arg
*) alloca (nargs
* sizeof (struct stack_arg
));
1049 int nstack_args
= 0;
1052 /* Initialize the integer and float register pointers. */
1054 float_argreg
= F0_REGNUM
;
1056 /* the struct_return pointer occupies the first parameter-passing reg */
1058 write_register (argreg
++, struct_addr
);
1060 /* The offset onto the stack at which we will start copying parameters
1061 (after the registers are used up) begins at 16 in the old ABI.
1062 This leaves room for the "home" area for register parameters. */
1063 stack_offset
= REGISTER_SIZE
* 4;
1065 /* Process args from left to right. Store as many as allowed in
1066 registers, save the rest to be pushed on the stack */
1067 for (argnum
= 0; argnum
< nargs
; argnum
++)
1070 value_ptr arg
= args
[argnum
];
1071 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1072 struct type
*target_type
= TYPE_TARGET_TYPE (arg_type
);
1073 int len
= TYPE_LENGTH (arg_type
);
1074 enum type_code typecode
= TYPE_CODE (arg_type
);
1078 val
= (char *) VALUE_CONTENTS (arg
);
1080 /* If the argument is a pointer to a function, and it's a Thumb
1081 function, set the low bit of the pointer. */
1082 if (typecode
== TYPE_CODE_PTR
1083 && target_type
!= NULL
1084 && TYPE_CODE (target_type
) == TYPE_CODE_FUNC
)
1086 regval
= extract_address (val
, len
);
1087 if (arm_pc_is_thumb (regval
))
1088 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1091 #define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */
1093 /* Up to four floating point arguments can be passed in floating
1094 point registers on ARM (not on Thumb). */
1095 if (typecode
== TYPE_CODE_FLT
1096 && float_argreg
<= ARM_LAST_FP_ARG_REGNUM
1097 && !target_is_thumb
)
1099 /* This is a floating point value that fits entirely
1100 in a single register. */
1101 regval
= extract_address (val
, len
);
1102 write_register (float_argreg
++, regval
);
1107 /* Copy the argument to general registers or the stack in
1108 register-sized pieces. Large arguments are split between
1109 registers and stack. */
1112 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1114 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1115 regval
= extract_address (val
, partial_len
);
1117 /* It's a simple argument being passed in a general
1119 write_register (argreg
, regval
);
1126 /* keep for later pushing */
1127 stack_args
[nstack_args
].val
= val
;
1128 stack_args
[nstack_args
++].len
= len
;
1134 /* now do the real stack pushing, process args right to left */
1135 while (nstack_args
--)
1137 sp
-= stack_args
[nstack_args
].len
;
1138 write_memory (sp
, stack_args
[nstack_args
].val
,
1139 stack_args
[nstack_args
].len
);
1142 /* Return adjusted stack pointer. */
1149 struct frame_info
*frame
= get_current_frame ();
1153 old_SP
= read_register (frame
->framereg
);
1154 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1155 if (frame
->fsr
.regs
[regnum
] != 0)
1156 write_register (regnum
,
1157 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1159 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1160 write_register (SP_REGNUM
, old_SP
);
1162 flush_cached_frames ();
1166 print_fpu_flags (flags
)
1169 if (flags
& (1 << 0))
1170 fputs ("IVO ", stdout
);
1171 if (flags
& (1 << 1))
1172 fputs ("DVZ ", stdout
);
1173 if (flags
& (1 << 2))
1174 fputs ("OFL ", stdout
);
1175 if (flags
& (1 << 3))
1176 fputs ("UFL ", stdout
);
1177 if (flags
& (1 << 4))
1178 fputs ("INX ", stdout
);
1185 register unsigned long status
= read_register (FPS_REGNUM
);
1188 type
= (status
>> 24) & 127;
1189 printf ("%s FPU type %d\n",
1190 (status
& (1<<31)) ? "Hardware" : "Software",
1192 fputs ("mask: ", stdout
);
1193 print_fpu_flags (status
>> 16);
1194 fputs ("flags: ", stdout
);
1195 print_fpu_flags (status
);
1198 /* If the disassembly mode is APCS, we have to also switch the
1199 bfd mach_type. This function is run in the set disassembly_flavor
1200 command, and does that. */
1203 set_disassembly_flavor_sfunc (args
, from_tty
, c
)
1206 struct cmd_list_element
*c
;
1208 set_disassembly_flavor ();
1212 set_disassembly_flavor ()
1214 if (disassembly_flavor
== apcs_flavor
)
1216 if (arm_toggle_regnames () == 0)
1217 arm_toggle_regnames ();
1218 arm_register_names
= apcs_register_names
;
1220 else if (disassembly_flavor
== r_prefix_flavor
)
1222 if (arm_toggle_regnames () == 1)
1223 arm_toggle_regnames ();
1224 arm_register_names
= additional_register_names
;
1228 /* arm_othernames implements the "othernames" command. This is kind of
1229 hacky, and I prefer the set-show disassembly-flavor which is also used
1230 for the x86 gdb. I will keep this around, however, in case anyone is
1231 actually using it. */
1236 if (disassembly_flavor
== r_prefix_flavor
)
1238 disassembly_flavor
= apcs_flavor
;
1239 set_disassembly_flavor ();
1243 disassembly_flavor
= r_prefix_flavor
;
1244 set_disassembly_flavor ();
1248 /* FIXME: Fill in with the 'right thing', see asm
1249 template in arm-convert.s */
1252 convert_from_extended (ptr
, dbl
)
1256 *(double *) dbl
= *(double *) ptr
;
1260 convert_to_extended (dbl
, ptr
)
1264 *(double *) ptr
= *(double *) dbl
;
1268 condition_true (cond
, status_reg
)
1270 unsigned long status_reg
;
1272 if (cond
== INST_AL
|| cond
== INST_NV
)
1278 return ((status_reg
& FLAG_Z
) != 0);
1280 return ((status_reg
& FLAG_Z
) == 0);
1282 return ((status_reg
& FLAG_C
) != 0);
1284 return ((status_reg
& FLAG_C
) == 0);
1286 return ((status_reg
& FLAG_N
) != 0);
1288 return ((status_reg
& FLAG_N
) == 0);
1290 return ((status_reg
& FLAG_V
) != 0);
1292 return ((status_reg
& FLAG_V
) == 0);
1294 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1296 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1298 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1300 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1302 return (((status_reg
& FLAG_Z
) == 0) &&
1303 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1305 return (((status_reg
& FLAG_Z
) != 0) ||
1306 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1311 #define submask(x) ((1L << ((x) + 1)) - 1)
1312 #define bit(obj,st) (((obj) >> (st)) & 1)
1313 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1314 #define sbits(obj,st,fn) \
1315 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1316 #define BranchDest(addr,instr) \
1317 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1320 static unsigned long
1321 shifted_reg_val (inst
, carry
, pc_val
, status_reg
)
1324 unsigned long pc_val
;
1325 unsigned long status_reg
;
1327 unsigned long res
, shift
;
1328 int rm
= bits (inst
, 0, 3);
1329 unsigned long shifttype
= bits (inst
, 5, 6);
1333 int rs
= bits (inst
, 8, 11);
1334 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1337 shift
= bits (inst
, 7, 11);
1340 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1341 + (bit (inst
, 4) ? 12 : 8))
1342 : read_register (rm
));
1347 res
= shift
>= 32 ? 0 : res
<< shift
;
1351 res
= shift
>= 32 ? 0 : res
>> shift
;
1357 res
= ((res
& 0x80000000L
)
1358 ? ~((~res
) >> shift
) : res
>> shift
);
1361 case 3: /* ROR/RRX */
1364 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1366 res
= (res
>> shift
) | (res
<< (32 - shift
));
1370 return res
& 0xffffffff;
1374 /* Return number of 1-bits in VAL. */
1381 for (nbits
= 0; val
!= 0; nbits
++)
1382 val
&= val
- 1; /* delete rightmost 1-bit in val */
1388 thumb_get_next_pc (pc
)
1391 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1392 unsigned short inst1
= read_memory_integer (pc
, 2);
1393 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1394 unsigned long offset
;
1396 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1400 /* Fetch the saved PC from the stack. It's stored above
1401 all of the other registers. */
1402 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1403 sp
= read_register (SP_REGNUM
);
1404 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1405 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1407 error ("Infinite loop detected");
1409 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1411 unsigned long status
= read_register (PS_REGNUM
);
1412 unsigned long cond
= bits (inst1
, 8, 11);
1413 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1414 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1416 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1418 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1420 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1422 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1423 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1424 nextpc
= pc_val
+ offset
;
1432 arm_get_next_pc (pc
)
1435 unsigned long pc_val
;
1436 unsigned long this_instr
;
1437 unsigned long status
;
1440 if (arm_pc_is_thumb (pc
))
1441 return thumb_get_next_pc (pc
);
1443 pc_val
= (unsigned long) pc
;
1444 this_instr
= read_memory_integer (pc
, 4);
1445 status
= read_register (PS_REGNUM
);
1446 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1448 if (condition_true (bits (this_instr
, 28, 31), status
))
1450 switch (bits (this_instr
, 24, 27))
1453 case 0x1: /* data processing */
1457 unsigned long operand1
, operand2
, result
= 0;
1461 if (bits (this_instr
, 12, 15) != 15)
1464 if (bits (this_instr
, 22, 25) == 0
1465 && bits (this_instr
, 4, 7) == 9) /* multiply */
1466 error ("Illegal update to pc in instruction");
1468 /* Multiply into PC */
1469 c
= (status
& FLAG_C
) ? 1 : 0;
1470 rn
= bits (this_instr
, 16, 19);
1471 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1473 if (bit (this_instr
, 25))
1475 unsigned long immval
= bits (this_instr
, 0, 7);
1476 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1477 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1480 else /* operand 2 is a shifted register */
1481 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1483 switch (bits (this_instr
, 21, 24))
1486 result
= operand1
& operand2
;
1490 result
= operand1
^ operand2
;
1494 result
= operand1
- operand2
;
1498 result
= operand2
- operand1
;
1502 result
= operand1
+ operand2
;
1506 result
= operand1
+ operand2
+ c
;
1510 result
= operand1
- operand2
+ c
;
1514 result
= operand2
- operand1
+ c
;
1520 case 0xb: /* tst, teq, cmp, cmn */
1521 result
= (unsigned long) nextpc
;
1525 result
= operand1
| operand2
;
1529 /* Always step into a function. */
1534 result
= operand1
& ~operand2
;
1541 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1544 error ("Infinite loop detected");
1549 case 0x5: /* data transfer */
1552 if (bit (this_instr
, 20))
1555 if (bits (this_instr
, 12, 15) == 15)
1561 if (bit (this_instr
, 22))
1562 error ("Illegal update to pc in instruction");
1564 /* byte write to PC */
1565 rn
= bits (this_instr
, 16, 19);
1566 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1567 if (bit (this_instr
, 24))
1570 int c
= (status
& FLAG_C
) ? 1 : 0;
1571 unsigned long offset
=
1572 (bit (this_instr
, 25)
1573 ? shifted_reg_val (this_instr
, c
, pc_val
)
1574 : bits (this_instr
, 0, 11));
1576 if (bit (this_instr
, 23))
1581 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1584 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1587 error ("Infinite loop detected");
1593 case 0x9: /* block transfer */
1594 if (bit (this_instr
, 20))
1597 if (bit (this_instr
, 15))
1602 if (bit (this_instr
, 23))
1605 unsigned long reglist
= bits (this_instr
, 0, 14);
1606 offset
= bitcount (reglist
) * 4;
1607 if (bit (this_instr
, 24)) /* pre */
1610 else if (bit (this_instr
, 24))
1614 unsigned long rn_val
=
1615 read_register (bits (this_instr
, 16, 19));
1617 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1621 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1623 error ("Infinite loop detected");
1628 case 0xb: /* branch & link */
1629 case 0xa: /* branch */
1631 nextpc
= BranchDest (pc
, this_instr
);
1633 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1635 error ("Infinite loop detected");
1641 case 0xe: /* coproc ops */
1646 fprintf (stderr
, "Bad bit-field extraction\n");
1654 #include "bfd-in2.h"
1655 #include "libcoff.h"
1658 gdb_print_insn_arm (memaddr
, info
)
1660 disassemble_info
*info
;
1662 if (arm_pc_is_thumb (memaddr
))
1664 static asymbol
*asym
;
1665 static combined_entry_type ce
;
1666 static struct coff_symbol_struct csym
;
1667 static struct _bfd fake_bfd
;
1668 static bfd_target fake_target
;
1670 if (csym
.native
== NULL
)
1672 /* Create a fake symbol vector containing a Thumb symbol. This is
1673 solely so that the code in print_insn_little_arm() and
1674 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1675 of a Thumb symbol and switch to decoding Thumb instructions. */
1677 fake_target
.flavour
= bfd_target_coff_flavour
;
1678 fake_bfd
.xvec
= &fake_target
;
1679 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1681 csym
.symbol
.the_bfd
= &fake_bfd
;
1682 csym
.symbol
.name
= "fake";
1683 asym
= (asymbol
*) & csym
;
1686 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1687 info
->symbols
= &asym
;
1690 info
->symbols
= NULL
;
1692 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1693 return print_insn_big_arm (memaddr
, info
);
1695 return print_insn_little_arm (memaddr
, info
);
1698 /* Sequence of bytes for breakpoint instruction. */
1699 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} /* Recognized illegal opcodes */
1700 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1701 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
1702 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
1704 /* The following has been superseded by BREAKPOINT_FOR_PC, but
1705 is defined merely to keep mem-break.c happy. */
1706 #define LITTLE_BREAKPOINT ARM_LE_BREAKPOINT
1707 #define BIG_BREAKPOINT ARM_BE_BREAKPOINT
1709 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
1710 counter value to determine whether a 16- or 32-bit breakpoint should be
1711 used. It returns a pointer to a string of bytes that encode a breakpoint
1712 instruction, stores the length of the string to *lenptr, and adjusts pc
1713 (if necessary) to point to the actual memory location where the
1714 breakpoint should be inserted. */
1717 arm_breakpoint_from_pc (pcptr
, lenptr
)
1721 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1723 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1725 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1726 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1727 *lenptr
= sizeof (thumb_breakpoint
);
1728 return thumb_breakpoint
;
1732 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1733 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1734 *lenptr
= sizeof (thumb_breakpoint
);
1735 return thumb_breakpoint
;
1740 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1742 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1743 *lenptr
= sizeof (arm_breakpoint
);
1744 return arm_breakpoint
;
1748 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1749 *lenptr
= sizeof (arm_breakpoint
);
1750 return arm_breakpoint
;
1754 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
1755 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
1758 arm_in_call_stub (pc
, name
)
1762 CORE_ADDR start_addr
;
1764 /* Find the starting address of the function containing the PC. If the
1765 caller didn't give us a name, look it up at the same time. */
1766 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1769 return strncmp (name
, "_call_via_r", 11) == 0;
1773 /* If PC is in a Thumb call or return stub, return the address of the target
1774 PC, which is in a register. The thunk functions are called _called_via_xx,
1775 where x is the register name. The possible names are r0-r9, sl, fp, ip,
1783 CORE_ADDR start_addr
;
1785 /* Find the starting address and name of the function containing the PC. */
1786 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1789 /* Call thunks always start with "_call_via_". */
1790 if (strncmp (name
, "_call_via_", 10) == 0)
1792 /* Use the name suffix to determine which register contains
1794 static char *table
[15] =
1795 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1796 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
1800 for (regno
= 0; regno
<= 14; regno
++)
1801 if (strcmp (&name
[10], table
[regno
]) == 0)
1802 return read_register (regno
);
1804 return 0; /* not a stub */
1809 _initialize_arm_tdep ()
1811 struct cmd_list_element
*new_cmd
;
1813 tm_print_insn
= gdb_print_insn_arm
;
1815 /* Sync the opcode insn printer with our register viewer: */
1817 if (arm_toggle_regnames () != 1)
1818 arm_toggle_regnames ();
1820 /* Add the deprecated "othernames" command */
1822 add_com ("othernames", class_obscure
, arm_othernames
,
1823 "Switch to the other set of register names.");
1825 /* Add the disassembly-flavor command */
1827 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
1829 (char *) &disassembly_flavor
,
1830 "Set the disassembly flavor, \
1831 the valid values are \"apcs\" and \"r-prefix\", \
1832 and the default value is \"apcs\".",
1834 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
1835 add_show_from_set(new_cmd
, &showlist
);
1837 /* ??? Maybe this should be a boolean. */
1838 add_show_from_set (add_set_cmd ("apcs32", no_class
,
1839 var_zinteger
, (char *)&arm_apcs_32
,
1840 "Set usage of ARM 32-bit mode.\n", &setlist
),
1845 /* Test whether the coff symbol specific value corresponds to a Thumb function */
1847 coff_sym_is_thumb (int val
)
1849 return (val
== C_THUMBEXT
||
1850 val
== C_THUMBSTAT
||
1851 val
== C_THUMBEXTFUNC
||
1852 val
== C_THUMBSTATFUNC
||
1853 val
== C_THUMBLABEL
);