* gdbarch.sh (addr_bits_remove): Change type to 'm'.
[deliverable/binutils-gdb.git] / gdb / arm-tdep.c
1 /* Common target dependent code for GDB on ARM systems.
2
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include <ctype.h> /* XXX for isupper () */
23
24 #include "defs.h"
25 #include "frame.h"
26 #include "inferior.h"
27 #include "gdbcmd.h"
28 #include "gdbcore.h"
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
31 #include "regcache.h"
32 #include "doublest.h"
33 #include "value.h"
34 #include "arch-utils.h"
35 #include "osabi.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
39 #include "objfiles.h"
40 #include "dwarf2-frame.h"
41 #include "gdbtypes.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
45
46 #include "arm-tdep.h"
47 #include "gdb/sim-arm.h"
48
49 #include "elf-bfd.h"
50 #include "coff/internal.h"
51 #include "elf/arm.h"
52
53 #include "gdb_assert.h"
54 #include "vec.h"
55
56 static int arm_debug;
57
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
61
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
64
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 | 0x80000000)
68
69 #define MSYMBOL_IS_SPECIAL(msym) \
70 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
71
72 /* Macros for swapping shorts and ints. In the unlikely case that anybody else needs these,
73 move to a general header. (A better solution might be to define memory read routines that
74 know whether they are reading code or data.) */
75
76 #define SWAP_SHORT(x) \
77 ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
78
79 #define SWAP_INT(x) \
80 ( ((x & 0xff000000) >> 24) \
81 | ((x & 0x00ff0000) >> 8) \
82 | ((x & 0x0000ff00) << 8) \
83 | ((x & 0x000000ff) << 24))
84
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data *arm_objfile_data_key;
87
88 struct arm_mapping_symbol
89 {
90 bfd_vma value;
91 char type;
92 };
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s;
94 DEF_VEC_O(arm_mapping_symbol_s);
95
96 struct arm_per_objfile
97 {
98 VEC(arm_mapping_symbol_s) **section_maps;
99 };
100
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element *setarmcmdlist = NULL;
103 static struct cmd_list_element *showarmcmdlist = NULL;
104
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *fp_model_strings[] =
108 {
109 "auto",
110 "softfpa",
111 "fpa",
112 "softvfp",
113 "vfp",
114 NULL
115 };
116
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
119 static const char *current_fp_model = "auto";
120
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *arm_abi_strings[] =
123 {
124 "auto",
125 "APCS",
126 "AAPCS",
127 NULL
128 };
129
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
132 static const char *arm_abi_string = "auto";
133
134 /* The execution mode to assume. */
135 static const char *arm_mode_strings[] =
136 {
137 "auto",
138 "arm",
139 "thumb"
140 };
141
142 static const char *arm_fallback_mode_string = "auto";
143 static const char *arm_force_mode_string = "auto";
144
145 /* Number of different reg name sets (options). */
146 static int num_disassembly_options;
147
148 /* The standard register names, and all the valid aliases for them. */
149 static const struct
150 {
151 const char *name;
152 int regnum;
153 } arm_register_aliases[] = {
154 /* Basic register numbers. */
155 { "r0", 0 },
156 { "r1", 1 },
157 { "r2", 2 },
158 { "r3", 3 },
159 { "r4", 4 },
160 { "r5", 5 },
161 { "r6", 6 },
162 { "r7", 7 },
163 { "r8", 8 },
164 { "r9", 9 },
165 { "r10", 10 },
166 { "r11", 11 },
167 { "r12", 12 },
168 { "r13", 13 },
169 { "r14", 14 },
170 { "r15", 15 },
171 /* Synonyms (argument and variable registers). */
172 { "a1", 0 },
173 { "a2", 1 },
174 { "a3", 2 },
175 { "a4", 3 },
176 { "v1", 4 },
177 { "v2", 5 },
178 { "v3", 6 },
179 { "v4", 7 },
180 { "v5", 8 },
181 { "v6", 9 },
182 { "v7", 10 },
183 { "v8", 11 },
184 /* Other platform-specific names for r9. */
185 { "sb", 9 },
186 { "tr", 9 },
187 /* Special names. */
188 { "ip", 12 },
189 { "sp", 13 },
190 { "lr", 14 },
191 { "pc", 15 },
192 /* Names used by GCC (not listed in the ARM EABI). */
193 { "sl", 10 },
194 { "fp", 11 },
195 /* A special name from the older ATPCS. */
196 { "wr", 7 },
197 };
198
199 static const char *const arm_register_names[] =
200 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
201 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
202 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
203 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
204 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
205 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
206 "fps", "cpsr" }; /* 24 25 */
207
208 /* Valid register name styles. */
209 static const char **valid_disassembly_styles;
210
211 /* Disassembly style to use. Default to "std" register names. */
212 static const char *disassembly_style;
213
214 /* This is used to keep the bfd arch_info in sync with the disassembly
215 style. */
216 static void set_disassembly_style_sfunc(char *, int,
217 struct cmd_list_element *);
218 static void set_disassembly_style (void);
219
220 static void convert_from_extended (const struct floatformat *, const void *,
221 void *, int);
222 static void convert_to_extended (const struct floatformat *, void *,
223 const void *, int);
224
225 struct arm_prologue_cache
226 {
227 /* The stack pointer at the time this frame was created; i.e. the
228 caller's stack pointer when this function was called. It is used
229 to identify this frame. */
230 CORE_ADDR prev_sp;
231
232 /* The frame base for this frame is just prev_sp - frame size.
233 FRAMESIZE is the distance from the frame pointer to the
234 initial stack pointer. */
235
236 int framesize;
237
238 /* The register used to hold the frame pointer for this frame. */
239 int framereg;
240
241 /* Saved register offsets. */
242 struct trad_frame_saved_reg *saved_regs;
243 };
244
245 /* Addresses for calling Thumb functions have the bit 0 set.
246 Here are some macros to test, set, or clear bit 0 of addresses. */
247 #define IS_THUMB_ADDR(addr) ((addr) & 1)
248 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
249 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
250
251 /* Set to true if the 32-bit mode is in use. */
252
253 int arm_apcs_32 = 1;
254
255 /* Determine if FRAME is executing in Thumb mode. */
256
257 static int
258 arm_frame_is_thumb (struct frame_info *frame)
259 {
260 CORE_ADDR cpsr;
261
262 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
263 directly (from a signal frame or dummy frame) or by interpreting
264 the saved LR (from a prologue or DWARF frame). So consult it and
265 trust the unwinders. */
266 cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
267
268 return (cpsr & CPSR_T) != 0;
269 }
270
271 /* Callback for VEC_lower_bound. */
272
273 static inline int
274 arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
275 const struct arm_mapping_symbol *rhs)
276 {
277 return lhs->value < rhs->value;
278 }
279
280 /* Determine if the program counter specified in MEMADDR is in a Thumb
281 function. This function should be called for addresses unrelated to
282 any executing frame; otherwise, prefer arm_frame_is_thumb. */
283
284 static int
285 arm_pc_is_thumb (CORE_ADDR memaddr)
286 {
287 struct obj_section *sec;
288 struct minimal_symbol *sym;
289
290 /* If bit 0 of the address is set, assume this is a Thumb address. */
291 if (IS_THUMB_ADDR (memaddr))
292 return 1;
293
294 /* If the user wants to override the symbol table, let him. */
295 if (strcmp (arm_force_mode_string, "arm") == 0)
296 return 0;
297 if (strcmp (arm_force_mode_string, "thumb") == 0)
298 return 1;
299
300 /* If there are mapping symbols, consult them. */
301 sec = find_pc_section (memaddr);
302 if (sec != NULL)
303 {
304 struct arm_per_objfile *data;
305 VEC(arm_mapping_symbol_s) *map;
306 struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
307 0 };
308 unsigned int idx;
309
310 data = objfile_data (sec->objfile, arm_objfile_data_key);
311 if (data != NULL)
312 {
313 map = data->section_maps[sec->the_bfd_section->index];
314 if (!VEC_empty (arm_mapping_symbol_s, map))
315 {
316 struct arm_mapping_symbol *map_sym;
317
318 idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
319 arm_compare_mapping_symbols);
320
321 /* VEC_lower_bound finds the earliest ordered insertion
322 point. If the following symbol starts at this exact
323 address, we use that; otherwise, the preceding
324 mapping symbol covers this address. */
325 if (idx < VEC_length (arm_mapping_symbol_s, map))
326 {
327 map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
328 if (map_sym->value == map_key.value)
329 return map_sym->type == 't';
330 }
331
332 if (idx > 0)
333 {
334 map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
335 return map_sym->type == 't';
336 }
337 }
338 }
339 }
340
341 /* Thumb functions have a "special" bit set in minimal symbols. */
342 sym = lookup_minimal_symbol_by_pc (memaddr);
343 if (sym)
344 return (MSYMBOL_IS_SPECIAL (sym));
345
346 /* If the user wants to override the fallback mode, let them. */
347 if (strcmp (arm_fallback_mode_string, "arm") == 0)
348 return 0;
349 if (strcmp (arm_fallback_mode_string, "thumb") == 0)
350 return 1;
351
352 /* If we couldn't find any symbol, but we're talking to a running
353 target, then trust the current value of $cpsr. This lets
354 "display/i $pc" always show the correct mode (though if there is
355 a symbol table we will not reach here, so it still may not be
356 displayed in the mode it will be executed). */
357 if (target_has_registers)
358 return arm_frame_is_thumb (get_current_frame ());
359
360 /* Otherwise we're out of luck; we assume ARM. */
361 return 0;
362 }
363
364 /* Remove useless bits from addresses in a running program. */
365 static CORE_ADDR
366 arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
367 {
368 if (arm_apcs_32)
369 return UNMAKE_THUMB_ADDR (val);
370 else
371 return (val & 0x03fffffc);
372 }
373
374 /* When reading symbols, we need to zap the low bit of the address,
375 which may be set to 1 for Thumb functions. */
376 static CORE_ADDR
377 arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
378 {
379 return val & ~1;
380 }
381
382 /* Analyze a Thumb prologue, looking for a recognizable stack frame
383 and frame pointer. Scan until we encounter a store that could
384 clobber the stack frame unexpectedly, or an unknown instruction. */
385
386 static CORE_ADDR
387 thumb_analyze_prologue (struct gdbarch *gdbarch,
388 CORE_ADDR start, CORE_ADDR limit,
389 struct arm_prologue_cache *cache)
390 {
391 int i;
392 pv_t regs[16];
393 struct pv_area *stack;
394 struct cleanup *back_to;
395 CORE_ADDR offset;
396
397 for (i = 0; i < 16; i++)
398 regs[i] = pv_register (i, 0);
399 stack = make_pv_area (ARM_SP_REGNUM);
400 back_to = make_cleanup_free_pv_area (stack);
401
402 while (start < limit)
403 {
404 unsigned short insn;
405
406 insn = read_memory_unsigned_integer (start, 2);
407
408 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
409 insn = SWAP_SHORT (insn);
410
411 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
412 {
413 int regno;
414 int mask;
415
416 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
417 break;
418
419 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
420 whether to save LR (R14). */
421 mask = (insn & 0xff) | ((insn & 0x100) << 6);
422
423 /* Calculate offsets of saved R0-R7 and LR. */
424 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
425 if (mask & (1 << regno))
426 {
427 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
428 -4);
429 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
430 }
431 }
432 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
433 sub sp, #simm */
434 {
435 offset = (insn & 0x7f) << 2; /* get scaled offset */
436 if (insn & 0x80) /* Check for SUB. */
437 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
438 -offset);
439 else
440 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
441 offset);
442 }
443 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
444 regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
445 (insn & 0xff) << 2);
446 else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
447 {
448 int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
449 int src_reg = (insn & 0x78) >> 3;
450 regs[dst_reg] = regs[src_reg];
451 }
452 else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
453 {
454 /* Handle stores to the stack. Normally pushes are used,
455 but with GCC -mtpcs-frame, there may be other stores
456 in the prologue to create the frame. */
457 int regno = (insn >> 8) & 0x7;
458 pv_t addr;
459
460 offset = (insn & 0xff) << 2;
461 addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
462
463 if (pv_area_store_would_trash (stack, addr))
464 break;
465
466 pv_area_store (stack, addr, 4, regs[regno]);
467 }
468 else
469 {
470 /* We don't know what this instruction is. We're finished
471 scanning. NOTE: Recognizing more safe-to-ignore
472 instructions here will improve support for optimized
473 code. */
474 break;
475 }
476
477 start += 2;
478 }
479
480 if (cache == NULL)
481 {
482 do_cleanups (back_to);
483 return start;
484 }
485
486 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
487 {
488 /* Frame pointer is fp. Frame size is constant. */
489 cache->framereg = ARM_FP_REGNUM;
490 cache->framesize = -regs[ARM_FP_REGNUM].k;
491 }
492 else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
493 {
494 /* Frame pointer is r7. Frame size is constant. */
495 cache->framereg = THUMB_FP_REGNUM;
496 cache->framesize = -regs[THUMB_FP_REGNUM].k;
497 }
498 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
499 {
500 /* Try the stack pointer... this is a bit desperate. */
501 cache->framereg = ARM_SP_REGNUM;
502 cache->framesize = -regs[ARM_SP_REGNUM].k;
503 }
504 else
505 {
506 /* We're just out of luck. We don't know where the frame is. */
507 cache->framereg = -1;
508 cache->framesize = 0;
509 }
510
511 for (i = 0; i < 16; i++)
512 if (pv_area_find_reg (stack, gdbarch, i, &offset))
513 cache->saved_regs[i].addr = offset;
514
515 do_cleanups (back_to);
516 return start;
517 }
518
519 /* Advance the PC across any function entry prologue instructions to
520 reach some "real" code.
521
522 The APCS (ARM Procedure Call Standard) defines the following
523 prologue:
524
525 mov ip, sp
526 [stmfd sp!, {a1,a2,a3,a4}]
527 stmfd sp!, {...,fp,ip,lr,pc}
528 [stfe f7, [sp, #-12]!]
529 [stfe f6, [sp, #-12]!]
530 [stfe f5, [sp, #-12]!]
531 [stfe f4, [sp, #-12]!]
532 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
533
534 static CORE_ADDR
535 arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
536 {
537 unsigned long inst;
538 CORE_ADDR skip_pc;
539 CORE_ADDR func_addr, func_end = 0;
540 char *func_name;
541 struct symtab_and_line sal;
542
543 /* If we're in a dummy frame, don't even try to skip the prologue. */
544 if (deprecated_pc_in_call_dummy (pc))
545 return pc;
546
547 /* See what the symbol table says. */
548
549 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
550 {
551 struct symbol *sym;
552
553 /* Found a function. */
554 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL);
555 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
556 {
557 /* Don't use this trick for assembly source files. */
558 sal = find_pc_line (func_addr, 0);
559 if ((sal.line != 0) && (sal.end < func_end))
560 return sal.end;
561 }
562 }
563
564 /* Can't find the prologue end in the symbol table, try it the hard way
565 by disassembling the instructions. */
566
567 /* Like arm_scan_prologue, stop no later than pc + 64. */
568 if (func_end == 0 || func_end > pc + 64)
569 func_end = pc + 64;
570
571 /* Check if this is Thumb code. */
572 if (arm_pc_is_thumb (pc))
573 return thumb_analyze_prologue (gdbarch, pc, func_end, NULL);
574
575 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
576 {
577 inst = read_memory_unsigned_integer (skip_pc, 4);
578
579 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
580 inst = SWAP_INT (inst);
581
582 /* "mov ip, sp" is no longer a required part of the prologue. */
583 if (inst == 0xe1a0c00d) /* mov ip, sp */
584 continue;
585
586 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
587 continue;
588
589 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
590 continue;
591
592 /* Some prologues begin with "str lr, [sp, #-4]!". */
593 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
594 continue;
595
596 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
597 continue;
598
599 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
600 continue;
601
602 /* Any insns after this point may float into the code, if it makes
603 for better instruction scheduling, so we skip them only if we
604 find them, but still consider the function to be frame-ful. */
605
606 /* We may have either one sfmfd instruction here, or several stfe
607 insns, depending on the version of floating point code we
608 support. */
609 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
610 continue;
611
612 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
613 continue;
614
615 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
616 continue;
617
618 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
619 continue;
620
621 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
622 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
623 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
624 continue;
625
626 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
627 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
628 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
629 continue;
630
631 /* Un-recognized instruction; stop scanning. */
632 break;
633 }
634
635 return skip_pc; /* End of prologue */
636 }
637
638 /* *INDENT-OFF* */
639 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
640 This function decodes a Thumb function prologue to determine:
641 1) the size of the stack frame
642 2) which registers are saved on it
643 3) the offsets of saved regs
644 4) the offset from the stack pointer to the frame pointer
645
646 A typical Thumb function prologue would create this stack frame
647 (offsets relative to FP)
648 old SP -> 24 stack parameters
649 20 LR
650 16 R7
651 R7 -> 0 local variables (16 bytes)
652 SP -> -12 additional stack space (12 bytes)
653 The frame size would thus be 36 bytes, and the frame offset would be
654 12 bytes. The frame register is R7.
655
656 The comments for thumb_skip_prolog() describe the algorithm we use
657 to detect the end of the prolog. */
658 /* *INDENT-ON* */
659
660 static void
661 thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
662 CORE_ADDR block_addr, struct arm_prologue_cache *cache)
663 {
664 CORE_ADDR prologue_start;
665 CORE_ADDR prologue_end;
666 CORE_ADDR current_pc;
667
668 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
669 &prologue_end))
670 {
671 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
672
673 if (sal.line == 0) /* no line info, use current PC */
674 prologue_end = prev_pc;
675 else if (sal.end < prologue_end) /* next line begins after fn end */
676 prologue_end = sal.end; /* (probably means no prologue) */
677 }
678 else
679 /* We're in the boondocks: we have no idea where the start of the
680 function is. */
681 return;
682
683 prologue_end = min (prologue_end, prev_pc);
684
685 thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
686 }
687
688 /* This function decodes an ARM function prologue to determine:
689 1) the size of the stack frame
690 2) which registers are saved on it
691 3) the offsets of saved regs
692 4) the offset from the stack pointer to the frame pointer
693 This information is stored in the "extra" fields of the frame_info.
694
695 There are two basic forms for the ARM prologue. The fixed argument
696 function call will look like:
697
698 mov ip, sp
699 stmfd sp!, {fp, ip, lr, pc}
700 sub fp, ip, #4
701 [sub sp, sp, #4]
702
703 Which would create this stack frame (offsets relative to FP):
704 IP -> 4 (caller's stack)
705 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
706 -4 LR (return address in caller)
707 -8 IP (copy of caller's SP)
708 -12 FP (caller's FP)
709 SP -> -28 Local variables
710
711 The frame size would thus be 32 bytes, and the frame offset would be
712 28 bytes. The stmfd call can also save any of the vN registers it
713 plans to use, which increases the frame size accordingly.
714
715 Note: The stored PC is 8 off of the STMFD instruction that stored it
716 because the ARM Store instructions always store PC + 8 when you read
717 the PC register.
718
719 A variable argument function call will look like:
720
721 mov ip, sp
722 stmfd sp!, {a1, a2, a3, a4}
723 stmfd sp!, {fp, ip, lr, pc}
724 sub fp, ip, #20
725
726 Which would create this stack frame (offsets relative to FP):
727 IP -> 20 (caller's stack)
728 16 A4
729 12 A3
730 8 A2
731 4 A1
732 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
733 -4 LR (return address in caller)
734 -8 IP (copy of caller's SP)
735 -12 FP (caller's FP)
736 SP -> -28 Local variables
737
738 The frame size would thus be 48 bytes, and the frame offset would be
739 28 bytes.
740
741 There is another potential complication, which is that the optimizer
742 will try to separate the store of fp in the "stmfd" instruction from
743 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
744 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
745
746 Also, note, the original version of the ARM toolchain claimed that there
747 should be an
748
749 instruction at the end of the prologue. I have never seen GCC produce
750 this, and the ARM docs don't mention it. We still test for it below in
751 case it happens...
752
753 */
754
755 static void
756 arm_scan_prologue (struct frame_info *this_frame,
757 struct arm_prologue_cache *cache)
758 {
759 struct gdbarch *gdbarch = get_frame_arch (this_frame);
760 int regno;
761 CORE_ADDR prologue_start, prologue_end, current_pc;
762 CORE_ADDR prev_pc = get_frame_pc (this_frame);
763 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
764 pv_t regs[ARM_FPS_REGNUM];
765 struct pv_area *stack;
766 struct cleanup *back_to;
767 CORE_ADDR offset;
768
769 /* Assume there is no frame until proven otherwise. */
770 cache->framereg = ARM_SP_REGNUM;
771 cache->framesize = 0;
772
773 /* Check for Thumb prologue. */
774 if (arm_frame_is_thumb (this_frame))
775 {
776 thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
777 return;
778 }
779
780 /* Find the function prologue. If we can't find the function in
781 the symbol table, peek in the stack frame to find the PC. */
782 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
783 &prologue_end))
784 {
785 /* One way to find the end of the prologue (which works well
786 for unoptimized code) is to do the following:
787
788 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
789
790 if (sal.line == 0)
791 prologue_end = prev_pc;
792 else if (sal.end < prologue_end)
793 prologue_end = sal.end;
794
795 This mechanism is very accurate so long as the optimizer
796 doesn't move any instructions from the function body into the
797 prologue. If this happens, sal.end will be the last
798 instruction in the first hunk of prologue code just before
799 the first instruction that the scheduler has moved from
800 the body to the prologue.
801
802 In order to make sure that we scan all of the prologue
803 instructions, we use a slightly less accurate mechanism which
804 may scan more than necessary. To help compensate for this
805 lack of accuracy, the prologue scanning loop below contains
806 several clauses which'll cause the loop to terminate early if
807 an implausible prologue instruction is encountered.
808
809 The expression
810
811 prologue_start + 64
812
813 is a suitable endpoint since it accounts for the largest
814 possible prologue plus up to five instructions inserted by
815 the scheduler. */
816
817 if (prologue_end > prologue_start + 64)
818 {
819 prologue_end = prologue_start + 64; /* See above. */
820 }
821 }
822 else
823 {
824 /* We have no symbol information. Our only option is to assume this
825 function has a standard stack frame and the normal frame register.
826 Then, we can find the value of our frame pointer on entrance to
827 the callee (or at the present moment if this is the innermost frame).
828 The value stored there should be the address of the stmfd + 8. */
829 CORE_ADDR frame_loc;
830 LONGEST return_value;
831
832 frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
833 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
834 return;
835 else
836 {
837 prologue_start = gdbarch_addr_bits_remove
838 (gdbarch, return_value) - 8;
839 prologue_end = prologue_start + 64; /* See above. */
840 }
841 }
842
843 if (prev_pc < prologue_end)
844 prologue_end = prev_pc;
845
846 /* Now search the prologue looking for instructions that set up the
847 frame pointer, adjust the stack pointer, and save registers.
848
849 Be careful, however, and if it doesn't look like a prologue,
850 don't try to scan it. If, for instance, a frameless function
851 begins with stmfd sp!, then we will tell ourselves there is
852 a frame, which will confuse stack traceback, as well as "finish"
853 and other operations that rely on a knowledge of the stack
854 traceback.
855
856 In the APCS, the prologue should start with "mov ip, sp" so
857 if we don't see this as the first insn, we will stop.
858
859 [Note: This doesn't seem to be true any longer, so it's now an
860 optional part of the prologue. - Kevin Buettner, 2001-11-20]
861
862 [Note further: The "mov ip,sp" only seems to be missing in
863 frameless functions at optimization level "-O2" or above,
864 in which case it is often (but not always) replaced by
865 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
866
867 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
868 regs[regno] = pv_register (regno, 0);
869 stack = make_pv_area (ARM_SP_REGNUM);
870 back_to = make_cleanup_free_pv_area (stack);
871
872 for (current_pc = prologue_start;
873 current_pc < prologue_end;
874 current_pc += 4)
875 {
876 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
877
878 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
879 insn = SWAP_INT (insn);
880
881 if (insn == 0xe1a0c00d) /* mov ip, sp */
882 {
883 regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
884 continue;
885 }
886 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
887 {
888 unsigned imm = insn & 0xff; /* immediate value */
889 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
890 imm = (imm >> rot) | (imm << (32 - rot));
891 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
892 continue;
893 }
894 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
895 {
896 unsigned imm = insn & 0xff; /* immediate value */
897 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
898 imm = (imm >> rot) | (imm << (32 - rot));
899 regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
900 continue;
901 }
902 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
903 {
904 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
905 break;
906 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
907 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
908 continue;
909 }
910 else if ((insn & 0xffff0000) == 0xe92d0000)
911 /* stmfd sp!, {..., fp, ip, lr, pc}
912 or
913 stmfd sp!, {a1, a2, a3, a4} */
914 {
915 int mask = insn & 0xffff;
916
917 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
918 break;
919
920 /* Calculate offsets of saved registers. */
921 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
922 if (mask & (1 << regno))
923 {
924 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
925 pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
926 }
927 }
928 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
929 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
930 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
931 {
932 /* No need to add this to saved_regs -- it's just an arg reg. */
933 continue;
934 }
935 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
936 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
937 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
938 {
939 /* No need to add this to saved_regs -- it's just an arg reg. */
940 continue;
941 }
942 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
943 {
944 unsigned imm = insn & 0xff; /* immediate value */
945 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
946 imm = (imm >> rot) | (imm << (32 - rot));
947 regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
948 }
949 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
950 {
951 unsigned imm = insn & 0xff; /* immediate value */
952 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
953 imm = (imm >> rot) | (imm << (32 - rot));
954 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
955 }
956 else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
957 && gdbarch_tdep (gdbarch)->have_fpa_registers)
958 {
959 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
960 break;
961
962 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
963 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
964 pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
965 }
966 else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
967 && gdbarch_tdep (gdbarch)->have_fpa_registers)
968 {
969 int n_saved_fp_regs;
970 unsigned int fp_start_reg, fp_bound_reg;
971
972 if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
973 break;
974
975 if ((insn & 0x800) == 0x800) /* N0 is set */
976 {
977 if ((insn & 0x40000) == 0x40000) /* N1 is set */
978 n_saved_fp_regs = 3;
979 else
980 n_saved_fp_regs = 1;
981 }
982 else
983 {
984 if ((insn & 0x40000) == 0x40000) /* N1 is set */
985 n_saved_fp_regs = 2;
986 else
987 n_saved_fp_regs = 4;
988 }
989
990 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
991 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
992 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
993 {
994 regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
995 pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
996 regs[fp_start_reg++]);
997 }
998 }
999 else if ((insn & 0xf0000000) != 0xe0000000)
1000 break; /* Condition not true, exit early */
1001 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
1002 break; /* Don't scan past a block load */
1003 else
1004 /* The optimizer might shove anything into the prologue,
1005 so we just skip what we don't recognize. */
1006 continue;
1007 }
1008
1009 /* The frame size is just the distance from the frame register
1010 to the original stack pointer. */
1011 if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
1012 {
1013 /* Frame pointer is fp. */
1014 cache->framereg = ARM_FP_REGNUM;
1015 cache->framesize = -regs[ARM_FP_REGNUM].k;
1016 }
1017 else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
1018 {
1019 /* Try the stack pointer... this is a bit desperate. */
1020 cache->framereg = ARM_SP_REGNUM;
1021 cache->framesize = -regs[ARM_SP_REGNUM].k;
1022 }
1023 else
1024 {
1025 /* We're just out of luck. We don't know where the frame is. */
1026 cache->framereg = -1;
1027 cache->framesize = 0;
1028 }
1029
1030 for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
1031 if (pv_area_find_reg (stack, gdbarch, regno, &offset))
1032 cache->saved_regs[regno].addr = offset;
1033
1034 do_cleanups (back_to);
1035 }
1036
1037 static struct arm_prologue_cache *
1038 arm_make_prologue_cache (struct frame_info *this_frame)
1039 {
1040 int reg;
1041 struct arm_prologue_cache *cache;
1042 CORE_ADDR unwound_fp;
1043
1044 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1045 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1046
1047 arm_scan_prologue (this_frame, cache);
1048
1049 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
1050 if (unwound_fp == 0)
1051 return cache;
1052
1053 cache->prev_sp = unwound_fp + cache->framesize;
1054
1055 /* Calculate actual addresses of saved registers using offsets
1056 determined by arm_scan_prologue. */
1057 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
1058 if (trad_frame_addr_p (cache->saved_regs, reg))
1059 cache->saved_regs[reg].addr += cache->prev_sp;
1060
1061 return cache;
1062 }
1063
1064 /* Our frame ID for a normal frame is the current function's starting PC
1065 and the caller's SP when we were called. */
1066
1067 static void
1068 arm_prologue_this_id (struct frame_info *this_frame,
1069 void **this_cache,
1070 struct frame_id *this_id)
1071 {
1072 struct arm_prologue_cache *cache;
1073 struct frame_id id;
1074 CORE_ADDR pc, func;
1075
1076 if (*this_cache == NULL)
1077 *this_cache = arm_make_prologue_cache (this_frame);
1078 cache = *this_cache;
1079
1080 /* This is meant to halt the backtrace at "_start". */
1081 pc = get_frame_pc (this_frame);
1082 if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
1083 return;
1084
1085 /* If we've hit a wall, stop. */
1086 if (cache->prev_sp == 0)
1087 return;
1088
1089 func = get_frame_func (this_frame);
1090 id = frame_id_build (cache->prev_sp, func);
1091 *this_id = id;
1092 }
1093
1094 static struct value *
1095 arm_prologue_prev_register (struct frame_info *this_frame,
1096 void **this_cache,
1097 int prev_regnum)
1098 {
1099 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1100 struct arm_prologue_cache *cache;
1101
1102 if (*this_cache == NULL)
1103 *this_cache = arm_make_prologue_cache (this_frame);
1104 cache = *this_cache;
1105
1106 /* If we are asked to unwind the PC, then we need to return the LR
1107 instead. The prologue may save PC, but it will point into this
1108 frame's prologue, not the next frame's resume location. Also
1109 strip the saved T bit. A valid LR may have the low bit set, but
1110 a valid PC never does. */
1111 if (prev_regnum == ARM_PC_REGNUM)
1112 {
1113 CORE_ADDR lr;
1114
1115 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1116 return frame_unwind_got_constant (this_frame, prev_regnum,
1117 arm_addr_bits_remove (gdbarch, lr));
1118 }
1119
1120 /* SP is generally not saved to the stack, but this frame is
1121 identified by the next frame's stack pointer at the time of the call.
1122 The value was already reconstructed into PREV_SP. */
1123 if (prev_regnum == ARM_SP_REGNUM)
1124 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
1125
1126 /* The CPSR may have been changed by the call instruction and by the
1127 called function. The only bit we can reconstruct is the T bit,
1128 by checking the low bit of LR as of the call. This is a reliable
1129 indicator of Thumb-ness except for some ARM v4T pre-interworking
1130 Thumb code, which could get away with a clear low bit as long as
1131 the called function did not use bx. Guess that all other
1132 bits are unchanged; the condition flags are presumably lost,
1133 but the processor status is likely valid. */
1134 if (prev_regnum == ARM_PS_REGNUM)
1135 {
1136 CORE_ADDR lr, cpsr;
1137
1138 cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
1139 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1140 if (IS_THUMB_ADDR (lr))
1141 cpsr |= CPSR_T;
1142 else
1143 cpsr &= ~CPSR_T;
1144 return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
1145 }
1146
1147 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
1148 prev_regnum);
1149 }
1150
1151 struct frame_unwind arm_prologue_unwind = {
1152 NORMAL_FRAME,
1153 arm_prologue_this_id,
1154 arm_prologue_prev_register,
1155 NULL,
1156 default_frame_sniffer
1157 };
1158
1159 static struct arm_prologue_cache *
1160 arm_make_stub_cache (struct frame_info *this_frame)
1161 {
1162 int reg;
1163 struct arm_prologue_cache *cache;
1164 CORE_ADDR unwound_fp;
1165
1166 cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
1167 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1168
1169 cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
1170
1171 return cache;
1172 }
1173
1174 /* Our frame ID for a stub frame is the current SP and LR. */
1175
1176 static void
1177 arm_stub_this_id (struct frame_info *this_frame,
1178 void **this_cache,
1179 struct frame_id *this_id)
1180 {
1181 struct arm_prologue_cache *cache;
1182
1183 if (*this_cache == NULL)
1184 *this_cache = arm_make_stub_cache (this_frame);
1185 cache = *this_cache;
1186
1187 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
1188 }
1189
1190 static int
1191 arm_stub_unwind_sniffer (const struct frame_unwind *self,
1192 struct frame_info *this_frame,
1193 void **this_prologue_cache)
1194 {
1195 CORE_ADDR addr_in_block;
1196 char dummy[4];
1197
1198 addr_in_block = get_frame_address_in_block (this_frame);
1199 if (in_plt_section (addr_in_block, NULL)
1200 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1201 return 1;
1202
1203 return 0;
1204 }
1205
1206 struct frame_unwind arm_stub_unwind = {
1207 NORMAL_FRAME,
1208 arm_stub_this_id,
1209 arm_prologue_prev_register,
1210 NULL,
1211 arm_stub_unwind_sniffer
1212 };
1213
1214 static CORE_ADDR
1215 arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1216 {
1217 struct arm_prologue_cache *cache;
1218
1219 if (*this_cache == NULL)
1220 *this_cache = arm_make_prologue_cache (this_frame);
1221 cache = *this_cache;
1222
1223 return cache->prev_sp - cache->framesize;
1224 }
1225
1226 struct frame_base arm_normal_base = {
1227 &arm_prologue_unwind,
1228 arm_normal_frame_base,
1229 arm_normal_frame_base,
1230 arm_normal_frame_base
1231 };
1232
1233 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1234 dummy frame. The frame ID's base needs to match the TOS value
1235 saved by save_dummy_frame_tos() and returned from
1236 arm_push_dummy_call, and the PC needs to match the dummy frame's
1237 breakpoint. */
1238
1239 static struct frame_id
1240 arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1241 {
1242 return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
1243 get_frame_pc (this_frame));
1244 }
1245
1246 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1247 be used to construct the previous frame's ID, after looking up the
1248 containing function). */
1249
1250 static CORE_ADDR
1251 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1252 {
1253 CORE_ADDR pc;
1254 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1255 return arm_addr_bits_remove (gdbarch, pc);
1256 }
1257
1258 static CORE_ADDR
1259 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1260 {
1261 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1262 }
1263
1264 static struct value *
1265 arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
1266 int regnum)
1267 {
1268 struct gdbarch * gdbarch = get_frame_arch (this_frame);
1269 CORE_ADDR lr, cpsr;
1270
1271 switch (regnum)
1272 {
1273 case ARM_PC_REGNUM:
1274 /* The PC is normally copied from the return column, which
1275 describes saves of LR. However, that version may have an
1276 extra bit set to indicate Thumb state. The bit is not
1277 part of the PC. */
1278 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1279 return frame_unwind_got_constant (this_frame, regnum,
1280 arm_addr_bits_remove (gdbarch, lr));
1281
1282 case ARM_PS_REGNUM:
1283 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1284 cpsr = get_frame_register_unsigned (this_frame, regnum);
1285 lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
1286 if (IS_THUMB_ADDR (lr))
1287 cpsr |= CPSR_T;
1288 else
1289 cpsr &= ~CPSR_T;
1290 return frame_unwind_got_constant (this_frame, regnum, cpsr);
1291
1292 default:
1293 internal_error (__FILE__, __LINE__,
1294 _("Unexpected register %d"), regnum);
1295 }
1296 }
1297
1298 static void
1299 arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1300 struct dwarf2_frame_state_reg *reg,
1301 struct frame_info *this_frame)
1302 {
1303 switch (regnum)
1304 {
1305 case ARM_PC_REGNUM:
1306 case ARM_PS_REGNUM:
1307 reg->how = DWARF2_FRAME_REG_FN;
1308 reg->loc.fn = arm_dwarf2_prev_register;
1309 break;
1310 case ARM_SP_REGNUM:
1311 reg->how = DWARF2_FRAME_REG_CFA;
1312 break;
1313 }
1314 }
1315
1316 /* When arguments must be pushed onto the stack, they go on in reverse
1317 order. The code below implements a FILO (stack) to do this. */
1318
1319 struct stack_item
1320 {
1321 int len;
1322 struct stack_item *prev;
1323 void *data;
1324 };
1325
1326 static struct stack_item *
1327 push_stack_item (struct stack_item *prev, void *contents, int len)
1328 {
1329 struct stack_item *si;
1330 si = xmalloc (sizeof (struct stack_item));
1331 si->data = xmalloc (len);
1332 si->len = len;
1333 si->prev = prev;
1334 memcpy (si->data, contents, len);
1335 return si;
1336 }
1337
1338 static struct stack_item *
1339 pop_stack_item (struct stack_item *si)
1340 {
1341 struct stack_item *dead = si;
1342 si = si->prev;
1343 xfree (dead->data);
1344 xfree (dead);
1345 return si;
1346 }
1347
1348
1349 /* Return the alignment (in bytes) of the given type. */
1350
1351 static int
1352 arm_type_align (struct type *t)
1353 {
1354 int n;
1355 int align;
1356 int falign;
1357
1358 t = check_typedef (t);
1359 switch (TYPE_CODE (t))
1360 {
1361 default:
1362 /* Should never happen. */
1363 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1364 return 4;
1365
1366 case TYPE_CODE_PTR:
1367 case TYPE_CODE_ENUM:
1368 case TYPE_CODE_INT:
1369 case TYPE_CODE_FLT:
1370 case TYPE_CODE_SET:
1371 case TYPE_CODE_RANGE:
1372 case TYPE_CODE_BITSTRING:
1373 case TYPE_CODE_REF:
1374 case TYPE_CODE_CHAR:
1375 case TYPE_CODE_BOOL:
1376 return TYPE_LENGTH (t);
1377
1378 case TYPE_CODE_ARRAY:
1379 case TYPE_CODE_COMPLEX:
1380 /* TODO: What about vector types? */
1381 return arm_type_align (TYPE_TARGET_TYPE (t));
1382
1383 case TYPE_CODE_STRUCT:
1384 case TYPE_CODE_UNION:
1385 align = 1;
1386 for (n = 0; n < TYPE_NFIELDS (t); n++)
1387 {
1388 falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
1389 if (falign > align)
1390 align = falign;
1391 }
1392 return align;
1393 }
1394 }
1395
1396 /* We currently only support passing parameters in integer registers. This
1397 conforms with GCC's default model. Several other variants exist and
1398 we should probably support some of them based on the selected ABI. */
1399
1400 static CORE_ADDR
1401 arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1402 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1403 struct value **args, CORE_ADDR sp, int struct_return,
1404 CORE_ADDR struct_addr)
1405 {
1406 int argnum;
1407 int argreg;
1408 int nstack;
1409 struct stack_item *si = NULL;
1410
1411 /* Set the return address. For the ARM, the return breakpoint is
1412 always at BP_ADDR. */
1413 /* XXX Fix for Thumb. */
1414 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1415
1416 /* Walk through the list of args and determine how large a temporary
1417 stack is required. Need to take care here as structs may be
1418 passed on the stack, and we have to to push them. */
1419 nstack = 0;
1420
1421 argreg = ARM_A1_REGNUM;
1422 nstack = 0;
1423
1424 /* The struct_return pointer occupies the first parameter
1425 passing register. */
1426 if (struct_return)
1427 {
1428 if (arm_debug)
1429 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1430 gdbarch_register_name (gdbarch, argreg),
1431 paddr (struct_addr));
1432 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1433 argreg++;
1434 }
1435
1436 for (argnum = 0; argnum < nargs; argnum++)
1437 {
1438 int len;
1439 struct type *arg_type;
1440 struct type *target_type;
1441 enum type_code typecode;
1442 bfd_byte *val;
1443 int align;
1444
1445 arg_type = check_typedef (value_type (args[argnum]));
1446 len = TYPE_LENGTH (arg_type);
1447 target_type = TYPE_TARGET_TYPE (arg_type);
1448 typecode = TYPE_CODE (arg_type);
1449 val = value_contents_writeable (args[argnum]);
1450
1451 align = arm_type_align (arg_type);
1452 /* Round alignment up to a whole number of words. */
1453 align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
1454 /* Different ABIs have different maximum alignments. */
1455 if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
1456 {
1457 /* The APCS ABI only requires word alignment. */
1458 align = INT_REGISTER_SIZE;
1459 }
1460 else
1461 {
1462 /* The AAPCS requires at most doubleword alignment. */
1463 if (align > INT_REGISTER_SIZE * 2)
1464 align = INT_REGISTER_SIZE * 2;
1465 }
1466
1467 /* Push stack padding for dowubleword alignment. */
1468 if (nstack & (align - 1))
1469 {
1470 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1471 nstack += INT_REGISTER_SIZE;
1472 }
1473
1474 /* Doubleword aligned quantities must go in even register pairs. */
1475 if (argreg <= ARM_LAST_ARG_REGNUM
1476 && align > INT_REGISTER_SIZE
1477 && argreg & 1)
1478 argreg++;
1479
1480 /* If the argument is a pointer to a function, and it is a
1481 Thumb function, create a LOCAL copy of the value and set
1482 the THUMB bit in it. */
1483 if (TYPE_CODE_PTR == typecode
1484 && target_type != NULL
1485 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1486 {
1487 CORE_ADDR regval = extract_unsigned_integer (val, len);
1488 if (arm_pc_is_thumb (regval))
1489 {
1490 val = alloca (len);
1491 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1492 }
1493 }
1494
1495 /* Copy the argument to general registers or the stack in
1496 register-sized pieces. Large arguments are split between
1497 registers and stack. */
1498 while (len > 0)
1499 {
1500 int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
1501
1502 if (argreg <= ARM_LAST_ARG_REGNUM)
1503 {
1504 /* The argument is being passed in a general purpose
1505 register. */
1506 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1507 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1508 regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
1509 if (arm_debug)
1510 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1511 argnum,
1512 gdbarch_register_name
1513 (gdbarch, argreg),
1514 phex (regval, INT_REGISTER_SIZE));
1515 regcache_cooked_write_unsigned (regcache, argreg, regval);
1516 argreg++;
1517 }
1518 else
1519 {
1520 /* Push the arguments onto the stack. */
1521 if (arm_debug)
1522 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1523 argnum, nstack);
1524 si = push_stack_item (si, val, INT_REGISTER_SIZE);
1525 nstack += INT_REGISTER_SIZE;
1526 }
1527
1528 len -= partial_len;
1529 val += partial_len;
1530 }
1531 }
1532 /* If we have an odd number of words to push, then decrement the stack
1533 by one word now, so first stack argument will be dword aligned. */
1534 if (nstack & 4)
1535 sp -= 4;
1536
1537 while (si)
1538 {
1539 sp -= si->len;
1540 write_memory (sp, si->data, si->len);
1541 si = pop_stack_item (si);
1542 }
1543
1544 /* Finally, update teh SP register. */
1545 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1546
1547 return sp;
1548 }
1549
1550
1551 /* Always align the frame to an 8-byte boundary. This is required on
1552 some platforms and harmless on the rest. */
1553
1554 static CORE_ADDR
1555 arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1556 {
1557 /* Align the stack to eight bytes. */
1558 return sp & ~ (CORE_ADDR) 7;
1559 }
1560
1561 static void
1562 print_fpu_flags (int flags)
1563 {
1564 if (flags & (1 << 0))
1565 fputs ("IVO ", stdout);
1566 if (flags & (1 << 1))
1567 fputs ("DVZ ", stdout);
1568 if (flags & (1 << 2))
1569 fputs ("OFL ", stdout);
1570 if (flags & (1 << 3))
1571 fputs ("UFL ", stdout);
1572 if (flags & (1 << 4))
1573 fputs ("INX ", stdout);
1574 putchar ('\n');
1575 }
1576
1577 /* Print interesting information about the floating point processor
1578 (if present) or emulator. */
1579 static void
1580 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1581 struct frame_info *frame, const char *args)
1582 {
1583 unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
1584 int type;
1585
1586 type = (status >> 24) & 127;
1587 if (status & (1 << 31))
1588 printf (_("Hardware FPU type %d\n"), type);
1589 else
1590 printf (_("Software FPU type %d\n"), type);
1591 /* i18n: [floating point unit] mask */
1592 fputs (_("mask: "), stdout);
1593 print_fpu_flags (status >> 16);
1594 /* i18n: [floating point unit] flags */
1595 fputs (_("flags: "), stdout);
1596 print_fpu_flags (status);
1597 }
1598
1599 /* Return the GDB type object for the "standard" data type of data in
1600 register N. */
1601
1602 static struct type *
1603 arm_register_type (struct gdbarch *gdbarch, int regnum)
1604 {
1605 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1606 return builtin_type_arm_ext;
1607 else if (regnum == ARM_SP_REGNUM)
1608 return builtin_type_void_data_ptr;
1609 else if (regnum == ARM_PC_REGNUM)
1610 return builtin_type_void_func_ptr;
1611 else if (regnum >= ARRAY_SIZE (arm_register_names))
1612 /* These registers are only supported on targets which supply
1613 an XML description. */
1614 return builtin_type_int0;
1615 else
1616 return builtin_type_uint32;
1617 }
1618
1619 /* Map a DWARF register REGNUM onto the appropriate GDB register
1620 number. */
1621
1622 static int
1623 arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1624 {
1625 /* Core integer regs. */
1626 if (reg >= 0 && reg <= 15)
1627 return reg;
1628
1629 /* Legacy FPA encoding. These were once used in a way which
1630 overlapped with VFP register numbering, so their use is
1631 discouraged, but GDB doesn't support the ARM toolchain
1632 which used them for VFP. */
1633 if (reg >= 16 && reg <= 23)
1634 return ARM_F0_REGNUM + reg - 16;
1635
1636 /* New assignments for the FPA registers. */
1637 if (reg >= 96 && reg <= 103)
1638 return ARM_F0_REGNUM + reg - 96;
1639
1640 /* WMMX register assignments. */
1641 if (reg >= 104 && reg <= 111)
1642 return ARM_WCGR0_REGNUM + reg - 104;
1643
1644 if (reg >= 112 && reg <= 127)
1645 return ARM_WR0_REGNUM + reg - 112;
1646
1647 if (reg >= 192 && reg <= 199)
1648 return ARM_WC0_REGNUM + reg - 192;
1649
1650 return -1;
1651 }
1652
1653 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1654 static int
1655 arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1656 {
1657 int reg = regnum;
1658 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
1659
1660 if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
1661 return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
1662
1663 if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
1664 return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
1665
1666 if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
1667 return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
1668
1669 if (reg < NUM_GREGS)
1670 return SIM_ARM_R0_REGNUM + reg;
1671 reg -= NUM_GREGS;
1672
1673 if (reg < NUM_FREGS)
1674 return SIM_ARM_FP0_REGNUM + reg;
1675 reg -= NUM_FREGS;
1676
1677 if (reg < NUM_SREGS)
1678 return SIM_ARM_FPS_REGNUM + reg;
1679 reg -= NUM_SREGS;
1680
1681 internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
1682 }
1683
1684 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1685 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1686 It is thought that this is is the floating-point register format on
1687 little-endian systems. */
1688
1689 static void
1690 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1691 void *dbl, int endianess)
1692 {
1693 DOUBLEST d;
1694
1695 if (endianess == BFD_ENDIAN_BIG)
1696 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1697 else
1698 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1699 ptr, &d);
1700 floatformat_from_doublest (fmt, &d, dbl);
1701 }
1702
1703 static void
1704 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
1705 int endianess)
1706 {
1707 DOUBLEST d;
1708
1709 floatformat_to_doublest (fmt, ptr, &d);
1710 if (endianess == BFD_ENDIAN_BIG)
1711 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1712 else
1713 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1714 &d, dbl);
1715 }
1716
1717 static int
1718 condition_true (unsigned long cond, unsigned long status_reg)
1719 {
1720 if (cond == INST_AL || cond == INST_NV)
1721 return 1;
1722
1723 switch (cond)
1724 {
1725 case INST_EQ:
1726 return ((status_reg & FLAG_Z) != 0);
1727 case INST_NE:
1728 return ((status_reg & FLAG_Z) == 0);
1729 case INST_CS:
1730 return ((status_reg & FLAG_C) != 0);
1731 case INST_CC:
1732 return ((status_reg & FLAG_C) == 0);
1733 case INST_MI:
1734 return ((status_reg & FLAG_N) != 0);
1735 case INST_PL:
1736 return ((status_reg & FLAG_N) == 0);
1737 case INST_VS:
1738 return ((status_reg & FLAG_V) != 0);
1739 case INST_VC:
1740 return ((status_reg & FLAG_V) == 0);
1741 case INST_HI:
1742 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1743 case INST_LS:
1744 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1745 case INST_GE:
1746 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1747 case INST_LT:
1748 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1749 case INST_GT:
1750 return (((status_reg & FLAG_Z) == 0) &&
1751 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1752 case INST_LE:
1753 return (((status_reg & FLAG_Z) != 0) ||
1754 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1755 }
1756 return 1;
1757 }
1758
1759 /* Support routines for single stepping. Calculate the next PC value. */
1760 #define submask(x) ((1L << ((x) + 1)) - 1)
1761 #define bit(obj,st) (((obj) >> (st)) & 1)
1762 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1763 #define sbits(obj,st,fn) \
1764 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1765 #define BranchDest(addr,instr) \
1766 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1767 #define ARM_PC_32 1
1768
1769 static unsigned long
1770 shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
1771 unsigned long pc_val, unsigned long status_reg)
1772 {
1773 unsigned long res, shift;
1774 int rm = bits (inst, 0, 3);
1775 unsigned long shifttype = bits (inst, 5, 6);
1776
1777 if (bit (inst, 4))
1778 {
1779 int rs = bits (inst, 8, 11);
1780 shift = (rs == 15 ? pc_val + 8
1781 : get_frame_register_unsigned (frame, rs)) & 0xFF;
1782 }
1783 else
1784 shift = bits (inst, 7, 11);
1785
1786 res = (rm == 15
1787 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1788 + (bit (inst, 4) ? 12 : 8))
1789 : get_frame_register_unsigned (frame, rm));
1790
1791 switch (shifttype)
1792 {
1793 case 0: /* LSL */
1794 res = shift >= 32 ? 0 : res << shift;
1795 break;
1796
1797 case 1: /* LSR */
1798 res = shift >= 32 ? 0 : res >> shift;
1799 break;
1800
1801 case 2: /* ASR */
1802 if (shift >= 32)
1803 shift = 31;
1804 res = ((res & 0x80000000L)
1805 ? ~((~res) >> shift) : res >> shift);
1806 break;
1807
1808 case 3: /* ROR/RRX */
1809 shift &= 31;
1810 if (shift == 0)
1811 res = (res >> 1) | (carry ? 0x80000000L : 0);
1812 else
1813 res = (res >> shift) | (res << (32 - shift));
1814 break;
1815 }
1816
1817 return res & 0xffffffff;
1818 }
1819
1820 /* Return number of 1-bits in VAL. */
1821
1822 static int
1823 bitcount (unsigned long val)
1824 {
1825 int nbits;
1826 for (nbits = 0; val != 0; nbits++)
1827 val &= val - 1; /* delete rightmost 1-bit in val */
1828 return nbits;
1829 }
1830
1831 static CORE_ADDR
1832 thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1833 {
1834 struct gdbarch *gdbarch = get_frame_arch (frame);
1835 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1836 unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
1837 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1838 unsigned long offset;
1839
1840 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
1841 inst1 = SWAP_SHORT (inst1);
1842
1843 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1844 {
1845 CORE_ADDR sp;
1846
1847 /* Fetch the saved PC from the stack. It's stored above
1848 all of the other registers. */
1849 offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
1850 sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
1851 nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
1852 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1853 if (nextpc == pc)
1854 error (_("Infinite loop detected"));
1855 }
1856 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1857 {
1858 unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1859 unsigned long cond = bits (inst1, 8, 11);
1860 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1861 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1862 }
1863 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1864 {
1865 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1866 }
1867 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1868 {
1869 unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
1870 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
1871 inst2 = SWAP_SHORT (inst2);
1872 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1873 nextpc = pc_val + offset;
1874 /* For BLX make sure to clear the low bits. */
1875 if (bits (inst2, 11, 12) == 1)
1876 nextpc = nextpc & 0xfffffffc;
1877 }
1878 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1879 {
1880 if (bits (inst1, 3, 6) == 0x0f)
1881 nextpc = pc_val;
1882 else
1883 nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
1884
1885 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1886 if (nextpc == pc)
1887 error (_("Infinite loop detected"));
1888 }
1889
1890 return nextpc;
1891 }
1892
1893 CORE_ADDR
1894 arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
1895 {
1896 struct gdbarch *gdbarch = get_frame_arch (frame);
1897 unsigned long pc_val;
1898 unsigned long this_instr;
1899 unsigned long status;
1900 CORE_ADDR nextpc;
1901
1902 if (arm_frame_is_thumb (frame))
1903 return thumb_get_next_pc (frame, pc);
1904
1905 pc_val = (unsigned long) pc;
1906 this_instr = read_memory_unsigned_integer (pc, 4);
1907
1908 if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
1909 this_instr = SWAP_INT (this_instr);
1910
1911 status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
1912 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1913
1914 if (bits (this_instr, 28, 31) == INST_NV)
1915 switch (bits (this_instr, 24, 27))
1916 {
1917 case 0xa:
1918 case 0xb:
1919 {
1920 /* Branch with Link and change to Thumb. */
1921 nextpc = BranchDest (pc, this_instr);
1922 nextpc |= bit (this_instr, 24) << 1;
1923
1924 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
1925 if (nextpc == pc)
1926 error (_("Infinite loop detected"));
1927 break;
1928 }
1929 case 0xc:
1930 case 0xd:
1931 case 0xe:
1932 /* Coprocessor register transfer. */
1933 if (bits (this_instr, 12, 15) == 15)
1934 error (_("Invalid update to pc in instruction"));
1935 break;
1936 }
1937 else if (condition_true (bits (this_instr, 28, 31), status))
1938 {
1939 switch (bits (this_instr, 24, 27))
1940 {
1941 case 0x0:
1942 case 0x1: /* data processing */
1943 case 0x2:
1944 case 0x3:
1945 {
1946 unsigned long operand1, operand2, result = 0;
1947 unsigned long rn;
1948 int c;
1949
1950 if (bits (this_instr, 12, 15) != 15)
1951 break;
1952
1953 if (bits (this_instr, 22, 25) == 0
1954 && bits (this_instr, 4, 7) == 9) /* multiply */
1955 error (_("Invalid update to pc in instruction"));
1956
1957 /* BX <reg>, BLX <reg> */
1958 if (bits (this_instr, 4, 27) == 0x12fff1
1959 || bits (this_instr, 4, 27) == 0x12fff3)
1960 {
1961 rn = bits (this_instr, 0, 3);
1962 result = (rn == 15) ? pc_val + 8
1963 : get_frame_register_unsigned (frame, rn);
1964 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
1965 (gdbarch, result);
1966
1967 if (nextpc == pc)
1968 error (_("Infinite loop detected"));
1969
1970 return nextpc;
1971 }
1972
1973 /* Multiply into PC */
1974 c = (status & FLAG_C) ? 1 : 0;
1975 rn = bits (this_instr, 16, 19);
1976 operand1 = (rn == 15) ? pc_val + 8
1977 : get_frame_register_unsigned (frame, rn);
1978
1979 if (bit (this_instr, 25))
1980 {
1981 unsigned long immval = bits (this_instr, 0, 7);
1982 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1983 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1984 & 0xffffffff;
1985 }
1986 else /* operand 2 is a shifted register */
1987 operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
1988
1989 switch (bits (this_instr, 21, 24))
1990 {
1991 case 0x0: /*and */
1992 result = operand1 & operand2;
1993 break;
1994
1995 case 0x1: /*eor */
1996 result = operand1 ^ operand2;
1997 break;
1998
1999 case 0x2: /*sub */
2000 result = operand1 - operand2;
2001 break;
2002
2003 case 0x3: /*rsb */
2004 result = operand2 - operand1;
2005 break;
2006
2007 case 0x4: /*add */
2008 result = operand1 + operand2;
2009 break;
2010
2011 case 0x5: /*adc */
2012 result = operand1 + operand2 + c;
2013 break;
2014
2015 case 0x6: /*sbc */
2016 result = operand1 - operand2 + c;
2017 break;
2018
2019 case 0x7: /*rsc */
2020 result = operand2 - operand1 + c;
2021 break;
2022
2023 case 0x8:
2024 case 0x9:
2025 case 0xa:
2026 case 0xb: /* tst, teq, cmp, cmn */
2027 result = (unsigned long) nextpc;
2028 break;
2029
2030 case 0xc: /*orr */
2031 result = operand1 | operand2;
2032 break;
2033
2034 case 0xd: /*mov */
2035 /* Always step into a function. */
2036 result = operand2;
2037 break;
2038
2039 case 0xe: /*bic */
2040 result = operand1 & ~operand2;
2041 break;
2042
2043 case 0xf: /*mvn */
2044 result = ~operand2;
2045 break;
2046 }
2047 nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
2048 (gdbarch, result);
2049
2050 if (nextpc == pc)
2051 error (_("Infinite loop detected"));
2052 break;
2053 }
2054
2055 case 0x4:
2056 case 0x5: /* data transfer */
2057 case 0x6:
2058 case 0x7:
2059 if (bit (this_instr, 20))
2060 {
2061 /* load */
2062 if (bits (this_instr, 12, 15) == 15)
2063 {
2064 /* rd == pc */
2065 unsigned long rn;
2066 unsigned long base;
2067
2068 if (bit (this_instr, 22))
2069 error (_("Invalid update to pc in instruction"));
2070
2071 /* byte write to PC */
2072 rn = bits (this_instr, 16, 19);
2073 base = (rn == 15) ? pc_val + 8
2074 : get_frame_register_unsigned (frame, rn);
2075 if (bit (this_instr, 24))
2076 {
2077 /* pre-indexed */
2078 int c = (status & FLAG_C) ? 1 : 0;
2079 unsigned long offset =
2080 (bit (this_instr, 25)
2081 ? shifted_reg_val (frame, this_instr, c, pc_val, status)
2082 : bits (this_instr, 0, 11));
2083
2084 if (bit (this_instr, 23))
2085 base += offset;
2086 else
2087 base -= offset;
2088 }
2089 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
2090 4);
2091
2092 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2093
2094 if (nextpc == pc)
2095 error (_("Infinite loop detected"));
2096 }
2097 }
2098 break;
2099
2100 case 0x8:
2101 case 0x9: /* block transfer */
2102 if (bit (this_instr, 20))
2103 {
2104 /* LDM */
2105 if (bit (this_instr, 15))
2106 {
2107 /* loading pc */
2108 int offset = 0;
2109
2110 if (bit (this_instr, 23))
2111 {
2112 /* up */
2113 unsigned long reglist = bits (this_instr, 0, 14);
2114 offset = bitcount (reglist) * 4;
2115 if (bit (this_instr, 24)) /* pre */
2116 offset += 4;
2117 }
2118 else if (bit (this_instr, 24))
2119 offset = -4;
2120
2121 {
2122 unsigned long rn_val =
2123 get_frame_register_unsigned (frame,
2124 bits (this_instr, 16, 19));
2125 nextpc =
2126 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
2127 + offset),
2128 4);
2129 }
2130 nextpc = gdbarch_addr_bits_remove
2131 (gdbarch, nextpc);
2132 if (nextpc == pc)
2133 error (_("Infinite loop detected"));
2134 }
2135 }
2136 break;
2137
2138 case 0xb: /* branch & link */
2139 case 0xa: /* branch */
2140 {
2141 nextpc = BranchDest (pc, this_instr);
2142
2143 nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
2144 if (nextpc == pc)
2145 error (_("Infinite loop detected"));
2146 break;
2147 }
2148
2149 case 0xc:
2150 case 0xd:
2151 case 0xe: /* coproc ops */
2152 case 0xf: /* SWI */
2153 break;
2154
2155 default:
2156 fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
2157 return (pc);
2158 }
2159 }
2160
2161 return nextpc;
2162 }
2163
2164 /* single_step() is called just before we want to resume the inferior,
2165 if we want to single-step it but there is no hardware or kernel
2166 single-step support. We find the target of the coming instruction
2167 and breakpoint it. */
2168
2169 int
2170 arm_software_single_step (struct frame_info *frame)
2171 {
2172 /* NOTE: This may insert the wrong breakpoint instruction when
2173 single-stepping over a mode-changing instruction, if the
2174 CPSR heuristics are used. */
2175
2176 CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
2177 insert_single_step_breakpoint (next_pc);
2178
2179 return 1;
2180 }
2181
2182 #include "bfd-in2.h"
2183 #include "libcoff.h"
2184
2185 static int
2186 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
2187 {
2188 if (arm_pc_is_thumb (memaddr))
2189 {
2190 static asymbol *asym;
2191 static combined_entry_type ce;
2192 static struct coff_symbol_struct csym;
2193 static struct bfd fake_bfd;
2194 static bfd_target fake_target;
2195
2196 if (csym.native == NULL)
2197 {
2198 /* Create a fake symbol vector containing a Thumb symbol.
2199 This is solely so that the code in print_insn_little_arm()
2200 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2201 the presence of a Thumb symbol and switch to decoding
2202 Thumb instructions. */
2203
2204 fake_target.flavour = bfd_target_coff_flavour;
2205 fake_bfd.xvec = &fake_target;
2206 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
2207 csym.native = &ce;
2208 csym.symbol.the_bfd = &fake_bfd;
2209 csym.symbol.name = "fake";
2210 asym = (asymbol *) & csym;
2211 }
2212
2213 memaddr = UNMAKE_THUMB_ADDR (memaddr);
2214 info->symbols = &asym;
2215 }
2216 else
2217 info->symbols = NULL;
2218
2219 if (info->endian == BFD_ENDIAN_BIG)
2220 return print_insn_big_arm (memaddr, info);
2221 else
2222 return print_insn_little_arm (memaddr, info);
2223 }
2224
2225 /* The following define instruction sequences that will cause ARM
2226 cpu's to take an undefined instruction trap. These are used to
2227 signal a breakpoint to GDB.
2228
2229 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2230 modes. A different instruction is required for each mode. The ARM
2231 cpu's can also be big or little endian. Thus four different
2232 instructions are needed to support all cases.
2233
2234 Note: ARMv4 defines several new instructions that will take the
2235 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2236 not in fact add the new instructions. The new undefined
2237 instructions in ARMv4 are all instructions that had no defined
2238 behaviour in earlier chips. There is no guarantee that they will
2239 raise an exception, but may be treated as NOP's. In practice, it
2240 may only safe to rely on instructions matching:
2241
2242 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2243 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2244 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2245
2246 Even this may only true if the condition predicate is true. The
2247 following use a condition predicate of ALWAYS so it is always TRUE.
2248
2249 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2250 and NetBSD all use a software interrupt rather than an undefined
2251 instruction to force a trap. This can be handled by by the
2252 abi-specific code during establishment of the gdbarch vector. */
2253
2254 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2255 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2256 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2257 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2258
2259 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
2260 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
2261 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
2262 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
2263
2264 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2265 the program counter value to determine whether a 16-bit or 32-bit
2266 breakpoint should be used. It returns a pointer to a string of
2267 bytes that encode a breakpoint instruction, stores the length of
2268 the string to *lenptr, and adjusts the program counter (if
2269 necessary) to point to the actual memory location where the
2270 breakpoint should be inserted. */
2271
2272 static const unsigned char *
2273 arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
2274 {
2275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2276
2277 if (arm_pc_is_thumb (*pcptr))
2278 {
2279 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
2280 *lenptr = tdep->thumb_breakpoint_size;
2281 return tdep->thumb_breakpoint;
2282 }
2283 else
2284 {
2285 *lenptr = tdep->arm_breakpoint_size;
2286 return tdep->arm_breakpoint;
2287 }
2288 }
2289
2290 /* Extract from an array REGBUF containing the (raw) register state a
2291 function return value of type TYPE, and copy that, in virtual
2292 format, into VALBUF. */
2293
2294 static void
2295 arm_extract_return_value (struct type *type, struct regcache *regs,
2296 gdb_byte *valbuf)
2297 {
2298 struct gdbarch *gdbarch = get_regcache_arch (regs);
2299
2300 if (TYPE_CODE_FLT == TYPE_CODE (type))
2301 {
2302 switch (gdbarch_tdep (gdbarch)->fp_model)
2303 {
2304 case ARM_FLOAT_FPA:
2305 {
2306 /* The value is in register F0 in internal format. We need to
2307 extract the raw value and then convert it to the desired
2308 internal type. */
2309 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2310
2311 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2312 convert_from_extended (floatformat_from_type (type), tmpbuf,
2313 valbuf, gdbarch_byte_order (gdbarch));
2314 }
2315 break;
2316
2317 case ARM_FLOAT_SOFT_FPA:
2318 case ARM_FLOAT_SOFT_VFP:
2319 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2320 if (TYPE_LENGTH (type) > 4)
2321 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2322 valbuf + INT_REGISTER_SIZE);
2323 break;
2324
2325 default:
2326 internal_error
2327 (__FILE__, __LINE__,
2328 _("arm_extract_return_value: Floating point model not supported"));
2329 break;
2330 }
2331 }
2332 else if (TYPE_CODE (type) == TYPE_CODE_INT
2333 || TYPE_CODE (type) == TYPE_CODE_CHAR
2334 || TYPE_CODE (type) == TYPE_CODE_BOOL
2335 || TYPE_CODE (type) == TYPE_CODE_PTR
2336 || TYPE_CODE (type) == TYPE_CODE_REF
2337 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2338 {
2339 /* If the the type is a plain integer, then the access is
2340 straight-forward. Otherwise we have to play around a bit more. */
2341 int len = TYPE_LENGTH (type);
2342 int regno = ARM_A1_REGNUM;
2343 ULONGEST tmp;
2344
2345 while (len > 0)
2346 {
2347 /* By using store_unsigned_integer we avoid having to do
2348 anything special for small big-endian values. */
2349 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2350 store_unsigned_integer (valbuf,
2351 (len > INT_REGISTER_SIZE
2352 ? INT_REGISTER_SIZE : len),
2353 tmp);
2354 len -= INT_REGISTER_SIZE;
2355 valbuf += INT_REGISTER_SIZE;
2356 }
2357 }
2358 else
2359 {
2360 /* For a structure or union the behaviour is as if the value had
2361 been stored to word-aligned memory and then loaded into
2362 registers with 32-bit load instruction(s). */
2363 int len = TYPE_LENGTH (type);
2364 int regno = ARM_A1_REGNUM;
2365 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2366
2367 while (len > 0)
2368 {
2369 regcache_cooked_read (regs, regno++, tmpbuf);
2370 memcpy (valbuf, tmpbuf,
2371 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2372 len -= INT_REGISTER_SIZE;
2373 valbuf += INT_REGISTER_SIZE;
2374 }
2375 }
2376 }
2377
2378
2379 /* Will a function return an aggregate type in memory or in a
2380 register? Return 0 if an aggregate type can be returned in a
2381 register, 1 if it must be returned in memory. */
2382
2383 static int
2384 arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2385 {
2386 int nRc;
2387 enum type_code code;
2388
2389 CHECK_TYPEDEF (type);
2390
2391 /* In the ARM ABI, "integer" like aggregate types are returned in
2392 registers. For an aggregate type to be integer like, its size
2393 must be less than or equal to INT_REGISTER_SIZE and the
2394 offset of each addressable subfield must be zero. Note that bit
2395 fields are not addressable, and all addressable subfields of
2396 unions always start at offset zero.
2397
2398 This function is based on the behaviour of GCC 2.95.1.
2399 See: gcc/arm.c: arm_return_in_memory() for details.
2400
2401 Note: All versions of GCC before GCC 2.95.2 do not set up the
2402 parameters correctly for a function returning the following
2403 structure: struct { float f;}; This should be returned in memory,
2404 not a register. Richard Earnshaw sent me a patch, but I do not
2405 know of any way to detect if a function like the above has been
2406 compiled with the correct calling convention. */
2407
2408 /* All aggregate types that won't fit in a register must be returned
2409 in memory. */
2410 if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
2411 {
2412 return 1;
2413 }
2414
2415 /* The AAPCS says all aggregates not larger than a word are returned
2416 in a register. */
2417 if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
2418 return 0;
2419
2420 /* The only aggregate types that can be returned in a register are
2421 structs and unions. Arrays must be returned in memory. */
2422 code = TYPE_CODE (type);
2423 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2424 {
2425 return 1;
2426 }
2427
2428 /* Assume all other aggregate types can be returned in a register.
2429 Run a check for structures, unions and arrays. */
2430 nRc = 0;
2431
2432 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2433 {
2434 int i;
2435 /* Need to check if this struct/union is "integer" like. For
2436 this to be true, its size must be less than or equal to
2437 INT_REGISTER_SIZE and the offset of each addressable
2438 subfield must be zero. Note that bit fields are not
2439 addressable, and unions always start at offset zero. If any
2440 of the subfields is a floating point type, the struct/union
2441 cannot be an integer type. */
2442
2443 /* For each field in the object, check:
2444 1) Is it FP? --> yes, nRc = 1;
2445 2) Is it addressable (bitpos != 0) and
2446 not packed (bitsize == 0)?
2447 --> yes, nRc = 1
2448 */
2449
2450 for (i = 0; i < TYPE_NFIELDS (type); i++)
2451 {
2452 enum type_code field_type_code;
2453 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2454
2455 /* Is it a floating point type field? */
2456 if (field_type_code == TYPE_CODE_FLT)
2457 {
2458 nRc = 1;
2459 break;
2460 }
2461
2462 /* If bitpos != 0, then we have to care about it. */
2463 if (TYPE_FIELD_BITPOS (type, i) != 0)
2464 {
2465 /* Bitfields are not addressable. If the field bitsize is
2466 zero, then the field is not packed. Hence it cannot be
2467 a bitfield or any other packed type. */
2468 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2469 {
2470 nRc = 1;
2471 break;
2472 }
2473 }
2474 }
2475 }
2476
2477 return nRc;
2478 }
2479
2480 /* Write into appropriate registers a function return value of type
2481 TYPE, given in virtual format. */
2482
2483 static void
2484 arm_store_return_value (struct type *type, struct regcache *regs,
2485 const gdb_byte *valbuf)
2486 {
2487 struct gdbarch *gdbarch = get_regcache_arch (regs);
2488
2489 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2490 {
2491 char buf[MAX_REGISTER_SIZE];
2492
2493 switch (gdbarch_tdep (gdbarch)->fp_model)
2494 {
2495 case ARM_FLOAT_FPA:
2496
2497 convert_to_extended (floatformat_from_type (type), buf, valbuf,
2498 gdbarch_byte_order (gdbarch));
2499 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2500 break;
2501
2502 case ARM_FLOAT_SOFT_FPA:
2503 case ARM_FLOAT_SOFT_VFP:
2504 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2505 if (TYPE_LENGTH (type) > 4)
2506 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2507 valbuf + INT_REGISTER_SIZE);
2508 break;
2509
2510 default:
2511 internal_error
2512 (__FILE__, __LINE__,
2513 _("arm_store_return_value: Floating point model not supported"));
2514 break;
2515 }
2516 }
2517 else if (TYPE_CODE (type) == TYPE_CODE_INT
2518 || TYPE_CODE (type) == TYPE_CODE_CHAR
2519 || TYPE_CODE (type) == TYPE_CODE_BOOL
2520 || TYPE_CODE (type) == TYPE_CODE_PTR
2521 || TYPE_CODE (type) == TYPE_CODE_REF
2522 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2523 {
2524 if (TYPE_LENGTH (type) <= 4)
2525 {
2526 /* Values of one word or less are zero/sign-extended and
2527 returned in r0. */
2528 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2529 LONGEST val = unpack_long (type, valbuf);
2530
2531 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2532 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2533 }
2534 else
2535 {
2536 /* Integral values greater than one word are stored in consecutive
2537 registers starting with r0. This will always be a multiple of
2538 the regiser size. */
2539 int len = TYPE_LENGTH (type);
2540 int regno = ARM_A1_REGNUM;
2541
2542 while (len > 0)
2543 {
2544 regcache_cooked_write (regs, regno++, valbuf);
2545 len -= INT_REGISTER_SIZE;
2546 valbuf += INT_REGISTER_SIZE;
2547 }
2548 }
2549 }
2550 else
2551 {
2552 /* For a structure or union the behaviour is as if the value had
2553 been stored to word-aligned memory and then loaded into
2554 registers with 32-bit load instruction(s). */
2555 int len = TYPE_LENGTH (type);
2556 int regno = ARM_A1_REGNUM;
2557 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2558
2559 while (len > 0)
2560 {
2561 memcpy (tmpbuf, valbuf,
2562 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2563 regcache_cooked_write (regs, regno++, tmpbuf);
2564 len -= INT_REGISTER_SIZE;
2565 valbuf += INT_REGISTER_SIZE;
2566 }
2567 }
2568 }
2569
2570
2571 /* Handle function return values. */
2572
2573 static enum return_value_convention
2574 arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
2575 struct type *valtype, struct regcache *regcache,
2576 gdb_byte *readbuf, const gdb_byte *writebuf)
2577 {
2578 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2579
2580 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2581 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2582 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2583 {
2584 if (tdep->struct_return == pcc_struct_return
2585 || arm_return_in_memory (gdbarch, valtype))
2586 return RETURN_VALUE_STRUCT_CONVENTION;
2587 }
2588
2589 if (writebuf)
2590 arm_store_return_value (valtype, regcache, writebuf);
2591
2592 if (readbuf)
2593 arm_extract_return_value (valtype, regcache, readbuf);
2594
2595 return RETURN_VALUE_REGISTER_CONVENTION;
2596 }
2597
2598
2599 static int
2600 arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2601 {
2602 CORE_ADDR jb_addr;
2603 char buf[INT_REGISTER_SIZE];
2604 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
2605
2606 jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
2607
2608 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2609 INT_REGISTER_SIZE))
2610 return 0;
2611
2612 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2613 return 1;
2614 }
2615
2616 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2617 return the target PC. Otherwise return 0. */
2618
2619 CORE_ADDR
2620 arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
2621 {
2622 char *name;
2623 int namelen;
2624 CORE_ADDR start_addr;
2625
2626 /* Find the starting address and name of the function containing the PC. */
2627 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2628 return 0;
2629
2630 /* If PC is in a Thumb call or return stub, return the address of the
2631 target PC, which is in a register. The thunk functions are called
2632 _call_via_xx, where x is the register name. The possible names
2633 are r0-r9, sl, fp, ip, sp, and lr. */
2634 if (strncmp (name, "_call_via_", 10) == 0)
2635 {
2636 /* Use the name suffix to determine which register contains the
2637 target PC. */
2638 static char *table[15] =
2639 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2640 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2641 };
2642 int regno;
2643 int offset = strlen (name) - 2;
2644
2645 for (regno = 0; regno <= 14; regno++)
2646 if (strcmp (&name[offset], table[regno]) == 0)
2647 return get_frame_register_unsigned (frame, regno);
2648 }
2649
2650 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2651 non-interworking calls to foo. We could decode the stubs
2652 to find the target but it's easier to use the symbol table. */
2653 namelen = strlen (name);
2654 if (name[0] == '_' && name[1] == '_'
2655 && ((namelen > 2 + strlen ("_from_thumb")
2656 && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
2657 strlen ("_from_thumb")) == 0)
2658 || (namelen > 2 + strlen ("_from_arm")
2659 && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
2660 strlen ("_from_arm")) == 0)))
2661 {
2662 char *target_name;
2663 int target_len = namelen - 2;
2664 struct minimal_symbol *minsym;
2665 struct objfile *objfile;
2666 struct obj_section *sec;
2667
2668 if (name[namelen - 1] == 'b')
2669 target_len -= strlen ("_from_thumb");
2670 else
2671 target_len -= strlen ("_from_arm");
2672
2673 target_name = alloca (target_len + 1);
2674 memcpy (target_name, name + 2, target_len);
2675 target_name[target_len] = '\0';
2676
2677 sec = find_pc_section (pc);
2678 objfile = (sec == NULL) ? NULL : sec->objfile;
2679 minsym = lookup_minimal_symbol (target_name, NULL, objfile);
2680 if (minsym != NULL)
2681 return SYMBOL_VALUE_ADDRESS (minsym);
2682 else
2683 return 0;
2684 }
2685
2686 return 0; /* not a stub */
2687 }
2688
2689 static void
2690 set_arm_command (char *args, int from_tty)
2691 {
2692 printf_unfiltered (_("\
2693 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2694 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2695 }
2696
2697 static void
2698 show_arm_command (char *args, int from_tty)
2699 {
2700 cmd_show_list (showarmcmdlist, from_tty, "");
2701 }
2702
2703 static void
2704 arm_update_current_architecture (void)
2705 {
2706 struct gdbarch_info info;
2707
2708 /* If the current architecture is not ARM, we have nothing to do. */
2709 if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
2710 return;
2711
2712 /* Update the architecture. */
2713 gdbarch_info_init (&info);
2714
2715 if (!gdbarch_update_p (info))
2716 internal_error (__FILE__, __LINE__, "could not update architecture");
2717 }
2718
2719 static void
2720 set_fp_model_sfunc (char *args, int from_tty,
2721 struct cmd_list_element *c)
2722 {
2723 enum arm_float_model fp_model;
2724
2725 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2726 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2727 {
2728 arm_fp_model = fp_model;
2729 break;
2730 }
2731
2732 if (fp_model == ARM_FLOAT_LAST)
2733 internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
2734 current_fp_model);
2735
2736 arm_update_current_architecture ();
2737 }
2738
2739 static void
2740 show_fp_model (struct ui_file *file, int from_tty,
2741 struct cmd_list_element *c, const char *value)
2742 {
2743 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
2744
2745 if (arm_fp_model == ARM_FLOAT_AUTO
2746 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
2747 fprintf_filtered (file, _("\
2748 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2749 fp_model_strings[tdep->fp_model]);
2750 else
2751 fprintf_filtered (file, _("\
2752 The current ARM floating point model is \"%s\".\n"),
2753 fp_model_strings[arm_fp_model]);
2754 }
2755
2756 static void
2757 arm_set_abi (char *args, int from_tty,
2758 struct cmd_list_element *c)
2759 {
2760 enum arm_abi_kind arm_abi;
2761
2762 for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
2763 if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
2764 {
2765 arm_abi_global = arm_abi;
2766 break;
2767 }
2768
2769 if (arm_abi == ARM_ABI_LAST)
2770 internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
2771 arm_abi_string);
2772
2773 arm_update_current_architecture ();
2774 }
2775
2776 static void
2777 arm_show_abi (struct ui_file *file, int from_tty,
2778 struct cmd_list_element *c, const char *value)
2779 {
2780 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
2781
2782 if (arm_abi_global == ARM_ABI_AUTO
2783 && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
2784 fprintf_filtered (file, _("\
2785 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2786 arm_abi_strings[tdep->arm_abi]);
2787 else
2788 fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
2789 arm_abi_string);
2790 }
2791
2792 static void
2793 arm_show_fallback_mode (struct ui_file *file, int from_tty,
2794 struct cmd_list_element *c, const char *value)
2795 {
2796 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
2797
2798 fprintf_filtered (file, _("\
2799 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2800 arm_fallback_mode_string);
2801 }
2802
2803 static void
2804 arm_show_force_mode (struct ui_file *file, int from_tty,
2805 struct cmd_list_element *c, const char *value)
2806 {
2807 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
2808
2809 fprintf_filtered (file, _("\
2810 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2811 arm_force_mode_string);
2812 }
2813
2814 /* If the user changes the register disassembly style used for info
2815 register and other commands, we have to also switch the style used
2816 in opcodes for disassembly output. This function is run in the "set
2817 arm disassembly" command, and does that. */
2818
2819 static void
2820 set_disassembly_style_sfunc (char *args, int from_tty,
2821 struct cmd_list_element *c)
2822 {
2823 set_disassembly_style ();
2824 }
2825 \f
2826 /* Return the ARM register name corresponding to register I. */
2827 static const char *
2828 arm_register_name (struct gdbarch *gdbarch, int i)
2829 {
2830 if (i >= ARRAY_SIZE (arm_register_names))
2831 /* These registers are only supported on targets which supply
2832 an XML description. */
2833 return "";
2834
2835 return arm_register_names[i];
2836 }
2837
2838 static void
2839 set_disassembly_style (void)
2840 {
2841 int current;
2842
2843 /* Find the style that the user wants. */
2844 for (current = 0; current < num_disassembly_options; current++)
2845 if (disassembly_style == valid_disassembly_styles[current])
2846 break;
2847 gdb_assert (current < num_disassembly_options);
2848
2849 /* Synchronize the disassembler. */
2850 set_arm_regname_option (current);
2851 }
2852
2853 /* Test whether the coff symbol specific value corresponds to a Thumb
2854 function. */
2855
2856 static int
2857 coff_sym_is_thumb (int val)
2858 {
2859 return (val == C_THUMBEXT ||
2860 val == C_THUMBSTAT ||
2861 val == C_THUMBEXTFUNC ||
2862 val == C_THUMBSTATFUNC ||
2863 val == C_THUMBLABEL);
2864 }
2865
2866 /* arm_coff_make_msymbol_special()
2867 arm_elf_make_msymbol_special()
2868
2869 These functions test whether the COFF or ELF symbol corresponds to
2870 an address in thumb code, and set a "special" bit in a minimal
2871 symbol to indicate that it does. */
2872
2873 static void
2874 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2875 {
2876 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2877 STT_ARM_TFUNC). */
2878 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2879 == STT_LOPROC)
2880 MSYMBOL_SET_SPECIAL (msym);
2881 }
2882
2883 static void
2884 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2885 {
2886 if (coff_sym_is_thumb (val))
2887 MSYMBOL_SET_SPECIAL (msym);
2888 }
2889
2890 static void
2891 arm_objfile_data_cleanup (struct objfile *objfile, void *arg)
2892 {
2893 struct arm_per_objfile *data = arg;
2894 unsigned int i;
2895
2896 for (i = 0; i < objfile->obfd->section_count; i++)
2897 VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
2898 }
2899
2900 static void
2901 arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
2902 asymbol *sym)
2903 {
2904 const char *name = bfd_asymbol_name (sym);
2905 struct arm_per_objfile *data;
2906 VEC(arm_mapping_symbol_s) **map_p;
2907 struct arm_mapping_symbol new_map_sym;
2908
2909 gdb_assert (name[0] == '$');
2910 if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
2911 return;
2912
2913 data = objfile_data (objfile, arm_objfile_data_key);
2914 if (data == NULL)
2915 {
2916 data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
2917 struct arm_per_objfile);
2918 set_objfile_data (objfile, arm_objfile_data_key, data);
2919 data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
2920 objfile->obfd->section_count,
2921 VEC(arm_mapping_symbol_s) *);
2922 }
2923 map_p = &data->section_maps[bfd_get_section (sym)->index];
2924
2925 new_map_sym.value = sym->value;
2926 new_map_sym.type = name[1];
2927
2928 /* Assume that most mapping symbols appear in order of increasing
2929 value. If they were randomly distributed, it would be faster to
2930 always push here and then sort at first use. */
2931 if (!VEC_empty (arm_mapping_symbol_s, *map_p))
2932 {
2933 struct arm_mapping_symbol *prev_map_sym;
2934
2935 prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
2936 if (prev_map_sym->value >= sym->value)
2937 {
2938 unsigned int idx;
2939 idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
2940 arm_compare_mapping_symbols);
2941 VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
2942 return;
2943 }
2944 }
2945
2946 VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
2947 }
2948
2949 static void
2950 arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
2951 {
2952 regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
2953
2954 /* If necessary, set the T bit. */
2955 if (arm_apcs_32)
2956 {
2957 ULONGEST val;
2958 regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
2959 if (arm_pc_is_thumb (pc))
2960 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
2961 else
2962 regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
2963 val & ~(ULONGEST) CPSR_T);
2964 }
2965 }
2966
2967 static struct value *
2968 value_of_arm_user_reg (struct frame_info *frame, const void *baton)
2969 {
2970 const int *reg_p = baton;
2971 return value_of_register (*reg_p, frame);
2972 }
2973 \f
2974 static enum gdb_osabi
2975 arm_elf_osabi_sniffer (bfd *abfd)
2976 {
2977 unsigned int elfosabi;
2978 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2979
2980 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2981
2982 if (elfosabi == ELFOSABI_ARM)
2983 /* GNU tools use this value. Check note sections in this case,
2984 as well. */
2985 bfd_map_over_sections (abfd,
2986 generic_elf_osabi_sniff_abi_tag_sections,
2987 &osabi);
2988
2989 /* Anything else will be handled by the generic ELF sniffer. */
2990 return osabi;
2991 }
2992
2993 \f
2994 /* Initialize the current architecture based on INFO. If possible,
2995 re-use an architecture from ARCHES, which is a list of
2996 architectures already created during this debugging session.
2997
2998 Called e.g. at program startup, when reading a core file, and when
2999 reading a binary file. */
3000
3001 static struct gdbarch *
3002 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3003 {
3004 struct gdbarch_tdep *tdep;
3005 struct gdbarch *gdbarch;
3006 struct gdbarch_list *best_arch;
3007 enum arm_abi_kind arm_abi = arm_abi_global;
3008 enum arm_float_model fp_model = arm_fp_model;
3009 struct tdesc_arch_data *tdesc_data = NULL;
3010 int i;
3011 int have_fpa_registers = 1;
3012
3013 /* Check any target description for validity. */
3014 if (tdesc_has_registers (info.target_desc))
3015 {
3016 /* For most registers we require GDB's default names; but also allow
3017 the numeric names for sp / lr / pc, as a convenience. */
3018 static const char *const arm_sp_names[] = { "r13", "sp", NULL };
3019 static const char *const arm_lr_names[] = { "r14", "lr", NULL };
3020 static const char *const arm_pc_names[] = { "r15", "pc", NULL };
3021
3022 const struct tdesc_feature *feature;
3023 int i, valid_p;
3024
3025 feature = tdesc_find_feature (info.target_desc,
3026 "org.gnu.gdb.arm.core");
3027 if (feature == NULL)
3028 return NULL;
3029
3030 tdesc_data = tdesc_data_alloc ();
3031
3032 valid_p = 1;
3033 for (i = 0; i < ARM_SP_REGNUM; i++)
3034 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3035 arm_register_names[i]);
3036 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3037 ARM_SP_REGNUM,
3038 arm_sp_names);
3039 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3040 ARM_LR_REGNUM,
3041 arm_lr_names);
3042 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3043 ARM_PC_REGNUM,
3044 arm_pc_names);
3045 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3046 ARM_PS_REGNUM, "cpsr");
3047
3048 if (!valid_p)
3049 {
3050 tdesc_data_cleanup (tdesc_data);
3051 return NULL;
3052 }
3053
3054 feature = tdesc_find_feature (info.target_desc,
3055 "org.gnu.gdb.arm.fpa");
3056 if (feature != NULL)
3057 {
3058 valid_p = 1;
3059 for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
3060 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
3061 arm_register_names[i]);
3062 if (!valid_p)
3063 {
3064 tdesc_data_cleanup (tdesc_data);
3065 return NULL;
3066 }
3067 }
3068 else
3069 have_fpa_registers = 0;
3070
3071 feature = tdesc_find_feature (info.target_desc,
3072 "org.gnu.gdb.xscale.iwmmxt");
3073 if (feature != NULL)
3074 {
3075 static const char *const iwmmxt_names[] = {
3076 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3077 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3078 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3079 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3080 };
3081
3082 valid_p = 1;
3083 for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
3084 valid_p
3085 &= tdesc_numbered_register (feature, tdesc_data, i,
3086 iwmmxt_names[i - ARM_WR0_REGNUM]);
3087
3088 /* Check for the control registers, but do not fail if they
3089 are missing. */
3090 for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
3091 tdesc_numbered_register (feature, tdesc_data, i,
3092 iwmmxt_names[i - ARM_WR0_REGNUM]);
3093
3094 for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
3095 valid_p
3096 &= tdesc_numbered_register (feature, tdesc_data, i,
3097 iwmmxt_names[i - ARM_WR0_REGNUM]);
3098
3099 if (!valid_p)
3100 {
3101 tdesc_data_cleanup (tdesc_data);
3102 return NULL;
3103 }
3104 }
3105 }
3106
3107 /* If we have an object to base this architecture on, try to determine
3108 its ABI. */
3109
3110 if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
3111 {
3112 int ei_osabi, e_flags;
3113
3114 switch (bfd_get_flavour (info.abfd))
3115 {
3116 case bfd_target_aout_flavour:
3117 /* Assume it's an old APCS-style ABI. */
3118 arm_abi = ARM_ABI_APCS;
3119 break;
3120
3121 case bfd_target_coff_flavour:
3122 /* Assume it's an old APCS-style ABI. */
3123 /* XXX WinCE? */
3124 arm_abi = ARM_ABI_APCS;
3125 break;
3126
3127 case bfd_target_elf_flavour:
3128 ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
3129 e_flags = elf_elfheader (info.abfd)->e_flags;
3130
3131 if (ei_osabi == ELFOSABI_ARM)
3132 {
3133 /* GNU tools used to use this value, but do not for EABI
3134 objects. There's nowhere to tag an EABI version
3135 anyway, so assume APCS. */
3136 arm_abi = ARM_ABI_APCS;
3137 }
3138 else if (ei_osabi == ELFOSABI_NONE)
3139 {
3140 int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
3141
3142 switch (eabi_ver)
3143 {
3144 case EF_ARM_EABI_UNKNOWN:
3145 /* Assume GNU tools. */
3146 arm_abi = ARM_ABI_APCS;
3147 break;
3148
3149 case EF_ARM_EABI_VER4:
3150 case EF_ARM_EABI_VER5:
3151 arm_abi = ARM_ABI_AAPCS;
3152 /* EABI binaries default to VFP float ordering. */
3153 if (fp_model == ARM_FLOAT_AUTO)
3154 fp_model = ARM_FLOAT_SOFT_VFP;
3155 break;
3156
3157 default:
3158 /* Leave it as "auto". */
3159 warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
3160 break;
3161 }
3162 }
3163
3164 if (fp_model == ARM_FLOAT_AUTO)
3165 {
3166 int e_flags = elf_elfheader (info.abfd)->e_flags;
3167
3168 switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
3169 {
3170 case 0:
3171 /* Leave it as "auto". Strictly speaking this case
3172 means FPA, but almost nobody uses that now, and
3173 many toolchains fail to set the appropriate bits
3174 for the floating-point model they use. */
3175 break;
3176 case EF_ARM_SOFT_FLOAT:
3177 fp_model = ARM_FLOAT_SOFT_FPA;
3178 break;
3179 case EF_ARM_VFP_FLOAT:
3180 fp_model = ARM_FLOAT_VFP;
3181 break;
3182 case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
3183 fp_model = ARM_FLOAT_SOFT_VFP;
3184 break;
3185 }
3186 }
3187
3188 if (e_flags & EF_ARM_BE8)
3189 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3190
3191 break;
3192
3193 default:
3194 /* Leave it as "auto". */
3195 break;
3196 }
3197 }
3198
3199 /* If there is already a candidate, use it. */
3200 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
3201 best_arch != NULL;
3202 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3203 {
3204 if (arm_abi != ARM_ABI_AUTO
3205 && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
3206 continue;
3207
3208 if (fp_model != ARM_FLOAT_AUTO
3209 && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
3210 continue;
3211
3212 /* Found a match. */
3213 break;
3214 }
3215
3216 if (best_arch != NULL)
3217 {
3218 if (tdesc_data != NULL)
3219 tdesc_data_cleanup (tdesc_data);
3220 return best_arch->gdbarch;
3221 }
3222
3223 tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
3224 gdbarch = gdbarch_alloc (&info, tdep);
3225
3226 /* Record additional information about the architecture we are defining.
3227 These are gdbarch discriminators, like the OSABI. */
3228 tdep->arm_abi = arm_abi;
3229 tdep->fp_model = fp_model;
3230 tdep->have_fpa_registers = have_fpa_registers;
3231
3232 /* Breakpoints. */
3233 switch (info.byte_order_for_code)
3234 {
3235 case BFD_ENDIAN_BIG:
3236 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
3237 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
3238 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
3239 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
3240
3241 break;
3242
3243 case BFD_ENDIAN_LITTLE:
3244 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
3245 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
3246 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
3247 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
3248
3249 break;
3250
3251 default:
3252 internal_error (__FILE__, __LINE__,
3253 _("arm_gdbarch_init: bad byte order for float format"));
3254 }
3255
3256 /* On ARM targets char defaults to unsigned. */
3257 set_gdbarch_char_signed (gdbarch, 0);
3258
3259 /* This should be low enough for everything. */
3260 tdep->lowest_pc = 0x20;
3261 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3262
3263 /* The default, for both APCS and AAPCS, is to return small
3264 structures in registers. */
3265 tdep->struct_return = reg_struct_return;
3266
3267 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
3268 set_gdbarch_frame_align (gdbarch, arm_frame_align);
3269
3270 set_gdbarch_write_pc (gdbarch, arm_write_pc);
3271
3272 /* Frame handling. */
3273 set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
3274 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
3275 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
3276
3277 frame_base_set_default (gdbarch, &arm_normal_base);
3278
3279 /* Address manipulation. */
3280 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
3281 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
3282
3283 /* Advance PC across function entry code. */
3284 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
3285
3286 /* Skip trampolines. */
3287 set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
3288
3289 /* The stack grows downward. */
3290 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3291
3292 /* Breakpoint manipulation. */
3293 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
3294
3295 /* Information about registers, etc. */
3296 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
3297 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
3298 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
3299 set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
3300 set_gdbarch_register_type (gdbarch, arm_register_type);
3301
3302 /* This "info float" is FPA-specific. Use the generic version if we
3303 do not have FPA. */
3304 if (gdbarch_tdep (gdbarch)->have_fpa_registers)
3305 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
3306
3307 /* Internal <-> external register number maps. */
3308 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
3309 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
3310
3311 set_gdbarch_register_name (gdbarch, arm_register_name);
3312
3313 /* Returning results. */
3314 set_gdbarch_return_value (gdbarch, arm_return_value);
3315
3316 /* Disassembly. */
3317 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
3318
3319 /* Minsymbol frobbing. */
3320 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
3321 set_gdbarch_coff_make_msymbol_special (gdbarch,
3322 arm_coff_make_msymbol_special);
3323 set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
3324
3325 /* Virtual tables. */
3326 set_gdbarch_vbit_in_delta (gdbarch, 1);
3327
3328 /* Hook in the ABI-specific overrides, if they have been registered. */
3329 gdbarch_init_osabi (info, gdbarch);
3330
3331 dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
3332
3333 /* Add some default predicates. */
3334 frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
3335 dwarf2_append_unwinders (gdbarch);
3336 frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
3337
3338 /* Now we have tuned the configuration, set a few final things,
3339 based on what the OS ABI has told us. */
3340
3341 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3342 binaries are always marked. */
3343 if (tdep->arm_abi == ARM_ABI_AUTO)
3344 tdep->arm_abi = ARM_ABI_APCS;
3345
3346 /* We used to default to FPA for generic ARM, but almost nobody
3347 uses that now, and we now provide a way for the user to force
3348 the model. So default to the most useful variant. */
3349 if (tdep->fp_model == ARM_FLOAT_AUTO)
3350 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
3351
3352 if (tdep->jb_pc >= 0)
3353 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
3354
3355 /* Floating point sizes and format. */
3356 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3357 if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
3358 {
3359 set_gdbarch_double_format
3360 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3361 set_gdbarch_long_double_format
3362 (gdbarch, floatformats_ieee_double_littlebyte_bigword);
3363 }
3364 else
3365 {
3366 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3367 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
3368 }
3369
3370 if (tdesc_data)
3371 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
3372
3373 /* Add standard register aliases. We add aliases even for those
3374 nanes which are used by the current architecture - it's simpler,
3375 and does no harm, since nothing ever lists user registers. */
3376 for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
3377 user_reg_add (gdbarch, arm_register_aliases[i].name,
3378 value_of_arm_user_reg, &arm_register_aliases[i].regnum);
3379
3380 return gdbarch;
3381 }
3382
3383 static void
3384 arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3385 {
3386 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3387
3388 if (tdep == NULL)
3389 return;
3390
3391 fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3392 (unsigned long) tdep->lowest_pc);
3393 }
3394
3395 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
3396
3397 void
3398 _initialize_arm_tdep (void)
3399 {
3400 struct ui_file *stb;
3401 long length;
3402 struct cmd_list_element *new_set, *new_show;
3403 const char *setname;
3404 const char *setdesc;
3405 const char *const *regnames;
3406 int numregs, i, j;
3407 static char *helptext;
3408 char regdesc[1024], *rdptr = regdesc;
3409 size_t rest = sizeof (regdesc);
3410
3411 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
3412
3413 arm_objfile_data_key
3414 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup);
3415
3416 /* Register an ELF OS ABI sniffer for ARM binaries. */
3417 gdbarch_register_osabi_sniffer (bfd_arch_arm,
3418 bfd_target_elf_flavour,
3419 arm_elf_osabi_sniffer);
3420
3421 /* Get the number of possible sets of register names defined in opcodes. */
3422 num_disassembly_options = get_arm_regname_num_options ();
3423
3424 /* Add root prefix command for all "set arm"/"show arm" commands. */
3425 add_prefix_cmd ("arm", no_class, set_arm_command,
3426 _("Various ARM-specific commands."),
3427 &setarmcmdlist, "set arm ", 0, &setlist);
3428
3429 add_prefix_cmd ("arm", no_class, show_arm_command,
3430 _("Various ARM-specific commands."),
3431 &showarmcmdlist, "show arm ", 0, &showlist);
3432
3433 /* Sync the opcode insn printer with our register viewer. */
3434 parse_arm_disassembler_option ("reg-names-std");
3435
3436 /* Initialize the array that will be passed to
3437 add_setshow_enum_cmd(). */
3438 valid_disassembly_styles
3439 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
3440 for (i = 0; i < num_disassembly_options; i++)
3441 {
3442 numregs = get_arm_regnames (i, &setname, &setdesc, &regnames);
3443 valid_disassembly_styles[i] = setname;
3444 length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
3445 rdptr += length;
3446 rest -= length;
3447 /* When we find the default names, tell the disassembler to use
3448 them. */
3449 if (!strcmp (setname, "std"))
3450 {
3451 disassembly_style = setname;
3452 set_arm_regname_option (i);
3453 }
3454 }
3455 /* Mark the end of valid options. */
3456 valid_disassembly_styles[num_disassembly_options] = NULL;
3457
3458 /* Create the help text. */
3459 stb = mem_fileopen ();
3460 fprintf_unfiltered (stb, "%s%s%s",
3461 _("The valid values are:\n"),
3462 regdesc,
3463 _("The default is \"std\"."));
3464 helptext = ui_file_xstrdup (stb, &length);
3465 ui_file_delete (stb);
3466
3467 add_setshow_enum_cmd("disassembler", no_class,
3468 valid_disassembly_styles, &disassembly_style,
3469 _("Set the disassembly style."),
3470 _("Show the disassembly style."),
3471 helptext,
3472 set_disassembly_style_sfunc,
3473 NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
3474 &setarmcmdlist, &showarmcmdlist);
3475
3476 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
3477 _("Set usage of ARM 32-bit mode."),
3478 _("Show usage of ARM 32-bit mode."),
3479 _("When off, a 26-bit PC will be used."),
3480 NULL,
3481 NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3482 &setarmcmdlist, &showarmcmdlist);
3483
3484 /* Add a command to allow the user to force the FPU model. */
3485 add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, &current_fp_model,
3486 _("Set the floating point type."),
3487 _("Show the floating point type."),
3488 _("auto - Determine the FP typefrom the OS-ABI.\n\
3489 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3490 fpa - FPA co-processor (GCC compiled).\n\
3491 softvfp - Software FP with pure-endian doubles.\n\
3492 vfp - VFP co-processor."),
3493 set_fp_model_sfunc, show_fp_model,
3494 &setarmcmdlist, &showarmcmdlist);
3495
3496 /* Add a command to allow the user to force the ABI. */
3497 add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
3498 _("Set the ABI."),
3499 _("Show the ABI."),
3500 NULL, arm_set_abi, arm_show_abi,
3501 &setarmcmdlist, &showarmcmdlist);
3502
3503 /* Add two commands to allow the user to force the assumed
3504 execution mode. */
3505 add_setshow_enum_cmd ("fallback-mode", class_support,
3506 arm_mode_strings, &arm_fallback_mode_string,
3507 _("Set the mode assumed when symbols are unavailable."),
3508 _("Show the mode assumed when symbols are unavailable."),
3509 NULL, NULL, arm_show_fallback_mode,
3510 &setarmcmdlist, &showarmcmdlist);
3511 add_setshow_enum_cmd ("force-mode", class_support,
3512 arm_mode_strings, &arm_force_mode_string,
3513 _("Set the mode assumed even when symbols are available."),
3514 _("Show the mode assumed even when symbols are available."),
3515 NULL, NULL, arm_show_force_mode,
3516 &setarmcmdlist, &showarmcmdlist);
3517
3518 /* Debugging flag. */
3519 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
3520 _("Set ARM debugging."),
3521 _("Show ARM debugging."),
3522 _("When on, arm-specific debugging is enabled."),
3523 NULL,
3524 NULL, /* FIXME: i18n: "ARM debugging is %s. */
3525 &setdebuglist, &showdebuglist);
3526 }
This page took 0.171265 seconds and 4 git commands to generate.