1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
56 #include "features/arm-with-m.c"
60 /* Macros for setting and testing a bit in a minimal symbol that marks
61 it as Thumb function. The MSB of the minimal symbol's "info" field
62 is used for this purpose.
64 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
65 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
67 #define MSYMBOL_SET_SPECIAL(msym) \
68 MSYMBOL_TARGET_FLAG_1 (msym) = 1
70 #define MSYMBOL_IS_SPECIAL(msym) \
71 MSYMBOL_TARGET_FLAG_1 (msym)
73 /* Per-objfile data used for mapping symbols. */
74 static const struct objfile_data
*arm_objfile_data_key
;
76 struct arm_mapping_symbol
81 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
82 DEF_VEC_O(arm_mapping_symbol_s
);
84 struct arm_per_objfile
86 VEC(arm_mapping_symbol_s
) **section_maps
;
89 /* The list of available "set arm ..." and "show arm ..." commands. */
90 static struct cmd_list_element
*setarmcmdlist
= NULL
;
91 static struct cmd_list_element
*showarmcmdlist
= NULL
;
93 /* The type of floating-point to use. Keep this in sync with enum
94 arm_float_model, and the help string in _initialize_arm_tdep. */
95 static const char *fp_model_strings
[] =
105 /* A variable that can be configured by the user. */
106 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
107 static const char *current_fp_model
= "auto";
109 /* The ABI to use. Keep this in sync with arm_abi_kind. */
110 static const char *arm_abi_strings
[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
120 static const char *arm_abi_string
= "auto";
122 /* The execution mode to assume. */
123 static const char *arm_mode_strings
[] =
130 static const char *arm_fallback_mode_string
= "auto";
131 static const char *arm_force_mode_string
= "auto";
133 /* Number of different reg name sets (options). */
134 static int num_disassembly_options
;
136 /* The standard register names, and all the valid aliases for them. */
141 } arm_register_aliases
[] = {
142 /* Basic register numbers. */
159 /* Synonyms (argument and variable registers). */
172 /* Other platform-specific names for r9. */
180 /* Names used by GCC (not listed in the ARM EABI). */
183 /* A special name from the older ATPCS. */
187 static const char *const arm_register_names
[] =
188 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
189 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
190 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
191 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
192 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
193 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
194 "fps", "cpsr" }; /* 24 25 */
196 /* Valid register name styles. */
197 static const char **valid_disassembly_styles
;
199 /* Disassembly style to use. Default to "std" register names. */
200 static const char *disassembly_style
;
202 /* This is used to keep the bfd arch_info in sync with the disassembly
204 static void set_disassembly_style_sfunc(char *, int,
205 struct cmd_list_element
*);
206 static void set_disassembly_style (void);
208 static void convert_from_extended (const struct floatformat
*, const void *,
210 static void convert_to_extended (const struct floatformat
*, void *,
213 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
214 struct regcache
*regcache
,
215 int regnum
, gdb_byte
*buf
);
216 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
217 struct regcache
*regcache
,
218 int regnum
, const gdb_byte
*buf
);
220 struct arm_prologue_cache
222 /* The stack pointer at the time this frame was created; i.e. the
223 caller's stack pointer when this function was called. It is used
224 to identify this frame. */
227 /* The frame base for this frame is just prev_sp - frame size.
228 FRAMESIZE is the distance from the frame pointer to the
229 initial stack pointer. */
233 /* The register used to hold the frame pointer for this frame. */
236 /* Saved register offsets. */
237 struct trad_frame_saved_reg
*saved_regs
;
240 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
241 CORE_ADDR prologue_start
,
242 CORE_ADDR prologue_end
,
243 struct arm_prologue_cache
*cache
);
245 /* Architecture version for displaced stepping. This effects the behaviour of
246 certain instructions, and really should not be hard-wired. */
248 #define DISPLACED_STEPPING_ARCH_VERSION 5
250 /* Addresses for calling Thumb functions have the bit 0 set.
251 Here are some macros to test, set, or clear bit 0 of addresses. */
252 #define IS_THUMB_ADDR(addr) ((addr) & 1)
253 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
254 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
256 /* Set to true if the 32-bit mode is in use. */
260 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
263 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
265 if (gdbarch_tdep (gdbarch
)->is_m
)
271 /* Determine if FRAME is executing in Thumb mode. */
274 arm_frame_is_thumb (struct frame_info
*frame
)
277 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
279 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
280 directly (from a signal frame or dummy frame) or by interpreting
281 the saved LR (from a prologue or DWARF frame). So consult it and
282 trust the unwinders. */
283 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
285 return (cpsr
& t_bit
) != 0;
288 /* Callback for VEC_lower_bound. */
291 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
292 const struct arm_mapping_symbol
*rhs
)
294 return lhs
->value
< rhs
->value
;
297 /* Search for the mapping symbol covering MEMADDR. If one is found,
298 return its type. Otherwise, return 0. If START is non-NULL,
299 set *START to the location of the mapping symbol. */
302 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
304 struct obj_section
*sec
;
306 /* If there are mapping symbols, consult them. */
307 sec
= find_pc_section (memaddr
);
310 struct arm_per_objfile
*data
;
311 VEC(arm_mapping_symbol_s
) *map
;
312 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
316 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
319 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
320 if (!VEC_empty (arm_mapping_symbol_s
, map
))
322 struct arm_mapping_symbol
*map_sym
;
324 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
325 arm_compare_mapping_symbols
);
327 /* VEC_lower_bound finds the earliest ordered insertion
328 point. If the following symbol starts at this exact
329 address, we use that; otherwise, the preceding
330 mapping symbol covers this address. */
331 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
333 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
334 if (map_sym
->value
== map_key
.value
)
337 *start
= map_sym
->value
+ obj_section_addr (sec
);
338 return map_sym
->type
;
344 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
346 *start
= map_sym
->value
+ obj_section_addr (sec
);
347 return map_sym
->type
;
356 static CORE_ADDR
arm_get_next_pc_raw (struct frame_info
*frame
,
357 CORE_ADDR pc
, int insert_bkpt
);
359 /* Determine if the program counter specified in MEMADDR is in a Thumb
360 function. This function should be called for addresses unrelated to
361 any executing frame; otherwise, prefer arm_frame_is_thumb. */
364 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
366 struct obj_section
*sec
;
367 struct minimal_symbol
*sym
;
370 /* If bit 0 of the address is set, assume this is a Thumb address. */
371 if (IS_THUMB_ADDR (memaddr
))
374 /* If the user wants to override the symbol table, let him. */
375 if (strcmp (arm_force_mode_string
, "arm") == 0)
377 if (strcmp (arm_force_mode_string
, "thumb") == 0)
380 /* ARM v6-M and v7-M are always in Thumb mode. */
381 if (gdbarch_tdep (gdbarch
)->is_m
)
384 /* If there are mapping symbols, consult them. */
385 type
= arm_find_mapping_symbol (memaddr
, NULL
);
389 /* Thumb functions have a "special" bit set in minimal symbols. */
390 sym
= lookup_minimal_symbol_by_pc (memaddr
);
392 return (MSYMBOL_IS_SPECIAL (sym
));
394 /* If the user wants to override the fallback mode, let them. */
395 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
397 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
400 /* If we couldn't find any symbol, but we're talking to a running
401 target, then trust the current value of $cpsr. This lets
402 "display/i $pc" always show the correct mode (though if there is
403 a symbol table we will not reach here, so it still may not be
404 displayed in the mode it will be executed).
406 As a further heuristic if we detect that we are doing a single-step we
407 see what state executing the current instruction ends up with us being
409 if (target_has_registers
)
411 struct frame_info
*current_frame
= get_current_frame ();
412 CORE_ADDR current_pc
= get_frame_pc (current_frame
);
413 int is_thumb
= arm_frame_is_thumb (current_frame
);
415 if (memaddr
== current_pc
)
419 struct gdbarch
*gdbarch
= get_frame_arch (current_frame
);
420 next_pc
= arm_get_next_pc_raw (current_frame
, current_pc
, FALSE
);
421 if (memaddr
== gdbarch_addr_bits_remove (gdbarch
, next_pc
))
422 return IS_THUMB_ADDR (next_pc
);
428 /* Otherwise we're out of luck; we assume ARM. */
432 /* Remove useless bits from addresses in a running program. */
434 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
437 return UNMAKE_THUMB_ADDR (val
);
439 return (val
& 0x03fffffc);
442 /* When reading symbols, we need to zap the low bit of the address,
443 which may be set to 1 for Thumb functions. */
445 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* Return 1 if PC is the start of a compiler helper function which
451 can be safely ignored during prologue skipping. */
453 skip_prologue_function (CORE_ADDR pc
)
455 struct minimal_symbol
*msym
;
458 msym
= lookup_minimal_symbol_by_pc (pc
);
459 if (msym
== NULL
|| SYMBOL_VALUE_ADDRESS (msym
) != pc
)
462 name
= SYMBOL_LINKAGE_NAME (msym
);
466 /* The GNU linker's Thumb call stub to foo is named
468 if (strstr (name
, "_from_thumb") != NULL
)
471 /* On soft-float targets, __truncdfsf2 is called to convert promoted
472 arguments to their argument types in non-prototyped
474 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
476 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
482 /* Support routines for instruction parsing. */
483 #define submask(x) ((1L << ((x) + 1)) - 1)
484 #define bit(obj,st) (((obj) >> (st)) & 1)
485 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
486 #define sbits(obj,st,fn) \
487 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
488 #define BranchDest(addr,instr) \
489 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
491 /* Analyze a Thumb prologue, looking for a recognizable stack frame
492 and frame pointer. Scan until we encounter a store that could
493 clobber the stack frame unexpectedly, or an unknown instruction.
494 Return the last address which is definitely safe to skip for an
495 initial breakpoint. */
498 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
499 CORE_ADDR start
, CORE_ADDR limit
,
500 struct arm_prologue_cache
*cache
)
502 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
503 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
506 struct pv_area
*stack
;
507 struct cleanup
*back_to
;
510 for (i
= 0; i
< 16; i
++)
511 regs
[i
] = pv_register (i
, 0);
512 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
513 back_to
= make_cleanup_free_pv_area (stack
);
515 while (start
< limit
)
519 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
521 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
526 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
529 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
530 whether to save LR (R14). */
531 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
533 /* Calculate offsets of saved R0-R7 and LR. */
534 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
535 if (mask
& (1 << regno
))
537 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
539 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
542 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
545 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
546 if (insn
& 0x80) /* Check for SUB. */
547 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
550 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
553 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
554 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
556 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
557 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
558 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
560 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
561 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
562 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
564 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
565 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
566 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
567 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
568 regs
[bits (insn
, 6, 8)]);
569 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
570 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
572 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
573 int rm
= bits (insn
, 3, 6);
574 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
576 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
578 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
579 int src_reg
= (insn
& 0x78) >> 3;
580 regs
[dst_reg
] = regs
[src_reg
];
582 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
584 /* Handle stores to the stack. Normally pushes are used,
585 but with GCC -mtpcs-frame, there may be other stores
586 in the prologue to create the frame. */
587 int regno
= (insn
>> 8) & 0x7;
590 offset
= (insn
& 0xff) << 2;
591 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
593 if (pv_area_store_would_trash (stack
, addr
))
596 pv_area_store (stack
, addr
, 4, regs
[regno
]);
598 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
600 int rd
= bits (insn
, 0, 2);
601 int rn
= bits (insn
, 3, 5);
604 offset
= bits (insn
, 6, 10) << 2;
605 addr
= pv_add_constant (regs
[rn
], offset
);
607 if (pv_area_store_would_trash (stack
, addr
))
610 pv_area_store (stack
, addr
, 4, regs
[rd
]);
612 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
613 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
614 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
615 /* Ignore stores of argument registers to the stack. */
617 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
618 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
619 /* Ignore block loads from the stack, potentially copying
620 parameters from memory. */
622 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
623 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
624 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
625 /* Similarly ignore single loads from the stack. */
627 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
628 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
629 /* Skip register copies, i.e. saves to another register
630 instead of the stack. */
632 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
633 /* Recognize constant loads; even with small stacks these are necessary
635 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
636 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
638 /* Constant pool loads, for the same reason. */
639 unsigned int constant
;
642 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
643 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
644 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
646 else if ((insn
& 0xe000) == 0xe000 && cache
== NULL
)
648 /* Only recognize 32-bit instructions for prologue skipping. */
649 unsigned short inst2
;
651 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
652 byte_order_for_code
);
654 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
656 /* BL, BLX. Allow some special function calls when
657 skipping the prologue; GCC generates these before
658 storing arguments to the stack. */
660 int j1
, j2
, imm1
, imm2
;
662 imm1
= sbits (insn
, 0, 10);
663 imm2
= bits (inst2
, 0, 10);
664 j1
= bit (inst2
, 13);
665 j2
= bit (inst2
, 11);
667 offset
= ((imm1
<< 12) + (imm2
<< 1));
668 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
670 nextpc
= start
+ 4 + offset
;
671 /* For BLX make sure to clear the low bits. */
672 if (bit (inst2
, 12) == 0)
673 nextpc
= nextpc
& 0xfffffffc;
675 if (!skip_prologue_function (nextpc
))
678 else if ((insn
& 0xfe50) == 0xe800 /* stm{db,ia} Rn[!], { registers } */
679 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
681 else if ((insn
& 0xfe50) == 0xe840 /* strd Rt, Rt2, [Rn, #imm] */
682 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
684 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
685 && (inst2
& 0x8000) == 0x0000
686 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
688 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
689 && (inst2
& 0x8000) == 0x0000)
690 /* Since we only recognize this for prologue skipping, do not bother
691 to compute the constant. */
692 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
693 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm12 */
694 && (inst2
& 0x8000) == 0x0000)
695 /* Since we only recognize this for prologue skipping, do not bother
696 to compute the constant. */
697 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
698 else if ((insn
& 0xfbf0) == 0xf2a0 /* sub.w Rd, Rn, #imm8 */
699 && (inst2
& 0x8000) == 0x0000)
700 /* Since we only recognize this for prologue skipping, do not bother
701 to compute the constant. */
702 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
703 else if ((insn
& 0xff50) == 0xf850 /* ldr.w Rd, [Rn, #imm]{!} */
704 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
706 else if ((insn
& 0xff50) == 0xe950 /* ldrd Rt, Rt2, [Rn, #imm]{!} */
707 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
709 else if ((insn
& 0xff50) == 0xf800 /* strb.w or strh.w */
710 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
714 /* We don't know what this instruction is. We're finished
715 scanning. NOTE: Recognizing more safe-to-ignore
716 instructions here will improve support for optimized
725 /* We don't know what this instruction is. We're finished
726 scanning. NOTE: Recognizing more safe-to-ignore
727 instructions here will improve support for optimized
736 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
737 paddress (gdbarch
, start
));
741 do_cleanups (back_to
);
745 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
747 /* Frame pointer is fp. Frame size is constant. */
748 cache
->framereg
= ARM_FP_REGNUM
;
749 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
751 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
753 /* Frame pointer is r7. Frame size is constant. */
754 cache
->framereg
= THUMB_FP_REGNUM
;
755 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
757 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
759 /* Try the stack pointer... this is a bit desperate. */
760 cache
->framereg
= ARM_SP_REGNUM
;
761 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
765 /* We're just out of luck. We don't know where the frame is. */
766 cache
->framereg
= -1;
767 cache
->framesize
= 0;
770 for (i
= 0; i
< 16; i
++)
771 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
772 cache
->saved_regs
[i
].addr
= offset
;
774 do_cleanups (back_to
);
778 /* Advance the PC across any function entry prologue instructions to
779 reach some "real" code.
781 The APCS (ARM Procedure Call Standard) defines the following
785 [stmfd sp!, {a1,a2,a3,a4}]
786 stmfd sp!, {...,fp,ip,lr,pc}
787 [stfe f7, [sp, #-12]!]
788 [stfe f6, [sp, #-12]!]
789 [stfe f5, [sp, #-12]!]
790 [stfe f4, [sp, #-12]!]
791 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
794 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
796 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
799 CORE_ADDR func_addr
, limit_pc
;
800 struct symtab_and_line sal
;
802 /* See if we can determine the end of the prologue via the symbol table.
803 If so, then return either PC, or the PC after the prologue, whichever
805 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
807 CORE_ADDR post_prologue_pc
808 = skip_prologue_using_sal (gdbarch
, func_addr
);
809 struct symtab
*s
= find_pc_symtab (func_addr
);
811 /* GCC always emits a line note before the prologue and another
812 one after, even if the two are at the same address or on the
813 same line. Take advantage of this so that we do not need to
814 know every instruction that might appear in the prologue. We
815 will have producer information for most binaries; if it is
816 missing (e.g. for -gstabs), assuming the GNU tools. */
819 || s
->producer
== NULL
820 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0))
821 return post_prologue_pc
;
823 if (post_prologue_pc
!= 0)
825 CORE_ADDR analyzed_limit
;
827 /* For non-GCC compilers, make sure the entire line is an
828 acceptable prologue; GDB will round this function's
829 return value up to the end of the following line so we
830 can not skip just part of a line (and we do not want to).
832 RealView does not treat the prologue specially, but does
833 associate prologue code with the opening brace; so this
834 lets us skip the first line if we think it is the opening
836 if (arm_pc_is_thumb (gdbarch
, func_addr
))
837 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
838 post_prologue_pc
, NULL
);
840 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
841 post_prologue_pc
, NULL
);
843 if (analyzed_limit
!= post_prologue_pc
)
846 return post_prologue_pc
;
850 /* Can't determine prologue from the symbol table, need to examine
853 /* Find an upper limit on the function prologue using the debug
854 information. If the debug information could not be used to provide
855 that bound, then use an arbitrary large number as the upper bound. */
856 /* Like arm_scan_prologue, stop no later than pc + 64. */
857 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
859 limit_pc
= pc
+ 64; /* Magic. */
862 /* Check if this is Thumb code. */
863 if (arm_pc_is_thumb (gdbarch
, pc
))
864 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
866 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
868 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
870 /* "mov ip, sp" is no longer a required part of the prologue. */
871 if (inst
== 0xe1a0c00d) /* mov ip, sp */
874 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
877 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
880 /* Some prologues begin with "str lr, [sp, #-4]!". */
881 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
884 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
887 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
890 /* Any insns after this point may float into the code, if it makes
891 for better instruction scheduling, so we skip them only if we
892 find them, but still consider the function to be frame-ful. */
894 /* We may have either one sfmfd instruction here, or several stfe
895 insns, depending on the version of floating point code we
897 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
900 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
903 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
906 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
909 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
910 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
911 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
914 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
915 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
916 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
919 /* Un-recognized instruction; stop scanning. */
923 return skip_pc
; /* End of prologue */
927 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
928 This function decodes a Thumb function prologue to determine:
929 1) the size of the stack frame
930 2) which registers are saved on it
931 3) the offsets of saved regs
932 4) the offset from the stack pointer to the frame pointer
934 A typical Thumb function prologue would create this stack frame
935 (offsets relative to FP)
936 old SP -> 24 stack parameters
939 R7 -> 0 local variables (16 bytes)
940 SP -> -12 additional stack space (12 bytes)
941 The frame size would thus be 36 bytes, and the frame offset would be
942 12 bytes. The frame register is R7.
944 The comments for thumb_skip_prolog() describe the algorithm we use
945 to detect the end of the prolog. */
949 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
950 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
952 CORE_ADDR prologue_start
;
953 CORE_ADDR prologue_end
;
954 CORE_ADDR current_pc
;
956 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
959 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
961 if (sal
.line
== 0) /* no line info, use current PC */
962 prologue_end
= prev_pc
;
963 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
964 prologue_end
= sal
.end
; /* (probably means no prologue) */
967 /* We're in the boondocks: we have no idea where the start of the
971 prologue_end
= min (prologue_end
, prev_pc
);
973 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
976 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
979 arm_instruction_changes_pc (uint32_t this_instr
)
981 if (bits (this_instr
, 28, 31) == INST_NV
)
982 /* Unconditional instructions. */
983 switch (bits (this_instr
, 24, 27))
987 /* Branch with Link and change to Thumb. */
992 /* Coprocessor register transfer. */
993 if (bits (this_instr
, 12, 15) == 15)
994 error (_("Invalid update to pc in instruction"));
1000 switch (bits (this_instr
, 25, 27))
1003 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1005 /* Multiplies and extra load/stores. */
1006 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1007 /* Neither multiplies nor extension load/stores are allowed
1011 /* Otherwise, miscellaneous instructions. */
1013 /* BX <reg>, BXJ <reg>, BLX <reg> */
1014 if (bits (this_instr
, 4, 27) == 0x12fff1
1015 || bits (this_instr
, 4, 27) == 0x12fff2
1016 || bits (this_instr
, 4, 27) == 0x12fff3)
1019 /* Other miscellaneous instructions are unpredictable if they
1023 /* Data processing instruction. Fall through. */
1026 if (bits (this_instr
, 12, 15) == 15)
1033 /* Media instructions and architecturally undefined instructions. */
1034 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1038 if (bit (this_instr
, 20) == 0)
1042 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1048 /* Load/store multiple. */
1049 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1055 /* Branch and branch with link. */
1060 /* Coprocessor transfers or SWIs can not affect PC. */
1064 internal_error (__FILE__
, __LINE__
, "bad value in switch");
1068 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1069 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1070 fill it in. Return the first address not recognized as a prologue
1073 We recognize all the instructions typically found in ARM prologues,
1074 plus harmless instructions which can be skipped (either for analysis
1075 purposes, or a more restrictive set that can be skipped when finding
1076 the end of the prologue). */
1079 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1080 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1081 struct arm_prologue_cache
*cache
)
1083 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1084 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1086 CORE_ADDR offset
, current_pc
;
1087 pv_t regs
[ARM_FPS_REGNUM
];
1088 struct pv_area
*stack
;
1089 struct cleanup
*back_to
;
1090 int framereg
, framesize
;
1091 CORE_ADDR unrecognized_pc
= 0;
1093 /* Search the prologue looking for instructions that set up the
1094 frame pointer, adjust the stack pointer, and save registers.
1096 Be careful, however, and if it doesn't look like a prologue,
1097 don't try to scan it. If, for instance, a frameless function
1098 begins with stmfd sp!, then we will tell ourselves there is
1099 a frame, which will confuse stack traceback, as well as "finish"
1100 and other operations that rely on a knowledge of the stack
1103 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1104 regs
[regno
] = pv_register (regno
, 0);
1105 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1106 back_to
= make_cleanup_free_pv_area (stack
);
1108 for (current_pc
= prologue_start
;
1109 current_pc
< prologue_end
;
1113 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1115 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1117 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1120 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1121 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1123 unsigned imm
= insn
& 0xff; /* immediate value */
1124 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1125 int rd
= bits (insn
, 12, 15);
1126 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1127 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1130 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1131 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1133 unsigned imm
= insn
& 0xff; /* immediate value */
1134 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1135 int rd
= bits (insn
, 12, 15);
1136 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1137 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1140 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */
1142 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1144 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1145 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1146 regs
[bits (insn
, 12, 15)]);
1149 else if ((insn
& 0xffff0000) == 0xe92d0000)
1150 /* stmfd sp!, {..., fp, ip, lr, pc}
1152 stmfd sp!, {a1, a2, a3, a4} */
1154 int mask
= insn
& 0xffff;
1156 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1159 /* Calculate offsets of saved registers. */
1160 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1161 if (mask
& (1 << regno
))
1163 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1164 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1167 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1168 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1169 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1171 /* No need to add this to saved_regs -- it's just an arg reg. */
1174 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1175 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1176 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1178 /* No need to add this to saved_regs -- it's just an arg reg. */
1181 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */
1182 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1184 /* No need to add this to saved_regs -- it's just arg regs. */
1187 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1189 unsigned imm
= insn
& 0xff; /* immediate value */
1190 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1191 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1192 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1194 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1196 unsigned imm
= insn
& 0xff; /* immediate value */
1197 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1198 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1199 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1201 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
1202 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1204 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1207 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1208 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1209 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1211 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
1212 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1214 int n_saved_fp_regs
;
1215 unsigned int fp_start_reg
, fp_bound_reg
;
1217 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1220 if ((insn
& 0x800) == 0x800) /* N0 is set */
1222 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1223 n_saved_fp_regs
= 3;
1225 n_saved_fp_regs
= 1;
1229 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1230 n_saved_fp_regs
= 2;
1232 n_saved_fp_regs
= 4;
1235 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1236 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1237 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1239 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1240 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1241 regs
[fp_start_reg
++]);
1244 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1246 /* Allow some special function calls when skipping the
1247 prologue; GCC generates these before storing arguments to
1249 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1251 if (skip_prologue_function (dest
))
1256 else if ((insn
& 0xf0000000) != 0xe0000000)
1257 break; /* Condition not true, exit early */
1258 else if (arm_instruction_changes_pc (insn
))
1259 /* Don't scan past anything that might change control flow. */
1261 else if ((insn
& 0xfe500000) == 0xe8100000) /* ldm */
1263 /* Ignore block loads from the stack, potentially copying
1264 parameters from memory. */
1265 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1270 else if ((insn
& 0xfc500000) == 0xe4100000)
1272 /* Similarly ignore single loads from the stack. */
1273 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1278 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1279 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1280 register instead of the stack. */
1284 /* The optimizer might shove anything into the prologue,
1285 so we just skip what we don't recognize. */
1286 unrecognized_pc
= current_pc
;
1291 if (unrecognized_pc
== 0)
1292 unrecognized_pc
= current_pc
;
1294 /* The frame size is just the distance from the frame register
1295 to the original stack pointer. */
1296 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1298 /* Frame pointer is fp. */
1299 framereg
= ARM_FP_REGNUM
;
1300 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1302 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1304 /* Try the stack pointer... this is a bit desperate. */
1305 framereg
= ARM_SP_REGNUM
;
1306 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1310 /* We're just out of luck. We don't know where the frame is. */
1317 cache
->framereg
= framereg
;
1318 cache
->framesize
= framesize
;
1320 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1321 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1322 cache
->saved_regs
[regno
].addr
= offset
;
1326 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1327 paddress (gdbarch
, unrecognized_pc
));
1329 do_cleanups (back_to
);
1330 return unrecognized_pc
;
1334 arm_scan_prologue (struct frame_info
*this_frame
,
1335 struct arm_prologue_cache
*cache
)
1337 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1338 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1340 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1341 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1342 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1343 pv_t regs
[ARM_FPS_REGNUM
];
1344 struct pv_area
*stack
;
1345 struct cleanup
*back_to
;
1348 /* Assume there is no frame until proven otherwise. */
1349 cache
->framereg
= ARM_SP_REGNUM
;
1350 cache
->framesize
= 0;
1352 /* Check for Thumb prologue. */
1353 if (arm_frame_is_thumb (this_frame
))
1355 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1359 /* Find the function prologue. If we can't find the function in
1360 the symbol table, peek in the stack frame to find the PC. */
1361 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1364 /* One way to find the end of the prologue (which works well
1365 for unoptimized code) is to do the following:
1367 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1370 prologue_end = prev_pc;
1371 else if (sal.end < prologue_end)
1372 prologue_end = sal.end;
1374 This mechanism is very accurate so long as the optimizer
1375 doesn't move any instructions from the function body into the
1376 prologue. If this happens, sal.end will be the last
1377 instruction in the first hunk of prologue code just before
1378 the first instruction that the scheduler has moved from
1379 the body to the prologue.
1381 In order to make sure that we scan all of the prologue
1382 instructions, we use a slightly less accurate mechanism which
1383 may scan more than necessary. To help compensate for this
1384 lack of accuracy, the prologue scanning loop below contains
1385 several clauses which'll cause the loop to terminate early if
1386 an implausible prologue instruction is encountered.
1392 is a suitable endpoint since it accounts for the largest
1393 possible prologue plus up to five instructions inserted by
1396 if (prologue_end
> prologue_start
+ 64)
1398 prologue_end
= prologue_start
+ 64; /* See above. */
1403 /* We have no symbol information. Our only option is to assume this
1404 function has a standard stack frame and the normal frame register.
1405 Then, we can find the value of our frame pointer on entrance to
1406 the callee (or at the present moment if this is the innermost frame).
1407 The value stored there should be the address of the stmfd + 8. */
1408 CORE_ADDR frame_loc
;
1409 LONGEST return_value
;
1411 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1412 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1416 prologue_start
= gdbarch_addr_bits_remove
1417 (gdbarch
, return_value
) - 8;
1418 prologue_end
= prologue_start
+ 64; /* See above. */
1422 if (prev_pc
< prologue_end
)
1423 prologue_end
= prev_pc
;
1425 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1428 static struct arm_prologue_cache
*
1429 arm_make_prologue_cache (struct frame_info
*this_frame
)
1432 struct arm_prologue_cache
*cache
;
1433 CORE_ADDR unwound_fp
;
1435 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1436 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1438 arm_scan_prologue (this_frame
, cache
);
1440 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1441 if (unwound_fp
== 0)
1444 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1446 /* Calculate actual addresses of saved registers using offsets
1447 determined by arm_scan_prologue. */
1448 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1449 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1450 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1455 /* Our frame ID for a normal frame is the current function's starting PC
1456 and the caller's SP when we were called. */
1459 arm_prologue_this_id (struct frame_info
*this_frame
,
1461 struct frame_id
*this_id
)
1463 struct arm_prologue_cache
*cache
;
1467 if (*this_cache
== NULL
)
1468 *this_cache
= arm_make_prologue_cache (this_frame
);
1469 cache
= *this_cache
;
1471 /* This is meant to halt the backtrace at "_start". */
1472 pc
= get_frame_pc (this_frame
);
1473 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1476 /* If we've hit a wall, stop. */
1477 if (cache
->prev_sp
== 0)
1480 func
= get_frame_func (this_frame
);
1481 id
= frame_id_build (cache
->prev_sp
, func
);
1485 static struct value
*
1486 arm_prologue_prev_register (struct frame_info
*this_frame
,
1490 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1491 struct arm_prologue_cache
*cache
;
1493 if (*this_cache
== NULL
)
1494 *this_cache
= arm_make_prologue_cache (this_frame
);
1495 cache
= *this_cache
;
1497 /* If we are asked to unwind the PC, then we need to return the LR
1498 instead. The prologue may save PC, but it will point into this
1499 frame's prologue, not the next frame's resume location. Also
1500 strip the saved T bit. A valid LR may have the low bit set, but
1501 a valid PC never does. */
1502 if (prev_regnum
== ARM_PC_REGNUM
)
1506 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1507 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1508 arm_addr_bits_remove (gdbarch
, lr
));
1511 /* SP is generally not saved to the stack, but this frame is
1512 identified by the next frame's stack pointer at the time of the call.
1513 The value was already reconstructed into PREV_SP. */
1514 if (prev_regnum
== ARM_SP_REGNUM
)
1515 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1517 /* The CPSR may have been changed by the call instruction and by the
1518 called function. The only bit we can reconstruct is the T bit,
1519 by checking the low bit of LR as of the call. This is a reliable
1520 indicator of Thumb-ness except for some ARM v4T pre-interworking
1521 Thumb code, which could get away with a clear low bit as long as
1522 the called function did not use bx. Guess that all other
1523 bits are unchanged; the condition flags are presumably lost,
1524 but the processor status is likely valid. */
1525 if (prev_regnum
== ARM_PS_REGNUM
)
1528 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1530 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1531 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1532 if (IS_THUMB_ADDR (lr
))
1536 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1539 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1543 struct frame_unwind arm_prologue_unwind
= {
1545 arm_prologue_this_id
,
1546 arm_prologue_prev_register
,
1548 default_frame_sniffer
1551 static struct arm_prologue_cache
*
1552 arm_make_stub_cache (struct frame_info
*this_frame
)
1554 struct arm_prologue_cache
*cache
;
1556 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1557 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1559 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1564 /* Our frame ID for a stub frame is the current SP and LR. */
1567 arm_stub_this_id (struct frame_info
*this_frame
,
1569 struct frame_id
*this_id
)
1571 struct arm_prologue_cache
*cache
;
1573 if (*this_cache
== NULL
)
1574 *this_cache
= arm_make_stub_cache (this_frame
);
1575 cache
= *this_cache
;
1577 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1581 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1582 struct frame_info
*this_frame
,
1583 void **this_prologue_cache
)
1585 CORE_ADDR addr_in_block
;
1588 addr_in_block
= get_frame_address_in_block (this_frame
);
1589 if (in_plt_section (addr_in_block
, NULL
)
1590 /* We also use the stub winder if the target memory is unreadable
1591 to avoid having the prologue unwinder trying to read it. */
1592 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1598 struct frame_unwind arm_stub_unwind
= {
1601 arm_prologue_prev_register
,
1603 arm_stub_unwind_sniffer
1607 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1609 struct arm_prologue_cache
*cache
;
1611 if (*this_cache
== NULL
)
1612 *this_cache
= arm_make_prologue_cache (this_frame
);
1613 cache
= *this_cache
;
1615 return cache
->prev_sp
- cache
->framesize
;
1618 struct frame_base arm_normal_base
= {
1619 &arm_prologue_unwind
,
1620 arm_normal_frame_base
,
1621 arm_normal_frame_base
,
1622 arm_normal_frame_base
1625 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1626 dummy frame. The frame ID's base needs to match the TOS value
1627 saved by save_dummy_frame_tos() and returned from
1628 arm_push_dummy_call, and the PC needs to match the dummy frame's
1631 static struct frame_id
1632 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1634 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1635 get_frame_pc (this_frame
));
1638 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1639 be used to construct the previous frame's ID, after looking up the
1640 containing function). */
1643 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1646 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1647 return arm_addr_bits_remove (gdbarch
, pc
);
1651 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1653 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1656 static struct value
*
1657 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1660 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1662 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1667 /* The PC is normally copied from the return column, which
1668 describes saves of LR. However, that version may have an
1669 extra bit set to indicate Thumb state. The bit is not
1671 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1672 return frame_unwind_got_constant (this_frame
, regnum
,
1673 arm_addr_bits_remove (gdbarch
, lr
));
1676 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1677 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1678 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1679 if (IS_THUMB_ADDR (lr
))
1683 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1686 internal_error (__FILE__
, __LINE__
,
1687 _("Unexpected register %d"), regnum
);
1692 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1693 struct dwarf2_frame_state_reg
*reg
,
1694 struct frame_info
*this_frame
)
1700 reg
->how
= DWARF2_FRAME_REG_FN
;
1701 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1704 reg
->how
= DWARF2_FRAME_REG_CFA
;
1709 /* Return true if we are in the function's epilogue, i.e. after the
1710 instruction that destroyed the function's stack frame. */
1713 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1715 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1716 unsigned int insn
, insn2
;
1717 int found_return
= 0, found_stack_adjust
= 0;
1718 CORE_ADDR func_start
, func_end
;
1722 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
1725 /* The epilogue is a sequence of instructions along the following lines:
1727 - add stack frame size to SP or FP
1728 - [if frame pointer used] restore SP from FP
1729 - restore registers from SP [may include PC]
1730 - a return-type instruction [if PC wasn't already restored]
1732 In a first pass, we scan forward from the current PC and verify the
1733 instructions we find as compatible with this sequence, ending in a
1736 However, this is not sufficient to distinguish indirect function calls
1737 within a function from indirect tail calls in the epilogue in some cases.
1738 Therefore, if we didn't already find any SP-changing instruction during
1739 forward scan, we add a backward scanning heuristic to ensure we actually
1740 are in the epilogue. */
1743 while (scan_pc
< func_end
&& !found_return
)
1745 if (target_read_memory (scan_pc
, buf
, 2))
1749 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
1751 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
1753 else if (insn
== 0x46f7) /* mov pc, lr */
1755 else if (insn
== 0x46bd) /* mov sp, r7 */
1756 found_stack_adjust
= 1;
1757 else if ((insn
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
1758 found_stack_adjust
= 1;
1759 else if ((insn
& 0xfe00) == 0xbc00) /* pop <registers> */
1761 found_stack_adjust
= 1;
1762 if (insn
& 0x0100) /* <registers> include PC. */
1765 else if ((insn
& 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */
1767 if (target_read_memory (scan_pc
, buf
, 2))
1771 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
1773 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
1775 found_stack_adjust
= 1;
1776 if (insn2
& 0x8000) /* <registers> include PC. */
1779 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
1780 && (insn2
& 0x0fff) == 0x0b04)
1782 found_stack_adjust
= 1;
1783 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
1786 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
1787 && (insn2
& 0x0e00) == 0x0a00)
1788 found_stack_adjust
= 1;
1799 /* Since any instruction in the epilogue sequence, with the possible
1800 exception of return itself, updates the stack pointer, we need to
1801 scan backwards for at most one instruction. Try either a 16-bit or
1802 a 32-bit instruction. This is just a heuristic, so we do not worry
1803 too much about false positives.*/
1805 if (!found_stack_adjust
)
1807 if (pc
- 4 < func_start
)
1809 if (target_read_memory (pc
- 4, buf
, 4))
1812 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
1813 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
1815 if (insn2
== 0x46bd) /* mov sp, r7 */
1816 found_stack_adjust
= 1;
1817 else if ((insn2
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
1818 found_stack_adjust
= 1;
1819 else if ((insn2
& 0xff00) == 0xbc00) /* pop <registers> without PC */
1820 found_stack_adjust
= 1;
1821 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
1822 found_stack_adjust
= 1;
1823 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
1824 && (insn2
& 0x0fff) == 0x0b04)
1825 found_stack_adjust
= 1;
1826 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
1827 && (insn2
& 0x0e00) == 0x0a00)
1828 found_stack_adjust
= 1;
1831 return found_stack_adjust
;
1834 /* Return true if we are in the function's epilogue, i.e. after the
1835 instruction that destroyed the function's stack frame. */
1838 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1840 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1842 int found_return
, found_stack_adjust
;
1843 CORE_ADDR func_start
, func_end
;
1845 if (arm_pc_is_thumb (gdbarch
, pc
))
1846 return thumb_in_function_epilogue_p (gdbarch
, pc
);
1848 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
1851 /* We are in the epilogue if the previous instruction was a stack
1852 adjustment and the next instruction is a possible return (bx, mov
1853 pc, or pop). We could have to scan backwards to find the stack
1854 adjustment, or forwards to find the return, but this is a decent
1855 approximation. First scan forwards. */
1858 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1859 if (bits (insn
, 28, 31) != INST_NV
)
1861 if ((insn
& 0x0ffffff0) == 0x012fff10)
1864 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
1867 else if ((insn
& 0x0fff0000) == 0x08bd0000
1868 && (insn
& 0x0000c000) != 0)
1869 /* POP (LDMIA), including PC or LR. */
1876 /* Scan backwards. This is just a heuristic, so do not worry about
1877 false positives from mode changes. */
1879 if (pc
< func_start
+ 4)
1882 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
1883 if (bits (insn
, 28, 31) != INST_NV
)
1885 if ((insn
& 0x0df0f000) == 0x0080d000)
1886 /* ADD SP (register or immediate). */
1887 found_stack_adjust
= 1;
1888 else if ((insn
& 0x0df0f000) == 0x0040d000)
1889 /* SUB SP (register or immediate). */
1890 found_stack_adjust
= 1;
1891 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
1894 else if ((insn
& 0x0fff0000) == 0x08bd0000)
1896 found_stack_adjust
= 1;
1899 if (found_stack_adjust
)
1906 /* When arguments must be pushed onto the stack, they go on in reverse
1907 order. The code below implements a FILO (stack) to do this. */
1912 struct stack_item
*prev
;
1916 static struct stack_item
*
1917 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
1919 struct stack_item
*si
;
1920 si
= xmalloc (sizeof (struct stack_item
));
1921 si
->data
= xmalloc (len
);
1924 memcpy (si
->data
, contents
, len
);
1928 static struct stack_item
*
1929 pop_stack_item (struct stack_item
*si
)
1931 struct stack_item
*dead
= si
;
1939 /* Return the alignment (in bytes) of the given type. */
1942 arm_type_align (struct type
*t
)
1948 t
= check_typedef (t
);
1949 switch (TYPE_CODE (t
))
1952 /* Should never happen. */
1953 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1957 case TYPE_CODE_ENUM
:
1961 case TYPE_CODE_RANGE
:
1962 case TYPE_CODE_BITSTRING
:
1964 case TYPE_CODE_CHAR
:
1965 case TYPE_CODE_BOOL
:
1966 return TYPE_LENGTH (t
);
1968 case TYPE_CODE_ARRAY
:
1969 case TYPE_CODE_COMPLEX
:
1970 /* TODO: What about vector types? */
1971 return arm_type_align (TYPE_TARGET_TYPE (t
));
1973 case TYPE_CODE_STRUCT
:
1974 case TYPE_CODE_UNION
:
1976 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1978 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1986 /* Possible base types for a candidate for passing and returning in
1989 enum arm_vfp_cprc_base_type
1998 /* The length of one element of base type B. */
2001 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
2005 case VFP_CPRC_SINGLE
:
2007 case VFP_CPRC_DOUBLE
:
2009 case VFP_CPRC_VEC64
:
2011 case VFP_CPRC_VEC128
:
2014 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
2019 /* The character ('s', 'd' or 'q') for the type of VFP register used
2020 for passing base type B. */
2023 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
2027 case VFP_CPRC_SINGLE
:
2029 case VFP_CPRC_DOUBLE
:
2031 case VFP_CPRC_VEC64
:
2033 case VFP_CPRC_VEC128
:
2036 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
2041 /* Determine whether T may be part of a candidate for passing and
2042 returning in VFP registers, ignoring the limit on the total number
2043 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
2044 classification of the first valid component found; if it is not
2045 VFP_CPRC_UNKNOWN, all components must have the same classification
2046 as *BASE_TYPE. If it is found that T contains a type not permitted
2047 for passing and returning in VFP registers, a type differently
2048 classified from *BASE_TYPE, or two types differently classified
2049 from each other, return -1, otherwise return the total number of
2050 base-type elements found (possibly 0 in an empty structure or
2051 array). Vectors and complex types are not currently supported,
2052 matching the generic AAPCS support. */
2055 arm_vfp_cprc_sub_candidate (struct type
*t
,
2056 enum arm_vfp_cprc_base_type
*base_type
)
2058 t
= check_typedef (t
);
2059 switch (TYPE_CODE (t
))
2062 switch (TYPE_LENGTH (t
))
2065 if (*base_type
== VFP_CPRC_UNKNOWN
)
2066 *base_type
= VFP_CPRC_SINGLE
;
2067 else if (*base_type
!= VFP_CPRC_SINGLE
)
2072 if (*base_type
== VFP_CPRC_UNKNOWN
)
2073 *base_type
= VFP_CPRC_DOUBLE
;
2074 else if (*base_type
!= VFP_CPRC_DOUBLE
)
2083 case TYPE_CODE_ARRAY
:
2087 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
2090 if (TYPE_LENGTH (t
) == 0)
2092 gdb_assert (count
== 0);
2095 else if (count
== 0)
2097 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
2098 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
2099 return TYPE_LENGTH (t
) / unitlen
;
2103 case TYPE_CODE_STRUCT
:
2108 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2110 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
2112 if (sub_count
== -1)
2116 if (TYPE_LENGTH (t
) == 0)
2118 gdb_assert (count
== 0);
2121 else if (count
== 0)
2123 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
2124 if (TYPE_LENGTH (t
) != unitlen
* count
)
2129 case TYPE_CODE_UNION
:
2134 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
2136 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
2138 if (sub_count
== -1)
2140 count
= (count
> sub_count
? count
: sub_count
);
2142 if (TYPE_LENGTH (t
) == 0)
2144 gdb_assert (count
== 0);
2147 else if (count
== 0)
2149 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
2150 if (TYPE_LENGTH (t
) != unitlen
* count
)
2162 /* Determine whether T is a VFP co-processor register candidate (CPRC)
2163 if passed to or returned from a non-variadic function with the VFP
2164 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
2165 *BASE_TYPE to the base type for T and *COUNT to the number of
2166 elements of that base type before returning. */
2169 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
2172 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
2173 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
2174 if (c
<= 0 || c
> 4)
2181 /* Return 1 if the VFP ABI should be used for passing arguments to and
2182 returning values from a function of type FUNC_TYPE, 0
2186 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
2188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2189 /* Variadic functions always use the base ABI. Assume that functions
2190 without debug info are not variadic. */
2191 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
2193 /* The VFP ABI is only supported as a variant of AAPCS. */
2194 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
2196 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
2199 /* We currently only support passing parameters in integer registers, which
2200 conforms with GCC's default model, and VFP argument passing following
2201 the VFP variant of AAPCS. Several other variants exist and
2202 we should probably support some of them based on the selected ABI. */
2205 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2206 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2207 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2208 CORE_ADDR struct_addr
)
2210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2214 struct stack_item
*si
= NULL
;
2217 unsigned vfp_regs_free
= (1 << 16) - 1;
2219 /* Determine the type of this function and whether the VFP ABI
2221 ftype
= check_typedef (value_type (function
));
2222 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2223 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2224 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
2226 /* Set the return address. For the ARM, the return breakpoint is
2227 always at BP_ADDR. */
2228 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
2230 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
2232 /* Walk through the list of args and determine how large a temporary
2233 stack is required. Need to take care here as structs may be
2234 passed on the stack, and we have to to push them. */
2237 argreg
= ARM_A1_REGNUM
;
2240 /* The struct_return pointer occupies the first parameter
2241 passing register. */
2245 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
2246 gdbarch_register_name (gdbarch
, argreg
),
2247 paddress (gdbarch
, struct_addr
));
2248 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
2252 for (argnum
= 0; argnum
< nargs
; argnum
++)
2255 struct type
*arg_type
;
2256 struct type
*target_type
;
2257 enum type_code typecode
;
2258 const bfd_byte
*val
;
2260 enum arm_vfp_cprc_base_type vfp_base_type
;
2262 int may_use_core_reg
= 1;
2264 arg_type
= check_typedef (value_type (args
[argnum
]));
2265 len
= TYPE_LENGTH (arg_type
);
2266 target_type
= TYPE_TARGET_TYPE (arg_type
);
2267 typecode
= TYPE_CODE (arg_type
);
2268 val
= value_contents (args
[argnum
]);
2270 align
= arm_type_align (arg_type
);
2271 /* Round alignment up to a whole number of words. */
2272 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
2273 /* Different ABIs have different maximum alignments. */
2274 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
2276 /* The APCS ABI only requires word alignment. */
2277 align
= INT_REGISTER_SIZE
;
2281 /* The AAPCS requires at most doubleword alignment. */
2282 if (align
> INT_REGISTER_SIZE
* 2)
2283 align
= INT_REGISTER_SIZE
* 2;
2287 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
2295 /* Because this is a CPRC it cannot go in a core register or
2296 cause a core register to be skipped for alignment.
2297 Either it goes in VFP registers and the rest of this loop
2298 iteration is skipped for this argument, or it goes on the
2299 stack (and the stack alignment code is correct for this
2301 may_use_core_reg
= 0;
2303 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
2304 shift
= unit_length
/ 4;
2305 mask
= (1 << (shift
* vfp_base_count
)) - 1;
2306 for (regno
= 0; regno
< 16; regno
+= shift
)
2307 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
2316 vfp_regs_free
&= ~(mask
<< regno
);
2317 reg_scaled
= regno
/ shift
;
2318 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
2319 for (i
= 0; i
< vfp_base_count
; i
++)
2323 if (reg_char
== 'q')
2324 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
2325 val
+ i
* unit_length
);
2328 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
2329 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2331 regcache_cooked_write (regcache
, regnum
,
2332 val
+ i
* unit_length
);
2339 /* This CPRC could not go in VFP registers, so all VFP
2340 registers are now marked as used. */
2345 /* Push stack padding for dowubleword alignment. */
2346 if (nstack
& (align
- 1))
2348 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
2349 nstack
+= INT_REGISTER_SIZE
;
2352 /* Doubleword aligned quantities must go in even register pairs. */
2353 if (may_use_core_reg
2354 && argreg
<= ARM_LAST_ARG_REGNUM
2355 && align
> INT_REGISTER_SIZE
2359 /* If the argument is a pointer to a function, and it is a
2360 Thumb function, create a LOCAL copy of the value and set
2361 the THUMB bit in it. */
2362 if (TYPE_CODE_PTR
== typecode
2363 && target_type
!= NULL
2364 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
2366 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
2367 if (arm_pc_is_thumb (gdbarch
, regval
))
2369 bfd_byte
*copy
= alloca (len
);
2370 store_unsigned_integer (copy
, len
, byte_order
,
2371 MAKE_THUMB_ADDR (regval
));
2376 /* Copy the argument to general registers or the stack in
2377 register-sized pieces. Large arguments are split between
2378 registers and stack. */
2381 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
2383 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
2385 /* The argument is being passed in a general purpose
2388 = extract_unsigned_integer (val
, partial_len
, byte_order
);
2389 if (byte_order
== BFD_ENDIAN_BIG
)
2390 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
2392 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
2394 gdbarch_register_name
2396 phex (regval
, INT_REGISTER_SIZE
));
2397 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2402 /* Push the arguments onto the stack. */
2404 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
2406 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
2407 nstack
+= INT_REGISTER_SIZE
;
2414 /* If we have an odd number of words to push, then decrement the stack
2415 by one word now, so first stack argument will be dword aligned. */
2422 write_memory (sp
, si
->data
, si
->len
);
2423 si
= pop_stack_item (si
);
2426 /* Finally, update teh SP register. */
2427 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
2433 /* Always align the frame to an 8-byte boundary. This is required on
2434 some platforms and harmless on the rest. */
2437 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2439 /* Align the stack to eight bytes. */
2440 return sp
& ~ (CORE_ADDR
) 7;
2444 print_fpu_flags (int flags
)
2446 if (flags
& (1 << 0))
2447 fputs ("IVO ", stdout
);
2448 if (flags
& (1 << 1))
2449 fputs ("DVZ ", stdout
);
2450 if (flags
& (1 << 2))
2451 fputs ("OFL ", stdout
);
2452 if (flags
& (1 << 3))
2453 fputs ("UFL ", stdout
);
2454 if (flags
& (1 << 4))
2455 fputs ("INX ", stdout
);
2459 /* Print interesting information about the floating point processor
2460 (if present) or emulator. */
2462 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2463 struct frame_info
*frame
, const char *args
)
2465 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
2468 type
= (status
>> 24) & 127;
2469 if (status
& (1 << 31))
2470 printf (_("Hardware FPU type %d\n"), type
);
2472 printf (_("Software FPU type %d\n"), type
);
2473 /* i18n: [floating point unit] mask */
2474 fputs (_("mask: "), stdout
);
2475 print_fpu_flags (status
>> 16);
2476 /* i18n: [floating point unit] flags */
2477 fputs (_("flags: "), stdout
);
2478 print_fpu_flags (status
);
2481 /* Construct the ARM extended floating point type. */
2482 static struct type
*
2483 arm_ext_type (struct gdbarch
*gdbarch
)
2485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2487 if (!tdep
->arm_ext_type
)
2489 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
2490 floatformats_arm_ext
);
2492 return tdep
->arm_ext_type
;
2495 static struct type
*
2496 arm_neon_double_type (struct gdbarch
*gdbarch
)
2498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2500 if (tdep
->neon_double_type
== NULL
)
2502 struct type
*t
, *elem
;
2504 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
2506 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2507 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
2508 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2509 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
2510 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2511 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
2512 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2513 append_composite_type_field (t
, "u64", elem
);
2514 elem
= builtin_type (gdbarch
)->builtin_float
;
2515 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
2516 elem
= builtin_type (gdbarch
)->builtin_double
;
2517 append_composite_type_field (t
, "f64", elem
);
2519 TYPE_VECTOR (t
) = 1;
2520 TYPE_NAME (t
) = "neon_d";
2521 tdep
->neon_double_type
= t
;
2524 return tdep
->neon_double_type
;
2527 /* FIXME: The vector types are not correctly ordered on big-endian
2528 targets. Just as s0 is the low bits of d0, d0[0] is also the low
2529 bits of d0 - regardless of what unit size is being held in d0. So
2530 the offset of the first uint8 in d0 is 7, but the offset of the
2531 first float is 4. This code works as-is for little-endian
2534 static struct type
*
2535 arm_neon_quad_type (struct gdbarch
*gdbarch
)
2537 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2539 if (tdep
->neon_quad_type
== NULL
)
2541 struct type
*t
, *elem
;
2543 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
2545 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2546 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
2547 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2548 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
2549 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2550 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
2551 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2552 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
2553 elem
= builtin_type (gdbarch
)->builtin_float
;
2554 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
2555 elem
= builtin_type (gdbarch
)->builtin_double
;
2556 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
2558 TYPE_VECTOR (t
) = 1;
2559 TYPE_NAME (t
) = "neon_q";
2560 tdep
->neon_quad_type
= t
;
2563 return tdep
->neon_quad_type
;
2566 /* Return the GDB type object for the "standard" data type of data in
2569 static struct type
*
2570 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
2572 int num_regs
= gdbarch_num_regs (gdbarch
);
2574 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
2575 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
2576 return builtin_type (gdbarch
)->builtin_float
;
2578 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
2579 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
2580 return arm_neon_quad_type (gdbarch
);
2582 /* If the target description has register information, we are only
2583 in this function so that we can override the types of
2584 double-precision registers for NEON. */
2585 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
2587 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
2589 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
2590 && TYPE_CODE (t
) == TYPE_CODE_FLT
2591 && gdbarch_tdep (gdbarch
)->have_neon
)
2592 return arm_neon_double_type (gdbarch
);
2597 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
2599 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2600 return builtin_type (gdbarch
)->builtin_void
;
2602 return arm_ext_type (gdbarch
);
2604 else if (regnum
== ARM_SP_REGNUM
)
2605 return builtin_type (gdbarch
)->builtin_data_ptr
;
2606 else if (regnum
== ARM_PC_REGNUM
)
2607 return builtin_type (gdbarch
)->builtin_func_ptr
;
2608 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
2609 /* These registers are only supported on targets which supply
2610 an XML description. */
2611 return builtin_type (gdbarch
)->builtin_int0
;
2613 return builtin_type (gdbarch
)->builtin_uint32
;
2616 /* Map a DWARF register REGNUM onto the appropriate GDB register
2620 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2622 /* Core integer regs. */
2623 if (reg
>= 0 && reg
<= 15)
2626 /* Legacy FPA encoding. These were once used in a way which
2627 overlapped with VFP register numbering, so their use is
2628 discouraged, but GDB doesn't support the ARM toolchain
2629 which used them for VFP. */
2630 if (reg
>= 16 && reg
<= 23)
2631 return ARM_F0_REGNUM
+ reg
- 16;
2633 /* New assignments for the FPA registers. */
2634 if (reg
>= 96 && reg
<= 103)
2635 return ARM_F0_REGNUM
+ reg
- 96;
2637 /* WMMX register assignments. */
2638 if (reg
>= 104 && reg
<= 111)
2639 return ARM_WCGR0_REGNUM
+ reg
- 104;
2641 if (reg
>= 112 && reg
<= 127)
2642 return ARM_WR0_REGNUM
+ reg
- 112;
2644 if (reg
>= 192 && reg
<= 199)
2645 return ARM_WC0_REGNUM
+ reg
- 192;
2647 /* VFP v2 registers. A double precision value is actually
2648 in d1 rather than s2, but the ABI only defines numbering
2649 for the single precision registers. This will "just work"
2650 in GDB for little endian targets (we'll read eight bytes,
2651 starting in s0 and then progressing to s1), but will be
2652 reversed on big endian targets with VFP. This won't
2653 be a problem for the new Neon quad registers; you're supposed
2654 to use DW_OP_piece for those. */
2655 if (reg
>= 64 && reg
<= 95)
2659 sprintf (name_buf
, "s%d", reg
- 64);
2660 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2664 /* VFP v3 / Neon registers. This range is also used for VFP v2
2665 registers, except that it now describes d0 instead of s0. */
2666 if (reg
>= 256 && reg
<= 287)
2670 sprintf (name_buf
, "d%d", reg
- 256);
2671 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2678 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
2680 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
2683 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
2685 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
2686 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
2688 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
2689 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
2691 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
2692 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
2694 if (reg
< NUM_GREGS
)
2695 return SIM_ARM_R0_REGNUM
+ reg
;
2698 if (reg
< NUM_FREGS
)
2699 return SIM_ARM_FP0_REGNUM
+ reg
;
2702 if (reg
< NUM_SREGS
)
2703 return SIM_ARM_FPS_REGNUM
+ reg
;
2706 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
2709 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
2710 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
2711 It is thought that this is is the floating-point register format on
2712 little-endian systems. */
2715 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
2716 void *dbl
, int endianess
)
2720 if (endianess
== BFD_ENDIAN_BIG
)
2721 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
2723 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2725 floatformat_from_doublest (fmt
, &d
, dbl
);
2729 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
2734 floatformat_to_doublest (fmt
, ptr
, &d
);
2735 if (endianess
== BFD_ENDIAN_BIG
)
2736 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
2738 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2743 condition_true (unsigned long cond
, unsigned long status_reg
)
2745 if (cond
== INST_AL
|| cond
== INST_NV
)
2751 return ((status_reg
& FLAG_Z
) != 0);
2753 return ((status_reg
& FLAG_Z
) == 0);
2755 return ((status_reg
& FLAG_C
) != 0);
2757 return ((status_reg
& FLAG_C
) == 0);
2759 return ((status_reg
& FLAG_N
) != 0);
2761 return ((status_reg
& FLAG_N
) == 0);
2763 return ((status_reg
& FLAG_V
) != 0);
2765 return ((status_reg
& FLAG_V
) == 0);
2767 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
2769 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
2771 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
2773 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
2775 return (((status_reg
& FLAG_Z
) == 0)
2776 && (((status_reg
& FLAG_N
) == 0)
2777 == ((status_reg
& FLAG_V
) == 0)));
2779 return (((status_reg
& FLAG_Z
) != 0)
2780 || (((status_reg
& FLAG_N
) == 0)
2781 != ((status_reg
& FLAG_V
) == 0)));
2786 static unsigned long
2787 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
2788 unsigned long pc_val
, unsigned long status_reg
)
2790 unsigned long res
, shift
;
2791 int rm
= bits (inst
, 0, 3);
2792 unsigned long shifttype
= bits (inst
, 5, 6);
2796 int rs
= bits (inst
, 8, 11);
2797 shift
= (rs
== 15 ? pc_val
+ 8
2798 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
2801 shift
= bits (inst
, 7, 11);
2804 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
2805 : get_frame_register_unsigned (frame
, rm
));
2810 res
= shift
>= 32 ? 0 : res
<< shift
;
2814 res
= shift
>= 32 ? 0 : res
>> shift
;
2820 res
= ((res
& 0x80000000L
)
2821 ? ~((~res
) >> shift
) : res
>> shift
);
2824 case 3: /* ROR/RRX */
2827 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
2829 res
= (res
>> shift
) | (res
<< (32 - shift
));
2833 return res
& 0xffffffff;
2836 /* Return number of 1-bits in VAL. */
2839 bitcount (unsigned long val
)
2842 for (nbits
= 0; val
!= 0; nbits
++)
2843 val
&= val
- 1; /* delete rightmost 1-bit in val */
2847 /* Return the size in bytes of the complete Thumb instruction whose
2848 first halfword is INST1. */
2851 thumb_insn_size (unsigned short inst1
)
2853 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2860 thumb_advance_itstate (unsigned int itstate
)
2862 /* Preserve IT[7:5], the first three bits of the condition. Shift
2863 the upcoming condition flags left by one bit. */
2864 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
2866 /* If we have finished the IT block, clear the state. */
2867 if ((itstate
& 0x0f) == 0)
2873 /* Find the next PC after the current instruction executes. In some
2874 cases we can not statically determine the answer (see the IT state
2875 handling in this function); in that case, a breakpoint may be
2876 inserted in addition to the returned PC, which will be used to set
2877 another breakpoint by our caller. */
2880 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
2882 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2883 struct address_space
*aspace
= get_frame_address_space (frame
);
2884 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2885 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2886 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
2887 unsigned short inst1
;
2888 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
2889 unsigned long offset
;
2890 ULONGEST status
, itstate
;
2892 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2893 pc_val
= MAKE_THUMB_ADDR (pc_val
);
2895 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2897 /* Thumb-2 conditional execution support. There are eight bits in
2898 the CPSR which describe conditional execution state. Once
2899 reconstructed (they're in a funny order), the low five bits
2900 describe the low bit of the condition for each instruction and
2901 how many instructions remain. The high three bits describe the
2902 base condition. One of the low four bits will be set if an IT
2903 block is active. These bits read as zero on earlier
2905 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2906 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
2908 /* If-Then handling. On GNU/Linux, where this routine is used, we
2909 use an undefined instruction as a breakpoint. Unlike BKPT, IT
2910 can disable execution of the undefined instruction. So we might
2911 miss the breakpoint if we set it on a skipped conditional
2912 instruction. Because conditional instructions can change the
2913 flags, affecting the execution of further instructions, we may
2914 need to set two breakpoints. */
2916 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
2918 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
2920 /* An IT instruction. Because this instruction does not
2921 modify the flags, we can accurately predict the next
2922 executed instruction. */
2923 itstate
= inst1
& 0x00ff;
2924 pc
+= thumb_insn_size (inst1
);
2926 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2928 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2929 pc
+= thumb_insn_size (inst1
);
2930 itstate
= thumb_advance_itstate (itstate
);
2933 return MAKE_THUMB_ADDR (pc
);
2935 else if (itstate
!= 0)
2937 /* We are in a conditional block. Check the condition. */
2938 if (! condition_true (itstate
>> 4, status
))
2940 /* Advance to the next executed instruction. */
2941 pc
+= thumb_insn_size (inst1
);
2942 itstate
= thumb_advance_itstate (itstate
);
2944 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2946 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2947 pc
+= thumb_insn_size (inst1
);
2948 itstate
= thumb_advance_itstate (itstate
);
2951 return MAKE_THUMB_ADDR (pc
);
2953 else if ((itstate
& 0x0f) == 0x08)
2955 /* This is the last instruction of the conditional
2956 block, and it is executed. We can handle it normally
2957 because the following instruction is not conditional,
2958 and we must handle it normally because it is
2959 permitted to branch. Fall through. */
2965 /* There are conditional instructions after this one.
2966 If this instruction modifies the flags, then we can
2967 not predict what the next executed instruction will
2968 be. Fortunately, this instruction is architecturally
2969 forbidden to branch; we know it will fall through.
2970 Start by skipping past it. */
2971 pc
+= thumb_insn_size (inst1
);
2972 itstate
= thumb_advance_itstate (itstate
);
2974 /* Set a breakpoint on the following instruction. */
2975 gdb_assert ((itstate
& 0x0f) != 0);
2977 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
2978 cond_negated
= (itstate
>> 4) & 1;
2980 /* Skip all following instructions with the same
2981 condition. If there is a later instruction in the IT
2982 block with the opposite condition, set the other
2983 breakpoint there. If not, then set a breakpoint on
2984 the instruction after the IT block. */
2987 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2988 pc
+= thumb_insn_size (inst1
);
2989 itstate
= thumb_advance_itstate (itstate
);
2991 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
2993 return MAKE_THUMB_ADDR (pc
);
2997 else if (itstate
& 0x0f)
2999 /* We are in a conditional block. Check the condition. */
3000 int cond
= itstate
>> 4;
3002 if (! condition_true (cond
, status
))
3004 /* Advance to the next instruction. All the 32-bit
3005 instructions share a common prefix. */
3006 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
3007 return MAKE_THUMB_ADDR (pc
+ 4);
3009 return MAKE_THUMB_ADDR (pc
+ 2);
3012 /* Otherwise, handle the instruction normally. */
3015 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
3019 /* Fetch the saved PC from the stack. It's stored above
3020 all of the other registers. */
3021 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
3022 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
3023 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
3025 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
3027 unsigned long cond
= bits (inst1
, 8, 11);
3028 if (cond
== 0x0f) /* 0x0f = SWI */
3030 struct gdbarch_tdep
*tdep
;
3031 tdep
= gdbarch_tdep (gdbarch
);
3033 if (tdep
->syscall_next_pc
!= NULL
)
3034 nextpc
= tdep
->syscall_next_pc (frame
);
3037 else if (cond
!= 0x0f && condition_true (cond
, status
))
3038 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
3040 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
3042 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
3044 else if ((inst1
& 0xe000) == 0xe000) /* 32-bit instruction */
3046 unsigned short inst2
;
3047 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
3049 /* Default to the next instruction. */
3051 nextpc
= MAKE_THUMB_ADDR (nextpc
);
3053 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
3055 /* Branches and miscellaneous control instructions. */
3057 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
3060 int j1
, j2
, imm1
, imm2
;
3062 imm1
= sbits (inst1
, 0, 10);
3063 imm2
= bits (inst2
, 0, 10);
3064 j1
= bit (inst2
, 13);
3065 j2
= bit (inst2
, 11);
3067 offset
= ((imm1
<< 12) + (imm2
<< 1));
3068 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
3070 nextpc
= pc_val
+ offset
;
3071 /* For BLX make sure to clear the low bits. */
3072 if (bit (inst2
, 12) == 0)
3073 nextpc
= nextpc
& 0xfffffffc;
3075 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
3077 /* SUBS PC, LR, #imm8. */
3078 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
3079 nextpc
-= inst2
& 0x00ff;
3081 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
3083 /* Conditional branch. */
3084 if (condition_true (bits (inst1
, 6, 9), status
))
3086 int sign
, j1
, j2
, imm1
, imm2
;
3088 sign
= sbits (inst1
, 10, 10);
3089 imm1
= bits (inst1
, 0, 5);
3090 imm2
= bits (inst2
, 0, 10);
3091 j1
= bit (inst2
, 13);
3092 j2
= bit (inst2
, 11);
3094 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
3095 offset
+= (imm1
<< 12) + (imm2
<< 1);
3097 nextpc
= pc_val
+ offset
;
3101 else if ((inst1
& 0xfe50) == 0xe810)
3103 /* Load multiple or RFE. */
3104 int rn
, offset
, load_pc
= 1;
3106 rn
= bits (inst1
, 0, 3);
3107 if (bit (inst1
, 7) && !bit (inst1
, 8))
3110 if (!bit (inst2
, 15))
3112 offset
= bitcount (inst2
) * 4 - 4;
3114 else if (!bit (inst1
, 7) && bit (inst1
, 8))
3117 if (!bit (inst2
, 15))
3121 else if (bit (inst1
, 7) && bit (inst1
, 8))
3126 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
3136 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
3137 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
3140 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
3142 /* MOV PC or MOVS PC. */
3143 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
3144 nextpc
= MAKE_THUMB_ADDR (nextpc
);
3146 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
3150 int rn
, load_pc
= 1;
3152 rn
= bits (inst1
, 0, 3);
3153 base
= get_frame_register_unsigned (frame
, rn
);
3156 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
3158 base
+= bits (inst2
, 0, 11);
3160 base
-= bits (inst2
, 0, 11);
3162 else if (bit (inst1
, 7))
3163 base
+= bits (inst2
, 0, 11);
3164 else if (bit (inst2
, 11))
3166 if (bit (inst2
, 10))
3169 base
+= bits (inst2
, 0, 7);
3171 base
-= bits (inst2
, 0, 7);
3174 else if ((inst2
& 0x0fc0) == 0x0000)
3176 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
3177 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
3184 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
3186 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
3189 CORE_ADDR tbl_reg
, table
, offset
, length
;
3191 tbl_reg
= bits (inst1
, 0, 3);
3192 if (tbl_reg
== 0x0f)
3193 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
3195 table
= get_frame_register_unsigned (frame
, tbl_reg
);
3197 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
3198 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
3199 nextpc
= pc_val
+ length
;
3201 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
3204 CORE_ADDR tbl_reg
, table
, offset
, length
;
3206 tbl_reg
= bits (inst1
, 0, 3);
3207 if (tbl_reg
== 0x0f)
3208 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
3210 table
= get_frame_register_unsigned (frame
, tbl_reg
);
3212 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
3213 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
3214 nextpc
= pc_val
+ length
;
3217 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
3219 if (bits (inst1
, 3, 6) == 0x0f)
3222 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
3224 else if ((inst1
& 0xf500) == 0xb100)
3227 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
3228 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
3230 if (bit (inst1
, 11) && reg
!= 0)
3231 nextpc
= pc_val
+ imm
;
3232 else if (!bit (inst1
, 11) && reg
== 0)
3233 nextpc
= pc_val
+ imm
;
3238 /* Get the raw next address. PC is the current program counter, in
3239 FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on
3240 the alternative next instruction if there are two options.
3242 The value returned has the execution state of the next instruction
3243 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
3244 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
3248 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
3250 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3251 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3252 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3253 unsigned long pc_val
;
3254 unsigned long this_instr
;
3255 unsigned long status
;
3258 if (arm_frame_is_thumb (frame
))
3259 return thumb_get_next_pc_raw (frame
, pc
, insert_bkpt
);
3261 pc_val
= (unsigned long) pc
;
3262 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3264 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
3265 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
3267 if (bits (this_instr
, 28, 31) == INST_NV
)
3268 switch (bits (this_instr
, 24, 27))
3273 /* Branch with Link and change to Thumb. */
3274 nextpc
= BranchDest (pc
, this_instr
);
3275 nextpc
|= bit (this_instr
, 24) << 1;
3276 nextpc
= MAKE_THUMB_ADDR (nextpc
);
3282 /* Coprocessor register transfer. */
3283 if (bits (this_instr
, 12, 15) == 15)
3284 error (_("Invalid update to pc in instruction"));
3287 else if (condition_true (bits (this_instr
, 28, 31), status
))
3289 switch (bits (this_instr
, 24, 27))
3292 case 0x1: /* data processing */
3296 unsigned long operand1
, operand2
, result
= 0;
3300 if (bits (this_instr
, 12, 15) != 15)
3303 if (bits (this_instr
, 22, 25) == 0
3304 && bits (this_instr
, 4, 7) == 9) /* multiply */
3305 error (_("Invalid update to pc in instruction"));
3307 /* BX <reg>, BLX <reg> */
3308 if (bits (this_instr
, 4, 27) == 0x12fff1
3309 || bits (this_instr
, 4, 27) == 0x12fff3)
3311 rn
= bits (this_instr
, 0, 3);
3312 nextpc
= (rn
== 15) ? pc_val
+ 8
3313 : get_frame_register_unsigned (frame
, rn
);
3317 /* Multiply into PC */
3318 c
= (status
& FLAG_C
) ? 1 : 0;
3319 rn
= bits (this_instr
, 16, 19);
3320 operand1
= (rn
== 15) ? pc_val
+ 8
3321 : get_frame_register_unsigned (frame
, rn
);
3323 if (bit (this_instr
, 25))
3325 unsigned long immval
= bits (this_instr
, 0, 7);
3326 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
3327 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
3330 else /* operand 2 is a shifted register */
3331 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
3333 switch (bits (this_instr
, 21, 24))
3336 result
= operand1
& operand2
;
3340 result
= operand1
^ operand2
;
3344 result
= operand1
- operand2
;
3348 result
= operand2
- operand1
;
3352 result
= operand1
+ operand2
;
3356 result
= operand1
+ operand2
+ c
;
3360 result
= operand1
- operand2
+ c
;
3364 result
= operand2
- operand1
+ c
;
3370 case 0xb: /* tst, teq, cmp, cmn */
3371 result
= (unsigned long) nextpc
;
3375 result
= operand1
| operand2
;
3379 /* Always step into a function. */
3384 result
= operand1
& ~operand2
;
3392 /* In 26-bit APCS the bottom two bits of the result are
3393 ignored, and we always end up in ARM state. */
3395 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
3403 case 0x5: /* data transfer */
3406 if (bit (this_instr
, 20))
3409 if (bits (this_instr
, 12, 15) == 15)
3415 if (bit (this_instr
, 22))
3416 error (_("Invalid update to pc in instruction"));
3418 /* byte write to PC */
3419 rn
= bits (this_instr
, 16, 19);
3420 base
= (rn
== 15) ? pc_val
+ 8
3421 : get_frame_register_unsigned (frame
, rn
);
3422 if (bit (this_instr
, 24))
3425 int c
= (status
& FLAG_C
) ? 1 : 0;
3426 unsigned long offset
=
3427 (bit (this_instr
, 25)
3428 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
3429 : bits (this_instr
, 0, 11));
3431 if (bit (this_instr
, 23))
3436 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
3443 case 0x9: /* block transfer */
3444 if (bit (this_instr
, 20))
3447 if (bit (this_instr
, 15))
3452 if (bit (this_instr
, 23))
3455 unsigned long reglist
= bits (this_instr
, 0, 14);
3456 offset
= bitcount (reglist
) * 4;
3457 if (bit (this_instr
, 24)) /* pre */
3460 else if (bit (this_instr
, 24))
3464 unsigned long rn_val
=
3465 get_frame_register_unsigned (frame
,
3466 bits (this_instr
, 16, 19));
3468 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
3476 case 0xb: /* branch & link */
3477 case 0xa: /* branch */
3479 nextpc
= BranchDest (pc
, this_instr
);
3485 case 0xe: /* coproc ops */
3489 struct gdbarch_tdep
*tdep
;
3490 tdep
= gdbarch_tdep (gdbarch
);
3492 if (tdep
->syscall_next_pc
!= NULL
)
3493 nextpc
= tdep
->syscall_next_pc (frame
);
3499 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
3508 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
3510 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3512 gdbarch_addr_bits_remove (gdbarch
,
3513 arm_get_next_pc_raw (frame
, pc
, TRUE
));
3515 error (_("Infinite loop detected"));
3519 /* single_step() is called just before we want to resume the inferior,
3520 if we want to single-step it but there is no hardware or kernel
3521 single-step support. We find the target of the coming instruction
3522 and breakpoint it. */
3525 arm_software_single_step (struct frame_info
*frame
)
3527 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3528 struct address_space
*aspace
= get_frame_address_space (frame
);
3530 /* NOTE: This may insert the wrong breakpoint instruction when
3531 single-stepping over a mode-changing instruction, if the
3532 CPSR heuristics are used. */
3534 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
3535 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3540 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
3541 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
3542 NULL if an error occurs. BUF is freed. */
3545 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
3546 int old_len
, int new_len
)
3548 gdb_byte
*new_buf
, *middle
;
3549 int bytes_to_read
= new_len
- old_len
;
3551 new_buf
= xmalloc (new_len
);
3552 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
3554 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
3562 /* An IT block is at most the 2-byte IT instruction followed by
3563 four 4-byte instructions. The furthest back we must search to
3564 find an IT block that affects the current instruction is thus
3565 2 + 3 * 4 == 14 bytes. */
3566 #define MAX_IT_BLOCK_PREFIX 14
3568 /* Use a quick scan if there are more than this many bytes of
3570 #define IT_SCAN_THRESHOLD 32
3572 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
3573 A breakpoint in an IT block may not be hit, depending on the
3576 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
3580 CORE_ADDR boundary
, func_start
;
3581 int buf_len
, buf2_len
;
3582 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
3583 int i
, any
, last_it
, last_it_count
;
3585 /* If we are using BKPT breakpoints, none of this is necessary. */
3586 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
3589 /* ARM mode does not have this problem. */
3590 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
3593 /* We are setting a breakpoint in Thumb code that could potentially
3594 contain an IT block. The first step is to find how much Thumb
3595 code there is; we do not need to read outside of known Thumb
3597 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
3599 /* Thumb-2 code must have mapping symbols to have a chance. */
3602 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
3604 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
3605 && func_start
> boundary
)
3606 boundary
= func_start
;
3608 /* Search for a candidate IT instruction. We have to do some fancy
3609 footwork to distinguish a real IT instruction from the second
3610 half of a 32-bit instruction, but there is no need for that if
3611 there's no candidate. */
3612 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
3614 /* No room for an IT instruction. */
3617 buf
= xmalloc (buf_len
);
3618 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
3621 for (i
= 0; i
< buf_len
; i
+= 2)
3623 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3624 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3636 /* OK, the code bytes before this instruction contain at least one
3637 halfword which resembles an IT instruction. We know that it's
3638 Thumb code, but there are still two possibilities. Either the
3639 halfword really is an IT instruction, or it is the second half of
3640 a 32-bit Thumb instruction. The only way we can tell is to
3641 scan forwards from a known instruction boundary. */
3642 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
3646 /* There's a lot of code before this instruction. Start with an
3647 optimistic search; it's easy to recognize halfwords that can
3648 not be the start of a 32-bit instruction, and use that to
3649 lock on to the instruction boundaries. */
3650 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
3653 buf_len
= IT_SCAN_THRESHOLD
;
3656 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
3658 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3659 if (thumb_insn_size (inst1
) == 2)
3666 /* At this point, if DEFINITE, BUF[I] is the first place we
3667 are sure that we know the instruction boundaries, and it is far
3668 enough from BPADDR that we could not miss an IT instruction
3669 affecting BPADDR. If ! DEFINITE, give up - start from a
3673 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3676 buf_len
= bpaddr
- boundary
;
3682 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3685 buf_len
= bpaddr
- boundary
;
3689 /* Scan forwards. Find the last IT instruction before BPADDR. */
3694 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3696 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3701 else if (inst1
& 0x0002)
3703 else if (inst1
& 0x0004)
3708 i
+= thumb_insn_size (inst1
);
3714 /* There wasn't really an IT instruction after all. */
3717 if (last_it_count
< 1)
3718 /* It was too far away. */
3721 /* This really is a trouble spot. Move the breakpoint to the IT
3723 return bpaddr
- buf_len
+ last_it
;
3726 /* ARM displaced stepping support.
3728 Generally ARM displaced stepping works as follows:
3730 1. When an instruction is to be single-stepped, it is first decoded by
3731 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
3732 Depending on the type of instruction, it is then copied to a scratch
3733 location, possibly in a modified form. The copy_* set of functions
3734 performs such modification, as necessary. A breakpoint is placed after
3735 the modified instruction in the scratch space to return control to GDB.
3736 Note in particular that instructions which modify the PC will no longer
3737 do so after modification.
3739 2. The instruction is single-stepped, by setting the PC to the scratch
3740 location address, and resuming. Control returns to GDB when the
3743 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
3744 function used for the current instruction. This function's job is to
3745 put the CPU/memory state back to what it would have been if the
3746 instruction had been executed unmodified in its original location. */
3748 /* NOP instruction (mov r0, r0). */
3749 #define ARM_NOP 0xe1a00000
3751 /* Helper for register reads for displaced stepping. In particular, this
3752 returns the PC as it would be seen by the instruction at its original
3756 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
3762 if (debug_displaced
)
3763 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
3764 (unsigned long) from
+ 8);
3765 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
3769 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
3770 if (debug_displaced
)
3771 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
3772 regno
, (unsigned long) ret
);
3778 displaced_in_arm_mode (struct regcache
*regs
)
3781 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
3783 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3785 return (ps
& t_bit
) == 0;
3788 /* Write to the PC as from a branch instruction. */
3791 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
3793 if (displaced_in_arm_mode (regs
))
3794 /* Note: If bits 0/1 are set, this branch would be unpredictable for
3795 architecture versions < 6. */
3796 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x3);
3798 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x1);
3801 /* Write to the PC as from a branch-exchange instruction. */
3804 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
3807 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
3809 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3813 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
3814 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
3816 else if ((val
& 2) == 0)
3818 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
3819 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
3823 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
3824 mode, align dest to 4 bytes). */
3825 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
3826 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
3827 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
3831 /* Write to the PC as if from a load instruction. */
3834 load_write_pc (struct regcache
*regs
, ULONGEST val
)
3836 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
3837 bx_write_pc (regs
, val
);
3839 branch_write_pc (regs
, val
);
3842 /* Write to the PC as if from an ALU instruction. */
3845 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
3847 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
3848 bx_write_pc (regs
, val
);
3850 branch_write_pc (regs
, val
);
3853 /* Helper for writing to registers for displaced stepping. Writing to the PC
3854 has a varying effects depending on the instruction which does the write:
3855 this is controlled by the WRITE_PC argument. */
3858 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
3859 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
3863 if (debug_displaced
)
3864 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
3865 (unsigned long) val
);
3868 case BRANCH_WRITE_PC
:
3869 branch_write_pc (regs
, val
);
3873 bx_write_pc (regs
, val
);
3877 load_write_pc (regs
, val
);
3881 alu_write_pc (regs
, val
);
3884 case CANNOT_WRITE_PC
:
3885 warning (_("Instruction wrote to PC in an unexpected way when "
3886 "single-stepping"));
3890 internal_error (__FILE__
, __LINE__
,
3891 _("Invalid argument to displaced_write_reg"));
3894 dsc
->wrote_to_pc
= 1;
3898 if (debug_displaced
)
3899 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
3900 regno
, (unsigned long) val
);
3901 regcache_cooked_write_unsigned (regs
, regno
, val
);
3905 /* This function is used to concisely determine if an instruction INSN
3906 references PC. Register fields of interest in INSN should have the
3907 corresponding fields of BITMASK set to 0b1111. The function returns return 1
3908 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
3912 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
3914 uint32_t lowbit
= 1;
3916 while (bitmask
!= 0)
3920 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
3926 mask
= lowbit
* 0xf;
3928 if ((insn
& mask
) == mask
)
3937 /* The simplest copy function. Many instructions have the same effect no
3938 matter what address they are executed at: in those cases, use this. */
3941 copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
3942 const char *iname
, struct displaced_step_closure
*dsc
)
3944 if (debug_displaced
)
3945 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
3946 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
3949 dsc
->modinsn
[0] = insn
;
3954 /* Preload instructions with immediate offset. */
3957 cleanup_preload (struct gdbarch
*gdbarch
,
3958 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3960 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3961 if (!dsc
->u
.preload
.immed
)
3962 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3966 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3967 struct displaced_step_closure
*dsc
)
3969 unsigned int rn
= bits (insn
, 16, 19);
3971 CORE_ADDR from
= dsc
->insn_addr
;
3973 if (!insn_references_pc (insn
, 0x000f0000ul
))
3974 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
3976 if (debug_displaced
)
3977 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3978 (unsigned long) insn
);
3980 /* Preload instructions:
3982 {pli/pld} [rn, #+/-imm]
3984 {pli/pld} [r0, #+/-imm]. */
3986 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3987 rn_val
= displaced_read_reg (regs
, from
, rn
);
3988 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3990 dsc
->u
.preload
.immed
= 1;
3992 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3994 dsc
->cleanup
= &cleanup_preload
;
3999 /* Preload instructions with register offset. */
4002 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4003 struct displaced_step_closure
*dsc
)
4005 unsigned int rn
= bits (insn
, 16, 19);
4006 unsigned int rm
= bits (insn
, 0, 3);
4007 ULONGEST rn_val
, rm_val
;
4008 CORE_ADDR from
= dsc
->insn_addr
;
4010 if (!insn_references_pc (insn
, 0x000f000ful
))
4011 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4013 if (debug_displaced
)
4014 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4015 (unsigned long) insn
);
4017 /* Preload register-offset instructions:
4019 {pli/pld} [rn, rm {, shift}]
4021 {pli/pld} [r0, r1 {, shift}]. */
4023 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4024 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4025 rn_val
= displaced_read_reg (regs
, from
, rn
);
4026 rm_val
= displaced_read_reg (regs
, from
, rm
);
4027 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4028 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4030 dsc
->u
.preload
.immed
= 0;
4032 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4034 dsc
->cleanup
= &cleanup_preload
;
4039 /* Copy/cleanup coprocessor load and store instructions. */
4042 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4043 struct regcache
*regs
,
4044 struct displaced_step_closure
*dsc
)
4046 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4048 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4050 if (dsc
->u
.ldst
.writeback
)
4051 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4055 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4056 struct regcache
*regs
,
4057 struct displaced_step_closure
*dsc
)
4059 unsigned int rn
= bits (insn
, 16, 19);
4061 CORE_ADDR from
= dsc
->insn_addr
;
4063 if (!insn_references_pc (insn
, 0x000f0000ul
))
4064 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4066 if (debug_displaced
)
4067 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4068 "load/store insn %.8lx\n", (unsigned long) insn
);
4070 /* Coprocessor load/store instructions:
4072 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4074 {stc/stc2} [r0, #+/-imm].
4076 ldc/ldc2 are handled identically. */
4078 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4079 rn_val
= displaced_read_reg (regs
, from
, rn
);
4080 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4082 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
4083 dsc
->u
.ldst
.rn
= rn
;
4085 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4087 dsc
->cleanup
= &cleanup_copro_load_store
;
4092 /* Clean up branch instructions (actually perform the branch, by setting
4096 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4097 struct displaced_step_closure
*dsc
)
4099 ULONGEST from
= dsc
->insn_addr
;
4100 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4101 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4102 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4103 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4108 if (dsc
->u
.branch
.link
)
4110 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
4111 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
4114 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
4117 /* Copy B/BL/BLX instructions with immediate destinations. */
4120 copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4121 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4123 unsigned int cond
= bits (insn
, 28, 31);
4124 int exchange
= (cond
== 0xf);
4125 int link
= exchange
|| bit (insn
, 24);
4126 CORE_ADDR from
= dsc
->insn_addr
;
4129 if (debug_displaced
)
4130 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
4131 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
4132 (unsigned long) insn
);
4134 /* Implement "BL<cond> <label>" as:
4136 Preparation: cond <- instruction condition
4137 Insn: mov r0, r0 (nop)
4138 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4140 B<cond> similar, but don't set r14 in cleanup. */
4143 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4144 then arrange the switch into Thumb mode. */
4145 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
4147 offset
= bits (insn
, 0, 23) << 2;
4149 if (bit (offset
, 25))
4150 offset
= offset
| ~0x3ffffff;
4152 dsc
->u
.branch
.cond
= cond
;
4153 dsc
->u
.branch
.link
= link
;
4154 dsc
->u
.branch
.exchange
= exchange
;
4155 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
4157 dsc
->modinsn
[0] = ARM_NOP
;
4159 dsc
->cleanup
= &cleanup_branch
;
4164 /* Copy BX/BLX with register-specified destinations. */
4167 copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4168 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4170 unsigned int cond
= bits (insn
, 28, 31);
4173 int link
= bit (insn
, 5);
4174 unsigned int rm
= bits (insn
, 0, 3);
4175 CORE_ADDR from
= dsc
->insn_addr
;
4177 if (debug_displaced
)
4178 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
4179 "%.8lx\n", (link
) ? "blx" : "bx", (unsigned long) insn
);
4181 /* Implement {BX,BLX}<cond> <reg>" as:
4183 Preparation: cond <- instruction condition
4184 Insn: mov r0, r0 (nop)
4185 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
4187 Don't set r14 in cleanup for BX. */
4189 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
4191 dsc
->u
.branch
.cond
= cond
;
4192 dsc
->u
.branch
.link
= link
;
4193 dsc
->u
.branch
.exchange
= 1;
4195 dsc
->modinsn
[0] = ARM_NOP
;
4197 dsc
->cleanup
= &cleanup_branch
;
4202 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
4205 cleanup_alu_imm (struct gdbarch
*gdbarch
,
4206 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4208 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4209 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4210 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4211 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4215 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4216 struct displaced_step_closure
*dsc
)
4218 unsigned int rn
= bits (insn
, 16, 19);
4219 unsigned int rd
= bits (insn
, 12, 15);
4220 unsigned int op
= bits (insn
, 21, 24);
4221 int is_mov
= (op
== 0xd);
4222 ULONGEST rd_val
, rn_val
;
4223 CORE_ADDR from
= dsc
->insn_addr
;
4225 if (!insn_references_pc (insn
, 0x000ff000ul
))
4226 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
4228 if (debug_displaced
)
4229 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
4230 "%.8lx\n", is_mov
? "move" : "ALU",
4231 (unsigned long) insn
);
4233 /* Instruction is of form:
4235 <op><cond> rd, [rn,] #imm
4239 Preparation: tmp1, tmp2 <- r0, r1;
4241 Insn: <op><cond> r0, r1, #imm
4242 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
4245 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4246 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4247 rn_val
= displaced_read_reg (regs
, from
, rn
);
4248 rd_val
= displaced_read_reg (regs
, from
, rd
);
4249 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4250 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4254 dsc
->modinsn
[0] = insn
& 0xfff00fff;
4256 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
4258 dsc
->cleanup
= &cleanup_alu_imm
;
4263 /* Copy/cleanup arithmetic/logic insns with register RHS. */
4266 cleanup_alu_reg (struct gdbarch
*gdbarch
,
4267 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4272 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4274 for (i
= 0; i
< 3; i
++)
4275 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
4277 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4281 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4282 struct displaced_step_closure
*dsc
)
4284 unsigned int rn
= bits (insn
, 16, 19);
4285 unsigned int rm
= bits (insn
, 0, 3);
4286 unsigned int rd
= bits (insn
, 12, 15);
4287 unsigned int op
= bits (insn
, 21, 24);
4288 int is_mov
= (op
== 0xd);
4289 ULONGEST rd_val
, rn_val
, rm_val
;
4290 CORE_ADDR from
= dsc
->insn_addr
;
4292 if (!insn_references_pc (insn
, 0x000ff00ful
))
4293 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
4295 if (debug_displaced
)
4296 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
4297 is_mov
? "move" : "ALU", (unsigned long) insn
);
4299 /* Instruction is of form:
4301 <op><cond> rd, [rn,] rm [, <shift>]
4305 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
4306 r0, r1, r2 <- rd, rn, rm
4307 Insn: <op><cond> r0, r1, r2 [, <shift>]
4308 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
4311 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4312 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4313 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4314 rd_val
= displaced_read_reg (regs
, from
, rd
);
4315 rn_val
= displaced_read_reg (regs
, from
, rn
);
4316 rm_val
= displaced_read_reg (regs
, from
, rm
);
4317 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4318 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4319 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
4323 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
4325 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
4327 dsc
->cleanup
= &cleanup_alu_reg
;
4332 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
4335 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
4336 struct regcache
*regs
,
4337 struct displaced_step_closure
*dsc
)
4339 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4342 for (i
= 0; i
< 4; i
++)
4343 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
4345 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4349 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4350 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4352 unsigned int rn
= bits (insn
, 16, 19);
4353 unsigned int rm
= bits (insn
, 0, 3);
4354 unsigned int rd
= bits (insn
, 12, 15);
4355 unsigned int rs
= bits (insn
, 8, 11);
4356 unsigned int op
= bits (insn
, 21, 24);
4357 int is_mov
= (op
== 0xd), i
;
4358 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
4359 CORE_ADDR from
= dsc
->insn_addr
;
4361 if (!insn_references_pc (insn
, 0x000fff0ful
))
4362 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
4364 if (debug_displaced
)
4365 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
4366 "%.8lx\n", is_mov
? "move" : "ALU",
4367 (unsigned long) insn
);
4369 /* Instruction is of form:
4371 <op><cond> rd, [rn,] rm, <shift> rs
4375 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
4376 r0, r1, r2, r3 <- rd, rn, rm, rs
4377 Insn: <op><cond> r0, r1, r2, <shift> r3
4379 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
4383 for (i
= 0; i
< 4; i
++)
4384 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4386 rd_val
= displaced_read_reg (regs
, from
, rd
);
4387 rn_val
= displaced_read_reg (regs
, from
, rn
);
4388 rm_val
= displaced_read_reg (regs
, from
, rm
);
4389 rs_val
= displaced_read_reg (regs
, from
, rs
);
4390 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4391 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4392 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
4393 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
4397 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
4399 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
4401 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
4406 /* Clean up load instructions. */
4409 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4410 struct displaced_step_closure
*dsc
)
4412 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
4413 CORE_ADDR from
= dsc
->insn_addr
;
4415 rt_val
= displaced_read_reg (regs
, from
, 0);
4416 if (dsc
->u
.ldst
.xfersize
== 8)
4417 rt_val2
= displaced_read_reg (regs
, from
, 1);
4418 rn_val
= displaced_read_reg (regs
, from
, 2);
4420 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4421 if (dsc
->u
.ldst
.xfersize
> 4)
4422 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4423 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
4424 if (!dsc
->u
.ldst
.immed
)
4425 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
4427 /* Handle register writeback. */
4428 if (dsc
->u
.ldst
.writeback
)
4429 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
4430 /* Put result in right place. */
4431 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
4432 if (dsc
->u
.ldst
.xfersize
== 8)
4433 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
4436 /* Clean up store instructions. */
4439 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4440 struct displaced_step_closure
*dsc
)
4442 CORE_ADDR from
= dsc
->insn_addr
;
4443 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
4445 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4446 if (dsc
->u
.ldst
.xfersize
> 4)
4447 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4448 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
4449 if (!dsc
->u
.ldst
.immed
)
4450 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
4451 if (!dsc
->u
.ldst
.restore_r4
)
4452 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
4455 if (dsc
->u
.ldst
.writeback
)
4456 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
4459 /* Copy "extra" load/store instructions. These are halfword/doubleword
4460 transfers, which have a different encoding to byte/word transfers. */
4463 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
4464 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4466 unsigned int op1
= bits (insn
, 20, 24);
4467 unsigned int op2
= bits (insn
, 5, 6);
4468 unsigned int rt
= bits (insn
, 12, 15);
4469 unsigned int rn
= bits (insn
, 16, 19);
4470 unsigned int rm
= bits (insn
, 0, 3);
4471 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
4472 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
4473 int immed
= (op1
& 0x4) != 0;
4475 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
4476 CORE_ADDR from
= dsc
->insn_addr
;
4478 if (!insn_references_pc (insn
, 0x000ff00ful
))
4479 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
4481 if (debug_displaced
)
4482 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
4483 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
4484 (unsigned long) insn
);
4486 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
4489 internal_error (__FILE__
, __LINE__
,
4490 _("copy_extra_ld_st: instruction decode error"));
4492 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4493 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4494 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4496 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
4498 rt_val
= displaced_read_reg (regs
, from
, rt
);
4499 if (bytesize
[opcode
] == 8)
4500 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
4501 rn_val
= displaced_read_reg (regs
, from
, rn
);
4503 rm_val
= displaced_read_reg (regs
, from
, rm
);
4505 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4506 if (bytesize
[opcode
] == 8)
4507 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
4508 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4510 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4513 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
4514 dsc
->u
.ldst
.rn
= rn
;
4515 dsc
->u
.ldst
.immed
= immed
;
4516 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4517 dsc
->u
.ldst
.restore_r4
= 0;
4520 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
4522 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
4523 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4525 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
4527 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
4528 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4530 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
4535 /* Copy byte/word loads and stores. */
4538 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
4539 struct regcache
*regs
,
4540 struct displaced_step_closure
*dsc
, int load
, int byte
,
4543 int immed
= !bit (insn
, 25);
4544 unsigned int rt
= bits (insn
, 12, 15);
4545 unsigned int rn
= bits (insn
, 16, 19);
4546 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
4547 ULONGEST rt_val
, rn_val
, rm_val
= 0;
4548 CORE_ADDR from
= dsc
->insn_addr
;
4550 if (!insn_references_pc (insn
, 0x000ff00ful
))
4551 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
4553 if (debug_displaced
)
4554 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
4555 load
? (byte
? "ldrb" : "ldr")
4556 : (byte
? "strb" : "str"), usermode
? "t" : "",
4557 (unsigned long) insn
);
4559 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4560 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4562 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
4564 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
4566 rt_val
= displaced_read_reg (regs
, from
, rt
);
4567 rn_val
= displaced_read_reg (regs
, from
, rn
);
4569 rm_val
= displaced_read_reg (regs
, from
, rm
);
4571 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4572 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4574 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4577 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
4578 dsc
->u
.ldst
.rn
= rn
;
4579 dsc
->u
.ldst
.immed
= immed
;
4580 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4582 /* To write PC we can do:
4584 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
4585 scratch+4: ldr r4, temp
4586 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
4587 scratch+12: add r4, r4, #8 (r4 = offset)
4588 scratch+16: add r0, r0, r4
4589 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
4592 Otherwise we don't know what value to write for PC, since the offset is
4593 architecture-dependent (sometimes PC+8, sometimes PC+12). */
4595 if (load
|| rt
!= 15)
4597 dsc
->u
.ldst
.restore_r4
= 0;
4600 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
4602 {ldr,str}[b]<cond> r0, [r2, #imm]. */
4603 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4605 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
4607 {ldr,str}[b]<cond> r0, [r2, r3]. */
4608 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4612 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
4613 dsc
->u
.ldst
.restore_r4
= 1;
4615 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
4616 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
4617 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
4618 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
4619 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
4623 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
4625 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
4627 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
4628 dsc
->modinsn
[7] = 0x0; /* scratch space. */
4633 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
4638 /* Cleanup LDM instructions with fully-populated register list. This is an
4639 unfortunate corner case: it's impossible to implement correctly by modifying
4640 the instruction. The issue is as follows: we have an instruction,
4644 which we must rewrite to avoid loading PC. A possible solution would be to
4645 do the load in two halves, something like (with suitable cleanup
4649 ldm[id][ab] r8!, {r0-r7}
4651 ldm[id][ab] r8, {r7-r14}
4654 but at present there's no suitable place for <temp>, since the scratch space
4655 is overwritten before the cleanup routine is called. For now, we simply
4656 emulate the instruction. */
4659 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4660 struct displaced_step_closure
*dsc
)
4662 ULONGEST from
= dsc
->insn_addr
;
4663 int inc
= dsc
->u
.block
.increment
;
4664 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
4665 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
4666 uint32_t regmask
= dsc
->u
.block
.regmask
;
4667 int regno
= inc
? 0 : 15;
4668 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
4669 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
4670 && (regmask
& 0x8000) != 0;
4671 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4672 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
4673 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4678 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
4679 sensible we can do here. Complain loudly. */
4680 if (exception_return
)
4681 error (_("Cannot single-step exception return"));
4683 /* We don't handle any stores here for now. */
4684 gdb_assert (dsc
->u
.block
.load
!= 0);
4686 if (debug_displaced
)
4687 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
4688 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
4689 dsc
->u
.block
.increment
? "inc" : "dec",
4690 dsc
->u
.block
.before
? "before" : "after");
4697 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
4700 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
4703 xfer_addr
+= bump_before
;
4705 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
4706 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
4708 xfer_addr
+= bump_after
;
4710 regmask
&= ~(1 << regno
);
4713 if (dsc
->u
.block
.writeback
)
4714 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
4718 /* Clean up an STM which included the PC in the register list. */
4721 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4722 struct displaced_step_closure
*dsc
)
4724 ULONGEST from
= dsc
->insn_addr
;
4725 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4726 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
4727 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
4728 CORE_ADDR stm_insn_addr
;
4731 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4733 /* If condition code fails, there's nothing else to do. */
4734 if (!store_executed
)
4737 if (dsc
->u
.block
.increment
)
4739 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
4741 if (dsc
->u
.block
.before
)
4746 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
4748 if (dsc
->u
.block
.before
)
4752 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
4753 stm_insn_addr
= dsc
->scratch_base
;
4754 offset
= pc_val
- stm_insn_addr
;
4756 if (debug_displaced
)
4757 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
4758 "STM instruction\n", offset
);
4760 /* Rewrite the stored PC to the proper value for the non-displaced original
4762 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
4763 dsc
->insn_addr
+ offset
);
4766 /* Clean up an LDM which includes the PC in the register list. We clumped all
4767 the registers in the transferred list into a contiguous range r0...rX (to
4768 avoid loading PC directly and losing control of the debugged program), so we
4769 must undo that here. */
4772 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
4773 struct regcache
*regs
,
4774 struct displaced_step_closure
*dsc
)
4776 ULONGEST from
= dsc
->insn_addr
;
4777 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4778 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
4779 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
4780 unsigned int regs_loaded
= bitcount (mask
);
4781 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
4783 /* The method employed here will fail if the register list is fully populated
4784 (we need to avoid loading PC directly). */
4785 gdb_assert (num_to_shuffle
< 16);
4790 clobbered
= (1 << num_to_shuffle
) - 1;
4792 while (num_to_shuffle
> 0)
4794 if ((mask
& (1 << write_reg
)) != 0)
4796 unsigned int read_reg
= num_to_shuffle
- 1;
4798 if (read_reg
!= write_reg
)
4800 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
4801 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
4802 if (debug_displaced
)
4803 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
4804 "loaded register r%d to r%d\n"), read_reg
,
4807 else if (debug_displaced
)
4808 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
4809 "r%d already in the right place\n"),
4812 clobbered
&= ~(1 << write_reg
);
4820 /* Restore any registers we scribbled over. */
4821 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
4823 if ((clobbered
& (1 << write_reg
)) != 0)
4825 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
4827 if (debug_displaced
)
4828 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
4829 "clobbered register r%d\n"), write_reg
);
4830 clobbered
&= ~(1 << write_reg
);
4834 /* Perform register writeback manually. */
4835 if (dsc
->u
.block
.writeback
)
4837 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
4839 if (dsc
->u
.block
.increment
)
4840 new_rn_val
+= regs_loaded
* 4;
4842 new_rn_val
-= regs_loaded
* 4;
4844 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
4849 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
4850 in user-level code (in particular exception return, ldm rn, {...pc}^). */
4853 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4854 struct displaced_step_closure
*dsc
)
4856 int load
= bit (insn
, 20);
4857 int user
= bit (insn
, 22);
4858 int increment
= bit (insn
, 23);
4859 int before
= bit (insn
, 24);
4860 int writeback
= bit (insn
, 21);
4861 int rn
= bits (insn
, 16, 19);
4862 CORE_ADDR from
= dsc
->insn_addr
;
4864 /* Block transfers which don't mention PC can be run directly out-of-line. */
4865 if (rn
!= 15 && (insn
& 0x8000) == 0)
4866 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
4870 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
4871 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
4874 if (debug_displaced
)
4875 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
4876 "%.8lx\n", (unsigned long) insn
);
4878 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
4879 dsc
->u
.block
.rn
= rn
;
4881 dsc
->u
.block
.load
= load
;
4882 dsc
->u
.block
.user
= user
;
4883 dsc
->u
.block
.increment
= increment
;
4884 dsc
->u
.block
.before
= before
;
4885 dsc
->u
.block
.writeback
= writeback
;
4886 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
4888 dsc
->u
.block
.regmask
= insn
& 0xffff;
4892 if ((insn
& 0xffff) == 0xffff)
4894 /* LDM with a fully-populated register list. This case is
4895 particularly tricky. Implement for now by fully emulating the
4896 instruction (which might not behave perfectly in all cases, but
4897 these instructions should be rare enough for that not to matter
4899 dsc
->modinsn
[0] = ARM_NOP
;
4901 dsc
->cleanup
= &cleanup_block_load_all
;
4905 /* LDM of a list of registers which includes PC. Implement by
4906 rewriting the list of registers to be transferred into a
4907 contiguous chunk r0...rX before doing the transfer, then shuffling
4908 registers into the correct places in the cleanup routine. */
4909 unsigned int regmask
= insn
& 0xffff;
4910 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
4911 unsigned int to
= 0, from
= 0, i
, new_rn
;
4913 for (i
= 0; i
< num_in_list
; i
++)
4914 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4916 /* Writeback makes things complicated. We need to avoid clobbering
4917 the base register with one of the registers in our modified
4918 register list, but just using a different register can't work in
4921 ldm r14!, {r0-r13,pc}
4923 which would need to be rewritten as:
4927 but that can't work, because there's no free register for N.
4929 Solve this by turning off the writeback bit, and emulating
4930 writeback manually in the cleanup routine. */
4935 new_regmask
= (1 << num_in_list
) - 1;
4937 if (debug_displaced
)
4938 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
4939 "{..., pc}: original reg list %.4x, modified "
4940 "list %.4x\n"), rn
, writeback
? "!" : "",
4941 (int) insn
& 0xffff, new_regmask
);
4943 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
4945 dsc
->cleanup
= &cleanup_block_load_pc
;
4950 /* STM of a list of registers which includes PC. Run the instruction
4951 as-is, but out of line: this will store the wrong value for the PC,
4952 so we must manually fix up the memory in the cleanup routine.
4953 Doing things this way has the advantage that we can auto-detect
4954 the offset of the PC write (which is architecture-dependent) in
4955 the cleanup routine. */
4956 dsc
->modinsn
[0] = insn
;
4958 dsc
->cleanup
= &cleanup_block_store_pc
;
4964 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
4965 for Linux, where some SVC instructions must be treated specially. */
4968 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4969 struct displaced_step_closure
*dsc
)
4971 CORE_ADDR from
= dsc
->insn_addr
;
4972 CORE_ADDR resume_addr
= from
+ 4;
4974 if (debug_displaced
)
4975 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
4976 "%.8lx\n", (unsigned long) resume_addr
);
4978 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
4982 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4983 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4985 CORE_ADDR from
= dsc
->insn_addr
;
4987 /* Allow OS-specific code to override SVC handling. */
4988 if (dsc
->u
.svc
.copy_svc_os
)
4989 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
4991 if (debug_displaced
)
4992 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
4993 (unsigned long) insn
);
4995 /* Preparation: none.
4996 Insn: unmodified svc.
4997 Cleanup: pc <- insn_addr + 4. */
4999 dsc
->modinsn
[0] = insn
;
5001 dsc
->cleanup
= &cleanup_svc
;
5002 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
5004 dsc
->wrote_to_pc
= 1;
5009 /* Copy undefined instructions. */
5012 copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
5013 struct displaced_step_closure
*dsc
)
5015 if (debug_displaced
)
5016 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn %.8lx\n",
5017 (unsigned long) insn
);
5019 dsc
->modinsn
[0] = insn
;
5024 /* Copy unpredictable instructions. */
5027 copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
5028 struct displaced_step_closure
*dsc
)
5030 if (debug_displaced
)
5031 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
5032 "%.8lx\n", (unsigned long) insn
);
5034 dsc
->modinsn
[0] = insn
;
5039 /* The decode_* functions are instruction decoding helpers. They mostly follow
5040 the presentation in the ARM ARM. */
5043 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
5044 struct regcache
*regs
,
5045 struct displaced_step_closure
*dsc
)
5047 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
5048 unsigned int rn
= bits (insn
, 16, 19);
5050 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
5051 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
5052 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
5053 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
5054 else if ((op1
& 0x60) == 0x20)
5055 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
5056 else if ((op1
& 0x71) == 0x40)
5057 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
5058 else if ((op1
& 0x77) == 0x41)
5059 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
5060 else if ((op1
& 0x77) == 0x45)
5061 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
5062 else if ((op1
& 0x77) == 0x51)
5065 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
5067 return copy_unpred (gdbarch
, insn
, dsc
);
5069 else if ((op1
& 0x77) == 0x55)
5070 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
5071 else if (op1
== 0x57)
5074 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
5075 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
5076 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
5077 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
5078 default: return copy_unpred (gdbarch
, insn
, dsc
);
5080 else if ((op1
& 0x63) == 0x43)
5081 return copy_unpred (gdbarch
, insn
, dsc
);
5082 else if ((op2
& 0x1) == 0x0)
5083 switch (op1
& ~0x80)
5086 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
5088 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
5089 case 0x71: case 0x75:
5091 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
5092 case 0x63: case 0x67: case 0x73: case 0x77:
5093 return copy_unpred (gdbarch
, insn
, dsc
);
5095 return copy_undef (gdbarch
, insn
, dsc
);
5098 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
5102 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
5103 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5105 if (bit (insn
, 27) == 0)
5106 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
5107 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
5108 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
5111 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
5114 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
5116 case 0x4: case 0x5: case 0x6: case 0x7:
5117 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
5120 switch ((insn
& 0xe00000) >> 21)
5122 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
5124 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5127 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
5130 return copy_undef (gdbarch
, insn
, dsc
);
5135 int rn_f
= (bits (insn
, 16, 19) == 0xf);
5136 switch ((insn
& 0xe00000) >> 21)
5139 /* ldc/ldc2 imm (undefined for rn == pc). */
5140 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
5141 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5144 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
5146 case 0x4: case 0x5: case 0x6: case 0x7:
5147 /* ldc/ldc2 lit (undefined for rn != pc). */
5148 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
5149 : copy_undef (gdbarch
, insn
, dsc
);
5152 return copy_undef (gdbarch
, insn
, dsc
);
5157 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
5160 if (bits (insn
, 16, 19) == 0xf)
5162 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5164 return copy_undef (gdbarch
, insn
, dsc
);
5168 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
5170 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
5174 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
5176 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
5179 return copy_undef (gdbarch
, insn
, dsc
);
5183 /* Decode miscellaneous instructions in dp/misc encoding space. */
5186 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
5187 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5189 unsigned int op2
= bits (insn
, 4, 6);
5190 unsigned int op
= bits (insn
, 21, 22);
5191 unsigned int op1
= bits (insn
, 16, 19);
5196 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
5199 if (op
== 0x1) /* bx. */
5200 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
5202 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
5204 return copy_undef (gdbarch
, insn
, dsc
);
5208 /* Not really supported. */
5209 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
5211 return copy_undef (gdbarch
, insn
, dsc
);
5215 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
); /* blx register. */
5217 return copy_undef (gdbarch
, insn
, dsc
);
5220 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
5224 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
5226 /* Not really supported. */
5227 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
5230 return copy_undef (gdbarch
, insn
, dsc
);
5235 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5236 struct displaced_step_closure
*dsc
)
5239 switch (bits (insn
, 20, 24))
5242 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
5245 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
5247 case 0x12: case 0x16:
5248 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
5251 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
5255 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
5257 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
5258 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
5259 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
5260 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
5261 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
5262 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
5263 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
5264 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
5265 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
5266 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
5267 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
5268 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
5269 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
5270 /* 2nd arg means "unpriveleged". */
5271 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
5275 /* Should be unreachable. */
5280 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
5281 struct regcache
*regs
,
5282 struct displaced_step_closure
*dsc
)
5284 int a
= bit (insn
, 25), b
= bit (insn
, 4);
5285 uint32_t op1
= bits (insn
, 20, 24);
5286 int rn_f
= bits (insn
, 16, 19) == 0xf;
5288 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
5289 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
5290 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
5291 else if ((!a
&& (op1
& 0x17) == 0x02)
5292 || (a
&& (op1
& 0x17) == 0x02 && !b
))
5293 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
5294 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
5295 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
5296 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
5297 else if ((!a
&& (op1
& 0x17) == 0x03)
5298 || (a
&& (op1
& 0x17) == 0x03 && !b
))
5299 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
5300 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
5301 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
5302 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
5303 else if ((!a
&& (op1
& 0x17) == 0x06)
5304 || (a
&& (op1
& 0x17) == 0x06 && !b
))
5305 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
5306 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
5307 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
5308 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
5309 else if ((!a
&& (op1
& 0x17) == 0x07)
5310 || (a
&& (op1
& 0x17) == 0x07 && !b
))
5311 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
5313 /* Should be unreachable. */
5318 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
5319 struct displaced_step_closure
*dsc
)
5321 switch (bits (insn
, 20, 24))
5323 case 0x00: case 0x01: case 0x02: case 0x03:
5324 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
5326 case 0x04: case 0x05: case 0x06: case 0x07:
5327 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
5329 case 0x08: case 0x09: case 0x0a: case 0x0b:
5330 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5331 return copy_unmodified (gdbarch
, insn
,
5332 "decode/pack/unpack/saturate/reverse", dsc
);
5335 if (bits (insn
, 5, 7) == 0) /* op2. */
5337 if (bits (insn
, 12, 15) == 0xf)
5338 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
5340 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
5343 return copy_undef (gdbarch
, insn
, dsc
);
5345 case 0x1a: case 0x1b:
5346 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
5347 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
5349 return copy_undef (gdbarch
, insn
, dsc
);
5351 case 0x1c: case 0x1d:
5352 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
5354 if (bits (insn
, 0, 3) == 0xf)
5355 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
5357 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
5360 return copy_undef (gdbarch
, insn
, dsc
);
5362 case 0x1e: case 0x1f:
5363 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
5364 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
5366 return copy_undef (gdbarch
, insn
, dsc
);
5369 /* Should be unreachable. */
5374 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
5375 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5378 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
5380 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
5384 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
5385 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5387 unsigned int opcode
= bits (insn
, 20, 24);
5391 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
5392 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
5394 case 0x08: case 0x0a: case 0x0c: case 0x0e:
5395 case 0x12: case 0x16:
5396 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
5398 case 0x09: case 0x0b: case 0x0d: case 0x0f:
5399 case 0x13: case 0x17:
5400 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
5402 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
5403 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
5404 /* Note: no writeback for these instructions. Bit 25 will always be
5405 zero though (via caller), so the following works OK. */
5406 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5409 /* Should be unreachable. */
5414 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
5415 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5417 unsigned int op1
= bits (insn
, 20, 25);
5418 int op
= bit (insn
, 4);
5419 unsigned int coproc
= bits (insn
, 8, 11);
5420 unsigned int rn
= bits (insn
, 16, 19);
5422 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
5423 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
5424 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
5425 && (coproc
& 0xe) != 0xa)
5427 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5428 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
5429 && (coproc
& 0xe) != 0xa)
5430 /* ldc/ldc2 imm/lit. */
5431 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5432 else if ((op1
& 0x3e) == 0x00)
5433 return copy_undef (gdbarch
, insn
, dsc
);
5434 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
5435 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
5436 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
5437 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
5438 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
5439 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
5440 else if ((op1
& 0x30) == 0x20 && !op
)
5442 if ((coproc
& 0xe) == 0xa)
5443 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
5445 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
5447 else if ((op1
& 0x30) == 0x20 && op
)
5448 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
5449 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
5450 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
5451 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
5452 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
5453 else if ((op1
& 0x30) == 0x30)
5454 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
5456 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
5460 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
5461 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
,
5462 struct displaced_step_closure
*dsc
)
5466 if (!displaced_in_arm_mode (regs
))
5467 error (_("Displaced stepping is only supported in ARM mode"));
5469 /* Most displaced instructions use a 1-instruction scratch space, so set this
5470 here and override below if/when necessary. */
5472 dsc
->insn_addr
= from
;
5473 dsc
->scratch_base
= to
;
5474 dsc
->cleanup
= NULL
;
5475 dsc
->wrote_to_pc
= 0;
5477 if ((insn
& 0xf0000000) == 0xf0000000)
5478 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
5479 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
5481 case 0x0: case 0x1: case 0x2: case 0x3:
5482 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
5485 case 0x4: case 0x5: case 0x6:
5486 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
5490 err
= decode_media (gdbarch
, insn
, dsc
);
5493 case 0x8: case 0x9: case 0xa: case 0xb:
5494 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
5497 case 0xc: case 0xd: case 0xe: case 0xf:
5498 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
5503 internal_error (__FILE__
, __LINE__
,
5504 _("arm_process_displaced_insn: Instruction decode error"));
5507 /* Actually set up the scratch space for a displaced instruction. */
5510 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
5511 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
5513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5515 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5517 /* Poke modified instruction(s). */
5518 for (i
= 0; i
< dsc
->numinsns
; i
++)
5520 if (debug_displaced
)
5521 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
5522 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
5523 (unsigned long) to
+ i
* 4);
5524 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
5528 /* Put breakpoint afterwards. */
5529 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
5530 tdep
->arm_breakpoint_size
);
5532 if (debug_displaced
)
5533 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
5534 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
5537 /* Entry point for copying an instruction into scratch space for displaced
5540 struct displaced_step_closure
*
5541 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
5542 CORE_ADDR from
, CORE_ADDR to
,
5543 struct regcache
*regs
)
5545 struct displaced_step_closure
*dsc
5546 = xmalloc (sizeof (struct displaced_step_closure
));
5547 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5548 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
5550 if (debug_displaced
)
5551 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
5552 "at %.8lx\n", (unsigned long) insn
,
5553 (unsigned long) from
);
5555 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
5556 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
5561 /* Entry point for cleaning things up after a displaced instruction has been
5565 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
5566 struct displaced_step_closure
*dsc
,
5567 CORE_ADDR from
, CORE_ADDR to
,
5568 struct regcache
*regs
)
5571 dsc
->cleanup (gdbarch
, regs
, dsc
);
5573 if (!dsc
->wrote_to_pc
)
5574 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
5577 #include "bfd-in2.h"
5578 #include "libcoff.h"
5581 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
5583 struct gdbarch
*gdbarch
= info
->application_data
;
5585 if (arm_pc_is_thumb (gdbarch
, memaddr
))
5587 static asymbol
*asym
;
5588 static combined_entry_type ce
;
5589 static struct coff_symbol_struct csym
;
5590 static struct bfd fake_bfd
;
5591 static bfd_target fake_target
;
5593 if (csym
.native
== NULL
)
5595 /* Create a fake symbol vector containing a Thumb symbol.
5596 This is solely so that the code in print_insn_little_arm()
5597 and print_insn_big_arm() in opcodes/arm-dis.c will detect
5598 the presence of a Thumb symbol and switch to decoding
5599 Thumb instructions. */
5601 fake_target
.flavour
= bfd_target_coff_flavour
;
5602 fake_bfd
.xvec
= &fake_target
;
5603 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
5605 csym
.symbol
.the_bfd
= &fake_bfd
;
5606 csym
.symbol
.name
= "fake";
5607 asym
= (asymbol
*) & csym
;
5610 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
5611 info
->symbols
= &asym
;
5614 info
->symbols
= NULL
;
5616 if (info
->endian
== BFD_ENDIAN_BIG
)
5617 return print_insn_big_arm (memaddr
, info
);
5619 return print_insn_little_arm (memaddr
, info
);
5622 /* The following define instruction sequences that will cause ARM
5623 cpu's to take an undefined instruction trap. These are used to
5624 signal a breakpoint to GDB.
5626 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
5627 modes. A different instruction is required for each mode. The ARM
5628 cpu's can also be big or little endian. Thus four different
5629 instructions are needed to support all cases.
5631 Note: ARMv4 defines several new instructions that will take the
5632 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
5633 not in fact add the new instructions. The new undefined
5634 instructions in ARMv4 are all instructions that had no defined
5635 behaviour in earlier chips. There is no guarantee that they will
5636 raise an exception, but may be treated as NOP's. In practice, it
5637 may only safe to rely on instructions matching:
5639 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
5640 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
5641 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
5643 Even this may only true if the condition predicate is true. The
5644 following use a condition predicate of ALWAYS so it is always TRUE.
5646 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
5647 and NetBSD all use a software interrupt rather than an undefined
5648 instruction to force a trap. This can be handled by by the
5649 abi-specific code during establishment of the gdbarch vector. */
5651 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
5652 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
5653 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
5654 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
5656 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
5657 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
5658 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
5659 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
5661 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
5662 the program counter value to determine whether a 16-bit or 32-bit
5663 breakpoint should be used. It returns a pointer to a string of
5664 bytes that encode a breakpoint instruction, stores the length of
5665 the string to *lenptr, and adjusts the program counter (if
5666 necessary) to point to the actual memory location where the
5667 breakpoint should be inserted. */
5669 static const unsigned char *
5670 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5672 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5673 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5675 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
5677 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
5679 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
5680 check whether we are replacing a 32-bit instruction. */
5681 if (tdep
->thumb2_breakpoint
!= NULL
)
5684 if (target_read_memory (*pcptr
, buf
, 2) == 0)
5686 unsigned short inst1
;
5687 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
5688 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
5690 *lenptr
= tdep
->thumb2_breakpoint_size
;
5691 return tdep
->thumb2_breakpoint
;
5696 *lenptr
= tdep
->thumb_breakpoint_size
;
5697 return tdep
->thumb_breakpoint
;
5701 *lenptr
= tdep
->arm_breakpoint_size
;
5702 return tdep
->arm_breakpoint
;
5707 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
5710 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5712 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
5714 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
5715 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
5716 that this is not confused with a 32-bit ARM breakpoint. */
5720 /* Extract from an array REGBUF containing the (raw) register state a
5721 function return value of type TYPE, and copy that, in virtual
5722 format, into VALBUF. */
5725 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
5728 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5729 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5731 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
5733 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5737 /* The value is in register F0 in internal format. We need to
5738 extract the raw value and then convert it to the desired
5740 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
5742 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
5743 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
5744 valbuf
, gdbarch_byte_order (gdbarch
));
5748 case ARM_FLOAT_SOFT_FPA
:
5749 case ARM_FLOAT_SOFT_VFP
:
5750 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5751 not using the VFP ABI code. */
5753 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
5754 if (TYPE_LENGTH (type
) > 4)
5755 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
5756 valbuf
+ INT_REGISTER_SIZE
);
5761 (__FILE__
, __LINE__
,
5762 _("arm_extract_return_value: Floating point model not supported"));
5766 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5767 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5768 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5769 || TYPE_CODE (type
) == TYPE_CODE_PTR
5770 || TYPE_CODE (type
) == TYPE_CODE_REF
5771 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5773 /* If the the type is a plain integer, then the access is
5774 straight-forward. Otherwise we have to play around a bit more. */
5775 int len
= TYPE_LENGTH (type
);
5776 int regno
= ARM_A1_REGNUM
;
5781 /* By using store_unsigned_integer we avoid having to do
5782 anything special for small big-endian values. */
5783 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
5784 store_unsigned_integer (valbuf
,
5785 (len
> INT_REGISTER_SIZE
5786 ? INT_REGISTER_SIZE
: len
),
5788 len
-= INT_REGISTER_SIZE
;
5789 valbuf
+= INT_REGISTER_SIZE
;
5794 /* For a structure or union the behaviour is as if the value had
5795 been stored to word-aligned memory and then loaded into
5796 registers with 32-bit load instruction(s). */
5797 int len
= TYPE_LENGTH (type
);
5798 int regno
= ARM_A1_REGNUM
;
5799 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5803 regcache_cooked_read (regs
, regno
++, tmpbuf
);
5804 memcpy (valbuf
, tmpbuf
,
5805 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5806 len
-= INT_REGISTER_SIZE
;
5807 valbuf
+= INT_REGISTER_SIZE
;
5813 /* Will a function return an aggregate type in memory or in a
5814 register? Return 0 if an aggregate type can be returned in a
5815 register, 1 if it must be returned in memory. */
5818 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
5821 enum type_code code
;
5823 CHECK_TYPEDEF (type
);
5825 /* In the ARM ABI, "integer" like aggregate types are returned in
5826 registers. For an aggregate type to be integer like, its size
5827 must be less than or equal to INT_REGISTER_SIZE and the
5828 offset of each addressable subfield must be zero. Note that bit
5829 fields are not addressable, and all addressable subfields of
5830 unions always start at offset zero.
5832 This function is based on the behaviour of GCC 2.95.1.
5833 See: gcc/arm.c: arm_return_in_memory() for details.
5835 Note: All versions of GCC before GCC 2.95.2 do not set up the
5836 parameters correctly for a function returning the following
5837 structure: struct { float f;}; This should be returned in memory,
5838 not a register. Richard Earnshaw sent me a patch, but I do not
5839 know of any way to detect if a function like the above has been
5840 compiled with the correct calling convention. */
5842 /* All aggregate types that won't fit in a register must be returned
5844 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
5849 /* The AAPCS says all aggregates not larger than a word are returned
5851 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
5854 /* The only aggregate types that can be returned in a register are
5855 structs and unions. Arrays must be returned in memory. */
5856 code
= TYPE_CODE (type
);
5857 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
5862 /* Assume all other aggregate types can be returned in a register.
5863 Run a check for structures, unions and arrays. */
5866 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
5869 /* Need to check if this struct/union is "integer" like. For
5870 this to be true, its size must be less than or equal to
5871 INT_REGISTER_SIZE and the offset of each addressable
5872 subfield must be zero. Note that bit fields are not
5873 addressable, and unions always start at offset zero. If any
5874 of the subfields is a floating point type, the struct/union
5875 cannot be an integer type. */
5877 /* For each field in the object, check:
5878 1) Is it FP? --> yes, nRc = 1;
5879 2) Is it addressable (bitpos != 0) and
5880 not packed (bitsize == 0)?
5884 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
5886 enum type_code field_type_code
;
5887 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
5889 /* Is it a floating point type field? */
5890 if (field_type_code
== TYPE_CODE_FLT
)
5896 /* If bitpos != 0, then we have to care about it. */
5897 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
5899 /* Bitfields are not addressable. If the field bitsize is
5900 zero, then the field is not packed. Hence it cannot be
5901 a bitfield or any other packed type. */
5902 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
5914 /* Write into appropriate registers a function return value of type
5915 TYPE, given in virtual format. */
5918 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
5919 const gdb_byte
*valbuf
)
5921 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5922 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5924 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
5926 char buf
[MAX_REGISTER_SIZE
];
5928 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5932 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
5933 gdbarch_byte_order (gdbarch
));
5934 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
5937 case ARM_FLOAT_SOFT_FPA
:
5938 case ARM_FLOAT_SOFT_VFP
:
5939 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5940 not using the VFP ABI code. */
5942 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
5943 if (TYPE_LENGTH (type
) > 4)
5944 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
5945 valbuf
+ INT_REGISTER_SIZE
);
5950 (__FILE__
, __LINE__
,
5951 _("arm_store_return_value: Floating point model not supported"));
5955 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5956 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5957 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5958 || TYPE_CODE (type
) == TYPE_CODE_PTR
5959 || TYPE_CODE (type
) == TYPE_CODE_REF
5960 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5962 if (TYPE_LENGTH (type
) <= 4)
5964 /* Values of one word or less are zero/sign-extended and
5966 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5967 LONGEST val
= unpack_long (type
, valbuf
);
5969 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
5970 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
5974 /* Integral values greater than one word are stored in consecutive
5975 registers starting with r0. This will always be a multiple of
5976 the regiser size. */
5977 int len
= TYPE_LENGTH (type
);
5978 int regno
= ARM_A1_REGNUM
;
5982 regcache_cooked_write (regs
, regno
++, valbuf
);
5983 len
-= INT_REGISTER_SIZE
;
5984 valbuf
+= INT_REGISTER_SIZE
;
5990 /* For a structure or union the behaviour is as if the value had
5991 been stored to word-aligned memory and then loaded into
5992 registers with 32-bit load instruction(s). */
5993 int len
= TYPE_LENGTH (type
);
5994 int regno
= ARM_A1_REGNUM
;
5995 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5999 memcpy (tmpbuf
, valbuf
,
6000 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
6001 regcache_cooked_write (regs
, regno
++, tmpbuf
);
6002 len
-= INT_REGISTER_SIZE
;
6003 valbuf
+= INT_REGISTER_SIZE
;
6009 /* Handle function return values. */
6011 static enum return_value_convention
6012 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
6013 struct type
*valtype
, struct regcache
*regcache
,
6014 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6017 enum arm_vfp_cprc_base_type vfp_base_type
;
6020 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
6021 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
6023 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
6024 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
6026 for (i
= 0; i
< vfp_base_count
; i
++)
6028 if (reg_char
== 'q')
6031 arm_neon_quad_write (gdbarch
, regcache
, i
,
6032 writebuf
+ i
* unit_length
);
6035 arm_neon_quad_read (gdbarch
, regcache
, i
,
6036 readbuf
+ i
* unit_length
);
6043 sprintf (name_buf
, "%c%d", reg_char
, i
);
6044 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6047 regcache_cooked_write (regcache
, regnum
,
6048 writebuf
+ i
* unit_length
);
6050 regcache_cooked_read (regcache
, regnum
,
6051 readbuf
+ i
* unit_length
);
6054 return RETURN_VALUE_REGISTER_CONVENTION
;
6057 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
6058 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
6059 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
6061 if (tdep
->struct_return
== pcc_struct_return
6062 || arm_return_in_memory (gdbarch
, valtype
))
6063 return RETURN_VALUE_STRUCT_CONVENTION
;
6067 arm_store_return_value (valtype
, regcache
, writebuf
);
6070 arm_extract_return_value (valtype
, regcache
, readbuf
);
6072 return RETURN_VALUE_REGISTER_CONVENTION
;
6077 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
6079 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6080 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6081 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6083 char buf
[INT_REGISTER_SIZE
];
6085 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
6087 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
6091 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
6095 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
6096 return the target PC. Otherwise return 0. */
6099 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
6103 CORE_ADDR start_addr
;
6105 /* Find the starting address and name of the function containing the PC. */
6106 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
6109 /* If PC is in a Thumb call or return stub, return the address of the
6110 target PC, which is in a register. The thunk functions are called
6111 _call_via_xx, where x is the register name. The possible names
6112 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
6113 functions, named __ARM_call_via_r[0-7]. */
6114 if (strncmp (name
, "_call_via_", 10) == 0
6115 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
6117 /* Use the name suffix to determine which register contains the
6119 static char *table
[15] =
6120 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6121 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
6124 int offset
= strlen (name
) - 2;
6126 for (regno
= 0; regno
<= 14; regno
++)
6127 if (strcmp (&name
[offset
], table
[regno
]) == 0)
6128 return get_frame_register_unsigned (frame
, regno
);
6131 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
6132 non-interworking calls to foo. We could decode the stubs
6133 to find the target but it's easier to use the symbol table. */
6134 namelen
= strlen (name
);
6135 if (name
[0] == '_' && name
[1] == '_'
6136 && ((namelen
> 2 + strlen ("_from_thumb")
6137 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
6138 strlen ("_from_thumb")) == 0)
6139 || (namelen
> 2 + strlen ("_from_arm")
6140 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
6141 strlen ("_from_arm")) == 0)))
6144 int target_len
= namelen
- 2;
6145 struct minimal_symbol
*minsym
;
6146 struct objfile
*objfile
;
6147 struct obj_section
*sec
;
6149 if (name
[namelen
- 1] == 'b')
6150 target_len
-= strlen ("_from_thumb");
6152 target_len
-= strlen ("_from_arm");
6154 target_name
= alloca (target_len
+ 1);
6155 memcpy (target_name
, name
+ 2, target_len
);
6156 target_name
[target_len
] = '\0';
6158 sec
= find_pc_section (pc
);
6159 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
6160 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
6162 return SYMBOL_VALUE_ADDRESS (minsym
);
6167 return 0; /* not a stub */
6171 set_arm_command (char *args
, int from_tty
)
6173 printf_unfiltered (_("\
6174 \"set arm\" must be followed by an apporpriate subcommand.\n"));
6175 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
6179 show_arm_command (char *args
, int from_tty
)
6181 cmd_show_list (showarmcmdlist
, from_tty
, "");
6185 arm_update_current_architecture (void)
6187 struct gdbarch_info info
;
6189 /* If the current architecture is not ARM, we have nothing to do. */
6190 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
6193 /* Update the architecture. */
6194 gdbarch_info_init (&info
);
6196 if (!gdbarch_update_p (info
))
6197 internal_error (__FILE__
, __LINE__
, "could not update architecture");
6201 set_fp_model_sfunc (char *args
, int from_tty
,
6202 struct cmd_list_element
*c
)
6204 enum arm_float_model fp_model
;
6206 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
6207 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
6209 arm_fp_model
= fp_model
;
6213 if (fp_model
== ARM_FLOAT_LAST
)
6214 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
6217 arm_update_current_architecture ();
6221 show_fp_model (struct ui_file
*file
, int from_tty
,
6222 struct cmd_list_element
*c
, const char *value
)
6224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6226 if (arm_fp_model
== ARM_FLOAT_AUTO
6227 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
6228 fprintf_filtered (file
, _("\
6229 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
6230 fp_model_strings
[tdep
->fp_model
]);
6232 fprintf_filtered (file
, _("\
6233 The current ARM floating point model is \"%s\".\n"),
6234 fp_model_strings
[arm_fp_model
]);
6238 arm_set_abi (char *args
, int from_tty
,
6239 struct cmd_list_element
*c
)
6241 enum arm_abi_kind arm_abi
;
6243 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
6244 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
6246 arm_abi_global
= arm_abi
;
6250 if (arm_abi
== ARM_ABI_LAST
)
6251 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
6254 arm_update_current_architecture ();
6258 arm_show_abi (struct ui_file
*file
, int from_tty
,
6259 struct cmd_list_element
*c
, const char *value
)
6261 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6263 if (arm_abi_global
== ARM_ABI_AUTO
6264 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
6265 fprintf_filtered (file
, _("\
6266 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
6267 arm_abi_strings
[tdep
->arm_abi
]);
6269 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
6274 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
6275 struct cmd_list_element
*c
, const char *value
)
6277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6279 fprintf_filtered (file
, _("\
6280 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
6281 arm_fallback_mode_string
);
6285 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
6286 struct cmd_list_element
*c
, const char *value
)
6288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6290 fprintf_filtered (file
, _("\
6291 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
6292 arm_force_mode_string
);
6295 /* If the user changes the register disassembly style used for info
6296 register and other commands, we have to also switch the style used
6297 in opcodes for disassembly output. This function is run in the "set
6298 arm disassembly" command, and does that. */
6301 set_disassembly_style_sfunc (char *args
, int from_tty
,
6302 struct cmd_list_element
*c
)
6304 set_disassembly_style ();
6307 /* Return the ARM register name corresponding to register I. */
6309 arm_register_name (struct gdbarch
*gdbarch
, int i
)
6311 const int num_regs
= gdbarch_num_regs (gdbarch
);
6313 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
6314 && i
>= num_regs
&& i
< num_regs
+ 32)
6316 static const char *const vfp_pseudo_names
[] = {
6317 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
6318 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
6319 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
6320 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6323 return vfp_pseudo_names
[i
- num_regs
];
6326 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
6327 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
6329 static const char *const neon_pseudo_names
[] = {
6330 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
6331 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
6334 return neon_pseudo_names
[i
- num_regs
- 32];
6337 if (i
>= ARRAY_SIZE (arm_register_names
))
6338 /* These registers are only supported on targets which supply
6339 an XML description. */
6342 return arm_register_names
[i
];
6346 set_disassembly_style (void)
6350 /* Find the style that the user wants. */
6351 for (current
= 0; current
< num_disassembly_options
; current
++)
6352 if (disassembly_style
== valid_disassembly_styles
[current
])
6354 gdb_assert (current
< num_disassembly_options
);
6356 /* Synchronize the disassembler. */
6357 set_arm_regname_option (current
);
6360 /* Test whether the coff symbol specific value corresponds to a Thumb
6364 coff_sym_is_thumb (int val
)
6366 return (val
== C_THUMBEXT
6367 || val
== C_THUMBSTAT
6368 || val
== C_THUMBEXTFUNC
6369 || val
== C_THUMBSTATFUNC
6370 || val
== C_THUMBLABEL
);
6373 /* arm_coff_make_msymbol_special()
6374 arm_elf_make_msymbol_special()
6376 These functions test whether the COFF or ELF symbol corresponds to
6377 an address in thumb code, and set a "special" bit in a minimal
6378 symbol to indicate that it does. */
6381 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
6383 /* Thumb symbols are of type STT_LOPROC, (synonymous with
6385 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
6387 MSYMBOL_SET_SPECIAL (msym
);
6391 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
6393 if (coff_sym_is_thumb (val
))
6394 MSYMBOL_SET_SPECIAL (msym
);
6398 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
6400 struct arm_per_objfile
*data
= arg
;
6403 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
6404 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
6408 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
6411 const char *name
= bfd_asymbol_name (sym
);
6412 struct arm_per_objfile
*data
;
6413 VEC(arm_mapping_symbol_s
) **map_p
;
6414 struct arm_mapping_symbol new_map_sym
;
6416 gdb_assert (name
[0] == '$');
6417 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
6420 data
= objfile_data (objfile
, arm_objfile_data_key
);
6423 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
6424 struct arm_per_objfile
);
6425 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
6426 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
6427 objfile
->obfd
->section_count
,
6428 VEC(arm_mapping_symbol_s
) *);
6430 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
6432 new_map_sym
.value
= sym
->value
;
6433 new_map_sym
.type
= name
[1];
6435 /* Assume that most mapping symbols appear in order of increasing
6436 value. If they were randomly distributed, it would be faster to
6437 always push here and then sort at first use. */
6438 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
6440 struct arm_mapping_symbol
*prev_map_sym
;
6442 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
6443 if (prev_map_sym
->value
>= sym
->value
)
6446 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
6447 arm_compare_mapping_symbols
);
6448 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
6453 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
6457 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
6459 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6460 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
6462 /* If necessary, set the T bit. */
6465 ULONGEST val
, t_bit
;
6466 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
6467 t_bit
= arm_psr_thumb_bit (gdbarch
);
6468 if (arm_pc_is_thumb (gdbarch
, pc
))
6469 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
6472 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
6477 /* Read the contents of a NEON quad register, by reading from two
6478 double registers. This is used to implement the quad pseudo
6479 registers, and for argument passing in case the quad registers are
6480 missing; vectors are passed in quad registers when using the VFP
6481 ABI, even if a NEON unit is not present. REGNUM is the index of
6482 the quad register, in [0, 15]. */
6485 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6486 int regnum
, gdb_byte
*buf
)
6489 gdb_byte reg_buf
[8];
6490 int offset
, double_regnum
;
6492 sprintf (name_buf
, "d%d", regnum
<< 1);
6493 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6496 /* d0 is always the least significant half of q0. */
6497 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6502 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6503 memcpy (buf
+ offset
, reg_buf
, 8);
6505 offset
= 8 - offset
;
6506 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
6507 memcpy (buf
+ offset
, reg_buf
, 8);
6511 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6512 int regnum
, gdb_byte
*buf
)
6514 const int num_regs
= gdbarch_num_regs (gdbarch
);
6516 gdb_byte reg_buf
[8];
6517 int offset
, double_regnum
;
6519 gdb_assert (regnum
>= num_regs
);
6522 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6523 /* Quad-precision register. */
6524 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
6527 /* Single-precision register. */
6528 gdb_assert (regnum
< 32);
6530 /* s0 is always the least significant half of d0. */
6531 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6532 offset
= (regnum
& 1) ? 0 : 4;
6534 offset
= (regnum
& 1) ? 4 : 0;
6536 sprintf (name_buf
, "d%d", regnum
>> 1);
6537 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6540 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6541 memcpy (buf
, reg_buf
+ offset
, 4);
6545 /* Store the contents of BUF to a NEON quad register, by writing to
6546 two double registers. This is used to implement the quad pseudo
6547 registers, and for argument passing in case the quad registers are
6548 missing; vectors are passed in quad registers when using the VFP
6549 ABI, even if a NEON unit is not present. REGNUM is the index
6550 of the quad register, in [0, 15]. */
6553 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6554 int regnum
, const gdb_byte
*buf
)
6557 gdb_byte reg_buf
[8];
6558 int offset
, double_regnum
;
6560 sprintf (name_buf
, "d%d", regnum
<< 1);
6561 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6564 /* d0 is always the least significant half of q0. */
6565 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6570 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
6571 offset
= 8 - offset
;
6572 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
6576 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6577 int regnum
, const gdb_byte
*buf
)
6579 const int num_regs
= gdbarch_num_regs (gdbarch
);
6581 gdb_byte reg_buf
[8];
6582 int offset
, double_regnum
;
6584 gdb_assert (regnum
>= num_regs
);
6587 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6588 /* Quad-precision register. */
6589 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
6592 /* Single-precision register. */
6593 gdb_assert (regnum
< 32);
6595 /* s0 is always the least significant half of d0. */
6596 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6597 offset
= (regnum
& 1) ? 0 : 4;
6599 offset
= (regnum
& 1) ? 4 : 0;
6601 sprintf (name_buf
, "d%d", regnum
>> 1);
6602 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6605 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6606 memcpy (reg_buf
+ offset
, buf
, 4);
6607 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
6611 static struct value
*
6612 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
6614 const int *reg_p
= baton
;
6615 return value_of_register (*reg_p
, frame
);
6618 static enum gdb_osabi
6619 arm_elf_osabi_sniffer (bfd
*abfd
)
6621 unsigned int elfosabi
;
6622 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
6624 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
6626 if (elfosabi
== ELFOSABI_ARM
)
6627 /* GNU tools use this value. Check note sections in this case,
6629 bfd_map_over_sections (abfd
,
6630 generic_elf_osabi_sniff_abi_tag_sections
,
6633 /* Anything else will be handled by the generic ELF sniffer. */
6638 /* Initialize the current architecture based on INFO. If possible,
6639 re-use an architecture from ARCHES, which is a list of
6640 architectures already created during this debugging session.
6642 Called e.g. at program startup, when reading a core file, and when
6643 reading a binary file. */
6645 static struct gdbarch
*
6646 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6648 struct gdbarch_tdep
*tdep
;
6649 struct gdbarch
*gdbarch
;
6650 struct gdbarch_list
*best_arch
;
6651 enum arm_abi_kind arm_abi
= arm_abi_global
;
6652 enum arm_float_model fp_model
= arm_fp_model
;
6653 struct tdesc_arch_data
*tdesc_data
= NULL
;
6655 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
6657 int have_fpa_registers
= 1;
6658 const struct target_desc
*tdesc
= info
.target_desc
;
6660 /* If we have an object to base this architecture on, try to determine
6663 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
6665 int ei_osabi
, e_flags
;
6667 switch (bfd_get_flavour (info
.abfd
))
6669 case bfd_target_aout_flavour
:
6670 /* Assume it's an old APCS-style ABI. */
6671 arm_abi
= ARM_ABI_APCS
;
6674 case bfd_target_coff_flavour
:
6675 /* Assume it's an old APCS-style ABI. */
6677 arm_abi
= ARM_ABI_APCS
;
6680 case bfd_target_elf_flavour
:
6681 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
6682 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6684 if (ei_osabi
== ELFOSABI_ARM
)
6686 /* GNU tools used to use this value, but do not for EABI
6687 objects. There's nowhere to tag an EABI version
6688 anyway, so assume APCS. */
6689 arm_abi
= ARM_ABI_APCS
;
6691 else if (ei_osabi
== ELFOSABI_NONE
)
6693 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
6694 int attr_arch
, attr_profile
;
6698 case EF_ARM_EABI_UNKNOWN
:
6699 /* Assume GNU tools. */
6700 arm_abi
= ARM_ABI_APCS
;
6703 case EF_ARM_EABI_VER4
:
6704 case EF_ARM_EABI_VER5
:
6705 arm_abi
= ARM_ABI_AAPCS
;
6706 /* EABI binaries default to VFP float ordering.
6707 They may also contain build attributes that can
6708 be used to identify if the VFP argument-passing
6710 if (fp_model
== ARM_FLOAT_AUTO
)
6713 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
6718 /* "The user intended FP parameter/result
6719 passing to conform to AAPCS, base
6721 fp_model
= ARM_FLOAT_SOFT_VFP
;
6724 /* "The user intended FP parameter/result
6725 passing to conform to AAPCS, VFP
6727 fp_model
= ARM_FLOAT_VFP
;
6730 /* "The user intended FP parameter/result
6731 passing to conform to tool chain-specific
6732 conventions" - we don't know any such
6733 conventions, so leave it as "auto". */
6736 /* Attribute value not mentioned in the
6737 October 2008 ABI, so leave it as
6742 fp_model
= ARM_FLOAT_SOFT_VFP
;
6748 /* Leave it as "auto". */
6749 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
6754 /* Detect M-profile programs. This only works if the
6755 executable file includes build attributes; GCC does
6756 copy them to the executable, but e.g. RealView does
6758 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
6760 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
6761 Tag_CPU_arch_profile
);
6762 /* GCC specifies the profile for v6-M; RealView only
6763 specifies the profile for architectures starting with
6764 V7 (as opposed to architectures with a tag
6765 numerically greater than TAG_CPU_ARCH_V7). */
6766 if (!tdesc_has_registers (tdesc
)
6767 && (attr_arch
== TAG_CPU_ARCH_V6_M
6768 || attr_arch
== TAG_CPU_ARCH_V6S_M
6769 || attr_profile
== 'M'))
6770 tdesc
= tdesc_arm_with_m
;
6774 if (fp_model
== ARM_FLOAT_AUTO
)
6776 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6778 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
6781 /* Leave it as "auto". Strictly speaking this case
6782 means FPA, but almost nobody uses that now, and
6783 many toolchains fail to set the appropriate bits
6784 for the floating-point model they use. */
6786 case EF_ARM_SOFT_FLOAT
:
6787 fp_model
= ARM_FLOAT_SOFT_FPA
;
6789 case EF_ARM_VFP_FLOAT
:
6790 fp_model
= ARM_FLOAT_VFP
;
6792 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
6793 fp_model
= ARM_FLOAT_SOFT_VFP
;
6798 if (e_flags
& EF_ARM_BE8
)
6799 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
6804 /* Leave it as "auto". */
6809 /* Check any target description for validity. */
6810 if (tdesc_has_registers (tdesc
))
6812 /* For most registers we require GDB's default names; but also allow
6813 the numeric names for sp / lr / pc, as a convenience. */
6814 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
6815 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
6816 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
6818 const struct tdesc_feature
*feature
;
6821 feature
= tdesc_find_feature (tdesc
,
6822 "org.gnu.gdb.arm.core");
6823 if (feature
== NULL
)
6825 feature
= tdesc_find_feature (tdesc
,
6826 "org.gnu.gdb.arm.m-profile");
6827 if (feature
== NULL
)
6833 tdesc_data
= tdesc_data_alloc ();
6836 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
6837 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6838 arm_register_names
[i
]);
6839 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6842 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6845 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6849 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6850 ARM_PS_REGNUM
, "xpsr");
6852 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6853 ARM_PS_REGNUM
, "cpsr");
6857 tdesc_data_cleanup (tdesc_data
);
6861 feature
= tdesc_find_feature (tdesc
,
6862 "org.gnu.gdb.arm.fpa");
6863 if (feature
!= NULL
)
6866 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
6867 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6868 arm_register_names
[i
]);
6871 tdesc_data_cleanup (tdesc_data
);
6876 have_fpa_registers
= 0;
6878 feature
= tdesc_find_feature (tdesc
,
6879 "org.gnu.gdb.xscale.iwmmxt");
6880 if (feature
!= NULL
)
6882 static const char *const iwmmxt_names
[] = {
6883 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
6884 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
6885 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
6886 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
6890 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
6892 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6893 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6895 /* Check for the control registers, but do not fail if they
6897 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
6898 tdesc_numbered_register (feature
, tdesc_data
, i
,
6899 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6901 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
6903 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6904 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6908 tdesc_data_cleanup (tdesc_data
);
6913 /* If we have a VFP unit, check whether the single precision registers
6914 are present. If not, then we will synthesize them as pseudo
6916 feature
= tdesc_find_feature (tdesc
,
6917 "org.gnu.gdb.arm.vfp");
6918 if (feature
!= NULL
)
6920 static const char *const vfp_double_names
[] = {
6921 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
6922 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
6923 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
6924 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6927 /* Require the double precision registers. There must be either
6930 for (i
= 0; i
< 32; i
++)
6932 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6934 vfp_double_names
[i
]);
6939 if (!valid_p
&& i
!= 16)
6941 tdesc_data_cleanup (tdesc_data
);
6945 if (tdesc_unnumbered_register (feature
, "s0") == 0)
6946 have_vfp_pseudos
= 1;
6948 have_vfp_registers
= 1;
6950 /* If we have VFP, also check for NEON. The architecture allows
6951 NEON without VFP (integer vector operations only), but GDB
6952 does not support that. */
6953 feature
= tdesc_find_feature (tdesc
,
6954 "org.gnu.gdb.arm.neon");
6955 if (feature
!= NULL
)
6957 /* NEON requires 32 double-precision registers. */
6960 tdesc_data_cleanup (tdesc_data
);
6964 /* If there are quad registers defined by the stub, use
6965 their type; otherwise (normally) provide them with
6966 the default type. */
6967 if (tdesc_unnumbered_register (feature
, "q0") == 0)
6968 have_neon_pseudos
= 1;
6975 /* If there is already a candidate, use it. */
6976 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
6978 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
6980 if (arm_abi
!= ARM_ABI_AUTO
6981 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
6984 if (fp_model
!= ARM_FLOAT_AUTO
6985 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
6988 /* There are various other properties in tdep that we do not
6989 need to check here: those derived from a target description,
6990 since gdbarches with a different target description are
6991 automatically disqualified. */
6993 /* Do check is_m, though, since it might come from the binary. */
6994 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
6997 /* Found a match. */
7001 if (best_arch
!= NULL
)
7003 if (tdesc_data
!= NULL
)
7004 tdesc_data_cleanup (tdesc_data
);
7005 return best_arch
->gdbarch
;
7008 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
7009 gdbarch
= gdbarch_alloc (&info
, tdep
);
7011 /* Record additional information about the architecture we are defining.
7012 These are gdbarch discriminators, like the OSABI. */
7013 tdep
->arm_abi
= arm_abi
;
7014 tdep
->fp_model
= fp_model
;
7016 tdep
->have_fpa_registers
= have_fpa_registers
;
7017 tdep
->have_vfp_registers
= have_vfp_registers
;
7018 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
7019 tdep
->have_neon_pseudos
= have_neon_pseudos
;
7020 tdep
->have_neon
= have_neon
;
7023 switch (info
.byte_order_for_code
)
7025 case BFD_ENDIAN_BIG
:
7026 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
7027 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
7028 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
7029 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
7033 case BFD_ENDIAN_LITTLE
:
7034 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
7035 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
7036 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
7037 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
7042 internal_error (__FILE__
, __LINE__
,
7043 _("arm_gdbarch_init: bad byte order for float format"));
7046 /* On ARM targets char defaults to unsigned. */
7047 set_gdbarch_char_signed (gdbarch
, 0);
7049 /* Note: for displaced stepping, this includes the breakpoint, and one word
7050 of additional scratch space. This setting isn't used for anything beside
7051 displaced stepping at present. */
7052 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
7054 /* This should be low enough for everything. */
7055 tdep
->lowest_pc
= 0x20;
7056 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
7058 /* The default, for both APCS and AAPCS, is to return small
7059 structures in registers. */
7060 tdep
->struct_return
= reg_struct_return
;
7062 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
7063 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
7065 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
7067 /* Frame handling. */
7068 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
7069 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
7070 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
7072 frame_base_set_default (gdbarch
, &arm_normal_base
);
7074 /* Address manipulation. */
7075 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
7076 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
7078 /* Advance PC across function entry code. */
7079 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
7081 /* Detect whether PC is in function epilogue. */
7082 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
7084 /* Skip trampolines. */
7085 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
7087 /* The stack grows downward. */
7088 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7090 /* Breakpoint manipulation. */
7091 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
7092 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
7093 arm_remote_breakpoint_from_pc
);
7095 /* Information about registers, etc. */
7096 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
7097 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
7098 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
7099 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
7100 set_gdbarch_register_type (gdbarch
, arm_register_type
);
7102 /* This "info float" is FPA-specific. Use the generic version if we
7104 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
7105 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
7107 /* Internal <-> external register number maps. */
7108 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
7109 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
7111 set_gdbarch_register_name (gdbarch
, arm_register_name
);
7113 /* Returning results. */
7114 set_gdbarch_return_value (gdbarch
, arm_return_value
);
7117 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
7119 /* Minsymbol frobbing. */
7120 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
7121 set_gdbarch_coff_make_msymbol_special (gdbarch
,
7122 arm_coff_make_msymbol_special
);
7123 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
7125 /* Thumb-2 IT block support. */
7126 set_gdbarch_adjust_breakpoint_address (gdbarch
,
7127 arm_adjust_breakpoint_address
);
7129 /* Virtual tables. */
7130 set_gdbarch_vbit_in_delta (gdbarch
, 1);
7132 /* Hook in the ABI-specific overrides, if they have been registered. */
7133 gdbarch_init_osabi (info
, gdbarch
);
7135 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
7137 /* Add some default predicates. */
7138 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
7139 dwarf2_append_unwinders (gdbarch
);
7140 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
7142 /* Now we have tuned the configuration, set a few final things,
7143 based on what the OS ABI has told us. */
7145 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
7146 binaries are always marked. */
7147 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
7148 tdep
->arm_abi
= ARM_ABI_APCS
;
7150 /* We used to default to FPA for generic ARM, but almost nobody
7151 uses that now, and we now provide a way for the user to force
7152 the model. So default to the most useful variant. */
7153 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
7154 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
7156 if (tdep
->jb_pc
>= 0)
7157 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
7159 /* Floating point sizes and format. */
7160 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
7161 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
7163 set_gdbarch_double_format
7164 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
7165 set_gdbarch_long_double_format
7166 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
7170 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
7171 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
7174 if (have_vfp_pseudos
)
7176 /* NOTE: These are the only pseudo registers used by
7177 the ARM target at the moment. If more are added, a
7178 little more care in numbering will be needed. */
7180 int num_pseudos
= 32;
7181 if (have_neon_pseudos
)
7183 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
7184 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
7185 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
7190 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
7192 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
7194 /* Override tdesc_register_type to adjust the types of VFP
7195 registers for NEON. */
7196 set_gdbarch_register_type (gdbarch
, arm_register_type
);
7199 /* Add standard register aliases. We add aliases even for those
7200 nanes which are used by the current architecture - it's simpler,
7201 and does no harm, since nothing ever lists user registers. */
7202 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
7203 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
7204 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
7210 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7217 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
7218 (unsigned long) tdep
->lowest_pc
);
7221 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
7224 _initialize_arm_tdep (void)
7226 struct ui_file
*stb
;
7228 struct cmd_list_element
*new_set
, *new_show
;
7229 const char *setname
;
7230 const char *setdesc
;
7231 const char *const *regnames
;
7233 static char *helptext
;
7234 char regdesc
[1024], *rdptr
= regdesc
;
7235 size_t rest
= sizeof (regdesc
);
7237 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
7239 arm_objfile_data_key
7240 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
7242 /* Register an ELF OS ABI sniffer for ARM binaries. */
7243 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
7244 bfd_target_elf_flavour
,
7245 arm_elf_osabi_sniffer
);
7247 /* Initialize the standard target descriptions. */
7248 initialize_tdesc_arm_with_m ();
7250 /* Get the number of possible sets of register names defined in opcodes. */
7251 num_disassembly_options
= get_arm_regname_num_options ();
7253 /* Add root prefix command for all "set arm"/"show arm" commands. */
7254 add_prefix_cmd ("arm", no_class
, set_arm_command
,
7255 _("Various ARM-specific commands."),
7256 &setarmcmdlist
, "set arm ", 0, &setlist
);
7258 add_prefix_cmd ("arm", no_class
, show_arm_command
,
7259 _("Various ARM-specific commands."),
7260 &showarmcmdlist
, "show arm ", 0, &showlist
);
7262 /* Sync the opcode insn printer with our register viewer. */
7263 parse_arm_disassembler_option ("reg-names-std");
7265 /* Initialize the array that will be passed to
7266 add_setshow_enum_cmd(). */
7267 valid_disassembly_styles
7268 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
7269 for (i
= 0; i
< num_disassembly_options
; i
++)
7271 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
7272 valid_disassembly_styles
[i
] = setname
;
7273 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
7276 /* When we find the default names, tell the disassembler to use
7278 if (!strcmp (setname
, "std"))
7280 disassembly_style
= setname
;
7281 set_arm_regname_option (i
);
7284 /* Mark the end of valid options. */
7285 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
7287 /* Create the help text. */
7288 stb
= mem_fileopen ();
7289 fprintf_unfiltered (stb
, "%s%s%s",
7290 _("The valid values are:\n"),
7292 _("The default is \"std\"."));
7293 helptext
= ui_file_xstrdup (stb
, NULL
);
7294 ui_file_delete (stb
);
7296 add_setshow_enum_cmd("disassembler", no_class
,
7297 valid_disassembly_styles
, &disassembly_style
,
7298 _("Set the disassembly style."),
7299 _("Show the disassembly style."),
7301 set_disassembly_style_sfunc
,
7302 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
7303 &setarmcmdlist
, &showarmcmdlist
);
7305 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
7306 _("Set usage of ARM 32-bit mode."),
7307 _("Show usage of ARM 32-bit mode."),
7308 _("When off, a 26-bit PC will be used."),
7310 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
7311 &setarmcmdlist
, &showarmcmdlist
);
7313 /* Add a command to allow the user to force the FPU model. */
7314 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
7315 _("Set the floating point type."),
7316 _("Show the floating point type."),
7317 _("auto - Determine the FP typefrom the OS-ABI.\n\
7318 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
7319 fpa - FPA co-processor (GCC compiled).\n\
7320 softvfp - Software FP with pure-endian doubles.\n\
7321 vfp - VFP co-processor."),
7322 set_fp_model_sfunc
, show_fp_model
,
7323 &setarmcmdlist
, &showarmcmdlist
);
7325 /* Add a command to allow the user to force the ABI. */
7326 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
7329 NULL
, arm_set_abi
, arm_show_abi
,
7330 &setarmcmdlist
, &showarmcmdlist
);
7332 /* Add two commands to allow the user to force the assumed
7334 add_setshow_enum_cmd ("fallback-mode", class_support
,
7335 arm_mode_strings
, &arm_fallback_mode_string
,
7336 _("Set the mode assumed when symbols are unavailable."),
7337 _("Show the mode assumed when symbols are unavailable."),
7338 NULL
, NULL
, arm_show_fallback_mode
,
7339 &setarmcmdlist
, &showarmcmdlist
);
7340 add_setshow_enum_cmd ("force-mode", class_support
,
7341 arm_mode_strings
, &arm_force_mode_string
,
7342 _("Set the mode assumed even when symbols are available."),
7343 _("Show the mode assumed even when symbols are available."),
7344 NULL
, NULL
, arm_show_force_mode
,
7345 &setarmcmdlist
, &showarmcmdlist
);
7347 /* Debugging flag. */
7348 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
7349 _("Set ARM debugging."),
7350 _("Show ARM debugging."),
7351 _("When on, arm-specific debugging is enabled."),
7353 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
7354 &setdebuglist
, &showdebuglist
);