1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-1989, 1991-1993, 1995-1996, 1998-2012 Free
4 Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include <ctype.h> /* XXX for isupper (). */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data
*arm_objfile_data_key
;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
92 DEF_VEC_O(arm_mapping_symbol_s
);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s
) **section_maps
;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element
*setarmcmdlist
= NULL
;
101 static struct cmd_list_element
*showarmcmdlist
= NULL
;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings
[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
117 static const char *current_fp_model
= "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
130 static const char *arm_abi_string
= "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode
= -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options
;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases
[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names
[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles
;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style
;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element
*);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat
*, const void *,
228 static void convert_to_extended (const struct floatformat
*, void *,
231 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
232 struct regcache
*regcache
,
233 int regnum
, gdb_byte
*buf
);
234 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, const gdb_byte
*buf
);
238 static int thumb_insn_size (unsigned short inst1
);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg
*saved_regs
;
260 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
261 CORE_ADDR prologue_start
,
262 CORE_ADDR prologue_end
,
263 struct arm_prologue_cache
*cache
);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
285 if (gdbarch_tdep (gdbarch
)->is_m
)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info
*frame
)
297 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
312 const struct arm_mapping_symbol
*rhs
)
314 return lhs
->value
< rhs
->value
;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
324 struct obj_section
*sec
;
326 /* If there are mapping symbols, consult them. */
327 sec
= find_pc_section (memaddr
);
330 struct arm_per_objfile
*data
;
331 VEC(arm_mapping_symbol_s
) *map
;
332 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
336 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
339 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
340 if (!VEC_empty (arm_mapping_symbol_s
, map
))
342 struct arm_mapping_symbol
*map_sym
;
344 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
345 arm_compare_mapping_symbols
);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
353 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
354 if (map_sym
->value
== map_key
.value
)
357 *start
= map_sym
->value
+ obj_section_addr (sec
);
358 return map_sym
->type
;
364 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
366 *start
= map_sym
->value
+ obj_section_addr (sec
);
367 return map_sym
->type
;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
383 struct obj_section
*sec
;
384 struct minimal_symbol
*sym
;
386 struct displaced_step_closure
* dsc
387 = get_displaced_step_closure_by_addr(memaddr
);
389 /* If checking the mode of displaced instruction in copy area, the mode
390 should be determined by instruction on the original address. */
394 fprintf_unfiltered (gdb_stdlog
,
395 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (unsigned long) dsc
->insn_addr
,
397 (unsigned long) memaddr
);
398 memaddr
= dsc
->insn_addr
;
401 /* If bit 0 of the address is set, assume this is a Thumb address. */
402 if (IS_THUMB_ADDR (memaddr
))
405 /* Respect internal mode override if active. */
406 if (arm_override_mode
!= -1)
407 return arm_override_mode
;
409 /* If the user wants to override the symbol table, let him. */
410 if (strcmp (arm_force_mode_string
, "arm") == 0)
412 if (strcmp (arm_force_mode_string
, "thumb") == 0)
415 /* ARM v6-M and v7-M are always in Thumb mode. */
416 if (gdbarch_tdep (gdbarch
)->is_m
)
419 /* If there are mapping symbols, consult them. */
420 type
= arm_find_mapping_symbol (memaddr
, NULL
);
424 /* Thumb functions have a "special" bit set in minimal symbols. */
425 sym
= lookup_minimal_symbol_by_pc (memaddr
);
427 return (MSYMBOL_IS_SPECIAL (sym
));
429 /* If the user wants to override the fallback mode, let them. */
430 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
432 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
435 /* If we couldn't find any symbol, but we're talking to a running
436 target, then trust the current value of $cpsr. This lets
437 "display/i $pc" always show the correct mode (though if there is
438 a symbol table we will not reach here, so it still may not be
439 displayed in the mode it will be executed). */
440 if (target_has_registers
)
441 return arm_frame_is_thumb (get_current_frame ());
443 /* Otherwise we're out of luck; we assume ARM. */
447 /* Remove useless bits from addresses in a running program. */
449 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
452 return UNMAKE_THUMB_ADDR (val
);
454 return (val
& 0x03fffffc);
457 /* When reading symbols, we need to zap the low bit of the address,
458 which may be set to 1 for Thumb functions. */
460 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
465 /* Return 1 if PC is the start of a compiler helper function which
466 can be safely ignored during prologue skipping. IS_THUMB is true
467 if the function is known to be a Thumb function due to the way it
470 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
472 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
473 struct minimal_symbol
*msym
;
475 msym
= lookup_minimal_symbol_by_pc (pc
);
477 && SYMBOL_VALUE_ADDRESS (msym
) == pc
478 && SYMBOL_LINKAGE_NAME (msym
) != NULL
)
480 const char *name
= SYMBOL_LINKAGE_NAME (msym
);
482 /* The GNU linker's Thumb call stub to foo is named
484 if (strstr (name
, "_from_thumb") != NULL
)
487 /* On soft-float targets, __truncdfsf2 is called to convert promoted
488 arguments to their argument types in non-prototyped
490 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
492 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
495 /* Internal functions related to thread-local storage. */
496 if (strncmp (name
, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
498 if (strncmp (name
, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
503 /* If we run against a stripped glibc, we may be unable to identify
504 special functions by name. Check for one important case,
505 __aeabi_read_tp, by comparing the *code* against the default
506 implementation (this is hand-written ARM assembler in glibc). */
509 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
510 == 0xe3e00a0f /* mov r0, #0xffff0fff */
511 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
512 == 0xe240f01f) /* sub pc, r0, #31 */
519 /* Support routines for instruction parsing. */
520 #define submask(x) ((1L << ((x) + 1)) - 1)
521 #define bit(obj,st) (((obj) >> (st)) & 1)
522 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
523 #define sbits(obj,st,fn) \
524 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
525 #define BranchDest(addr,instr) \
526 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
528 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
529 the first 16-bit of instruction, and INSN2 is the second 16-bit of
531 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
532 ((bits ((insn1), 0, 3) << 12) \
533 | (bits ((insn1), 10, 10) << 11) \
534 | (bits ((insn2), 12, 14) << 8) \
535 | bits ((insn2), 0, 7))
537 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
538 the 32-bit instruction. */
539 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
540 ((bits ((insn), 16, 19) << 12) \
541 | bits ((insn), 0, 11))
543 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
546 thumb_expand_immediate (unsigned int imm
)
548 unsigned int count
= imm
>> 7;
556 return (imm
& 0xff) | ((imm
& 0xff) << 16);
558 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
560 return (imm
& 0xff) | ((imm
& 0xff) << 8)
561 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
564 return (0x80 | (imm
& 0x7f)) << (32 - count
);
567 /* Return 1 if the 16-bit Thumb instruction INST might change
568 control flow, 0 otherwise. */
571 thumb_instruction_changes_pc (unsigned short inst
)
573 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
576 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
579 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
582 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
585 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
588 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
594 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
595 might change control flow, 0 otherwise. */
598 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
600 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
602 /* Branches and miscellaneous control instructions. */
604 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
609 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
611 /* SUBS PC, LR, #imm8. */
614 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
616 /* Conditional branch. */
623 if ((inst1
& 0xfe50) == 0xe810)
625 /* Load multiple or RFE. */
627 if (bit (inst1
, 7) && !bit (inst1
, 8))
633 else if (!bit (inst1
, 7) && bit (inst1
, 8))
639 else if (bit (inst1
, 7) && bit (inst1
, 8))
644 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
653 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
655 /* MOV PC or MOVS PC. */
659 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
662 if (bits (inst1
, 0, 3) == 15)
668 if ((inst2
& 0x0fc0) == 0x0000)
674 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
680 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
689 /* Analyze a Thumb prologue, looking for a recognizable stack frame
690 and frame pointer. Scan until we encounter a store that could
691 clobber the stack frame unexpectedly, or an unknown instruction.
692 Return the last address which is definitely safe to skip for an
693 initial breakpoint. */
696 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
697 CORE_ADDR start
, CORE_ADDR limit
,
698 struct arm_prologue_cache
*cache
)
700 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
701 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
704 struct pv_area
*stack
;
705 struct cleanup
*back_to
;
707 CORE_ADDR unrecognized_pc
= 0;
709 for (i
= 0; i
< 16; i
++)
710 regs
[i
] = pv_register (i
, 0);
711 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
712 back_to
= make_cleanup_free_pv_area (stack
);
714 while (start
< limit
)
718 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
720 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
725 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
728 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
729 whether to save LR (R14). */
730 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
732 /* Calculate offsets of saved R0-R7 and LR. */
733 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
734 if (mask
& (1 << regno
))
736 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
738 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
741 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
744 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
745 if (insn
& 0x80) /* Check for SUB. */
746 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
749 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
752 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
753 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
755 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
756 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
757 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
759 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
760 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
761 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
763 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
764 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
765 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
766 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
767 regs
[bits (insn
, 6, 8)]);
768 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
769 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
771 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
772 int rm
= bits (insn
, 3, 6);
773 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
775 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
777 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
778 int src_reg
= (insn
& 0x78) >> 3;
779 regs
[dst_reg
] = regs
[src_reg
];
781 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
783 /* Handle stores to the stack. Normally pushes are used,
784 but with GCC -mtpcs-frame, there may be other stores
785 in the prologue to create the frame. */
786 int regno
= (insn
>> 8) & 0x7;
789 offset
= (insn
& 0xff) << 2;
790 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
792 if (pv_area_store_would_trash (stack
, addr
))
795 pv_area_store (stack
, addr
, 4, regs
[regno
]);
797 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
799 int rd
= bits (insn
, 0, 2);
800 int rn
= bits (insn
, 3, 5);
803 offset
= bits (insn
, 6, 10) << 2;
804 addr
= pv_add_constant (regs
[rn
], offset
);
806 if (pv_area_store_would_trash (stack
, addr
))
809 pv_area_store (stack
, addr
, 4, regs
[rd
]);
811 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
812 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
813 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
814 /* Ignore stores of argument registers to the stack. */
816 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
817 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
818 /* Ignore block loads from the stack, potentially copying
819 parameters from memory. */
821 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
822 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
823 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
824 /* Similarly ignore single loads from the stack. */
826 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
827 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
828 /* Skip register copies, i.e. saves to another register
829 instead of the stack. */
831 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
832 /* Recognize constant loads; even with small stacks these are necessary
834 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
835 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
837 /* Constant pool loads, for the same reason. */
838 unsigned int constant
;
841 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
842 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
843 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
845 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
847 unsigned short inst2
;
849 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
850 byte_order_for_code
);
852 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
854 /* BL, BLX. Allow some special function calls when
855 skipping the prologue; GCC generates these before
856 storing arguments to the stack. */
858 int j1
, j2
, imm1
, imm2
;
860 imm1
= sbits (insn
, 0, 10);
861 imm2
= bits (inst2
, 0, 10);
862 j1
= bit (inst2
, 13);
863 j2
= bit (inst2
, 11);
865 offset
= ((imm1
<< 12) + (imm2
<< 1));
866 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
868 nextpc
= start
+ 4 + offset
;
869 /* For BLX make sure to clear the low bits. */
870 if (bit (inst2
, 12) == 0)
871 nextpc
= nextpc
& 0xfffffffc;
873 if (!skip_prologue_function (gdbarch
, nextpc
,
874 bit (inst2
, 12) != 0))
878 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
880 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
882 pv_t addr
= regs
[bits (insn
, 0, 3)];
885 if (pv_area_store_would_trash (stack
, addr
))
888 /* Calculate offsets of saved registers. */
889 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
890 if (inst2
& (1 << regno
))
892 addr
= pv_add_constant (addr
, -4);
893 pv_area_store (stack
, addr
, 4, regs
[regno
]);
897 regs
[bits (insn
, 0, 3)] = addr
;
900 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
902 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
904 int regno1
= bits (inst2
, 12, 15);
905 int regno2
= bits (inst2
, 8, 11);
906 pv_t addr
= regs
[bits (insn
, 0, 3)];
908 offset
= inst2
& 0xff;
910 addr
= pv_add_constant (addr
, offset
);
912 addr
= pv_add_constant (addr
, -offset
);
914 if (pv_area_store_would_trash (stack
, addr
))
917 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
918 pv_area_store (stack
, pv_add_constant (addr
, 4),
922 regs
[bits (insn
, 0, 3)] = addr
;
925 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
926 && (inst2
& 0x0c00) == 0x0c00
927 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
929 int regno
= bits (inst2
, 12, 15);
930 pv_t addr
= regs
[bits (insn
, 0, 3)];
932 offset
= inst2
& 0xff;
934 addr
= pv_add_constant (addr
, offset
);
936 addr
= pv_add_constant (addr
, -offset
);
938 if (pv_area_store_would_trash (stack
, addr
))
941 pv_area_store (stack
, addr
, 4, regs
[regno
]);
944 regs
[bits (insn
, 0, 3)] = addr
;
947 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
948 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
950 int regno
= bits (inst2
, 12, 15);
953 offset
= inst2
& 0xfff;
954 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
956 if (pv_area_store_would_trash (stack
, addr
))
959 pv_area_store (stack
, addr
, 4, regs
[regno
]);
962 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
963 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
964 /* Ignore stores of argument registers to the stack. */
967 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
968 && (inst2
& 0x0d00) == 0x0c00
969 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
970 /* Ignore stores of argument registers to the stack. */
973 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
975 && (inst2
& 0x8000) == 0x0000
976 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
977 /* Ignore block loads from the stack, potentially copying
978 parameters from memory. */
981 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
983 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
984 /* Similarly ignore dual loads from the stack. */
987 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
988 && (inst2
& 0x0d00) == 0x0c00
989 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
990 /* Similarly ignore single loads from the stack. */
993 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
994 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
995 /* Similarly ignore single loads from the stack. */
998 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
999 && (inst2
& 0x8000) == 0x0000)
1001 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1002 | (bits (inst2
, 12, 14) << 8)
1003 | bits (inst2
, 0, 7));
1005 regs
[bits (inst2
, 8, 11)]
1006 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1007 thumb_expand_immediate (imm
));
1010 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1011 && (inst2
& 0x8000) == 0x0000)
1013 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1014 | (bits (inst2
, 12, 14) << 8)
1015 | bits (inst2
, 0, 7));
1017 regs
[bits (inst2
, 8, 11)]
1018 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1021 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1022 && (inst2
& 0x8000) == 0x0000)
1024 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1025 | (bits (inst2
, 12, 14) << 8)
1026 | bits (inst2
, 0, 7));
1028 regs
[bits (inst2
, 8, 11)]
1029 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1030 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1033 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1034 && (inst2
& 0x8000) == 0x0000)
1036 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1037 | (bits (inst2
, 12, 14) << 8)
1038 | bits (inst2
, 0, 7));
1040 regs
[bits (inst2
, 8, 11)]
1041 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1044 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1046 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1047 | (bits (inst2
, 12, 14) << 8)
1048 | bits (inst2
, 0, 7));
1050 regs
[bits (inst2
, 8, 11)]
1051 = pv_constant (thumb_expand_immediate (imm
));
1054 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1057 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1059 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1062 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1063 && (inst2
& 0xf0f0) == 0)
1065 int dst_reg
= (inst2
& 0x0f00) >> 8;
1066 int src_reg
= inst2
& 0xf;
1067 regs
[dst_reg
] = regs
[src_reg
];
1070 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1072 /* Constant pool loads. */
1073 unsigned int constant
;
1076 offset
= bits (insn
, 0, 11);
1078 loc
= start
+ 4 + offset
;
1080 loc
= start
+ 4 - offset
;
1082 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1083 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1086 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1088 /* Constant pool loads. */
1089 unsigned int constant
;
1092 offset
= bits (insn
, 0, 7) << 2;
1094 loc
= start
+ 4 + offset
;
1096 loc
= start
+ 4 - offset
;
1098 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1099 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1101 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1102 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1105 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1107 /* Don't scan past anything that might change control flow. */
1112 /* The optimizer might shove anything into the prologue,
1113 so we just skip what we don't recognize. */
1114 unrecognized_pc
= start
;
1119 else if (thumb_instruction_changes_pc (insn
))
1121 /* Don't scan past anything that might change control flow. */
1126 /* The optimizer might shove anything into the prologue,
1127 so we just skip what we don't recognize. */
1128 unrecognized_pc
= start
;
1135 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1136 paddress (gdbarch
, start
));
1138 if (unrecognized_pc
== 0)
1139 unrecognized_pc
= start
;
1143 do_cleanups (back_to
);
1144 return unrecognized_pc
;
1147 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1149 /* Frame pointer is fp. Frame size is constant. */
1150 cache
->framereg
= ARM_FP_REGNUM
;
1151 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1153 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1155 /* Frame pointer is r7. Frame size is constant. */
1156 cache
->framereg
= THUMB_FP_REGNUM
;
1157 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1161 /* Try the stack pointer... this is a bit desperate. */
1162 cache
->framereg
= ARM_SP_REGNUM
;
1163 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1166 for (i
= 0; i
< 16; i
++)
1167 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1168 cache
->saved_regs
[i
].addr
= offset
;
1170 do_cleanups (back_to
);
1171 return unrecognized_pc
;
1175 /* Try to analyze the instructions starting from PC, which load symbol
1176 __stack_chk_guard. Return the address of instruction after loading this
1177 symbol, set the dest register number to *BASEREG, and set the size of
1178 instructions for loading symbol in OFFSET. Return 0 if instructions are
1182 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1183 unsigned int *destreg
, int *offset
)
1185 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1186 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1187 unsigned int low
, high
, address
;
1192 unsigned short insn1
1193 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1195 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1197 *destreg
= bits (insn1
, 8, 10);
1199 address
= bits (insn1
, 0, 7);
1201 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1203 unsigned short insn2
1204 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1206 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1209 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1211 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1213 /* movt Rd, #const */
1214 if ((insn1
& 0xfbc0) == 0xf2c0)
1216 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1217 *destreg
= bits (insn2
, 8, 11);
1219 address
= (high
<< 16 | low
);
1226 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1228 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1230 address
= bits (insn
, 0, 11);
1231 *destreg
= bits (insn
, 12, 15);
1234 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1236 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1239 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1241 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1243 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1244 *destreg
= bits (insn
, 12, 15);
1246 address
= (high
<< 16 | low
);
1254 /* Try to skip a sequence of instructions used for stack protector. If PC
1255 points to the first instruction of this sequence, return the address of
1256 first instruction after this sequence, otherwise, return original PC.
1258 On arm, this sequence of instructions is composed of mainly three steps,
1259 Step 1: load symbol __stack_chk_guard,
1260 Step 2: load from address of __stack_chk_guard,
1261 Step 3: store it to somewhere else.
1263 Usually, instructions on step 2 and step 3 are the same on various ARM
1264 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1265 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1266 instructions in step 1 vary from different ARM architectures. On ARMv7,
1269 movw Rn, #:lower16:__stack_chk_guard
1270 movt Rn, #:upper16:__stack_chk_guard
1277 .word __stack_chk_guard
1279 Since ldr/str is a very popular instruction, we can't use them as
1280 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1281 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1282 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1285 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1287 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1288 unsigned int address
, basereg
;
1289 struct minimal_symbol
*stack_chk_guard
;
1291 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1294 /* Try to parse the instructions in Step 1. */
1295 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1300 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1301 /* If name of symbol doesn't start with '__stack_chk_guard', this
1302 instruction sequence is not for stack protector. If symbol is
1303 removed, we conservatively think this sequence is for stack protector. */
1305 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard
), "__stack_chk_guard",
1306 strlen ("__stack_chk_guard")) != 0)
1311 unsigned int destreg
;
1313 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1315 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1316 if ((insn
& 0xf800) != 0x6800)
1318 if (bits (insn
, 3, 5) != basereg
)
1320 destreg
= bits (insn
, 0, 2);
1322 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1323 byte_order_for_code
);
1324 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1325 if ((insn
& 0xf800) != 0x6000)
1327 if (destreg
!= bits (insn
, 0, 2))
1332 unsigned int destreg
;
1334 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1336 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1337 if ((insn
& 0x0e500000) != 0x04100000)
1339 if (bits (insn
, 16, 19) != basereg
)
1341 destreg
= bits (insn
, 12, 15);
1342 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1343 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1344 4, byte_order_for_code
);
1345 if ((insn
& 0x0e500000) != 0x04000000)
1347 if (bits (insn
, 12, 15) != destreg
)
1350 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1353 return pc
+ offset
+ 4;
1355 return pc
+ offset
+ 8;
1358 /* Advance the PC across any function entry prologue instructions to
1359 reach some "real" code.
1361 The APCS (ARM Procedure Call Standard) defines the following
1365 [stmfd sp!, {a1,a2,a3,a4}]
1366 stmfd sp!, {...,fp,ip,lr,pc}
1367 [stfe f7, [sp, #-12]!]
1368 [stfe f6, [sp, #-12]!]
1369 [stfe f5, [sp, #-12]!]
1370 [stfe f4, [sp, #-12]!]
1371 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1374 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1376 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1379 CORE_ADDR func_addr
, limit_pc
;
1380 struct symtab_and_line sal
;
1382 /* See if we can determine the end of the prologue via the symbol table.
1383 If so, then return either PC, or the PC after the prologue, whichever
1385 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1387 CORE_ADDR post_prologue_pc
1388 = skip_prologue_using_sal (gdbarch
, func_addr
);
1389 struct symtab
*s
= find_pc_symtab (func_addr
);
1391 if (post_prologue_pc
)
1393 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1396 /* GCC always emits a line note before the prologue and another
1397 one after, even if the two are at the same address or on the
1398 same line. Take advantage of this so that we do not need to
1399 know every instruction that might appear in the prologue. We
1400 will have producer information for most binaries; if it is
1401 missing (e.g. for -gstabs), assuming the GNU tools. */
1402 if (post_prologue_pc
1404 || s
->producer
== NULL
1405 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0))
1406 return post_prologue_pc
;
1408 if (post_prologue_pc
!= 0)
1410 CORE_ADDR analyzed_limit
;
1412 /* For non-GCC compilers, make sure the entire line is an
1413 acceptable prologue; GDB will round this function's
1414 return value up to the end of the following line so we
1415 can not skip just part of a line (and we do not want to).
1417 RealView does not treat the prologue specially, but does
1418 associate prologue code with the opening brace; so this
1419 lets us skip the first line if we think it is the opening
1421 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1422 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1423 post_prologue_pc
, NULL
);
1425 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1426 post_prologue_pc
, NULL
);
1428 if (analyzed_limit
!= post_prologue_pc
)
1431 return post_prologue_pc
;
1435 /* Can't determine prologue from the symbol table, need to examine
1438 /* Find an upper limit on the function prologue using the debug
1439 information. If the debug information could not be used to provide
1440 that bound, then use an arbitrary large number as the upper bound. */
1441 /* Like arm_scan_prologue, stop no later than pc + 64. */
1442 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1444 limit_pc
= pc
+ 64; /* Magic. */
1447 /* Check if this is Thumb code. */
1448 if (arm_pc_is_thumb (gdbarch
, pc
))
1449 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1451 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
1453 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
1455 /* "mov ip, sp" is no longer a required part of the prologue. */
1456 if (inst
== 0xe1a0c00d) /* mov ip, sp */
1459 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1462 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1465 /* Some prologues begin with "str lr, [sp, #-4]!". */
1466 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
1469 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1472 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1475 /* Any insns after this point may float into the code, if it makes
1476 for better instruction scheduling, so we skip them only if we
1477 find them, but still consider the function to be frame-ful. */
1479 /* We may have either one sfmfd instruction here, or several stfe
1480 insns, depending on the version of floating point code we
1482 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1485 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1488 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1491 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1494 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1495 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1496 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1499 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1500 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1501 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1504 /* Un-recognized instruction; stop scanning. */
1508 return skip_pc
; /* End of prologue. */
1512 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1513 This function decodes a Thumb function prologue to determine:
1514 1) the size of the stack frame
1515 2) which registers are saved on it
1516 3) the offsets of saved regs
1517 4) the offset from the stack pointer to the frame pointer
1519 A typical Thumb function prologue would create this stack frame
1520 (offsets relative to FP)
1521 old SP -> 24 stack parameters
1524 R7 -> 0 local variables (16 bytes)
1525 SP -> -12 additional stack space (12 bytes)
1526 The frame size would thus be 36 bytes, and the frame offset would be
1527 12 bytes. The frame register is R7.
1529 The comments for thumb_skip_prolog() describe the algorithm we use
1530 to detect the end of the prolog. */
1534 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1535 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1537 CORE_ADDR prologue_start
;
1538 CORE_ADDR prologue_end
;
1539 CORE_ADDR current_pc
;
1541 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1544 /* See comment in arm_scan_prologue for an explanation of
1546 if (prologue_end
> prologue_start
+ 64)
1548 prologue_end
= prologue_start
+ 64;
1552 /* We're in the boondocks: we have no idea where the start of the
1556 prologue_end
= min (prologue_end
, prev_pc
);
1558 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1561 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1564 arm_instruction_changes_pc (uint32_t this_instr
)
1566 if (bits (this_instr
, 28, 31) == INST_NV
)
1567 /* Unconditional instructions. */
1568 switch (bits (this_instr
, 24, 27))
1572 /* Branch with Link and change to Thumb. */
1577 /* Coprocessor register transfer. */
1578 if (bits (this_instr
, 12, 15) == 15)
1579 error (_("Invalid update to pc in instruction"));
1585 switch (bits (this_instr
, 25, 27))
1588 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1590 /* Multiplies and extra load/stores. */
1591 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1592 /* Neither multiplies nor extension load/stores are allowed
1596 /* Otherwise, miscellaneous instructions. */
1598 /* BX <reg>, BXJ <reg>, BLX <reg> */
1599 if (bits (this_instr
, 4, 27) == 0x12fff1
1600 || bits (this_instr
, 4, 27) == 0x12fff2
1601 || bits (this_instr
, 4, 27) == 0x12fff3)
1604 /* Other miscellaneous instructions are unpredictable if they
1608 /* Data processing instruction. Fall through. */
1611 if (bits (this_instr
, 12, 15) == 15)
1618 /* Media instructions and architecturally undefined instructions. */
1619 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1623 if (bit (this_instr
, 20) == 0)
1627 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1633 /* Load/store multiple. */
1634 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1640 /* Branch and branch with link. */
1645 /* Coprocessor transfers or SWIs can not affect PC. */
1649 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1653 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1654 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1655 fill it in. Return the first address not recognized as a prologue
1658 We recognize all the instructions typically found in ARM prologues,
1659 plus harmless instructions which can be skipped (either for analysis
1660 purposes, or a more restrictive set that can be skipped when finding
1661 the end of the prologue). */
1664 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1665 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1666 struct arm_prologue_cache
*cache
)
1668 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1669 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1671 CORE_ADDR offset
, current_pc
;
1672 pv_t regs
[ARM_FPS_REGNUM
];
1673 struct pv_area
*stack
;
1674 struct cleanup
*back_to
;
1675 int framereg
, framesize
;
1676 CORE_ADDR unrecognized_pc
= 0;
1678 /* Search the prologue looking for instructions that set up the
1679 frame pointer, adjust the stack pointer, and save registers.
1681 Be careful, however, and if it doesn't look like a prologue,
1682 don't try to scan it. If, for instance, a frameless function
1683 begins with stmfd sp!, then we will tell ourselves there is
1684 a frame, which will confuse stack traceback, as well as "finish"
1685 and other operations that rely on a knowledge of the stack
1688 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1689 regs
[regno
] = pv_register (regno
, 0);
1690 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1691 back_to
= make_cleanup_free_pv_area (stack
);
1693 for (current_pc
= prologue_start
;
1694 current_pc
< prologue_end
;
1698 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1700 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1702 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1705 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1706 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1708 unsigned imm
= insn
& 0xff; /* immediate value */
1709 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1710 int rd
= bits (insn
, 12, 15);
1711 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1712 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1715 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1716 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1718 unsigned imm
= insn
& 0xff; /* immediate value */
1719 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1720 int rd
= bits (insn
, 12, 15);
1721 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1722 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1725 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1728 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1730 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1731 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1732 regs
[bits (insn
, 12, 15)]);
1735 else if ((insn
& 0xffff0000) == 0xe92d0000)
1736 /* stmfd sp!, {..., fp, ip, lr, pc}
1738 stmfd sp!, {a1, a2, a3, a4} */
1740 int mask
= insn
& 0xffff;
1742 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1745 /* Calculate offsets of saved registers. */
1746 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1747 if (mask
& (1 << regno
))
1750 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1751 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1754 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1755 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1756 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1758 /* No need to add this to saved_regs -- it's just an arg reg. */
1761 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1762 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1763 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1765 /* No need to add this to saved_regs -- it's just an arg reg. */
1768 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1770 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1772 /* No need to add this to saved_regs -- it's just arg regs. */
1775 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1777 unsigned imm
= insn
& 0xff; /* immediate value */
1778 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1779 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1780 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1782 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1784 unsigned imm
= insn
& 0xff; /* immediate value */
1785 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1786 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1787 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1789 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1791 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1793 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1796 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1797 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1798 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1800 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1802 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1804 int n_saved_fp_regs
;
1805 unsigned int fp_start_reg
, fp_bound_reg
;
1807 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1810 if ((insn
& 0x800) == 0x800) /* N0 is set */
1812 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1813 n_saved_fp_regs
= 3;
1815 n_saved_fp_regs
= 1;
1819 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1820 n_saved_fp_regs
= 2;
1822 n_saved_fp_regs
= 4;
1825 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1826 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1827 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1829 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1830 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1831 regs
[fp_start_reg
++]);
1834 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1836 /* Allow some special function calls when skipping the
1837 prologue; GCC generates these before storing arguments to
1839 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1841 if (skip_prologue_function (gdbarch
, dest
, 0))
1846 else if ((insn
& 0xf0000000) != 0xe0000000)
1847 break; /* Condition not true, exit early. */
1848 else if (arm_instruction_changes_pc (insn
))
1849 /* Don't scan past anything that might change control flow. */
1851 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1852 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1853 /* Ignore block loads from the stack, potentially copying
1854 parameters from memory. */
1856 else if ((insn
& 0xfc500000) == 0xe4100000
1857 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1858 /* Similarly ignore single loads from the stack. */
1860 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1861 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1862 register instead of the stack. */
1866 /* The optimizer might shove anything into the prologue,
1867 so we just skip what we don't recognize. */
1868 unrecognized_pc
= current_pc
;
1873 if (unrecognized_pc
== 0)
1874 unrecognized_pc
= current_pc
;
1876 /* The frame size is just the distance from the frame register
1877 to the original stack pointer. */
1878 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1880 /* Frame pointer is fp. */
1881 framereg
= ARM_FP_REGNUM
;
1882 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1886 /* Try the stack pointer... this is a bit desperate. */
1887 framereg
= ARM_SP_REGNUM
;
1888 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1893 cache
->framereg
= framereg
;
1894 cache
->framesize
= framesize
;
1896 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1897 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1898 cache
->saved_regs
[regno
].addr
= offset
;
1902 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1903 paddress (gdbarch
, unrecognized_pc
));
1905 do_cleanups (back_to
);
1906 return unrecognized_pc
;
1910 arm_scan_prologue (struct frame_info
*this_frame
,
1911 struct arm_prologue_cache
*cache
)
1913 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1914 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1916 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1917 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1918 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1919 pv_t regs
[ARM_FPS_REGNUM
];
1920 struct pv_area
*stack
;
1921 struct cleanup
*back_to
;
1924 /* Assume there is no frame until proven otherwise. */
1925 cache
->framereg
= ARM_SP_REGNUM
;
1926 cache
->framesize
= 0;
1928 /* Check for Thumb prologue. */
1929 if (arm_frame_is_thumb (this_frame
))
1931 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1935 /* Find the function prologue. If we can't find the function in
1936 the symbol table, peek in the stack frame to find the PC. */
1937 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1940 /* One way to find the end of the prologue (which works well
1941 for unoptimized code) is to do the following:
1943 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1946 prologue_end = prev_pc;
1947 else if (sal.end < prologue_end)
1948 prologue_end = sal.end;
1950 This mechanism is very accurate so long as the optimizer
1951 doesn't move any instructions from the function body into the
1952 prologue. If this happens, sal.end will be the last
1953 instruction in the first hunk of prologue code just before
1954 the first instruction that the scheduler has moved from
1955 the body to the prologue.
1957 In order to make sure that we scan all of the prologue
1958 instructions, we use a slightly less accurate mechanism which
1959 may scan more than necessary. To help compensate for this
1960 lack of accuracy, the prologue scanning loop below contains
1961 several clauses which'll cause the loop to terminate early if
1962 an implausible prologue instruction is encountered.
1968 is a suitable endpoint since it accounts for the largest
1969 possible prologue plus up to five instructions inserted by
1972 if (prologue_end
> prologue_start
+ 64)
1974 prologue_end
= prologue_start
+ 64; /* See above. */
1979 /* We have no symbol information. Our only option is to assume this
1980 function has a standard stack frame and the normal frame register.
1981 Then, we can find the value of our frame pointer on entrance to
1982 the callee (or at the present moment if this is the innermost frame).
1983 The value stored there should be the address of the stmfd + 8. */
1984 CORE_ADDR frame_loc
;
1985 LONGEST return_value
;
1987 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1988 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1992 prologue_start
= gdbarch_addr_bits_remove
1993 (gdbarch
, return_value
) - 8;
1994 prologue_end
= prologue_start
+ 64; /* See above. */
1998 if (prev_pc
< prologue_end
)
1999 prologue_end
= prev_pc
;
2001 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
2004 static struct arm_prologue_cache
*
2005 arm_make_prologue_cache (struct frame_info
*this_frame
)
2008 struct arm_prologue_cache
*cache
;
2009 CORE_ADDR unwound_fp
;
2011 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2012 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2014 arm_scan_prologue (this_frame
, cache
);
2016 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2017 if (unwound_fp
== 0)
2020 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2022 /* Calculate actual addresses of saved registers using offsets
2023 determined by arm_scan_prologue. */
2024 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2025 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2026 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2031 /* Our frame ID for a normal frame is the current function's starting PC
2032 and the caller's SP when we were called. */
2035 arm_prologue_this_id (struct frame_info
*this_frame
,
2037 struct frame_id
*this_id
)
2039 struct arm_prologue_cache
*cache
;
2043 if (*this_cache
== NULL
)
2044 *this_cache
= arm_make_prologue_cache (this_frame
);
2045 cache
= *this_cache
;
2047 /* This is meant to halt the backtrace at "_start". */
2048 pc
= get_frame_pc (this_frame
);
2049 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2052 /* If we've hit a wall, stop. */
2053 if (cache
->prev_sp
== 0)
2056 /* Use function start address as part of the frame ID. If we cannot
2057 identify the start address (due to missing symbol information),
2058 fall back to just using the current PC. */
2059 func
= get_frame_func (this_frame
);
2063 id
= frame_id_build (cache
->prev_sp
, func
);
2067 static struct value
*
2068 arm_prologue_prev_register (struct frame_info
*this_frame
,
2072 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2073 struct arm_prologue_cache
*cache
;
2075 if (*this_cache
== NULL
)
2076 *this_cache
= arm_make_prologue_cache (this_frame
);
2077 cache
= *this_cache
;
2079 /* If we are asked to unwind the PC, then we need to return the LR
2080 instead. The prologue may save PC, but it will point into this
2081 frame's prologue, not the next frame's resume location. Also
2082 strip the saved T bit. A valid LR may have the low bit set, but
2083 a valid PC never does. */
2084 if (prev_regnum
== ARM_PC_REGNUM
)
2088 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2089 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2090 arm_addr_bits_remove (gdbarch
, lr
));
2093 /* SP is generally not saved to the stack, but this frame is
2094 identified by the next frame's stack pointer at the time of the call.
2095 The value was already reconstructed into PREV_SP. */
2096 if (prev_regnum
== ARM_SP_REGNUM
)
2097 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2099 /* The CPSR may have been changed by the call instruction and by the
2100 called function. The only bit we can reconstruct is the T bit,
2101 by checking the low bit of LR as of the call. This is a reliable
2102 indicator of Thumb-ness except for some ARM v4T pre-interworking
2103 Thumb code, which could get away with a clear low bit as long as
2104 the called function did not use bx. Guess that all other
2105 bits are unchanged; the condition flags are presumably lost,
2106 but the processor status is likely valid. */
2107 if (prev_regnum
== ARM_PS_REGNUM
)
2110 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2112 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2113 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2114 if (IS_THUMB_ADDR (lr
))
2118 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2121 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2125 struct frame_unwind arm_prologue_unwind
= {
2127 default_frame_unwind_stop_reason
,
2128 arm_prologue_this_id
,
2129 arm_prologue_prev_register
,
2131 default_frame_sniffer
2134 /* Maintain a list of ARM exception table entries per objfile, similar to the
2135 list of mapping symbols. We only cache entries for standard ARM-defined
2136 personality routines; the cache will contain only the frame unwinding
2137 instructions associated with the entry (not the descriptors). */
2139 static const struct objfile_data
*arm_exidx_data_key
;
2141 struct arm_exidx_entry
2146 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2147 DEF_VEC_O(arm_exidx_entry_s
);
2149 struct arm_exidx_data
2151 VEC(arm_exidx_entry_s
) **section_maps
;
2155 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2157 struct arm_exidx_data
*data
= arg
;
2160 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2161 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2165 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2166 const struct arm_exidx_entry
*rhs
)
2168 return lhs
->addr
< rhs
->addr
;
2171 static struct obj_section
*
2172 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2174 struct obj_section
*osect
;
2176 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2177 if (bfd_get_section_flags (objfile
->obfd
,
2178 osect
->the_bfd_section
) & SEC_ALLOC
)
2180 bfd_vma start
, size
;
2181 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2182 size
= bfd_get_section_size (osect
->the_bfd_section
);
2184 if (start
<= vma
&& vma
< start
+ size
)
2191 /* Parse contents of exception table and exception index sections
2192 of OBJFILE, and fill in the exception table entry cache.
2194 For each entry that refers to a standard ARM-defined personality
2195 routine, extract the frame unwinding instructions (from either
2196 the index or the table section). The unwinding instructions
2198 - extracting them from the rest of the table data
2199 - converting to host endianness
2200 - appending the implicit 0xb0 ("Finish") code
2202 The extracted and normalized instructions are stored for later
2203 retrieval by the arm_find_exidx_entry routine. */
2206 arm_exidx_new_objfile (struct objfile
*objfile
)
2208 struct cleanup
*cleanups
;
2209 struct arm_exidx_data
*data
;
2210 asection
*exidx
, *extab
;
2211 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2212 bfd_size_type exidx_size
= 0, extab_size
= 0;
2213 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2216 /* If we've already touched this file, do nothing. */
2217 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2219 cleanups
= make_cleanup (null_cleanup
, NULL
);
2221 /* Read contents of exception table and index. */
2222 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2225 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2226 exidx_size
= bfd_get_section_size (exidx
);
2227 exidx_data
= xmalloc (exidx_size
);
2228 make_cleanup (xfree
, exidx_data
);
2230 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2231 exidx_data
, 0, exidx_size
))
2233 do_cleanups (cleanups
);
2238 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2241 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2242 extab_size
= bfd_get_section_size (extab
);
2243 extab_data
= xmalloc (extab_size
);
2244 make_cleanup (xfree
, extab_data
);
2246 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2247 extab_data
, 0, extab_size
))
2249 do_cleanups (cleanups
);
2254 /* Allocate exception table data structure. */
2255 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2256 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2257 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2258 objfile
->obfd
->section_count
,
2259 VEC(arm_exidx_entry_s
) *);
2261 /* Fill in exception table. */
2262 for (i
= 0; i
< exidx_size
/ 8; i
++)
2264 struct arm_exidx_entry new_exidx_entry
;
2265 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2266 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2267 bfd_vma addr
= 0, word
= 0;
2268 int n_bytes
= 0, n_words
= 0;
2269 struct obj_section
*sec
;
2270 gdb_byte
*entry
= NULL
;
2272 /* Extract address of start of function. */
2273 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2274 idx
+= exidx_vma
+ i
* 8;
2276 /* Find section containing function and compute section offset. */
2277 sec
= arm_obj_section_from_vma (objfile
, idx
);
2280 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2282 /* Determine address of exception table entry. */
2285 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2287 else if ((val
& 0xff000000) == 0x80000000)
2289 /* Exception table entry embedded in .ARM.exidx
2290 -- must be short form. */
2294 else if (!(val
& 0x80000000))
2296 /* Exception table entry in .ARM.extab. */
2297 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2298 addr
+= exidx_vma
+ i
* 8 + 4;
2300 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2302 word
= bfd_h_get_32 (objfile
->obfd
,
2303 extab_data
+ addr
- extab_vma
);
2306 if ((word
& 0xff000000) == 0x80000000)
2311 else if ((word
& 0xff000000) == 0x81000000
2312 || (word
& 0xff000000) == 0x82000000)
2316 n_words
= ((word
>> 16) & 0xff);
2318 else if (!(word
& 0x80000000))
2321 struct obj_section
*pers_sec
;
2322 int gnu_personality
= 0;
2324 /* Custom personality routine. */
2325 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2326 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2328 /* Check whether we've got one of the variants of the
2329 GNU personality routines. */
2330 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2333 static const char *personality
[] =
2335 "__gcc_personality_v0",
2336 "__gxx_personality_v0",
2337 "__gcj_personality_v0",
2338 "__gnu_objc_personality_v0",
2342 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2345 for (k
= 0; personality
[k
]; k
++)
2346 if (lookup_minimal_symbol_by_pc_name
2347 (pc
, personality
[k
], objfile
))
2349 gnu_personality
= 1;
2354 /* If so, the next word contains a word count in the high
2355 byte, followed by the same unwind instructions as the
2356 pre-defined forms. */
2358 && addr
+ 4 <= extab_vma
+ extab_size
)
2360 word
= bfd_h_get_32 (objfile
->obfd
,
2361 extab_data
+ addr
- extab_vma
);
2364 n_words
= ((word
>> 24) & 0xff);
2370 /* Sanity check address. */
2372 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2373 n_words
= n_bytes
= 0;
2375 /* The unwind instructions reside in WORD (only the N_BYTES least
2376 significant bytes are valid), followed by N_WORDS words in the
2377 extab section starting at ADDR. */
2378 if (n_bytes
|| n_words
)
2380 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2381 n_bytes
+ n_words
* 4 + 1);
2384 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2388 word
= bfd_h_get_32 (objfile
->obfd
,
2389 extab_data
+ addr
- extab_vma
);
2392 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2393 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2394 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2395 *p
++ = (gdb_byte
) (word
& 0xff);
2398 /* Implied "Finish" to terminate the list. */
2402 /* Push entry onto vector. They are guaranteed to always
2403 appear in order of increasing addresses. */
2404 new_exidx_entry
.addr
= idx
;
2405 new_exidx_entry
.entry
= entry
;
2406 VEC_safe_push (arm_exidx_entry_s
,
2407 data
->section_maps
[sec
->the_bfd_section
->index
],
2411 do_cleanups (cleanups
);
2414 /* Search for the exception table entry covering MEMADDR. If one is found,
2415 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2416 set *START to the start of the region covered by this entry. */
2419 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2421 struct obj_section
*sec
;
2423 sec
= find_pc_section (memaddr
);
2426 struct arm_exidx_data
*data
;
2427 VEC(arm_exidx_entry_s
) *map
;
2428 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2431 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2434 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2435 if (!VEC_empty (arm_exidx_entry_s
, map
))
2437 struct arm_exidx_entry
*map_sym
;
2439 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2440 arm_compare_exidx_entries
);
2442 /* VEC_lower_bound finds the earliest ordered insertion
2443 point. If the following symbol starts at this exact
2444 address, we use that; otherwise, the preceding
2445 exception table entry covers this address. */
2446 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2448 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2449 if (map_sym
->addr
== map_key
.addr
)
2452 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2453 return map_sym
->entry
;
2459 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2461 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2462 return map_sym
->entry
;
2471 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2472 instruction list from the ARM exception table entry ENTRY, allocate and
2473 return a prologue cache structure describing how to unwind this frame.
2475 Return NULL if the unwinding instruction list contains a "spare",
2476 "reserved" or "refuse to unwind" instruction as defined in section
2477 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2478 for the ARM Architecture" document. */
2480 static struct arm_prologue_cache
*
2481 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2486 struct arm_prologue_cache
*cache
;
2487 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2488 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2494 /* Whenever we reload SP, we actually have to retrieve its
2495 actual value in the current frame. */
2498 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2500 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2501 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2505 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2506 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2512 /* Decode next unwind instruction. */
2515 if ((insn
& 0xc0) == 0)
2517 int offset
= insn
& 0x3f;
2518 vsp
+= (offset
<< 2) + 4;
2520 else if ((insn
& 0xc0) == 0x40)
2522 int offset
= insn
& 0x3f;
2523 vsp
-= (offset
<< 2) + 4;
2525 else if ((insn
& 0xf0) == 0x80)
2527 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2530 /* The special case of an all-zero mask identifies
2531 "Refuse to unwind". We return NULL to fall back
2532 to the prologue analyzer. */
2536 /* Pop registers r4..r15 under mask. */
2537 for (i
= 0; i
< 12; i
++)
2538 if (mask
& (1 << i
))
2540 cache
->saved_regs
[4 + i
].addr
= vsp
;
2544 /* Special-case popping SP -- we need to reload vsp. */
2545 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2548 else if ((insn
& 0xf0) == 0x90)
2550 int reg
= insn
& 0xf;
2552 /* Reserved cases. */
2553 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2556 /* Set SP from another register and mark VSP for reload. */
2557 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2560 else if ((insn
& 0xf0) == 0xa0)
2562 int count
= insn
& 0x7;
2563 int pop_lr
= (insn
& 0x8) != 0;
2566 /* Pop r4..r[4+count]. */
2567 for (i
= 0; i
<= count
; i
++)
2569 cache
->saved_regs
[4 + i
].addr
= vsp
;
2573 /* If indicated by flag, pop LR as well. */
2576 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2580 else if (insn
== 0xb0)
2582 /* We could only have updated PC by popping into it; if so, it
2583 will show up as address. Otherwise, copy LR into PC. */
2584 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2585 cache
->saved_regs
[ARM_PC_REGNUM
]
2586 = cache
->saved_regs
[ARM_LR_REGNUM
];
2591 else if (insn
== 0xb1)
2593 int mask
= *entry
++;
2596 /* All-zero mask and mask >= 16 is "spare". */
2597 if (mask
== 0 || mask
>= 16)
2600 /* Pop r0..r3 under mask. */
2601 for (i
= 0; i
< 4; i
++)
2602 if (mask
& (1 << i
))
2604 cache
->saved_regs
[i
].addr
= vsp
;
2608 else if (insn
== 0xb2)
2610 ULONGEST offset
= 0;
2615 offset
|= (*entry
& 0x7f) << shift
;
2618 while (*entry
++ & 0x80);
2620 vsp
+= 0x204 + (offset
<< 2);
2622 else if (insn
== 0xb3)
2624 int start
= *entry
>> 4;
2625 int count
= (*entry
++) & 0xf;
2628 /* Only registers D0..D15 are valid here. */
2629 if (start
+ count
>= 16)
2632 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2633 for (i
= 0; i
<= count
; i
++)
2635 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2639 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2642 else if ((insn
& 0xf8) == 0xb8)
2644 int count
= insn
& 0x7;
2647 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2648 for (i
= 0; i
<= count
; i
++)
2650 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2654 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2657 else if (insn
== 0xc6)
2659 int start
= *entry
>> 4;
2660 int count
= (*entry
++) & 0xf;
2663 /* Only registers WR0..WR15 are valid. */
2664 if (start
+ count
>= 16)
2667 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2668 for (i
= 0; i
<= count
; i
++)
2670 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2674 else if (insn
== 0xc7)
2676 int mask
= *entry
++;
2679 /* All-zero mask and mask >= 16 is "spare". */
2680 if (mask
== 0 || mask
>= 16)
2683 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2684 for (i
= 0; i
< 4; i
++)
2685 if (mask
& (1 << i
))
2687 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2691 else if ((insn
& 0xf8) == 0xc0)
2693 int count
= insn
& 0x7;
2696 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2697 for (i
= 0; i
<= count
; i
++)
2699 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2703 else if (insn
== 0xc8)
2705 int start
= *entry
>> 4;
2706 int count
= (*entry
++) & 0xf;
2709 /* Only registers D0..D31 are valid. */
2710 if (start
+ count
>= 16)
2713 /* Pop VFP double-precision registers
2714 D[16+start]..D[16+start+count]. */
2715 for (i
= 0; i
<= count
; i
++)
2717 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2721 else if (insn
== 0xc9)
2723 int start
= *entry
>> 4;
2724 int count
= (*entry
++) & 0xf;
2727 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2728 for (i
= 0; i
<= count
; i
++)
2730 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2734 else if ((insn
& 0xf8) == 0xd0)
2736 int count
= insn
& 0x7;
2739 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2740 for (i
= 0; i
<= count
; i
++)
2742 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2748 /* Everything else is "spare". */
2753 /* If we restore SP from a register, assume this was the frame register.
2754 Otherwise just fall back to SP as frame register. */
2755 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2756 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2758 cache
->framereg
= ARM_SP_REGNUM
;
2760 /* Determine offset to previous frame. */
2762 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2764 /* We already got the previous SP. */
2765 cache
->prev_sp
= vsp
;
2770 /* Unwinding via ARM exception table entries. Note that the sniffer
2771 already computes a filled-in prologue cache, which is then used
2772 with the same arm_prologue_this_id and arm_prologue_prev_register
2773 routines also used for prologue-parsing based unwinding. */
2776 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2777 struct frame_info
*this_frame
,
2778 void **this_prologue_cache
)
2780 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2781 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2782 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2783 struct arm_prologue_cache
*cache
;
2786 /* See if we have an ARM exception table entry covering this address. */
2787 addr_in_block
= get_frame_address_in_block (this_frame
);
2788 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2792 /* The ARM exception table does not describe unwind information
2793 for arbitrary PC values, but is guaranteed to be correct only
2794 at call sites. We have to decide here whether we want to use
2795 ARM exception table information for this frame, or fall back
2796 to using prologue parsing. (Note that if we have DWARF CFI,
2797 this sniffer isn't even called -- CFI is always preferred.)
2799 Before we make this decision, however, we check whether we
2800 actually have *symbol* information for the current frame.
2801 If not, prologue parsing would not work anyway, so we might
2802 as well use the exception table and hope for the best. */
2803 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2807 /* If the next frame is "normal", we are at a call site in this
2808 frame, so exception information is guaranteed to be valid. */
2809 if (get_next_frame (this_frame
)
2810 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2813 /* We also assume exception information is valid if we're currently
2814 blocked in a system call. The system library is supposed to
2815 ensure this, so that e.g. pthread cancellation works. */
2816 if (arm_frame_is_thumb (this_frame
))
2820 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2821 byte_order_for_code
, &insn
)
2822 && (insn
& 0xff00) == 0xdf00 /* svc */)
2829 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2830 byte_order_for_code
, &insn
)
2831 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2835 /* Bail out if we don't know that exception information is valid. */
2839 /* The ARM exception index does not mark the *end* of the region
2840 covered by the entry, and some functions will not have any entry.
2841 To correctly recognize the end of the covered region, the linker
2842 should have inserted dummy records with a CANTUNWIND marker.
2844 Unfortunately, current versions of GNU ld do not reliably do
2845 this, and thus we may have found an incorrect entry above.
2846 As a (temporary) sanity check, we only use the entry if it
2847 lies *within* the bounds of the function. Note that this check
2848 might reject perfectly valid entries that just happen to cover
2849 multiple functions; therefore this check ought to be removed
2850 once the linker is fixed. */
2851 if (func_start
> exidx_region
)
2855 /* Decode the list of unwinding instructions into a prologue cache.
2856 Note that this may fail due to e.g. a "refuse to unwind" code. */
2857 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2861 *this_prologue_cache
= cache
;
2865 struct frame_unwind arm_exidx_unwind
= {
2867 default_frame_unwind_stop_reason
,
2868 arm_prologue_this_id
,
2869 arm_prologue_prev_register
,
2871 arm_exidx_unwind_sniffer
2874 static struct arm_prologue_cache
*
2875 arm_make_stub_cache (struct frame_info
*this_frame
)
2877 struct arm_prologue_cache
*cache
;
2879 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2880 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2882 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2887 /* Our frame ID for a stub frame is the current SP and LR. */
2890 arm_stub_this_id (struct frame_info
*this_frame
,
2892 struct frame_id
*this_id
)
2894 struct arm_prologue_cache
*cache
;
2896 if (*this_cache
== NULL
)
2897 *this_cache
= arm_make_stub_cache (this_frame
);
2898 cache
= *this_cache
;
2900 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2904 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2905 struct frame_info
*this_frame
,
2906 void **this_prologue_cache
)
2908 CORE_ADDR addr_in_block
;
2911 addr_in_block
= get_frame_address_in_block (this_frame
);
2912 if (in_plt_section (addr_in_block
, NULL
)
2913 /* We also use the stub winder if the target memory is unreadable
2914 to avoid having the prologue unwinder trying to read it. */
2915 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2921 struct frame_unwind arm_stub_unwind
= {
2923 default_frame_unwind_stop_reason
,
2925 arm_prologue_prev_register
,
2927 arm_stub_unwind_sniffer
2931 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
2933 struct arm_prologue_cache
*cache
;
2935 if (*this_cache
== NULL
)
2936 *this_cache
= arm_make_prologue_cache (this_frame
);
2937 cache
= *this_cache
;
2939 return cache
->prev_sp
- cache
->framesize
;
2942 struct frame_base arm_normal_base
= {
2943 &arm_prologue_unwind
,
2944 arm_normal_frame_base
,
2945 arm_normal_frame_base
,
2946 arm_normal_frame_base
2949 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2950 dummy frame. The frame ID's base needs to match the TOS value
2951 saved by save_dummy_frame_tos() and returned from
2952 arm_push_dummy_call, and the PC needs to match the dummy frame's
2955 static struct frame_id
2956 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2958 return frame_id_build (get_frame_register_unsigned (this_frame
,
2960 get_frame_pc (this_frame
));
2963 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2964 be used to construct the previous frame's ID, after looking up the
2965 containing function). */
2968 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2971 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
2972 return arm_addr_bits_remove (gdbarch
, pc
);
2976 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2978 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2981 static struct value
*
2982 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2985 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
2987 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2992 /* The PC is normally copied from the return column, which
2993 describes saves of LR. However, that version may have an
2994 extra bit set to indicate Thumb state. The bit is not
2996 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2997 return frame_unwind_got_constant (this_frame
, regnum
,
2998 arm_addr_bits_remove (gdbarch
, lr
));
3001 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3002 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3003 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3004 if (IS_THUMB_ADDR (lr
))
3008 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3011 internal_error (__FILE__
, __LINE__
,
3012 _("Unexpected register %d"), regnum
);
3017 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3018 struct dwarf2_frame_state_reg
*reg
,
3019 struct frame_info
*this_frame
)
3025 reg
->how
= DWARF2_FRAME_REG_FN
;
3026 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3029 reg
->how
= DWARF2_FRAME_REG_CFA
;
3034 /* Return true if we are in the function's epilogue, i.e. after the
3035 instruction that destroyed the function's stack frame. */
3038 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3040 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3041 unsigned int insn
, insn2
;
3042 int found_return
= 0, found_stack_adjust
= 0;
3043 CORE_ADDR func_start
, func_end
;
3047 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3050 /* The epilogue is a sequence of instructions along the following lines:
3052 - add stack frame size to SP or FP
3053 - [if frame pointer used] restore SP from FP
3054 - restore registers from SP [may include PC]
3055 - a return-type instruction [if PC wasn't already restored]
3057 In a first pass, we scan forward from the current PC and verify the
3058 instructions we find as compatible with this sequence, ending in a
3061 However, this is not sufficient to distinguish indirect function calls
3062 within a function from indirect tail calls in the epilogue in some cases.
3063 Therefore, if we didn't already find any SP-changing instruction during
3064 forward scan, we add a backward scanning heuristic to ensure we actually
3065 are in the epilogue. */
3068 while (scan_pc
< func_end
&& !found_return
)
3070 if (target_read_memory (scan_pc
, buf
, 2))
3074 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3076 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3078 else if (insn
== 0x46f7) /* mov pc, lr */
3080 else if (insn
== 0x46bd) /* mov sp, r7 */
3081 found_stack_adjust
= 1;
3082 else if ((insn
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3083 found_stack_adjust
= 1;
3084 else if ((insn
& 0xfe00) == 0xbc00) /* pop <registers> */
3086 found_stack_adjust
= 1;
3087 if (insn
& 0x0100) /* <registers> include PC. */
3090 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3092 if (target_read_memory (scan_pc
, buf
, 2))
3096 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3098 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3100 found_stack_adjust
= 1;
3101 if (insn2
& 0x8000) /* <registers> include PC. */
3104 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3105 && (insn2
& 0x0fff) == 0x0b04)
3107 found_stack_adjust
= 1;
3108 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3111 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3112 && (insn2
& 0x0e00) == 0x0a00)
3113 found_stack_adjust
= 1;
3124 /* Since any instruction in the epilogue sequence, with the possible
3125 exception of return itself, updates the stack pointer, we need to
3126 scan backwards for at most one instruction. Try either a 16-bit or
3127 a 32-bit instruction. This is just a heuristic, so we do not worry
3128 too much about false positives. */
3130 if (!found_stack_adjust
)
3132 if (pc
- 4 < func_start
)
3134 if (target_read_memory (pc
- 4, buf
, 4))
3137 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3138 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3140 if (insn2
== 0x46bd) /* mov sp, r7 */
3141 found_stack_adjust
= 1;
3142 else if ((insn2
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3143 found_stack_adjust
= 1;
3144 else if ((insn2
& 0xff00) == 0xbc00) /* pop <registers> without PC */
3145 found_stack_adjust
= 1;
3146 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3147 found_stack_adjust
= 1;
3148 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3149 && (insn2
& 0x0fff) == 0x0b04)
3150 found_stack_adjust
= 1;
3151 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3152 && (insn2
& 0x0e00) == 0x0a00)
3153 found_stack_adjust
= 1;
3156 return found_stack_adjust
;
3159 /* Return true if we are in the function's epilogue, i.e. after the
3160 instruction that destroyed the function's stack frame. */
3163 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3165 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3167 int found_return
, found_stack_adjust
;
3168 CORE_ADDR func_start
, func_end
;
3170 if (arm_pc_is_thumb (gdbarch
, pc
))
3171 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3173 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3176 /* We are in the epilogue if the previous instruction was a stack
3177 adjustment and the next instruction is a possible return (bx, mov
3178 pc, or pop). We could have to scan backwards to find the stack
3179 adjustment, or forwards to find the return, but this is a decent
3180 approximation. First scan forwards. */
3183 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3184 if (bits (insn
, 28, 31) != INST_NV
)
3186 if ((insn
& 0x0ffffff0) == 0x012fff10)
3189 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3192 else if ((insn
& 0x0fff0000) == 0x08bd0000
3193 && (insn
& 0x0000c000) != 0)
3194 /* POP (LDMIA), including PC or LR. */
3201 /* Scan backwards. This is just a heuristic, so do not worry about
3202 false positives from mode changes. */
3204 if (pc
< func_start
+ 4)
3207 found_stack_adjust
= 0;
3208 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3209 if (bits (insn
, 28, 31) != INST_NV
)
3211 if ((insn
& 0x0df0f000) == 0x0080d000)
3212 /* ADD SP (register or immediate). */
3213 found_stack_adjust
= 1;
3214 else if ((insn
& 0x0df0f000) == 0x0040d000)
3215 /* SUB SP (register or immediate). */
3216 found_stack_adjust
= 1;
3217 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
3219 found_stack_adjust
= 1;
3220 else if ((insn
& 0x0fff0000) == 0x08bd0000)
3222 found_stack_adjust
= 1;
3225 if (found_stack_adjust
)
3232 /* When arguments must be pushed onto the stack, they go on in reverse
3233 order. The code below implements a FILO (stack) to do this. */
3238 struct stack_item
*prev
;
3242 static struct stack_item
*
3243 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3245 struct stack_item
*si
;
3246 si
= xmalloc (sizeof (struct stack_item
));
3247 si
->data
= xmalloc (len
);
3250 memcpy (si
->data
, contents
, len
);
3254 static struct stack_item
*
3255 pop_stack_item (struct stack_item
*si
)
3257 struct stack_item
*dead
= si
;
3265 /* Return the alignment (in bytes) of the given type. */
3268 arm_type_align (struct type
*t
)
3274 t
= check_typedef (t
);
3275 switch (TYPE_CODE (t
))
3278 /* Should never happen. */
3279 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3283 case TYPE_CODE_ENUM
:
3287 case TYPE_CODE_RANGE
:
3288 case TYPE_CODE_BITSTRING
:
3290 case TYPE_CODE_CHAR
:
3291 case TYPE_CODE_BOOL
:
3292 return TYPE_LENGTH (t
);
3294 case TYPE_CODE_ARRAY
:
3295 case TYPE_CODE_COMPLEX
:
3296 /* TODO: What about vector types? */
3297 return arm_type_align (TYPE_TARGET_TYPE (t
));
3299 case TYPE_CODE_STRUCT
:
3300 case TYPE_CODE_UNION
:
3302 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3304 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3312 /* Possible base types for a candidate for passing and returning in
3315 enum arm_vfp_cprc_base_type
3324 /* The length of one element of base type B. */
3327 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3331 case VFP_CPRC_SINGLE
:
3333 case VFP_CPRC_DOUBLE
:
3335 case VFP_CPRC_VEC64
:
3337 case VFP_CPRC_VEC128
:
3340 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3345 /* The character ('s', 'd' or 'q') for the type of VFP register used
3346 for passing base type B. */
3349 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3353 case VFP_CPRC_SINGLE
:
3355 case VFP_CPRC_DOUBLE
:
3357 case VFP_CPRC_VEC64
:
3359 case VFP_CPRC_VEC128
:
3362 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3367 /* Determine whether T may be part of a candidate for passing and
3368 returning in VFP registers, ignoring the limit on the total number
3369 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3370 classification of the first valid component found; if it is not
3371 VFP_CPRC_UNKNOWN, all components must have the same classification
3372 as *BASE_TYPE. If it is found that T contains a type not permitted
3373 for passing and returning in VFP registers, a type differently
3374 classified from *BASE_TYPE, or two types differently classified
3375 from each other, return -1, otherwise return the total number of
3376 base-type elements found (possibly 0 in an empty structure or
3377 array). Vectors and complex types are not currently supported,
3378 matching the generic AAPCS support. */
3381 arm_vfp_cprc_sub_candidate (struct type
*t
,
3382 enum arm_vfp_cprc_base_type
*base_type
)
3384 t
= check_typedef (t
);
3385 switch (TYPE_CODE (t
))
3388 switch (TYPE_LENGTH (t
))
3391 if (*base_type
== VFP_CPRC_UNKNOWN
)
3392 *base_type
= VFP_CPRC_SINGLE
;
3393 else if (*base_type
!= VFP_CPRC_SINGLE
)
3398 if (*base_type
== VFP_CPRC_UNKNOWN
)
3399 *base_type
= VFP_CPRC_DOUBLE
;
3400 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3409 case TYPE_CODE_ARRAY
:
3413 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3416 if (TYPE_LENGTH (t
) == 0)
3418 gdb_assert (count
== 0);
3421 else if (count
== 0)
3423 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3424 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3425 return TYPE_LENGTH (t
) / unitlen
;
3429 case TYPE_CODE_STRUCT
:
3434 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3436 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3438 if (sub_count
== -1)
3442 if (TYPE_LENGTH (t
) == 0)
3444 gdb_assert (count
== 0);
3447 else if (count
== 0)
3449 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3450 if (TYPE_LENGTH (t
) != unitlen
* count
)
3455 case TYPE_CODE_UNION
:
3460 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3462 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3464 if (sub_count
== -1)
3466 count
= (count
> sub_count
? count
: sub_count
);
3468 if (TYPE_LENGTH (t
) == 0)
3470 gdb_assert (count
== 0);
3473 else if (count
== 0)
3475 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3476 if (TYPE_LENGTH (t
) != unitlen
* count
)
3488 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3489 if passed to or returned from a non-variadic function with the VFP
3490 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3491 *BASE_TYPE to the base type for T and *COUNT to the number of
3492 elements of that base type before returning. */
3495 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3498 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3499 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3500 if (c
<= 0 || c
> 4)
3507 /* Return 1 if the VFP ABI should be used for passing arguments to and
3508 returning values from a function of type FUNC_TYPE, 0
3512 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3515 /* Variadic functions always use the base ABI. Assume that functions
3516 without debug info are not variadic. */
3517 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3519 /* The VFP ABI is only supported as a variant of AAPCS. */
3520 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3522 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3525 /* We currently only support passing parameters in integer registers, which
3526 conforms with GCC's default model, and VFP argument passing following
3527 the VFP variant of AAPCS. Several other variants exist and
3528 we should probably support some of them based on the selected ABI. */
3531 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3532 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3533 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3534 CORE_ADDR struct_addr
)
3536 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3540 struct stack_item
*si
= NULL
;
3543 unsigned vfp_regs_free
= (1 << 16) - 1;
3545 /* Determine the type of this function and whether the VFP ABI
3547 ftype
= check_typedef (value_type (function
));
3548 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3549 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3550 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3552 /* Set the return address. For the ARM, the return breakpoint is
3553 always at BP_ADDR. */
3554 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3556 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3558 /* Walk through the list of args and determine how large a temporary
3559 stack is required. Need to take care here as structs may be
3560 passed on the stack, and we have to push them. */
3563 argreg
= ARM_A1_REGNUM
;
3566 /* The struct_return pointer occupies the first parameter
3567 passing register. */
3571 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3572 gdbarch_register_name (gdbarch
, argreg
),
3573 paddress (gdbarch
, struct_addr
));
3574 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3578 for (argnum
= 0; argnum
< nargs
; argnum
++)
3581 struct type
*arg_type
;
3582 struct type
*target_type
;
3583 enum type_code typecode
;
3584 const bfd_byte
*val
;
3586 enum arm_vfp_cprc_base_type vfp_base_type
;
3588 int may_use_core_reg
= 1;
3590 arg_type
= check_typedef (value_type (args
[argnum
]));
3591 len
= TYPE_LENGTH (arg_type
);
3592 target_type
= TYPE_TARGET_TYPE (arg_type
);
3593 typecode
= TYPE_CODE (arg_type
);
3594 val
= value_contents (args
[argnum
]);
3596 align
= arm_type_align (arg_type
);
3597 /* Round alignment up to a whole number of words. */
3598 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3599 /* Different ABIs have different maximum alignments. */
3600 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3602 /* The APCS ABI only requires word alignment. */
3603 align
= INT_REGISTER_SIZE
;
3607 /* The AAPCS requires at most doubleword alignment. */
3608 if (align
> INT_REGISTER_SIZE
* 2)
3609 align
= INT_REGISTER_SIZE
* 2;
3613 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3621 /* Because this is a CPRC it cannot go in a core register or
3622 cause a core register to be skipped for alignment.
3623 Either it goes in VFP registers and the rest of this loop
3624 iteration is skipped for this argument, or it goes on the
3625 stack (and the stack alignment code is correct for this
3627 may_use_core_reg
= 0;
3629 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3630 shift
= unit_length
/ 4;
3631 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3632 for (regno
= 0; regno
< 16; regno
+= shift
)
3633 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3642 vfp_regs_free
&= ~(mask
<< regno
);
3643 reg_scaled
= regno
/ shift
;
3644 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3645 for (i
= 0; i
< vfp_base_count
; i
++)
3649 if (reg_char
== 'q')
3650 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3651 val
+ i
* unit_length
);
3654 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
3655 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3657 regcache_cooked_write (regcache
, regnum
,
3658 val
+ i
* unit_length
);
3665 /* This CPRC could not go in VFP registers, so all VFP
3666 registers are now marked as used. */
3671 /* Push stack padding for dowubleword alignment. */
3672 if (nstack
& (align
- 1))
3674 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3675 nstack
+= INT_REGISTER_SIZE
;
3678 /* Doubleword aligned quantities must go in even register pairs. */
3679 if (may_use_core_reg
3680 && argreg
<= ARM_LAST_ARG_REGNUM
3681 && align
> INT_REGISTER_SIZE
3685 /* If the argument is a pointer to a function, and it is a
3686 Thumb function, create a LOCAL copy of the value and set
3687 the THUMB bit in it. */
3688 if (TYPE_CODE_PTR
== typecode
3689 && target_type
!= NULL
3690 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3692 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3693 if (arm_pc_is_thumb (gdbarch
, regval
))
3695 bfd_byte
*copy
= alloca (len
);
3696 store_unsigned_integer (copy
, len
, byte_order
,
3697 MAKE_THUMB_ADDR (regval
));
3702 /* Copy the argument to general registers or the stack in
3703 register-sized pieces. Large arguments are split between
3704 registers and stack. */
3707 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3709 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3711 /* The argument is being passed in a general purpose
3714 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3715 if (byte_order
== BFD_ENDIAN_BIG
)
3716 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3718 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3720 gdbarch_register_name
3722 phex (regval
, INT_REGISTER_SIZE
));
3723 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3728 /* Push the arguments onto the stack. */
3730 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3732 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3733 nstack
+= INT_REGISTER_SIZE
;
3740 /* If we have an odd number of words to push, then decrement the stack
3741 by one word now, so first stack argument will be dword aligned. */
3748 write_memory (sp
, si
->data
, si
->len
);
3749 si
= pop_stack_item (si
);
3752 /* Finally, update teh SP register. */
3753 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3759 /* Always align the frame to an 8-byte boundary. This is required on
3760 some platforms and harmless on the rest. */
3763 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3765 /* Align the stack to eight bytes. */
3766 return sp
& ~ (CORE_ADDR
) 7;
3770 print_fpu_flags (int flags
)
3772 if (flags
& (1 << 0))
3773 fputs ("IVO ", stdout
);
3774 if (flags
& (1 << 1))
3775 fputs ("DVZ ", stdout
);
3776 if (flags
& (1 << 2))
3777 fputs ("OFL ", stdout
);
3778 if (flags
& (1 << 3))
3779 fputs ("UFL ", stdout
);
3780 if (flags
& (1 << 4))
3781 fputs ("INX ", stdout
);
3785 /* Print interesting information about the floating point processor
3786 (if present) or emulator. */
3788 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3789 struct frame_info
*frame
, const char *args
)
3791 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3794 type
= (status
>> 24) & 127;
3795 if (status
& (1 << 31))
3796 printf (_("Hardware FPU type %d\n"), type
);
3798 printf (_("Software FPU type %d\n"), type
);
3799 /* i18n: [floating point unit] mask */
3800 fputs (_("mask: "), stdout
);
3801 print_fpu_flags (status
>> 16);
3802 /* i18n: [floating point unit] flags */
3803 fputs (_("flags: "), stdout
);
3804 print_fpu_flags (status
);
3807 /* Construct the ARM extended floating point type. */
3808 static struct type
*
3809 arm_ext_type (struct gdbarch
*gdbarch
)
3811 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3813 if (!tdep
->arm_ext_type
)
3815 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3816 floatformats_arm_ext
);
3818 return tdep
->arm_ext_type
;
3821 static struct type
*
3822 arm_neon_double_type (struct gdbarch
*gdbarch
)
3824 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3826 if (tdep
->neon_double_type
== NULL
)
3828 struct type
*t
, *elem
;
3830 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3832 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3833 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3834 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3835 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3836 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3837 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3838 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3839 append_composite_type_field (t
, "u64", elem
);
3840 elem
= builtin_type (gdbarch
)->builtin_float
;
3841 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3842 elem
= builtin_type (gdbarch
)->builtin_double
;
3843 append_composite_type_field (t
, "f64", elem
);
3845 TYPE_VECTOR (t
) = 1;
3846 TYPE_NAME (t
) = "neon_d";
3847 tdep
->neon_double_type
= t
;
3850 return tdep
->neon_double_type
;
3853 /* FIXME: The vector types are not correctly ordered on big-endian
3854 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3855 bits of d0 - regardless of what unit size is being held in d0. So
3856 the offset of the first uint8 in d0 is 7, but the offset of the
3857 first float is 4. This code works as-is for little-endian
3860 static struct type
*
3861 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3865 if (tdep
->neon_quad_type
== NULL
)
3867 struct type
*t
, *elem
;
3869 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
3871 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3872 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
3873 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3874 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
3875 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3876 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
3877 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3878 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
3879 elem
= builtin_type (gdbarch
)->builtin_float
;
3880 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
3881 elem
= builtin_type (gdbarch
)->builtin_double
;
3882 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
3884 TYPE_VECTOR (t
) = 1;
3885 TYPE_NAME (t
) = "neon_q";
3886 tdep
->neon_quad_type
= t
;
3889 return tdep
->neon_quad_type
;
3892 /* Return the GDB type object for the "standard" data type of data in
3895 static struct type
*
3896 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
3898 int num_regs
= gdbarch_num_regs (gdbarch
);
3900 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
3901 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
3902 return builtin_type (gdbarch
)->builtin_float
;
3904 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
3905 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
3906 return arm_neon_quad_type (gdbarch
);
3908 /* If the target description has register information, we are only
3909 in this function so that we can override the types of
3910 double-precision registers for NEON. */
3911 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
3913 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
3915 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
3916 && TYPE_CODE (t
) == TYPE_CODE_FLT
3917 && gdbarch_tdep (gdbarch
)->have_neon
)
3918 return arm_neon_double_type (gdbarch
);
3923 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
3925 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3926 return builtin_type (gdbarch
)->builtin_void
;
3928 return arm_ext_type (gdbarch
);
3930 else if (regnum
== ARM_SP_REGNUM
)
3931 return builtin_type (gdbarch
)->builtin_data_ptr
;
3932 else if (regnum
== ARM_PC_REGNUM
)
3933 return builtin_type (gdbarch
)->builtin_func_ptr
;
3934 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
3935 /* These registers are only supported on targets which supply
3936 an XML description. */
3937 return builtin_type (gdbarch
)->builtin_int0
;
3939 return builtin_type (gdbarch
)->builtin_uint32
;
3942 /* Map a DWARF register REGNUM onto the appropriate GDB register
3946 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3948 /* Core integer regs. */
3949 if (reg
>= 0 && reg
<= 15)
3952 /* Legacy FPA encoding. These were once used in a way which
3953 overlapped with VFP register numbering, so their use is
3954 discouraged, but GDB doesn't support the ARM toolchain
3955 which used them for VFP. */
3956 if (reg
>= 16 && reg
<= 23)
3957 return ARM_F0_REGNUM
+ reg
- 16;
3959 /* New assignments for the FPA registers. */
3960 if (reg
>= 96 && reg
<= 103)
3961 return ARM_F0_REGNUM
+ reg
- 96;
3963 /* WMMX register assignments. */
3964 if (reg
>= 104 && reg
<= 111)
3965 return ARM_WCGR0_REGNUM
+ reg
- 104;
3967 if (reg
>= 112 && reg
<= 127)
3968 return ARM_WR0_REGNUM
+ reg
- 112;
3970 if (reg
>= 192 && reg
<= 199)
3971 return ARM_WC0_REGNUM
+ reg
- 192;
3973 /* VFP v2 registers. A double precision value is actually
3974 in d1 rather than s2, but the ABI only defines numbering
3975 for the single precision registers. This will "just work"
3976 in GDB for little endian targets (we'll read eight bytes,
3977 starting in s0 and then progressing to s1), but will be
3978 reversed on big endian targets with VFP. This won't
3979 be a problem for the new Neon quad registers; you're supposed
3980 to use DW_OP_piece for those. */
3981 if (reg
>= 64 && reg
<= 95)
3985 sprintf (name_buf
, "s%d", reg
- 64);
3986 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3990 /* VFP v3 / Neon registers. This range is also used for VFP v2
3991 registers, except that it now describes d0 instead of s0. */
3992 if (reg
>= 256 && reg
<= 287)
3996 sprintf (name_buf
, "d%d", reg
- 256);
3997 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4004 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4006 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4009 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4011 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4012 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4014 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4015 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4017 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4018 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4020 if (reg
< NUM_GREGS
)
4021 return SIM_ARM_R0_REGNUM
+ reg
;
4024 if (reg
< NUM_FREGS
)
4025 return SIM_ARM_FP0_REGNUM
+ reg
;
4028 if (reg
< NUM_SREGS
)
4029 return SIM_ARM_FPS_REGNUM
+ reg
;
4032 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4035 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4036 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4037 It is thought that this is is the floating-point register format on
4038 little-endian systems. */
4041 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4042 void *dbl
, int endianess
)
4046 if (endianess
== BFD_ENDIAN_BIG
)
4047 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4049 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4051 floatformat_from_doublest (fmt
, &d
, dbl
);
4055 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4060 floatformat_to_doublest (fmt
, ptr
, &d
);
4061 if (endianess
== BFD_ENDIAN_BIG
)
4062 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4064 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4069 condition_true (unsigned long cond
, unsigned long status_reg
)
4071 if (cond
== INST_AL
|| cond
== INST_NV
)
4077 return ((status_reg
& FLAG_Z
) != 0);
4079 return ((status_reg
& FLAG_Z
) == 0);
4081 return ((status_reg
& FLAG_C
) != 0);
4083 return ((status_reg
& FLAG_C
) == 0);
4085 return ((status_reg
& FLAG_N
) != 0);
4087 return ((status_reg
& FLAG_N
) == 0);
4089 return ((status_reg
& FLAG_V
) != 0);
4091 return ((status_reg
& FLAG_V
) == 0);
4093 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4095 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4097 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4099 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4101 return (((status_reg
& FLAG_Z
) == 0)
4102 && (((status_reg
& FLAG_N
) == 0)
4103 == ((status_reg
& FLAG_V
) == 0)));
4105 return (((status_reg
& FLAG_Z
) != 0)
4106 || (((status_reg
& FLAG_N
) == 0)
4107 != ((status_reg
& FLAG_V
) == 0)));
4112 static unsigned long
4113 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4114 unsigned long pc_val
, unsigned long status_reg
)
4116 unsigned long res
, shift
;
4117 int rm
= bits (inst
, 0, 3);
4118 unsigned long shifttype
= bits (inst
, 5, 6);
4122 int rs
= bits (inst
, 8, 11);
4123 shift
= (rs
== 15 ? pc_val
+ 8
4124 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4127 shift
= bits (inst
, 7, 11);
4129 res
= (rm
== ARM_PC_REGNUM
4130 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4131 : get_frame_register_unsigned (frame
, rm
));
4136 res
= shift
>= 32 ? 0 : res
<< shift
;
4140 res
= shift
>= 32 ? 0 : res
>> shift
;
4146 res
= ((res
& 0x80000000L
)
4147 ? ~((~res
) >> shift
) : res
>> shift
);
4150 case 3: /* ROR/RRX */
4153 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4155 res
= (res
>> shift
) | (res
<< (32 - shift
));
4159 return res
& 0xffffffff;
4162 /* Return number of 1-bits in VAL. */
4165 bitcount (unsigned long val
)
4168 for (nbits
= 0; val
!= 0; nbits
++)
4169 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4173 /* Return the size in bytes of the complete Thumb instruction whose
4174 first halfword is INST1. */
4177 thumb_insn_size (unsigned short inst1
)
4179 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4186 thumb_advance_itstate (unsigned int itstate
)
4188 /* Preserve IT[7:5], the first three bits of the condition. Shift
4189 the upcoming condition flags left by one bit. */
4190 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4192 /* If we have finished the IT block, clear the state. */
4193 if ((itstate
& 0x0f) == 0)
4199 /* Find the next PC after the current instruction executes. In some
4200 cases we can not statically determine the answer (see the IT state
4201 handling in this function); in that case, a breakpoint may be
4202 inserted in addition to the returned PC, which will be used to set
4203 another breakpoint by our caller. */
4206 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4208 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4209 struct address_space
*aspace
= get_frame_address_space (frame
);
4210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4211 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4212 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4213 unsigned short inst1
;
4214 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4215 unsigned long offset
;
4216 ULONGEST status
, itstate
;
4218 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4219 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4221 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4223 /* Thumb-2 conditional execution support. There are eight bits in
4224 the CPSR which describe conditional execution state. Once
4225 reconstructed (they're in a funny order), the low five bits
4226 describe the low bit of the condition for each instruction and
4227 how many instructions remain. The high three bits describe the
4228 base condition. One of the low four bits will be set if an IT
4229 block is active. These bits read as zero on earlier
4231 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4232 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4234 /* If-Then handling. On GNU/Linux, where this routine is used, we
4235 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4236 can disable execution of the undefined instruction. So we might
4237 miss the breakpoint if we set it on a skipped conditional
4238 instruction. Because conditional instructions can change the
4239 flags, affecting the execution of further instructions, we may
4240 need to set two breakpoints. */
4242 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4244 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4246 /* An IT instruction. Because this instruction does not
4247 modify the flags, we can accurately predict the next
4248 executed instruction. */
4249 itstate
= inst1
& 0x00ff;
4250 pc
+= thumb_insn_size (inst1
);
4252 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4254 inst1
= read_memory_unsigned_integer (pc
, 2,
4255 byte_order_for_code
);
4256 pc
+= thumb_insn_size (inst1
);
4257 itstate
= thumb_advance_itstate (itstate
);
4260 return MAKE_THUMB_ADDR (pc
);
4262 else if (itstate
!= 0)
4264 /* We are in a conditional block. Check the condition. */
4265 if (! condition_true (itstate
>> 4, status
))
4267 /* Advance to the next executed instruction. */
4268 pc
+= thumb_insn_size (inst1
);
4269 itstate
= thumb_advance_itstate (itstate
);
4271 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4273 inst1
= read_memory_unsigned_integer (pc
, 2,
4274 byte_order_for_code
);
4275 pc
+= thumb_insn_size (inst1
);
4276 itstate
= thumb_advance_itstate (itstate
);
4279 return MAKE_THUMB_ADDR (pc
);
4281 else if ((itstate
& 0x0f) == 0x08)
4283 /* This is the last instruction of the conditional
4284 block, and it is executed. We can handle it normally
4285 because the following instruction is not conditional,
4286 and we must handle it normally because it is
4287 permitted to branch. Fall through. */
4293 /* There are conditional instructions after this one.
4294 If this instruction modifies the flags, then we can
4295 not predict what the next executed instruction will
4296 be. Fortunately, this instruction is architecturally
4297 forbidden to branch; we know it will fall through.
4298 Start by skipping past it. */
4299 pc
+= thumb_insn_size (inst1
);
4300 itstate
= thumb_advance_itstate (itstate
);
4302 /* Set a breakpoint on the following instruction. */
4303 gdb_assert ((itstate
& 0x0f) != 0);
4304 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4305 MAKE_THUMB_ADDR (pc
));
4306 cond_negated
= (itstate
>> 4) & 1;
4308 /* Skip all following instructions with the same
4309 condition. If there is a later instruction in the IT
4310 block with the opposite condition, set the other
4311 breakpoint there. If not, then set a breakpoint on
4312 the instruction after the IT block. */
4315 inst1
= read_memory_unsigned_integer (pc
, 2,
4316 byte_order_for_code
);
4317 pc
+= thumb_insn_size (inst1
);
4318 itstate
= thumb_advance_itstate (itstate
);
4320 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4322 return MAKE_THUMB_ADDR (pc
);
4326 else if (itstate
& 0x0f)
4328 /* We are in a conditional block. Check the condition. */
4329 int cond
= itstate
>> 4;
4331 if (! condition_true (cond
, status
))
4332 /* Advance to the next instruction. All the 32-bit
4333 instructions share a common prefix. */
4334 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4336 /* Otherwise, handle the instruction normally. */
4339 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4343 /* Fetch the saved PC from the stack. It's stored above
4344 all of the other registers. */
4345 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4346 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4347 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4349 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4351 unsigned long cond
= bits (inst1
, 8, 11);
4352 if (cond
== 0x0f) /* 0x0f = SWI */
4354 struct gdbarch_tdep
*tdep
;
4355 tdep
= gdbarch_tdep (gdbarch
);
4357 if (tdep
->syscall_next_pc
!= NULL
)
4358 nextpc
= tdep
->syscall_next_pc (frame
);
4361 else if (cond
!= 0x0f && condition_true (cond
, status
))
4362 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4364 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4366 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4368 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4370 unsigned short inst2
;
4371 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4373 /* Default to the next instruction. */
4375 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4377 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4379 /* Branches and miscellaneous control instructions. */
4381 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4384 int j1
, j2
, imm1
, imm2
;
4386 imm1
= sbits (inst1
, 0, 10);
4387 imm2
= bits (inst2
, 0, 10);
4388 j1
= bit (inst2
, 13);
4389 j2
= bit (inst2
, 11);
4391 offset
= ((imm1
<< 12) + (imm2
<< 1));
4392 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4394 nextpc
= pc_val
+ offset
;
4395 /* For BLX make sure to clear the low bits. */
4396 if (bit (inst2
, 12) == 0)
4397 nextpc
= nextpc
& 0xfffffffc;
4399 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4401 /* SUBS PC, LR, #imm8. */
4402 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4403 nextpc
-= inst2
& 0x00ff;
4405 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4407 /* Conditional branch. */
4408 if (condition_true (bits (inst1
, 6, 9), status
))
4410 int sign
, j1
, j2
, imm1
, imm2
;
4412 sign
= sbits (inst1
, 10, 10);
4413 imm1
= bits (inst1
, 0, 5);
4414 imm2
= bits (inst2
, 0, 10);
4415 j1
= bit (inst2
, 13);
4416 j2
= bit (inst2
, 11);
4418 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4419 offset
+= (imm1
<< 12) + (imm2
<< 1);
4421 nextpc
= pc_val
+ offset
;
4425 else if ((inst1
& 0xfe50) == 0xe810)
4427 /* Load multiple or RFE. */
4428 int rn
, offset
, load_pc
= 1;
4430 rn
= bits (inst1
, 0, 3);
4431 if (bit (inst1
, 7) && !bit (inst1
, 8))
4434 if (!bit (inst2
, 15))
4436 offset
= bitcount (inst2
) * 4 - 4;
4438 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4441 if (!bit (inst2
, 15))
4445 else if (bit (inst1
, 7) && bit (inst1
, 8))
4450 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4460 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4461 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4464 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4466 /* MOV PC or MOVS PC. */
4467 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4468 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4470 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4474 int rn
, load_pc
= 1;
4476 rn
= bits (inst1
, 0, 3);
4477 base
= get_frame_register_unsigned (frame
, rn
);
4478 if (rn
== ARM_PC_REGNUM
)
4480 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4482 base
+= bits (inst2
, 0, 11);
4484 base
-= bits (inst2
, 0, 11);
4486 else if (bit (inst1
, 7))
4487 base
+= bits (inst2
, 0, 11);
4488 else if (bit (inst2
, 11))
4490 if (bit (inst2
, 10))
4493 base
+= bits (inst2
, 0, 7);
4495 base
-= bits (inst2
, 0, 7);
4498 else if ((inst2
& 0x0fc0) == 0x0000)
4500 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4501 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4508 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4510 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4513 CORE_ADDR tbl_reg
, table
, offset
, length
;
4515 tbl_reg
= bits (inst1
, 0, 3);
4516 if (tbl_reg
== 0x0f)
4517 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4519 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4521 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4522 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4523 nextpc
= pc_val
+ length
;
4525 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4528 CORE_ADDR tbl_reg
, table
, offset
, length
;
4530 tbl_reg
= bits (inst1
, 0, 3);
4531 if (tbl_reg
== 0x0f)
4532 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4534 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4536 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4537 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4538 nextpc
= pc_val
+ length
;
4541 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4543 if (bits (inst1
, 3, 6) == 0x0f)
4546 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4548 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4550 if (bits (inst1
, 3, 6) == 0x0f)
4553 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4555 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4557 else if ((inst1
& 0xf500) == 0xb100)
4560 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4561 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4563 if (bit (inst1
, 11) && reg
!= 0)
4564 nextpc
= pc_val
+ imm
;
4565 else if (!bit (inst1
, 11) && reg
== 0)
4566 nextpc
= pc_val
+ imm
;
4571 /* Get the raw next address. PC is the current program counter, in
4572 FRAME, which is assumed to be executing in ARM mode.
4574 The value returned has the execution state of the next instruction
4575 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4576 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4580 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4582 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4583 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4584 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4585 unsigned long pc_val
;
4586 unsigned long this_instr
;
4587 unsigned long status
;
4590 pc_val
= (unsigned long) pc
;
4591 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4593 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4594 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4596 if (bits (this_instr
, 28, 31) == INST_NV
)
4597 switch (bits (this_instr
, 24, 27))
4602 /* Branch with Link and change to Thumb. */
4603 nextpc
= BranchDest (pc
, this_instr
);
4604 nextpc
|= bit (this_instr
, 24) << 1;
4605 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4611 /* Coprocessor register transfer. */
4612 if (bits (this_instr
, 12, 15) == 15)
4613 error (_("Invalid update to pc in instruction"));
4616 else if (condition_true (bits (this_instr
, 28, 31), status
))
4618 switch (bits (this_instr
, 24, 27))
4621 case 0x1: /* data processing */
4625 unsigned long operand1
, operand2
, result
= 0;
4629 if (bits (this_instr
, 12, 15) != 15)
4632 if (bits (this_instr
, 22, 25) == 0
4633 && bits (this_instr
, 4, 7) == 9) /* multiply */
4634 error (_("Invalid update to pc in instruction"));
4636 /* BX <reg>, BLX <reg> */
4637 if (bits (this_instr
, 4, 27) == 0x12fff1
4638 || bits (this_instr
, 4, 27) == 0x12fff3)
4640 rn
= bits (this_instr
, 0, 3);
4641 nextpc
= ((rn
== ARM_PC_REGNUM
)
4643 : get_frame_register_unsigned (frame
, rn
));
4648 /* Multiply into PC. */
4649 c
= (status
& FLAG_C
) ? 1 : 0;
4650 rn
= bits (this_instr
, 16, 19);
4651 operand1
= ((rn
== ARM_PC_REGNUM
)
4653 : get_frame_register_unsigned (frame
, rn
));
4655 if (bit (this_instr
, 25))
4657 unsigned long immval
= bits (this_instr
, 0, 7);
4658 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4659 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4662 else /* operand 2 is a shifted register. */
4663 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4666 switch (bits (this_instr
, 21, 24))
4669 result
= operand1
& operand2
;
4673 result
= operand1
^ operand2
;
4677 result
= operand1
- operand2
;
4681 result
= operand2
- operand1
;
4685 result
= operand1
+ operand2
;
4689 result
= operand1
+ operand2
+ c
;
4693 result
= operand1
- operand2
+ c
;
4697 result
= operand2
- operand1
+ c
;
4703 case 0xb: /* tst, teq, cmp, cmn */
4704 result
= (unsigned long) nextpc
;
4708 result
= operand1
| operand2
;
4712 /* Always step into a function. */
4717 result
= operand1
& ~operand2
;
4725 /* In 26-bit APCS the bottom two bits of the result are
4726 ignored, and we always end up in ARM state. */
4728 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4736 case 0x5: /* data transfer */
4739 if (bit (this_instr
, 20))
4742 if (bits (this_instr
, 12, 15) == 15)
4748 if (bit (this_instr
, 22))
4749 error (_("Invalid update to pc in instruction"));
4751 /* byte write to PC */
4752 rn
= bits (this_instr
, 16, 19);
4753 base
= ((rn
== ARM_PC_REGNUM
)
4755 : get_frame_register_unsigned (frame
, rn
));
4757 if (bit (this_instr
, 24))
4760 int c
= (status
& FLAG_C
) ? 1 : 0;
4761 unsigned long offset
=
4762 (bit (this_instr
, 25)
4763 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4764 : bits (this_instr
, 0, 11));
4766 if (bit (this_instr
, 23))
4772 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4779 case 0x9: /* block transfer */
4780 if (bit (this_instr
, 20))
4783 if (bit (this_instr
, 15))
4787 unsigned long rn_val
4788 = get_frame_register_unsigned (frame
,
4789 bits (this_instr
, 16, 19));
4791 if (bit (this_instr
, 23))
4794 unsigned long reglist
= bits (this_instr
, 0, 14);
4795 offset
= bitcount (reglist
) * 4;
4796 if (bit (this_instr
, 24)) /* pre */
4799 else if (bit (this_instr
, 24))
4803 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
4810 case 0xb: /* branch & link */
4811 case 0xa: /* branch */
4813 nextpc
= BranchDest (pc
, this_instr
);
4819 case 0xe: /* coproc ops */
4823 struct gdbarch_tdep
*tdep
;
4824 tdep
= gdbarch_tdep (gdbarch
);
4826 if (tdep
->syscall_next_pc
!= NULL
)
4827 nextpc
= tdep
->syscall_next_pc (frame
);
4833 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
4841 /* Determine next PC after current instruction executes. Will call either
4842 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4843 loop is detected. */
4846 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
4850 if (arm_frame_is_thumb (frame
))
4852 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
4853 if (nextpc
== MAKE_THUMB_ADDR (pc
))
4854 error (_("Infinite loop detected"));
4858 nextpc
= arm_get_next_pc_raw (frame
, pc
);
4860 error (_("Infinite loop detected"));
4866 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4867 of the appropriate mode (as encoded in the PC value), even if this
4868 differs from what would be expected according to the symbol tables. */
4871 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4872 struct address_space
*aspace
,
4875 struct cleanup
*old_chain
4876 = make_cleanup_restore_integer (&arm_override_mode
);
4878 arm_override_mode
= IS_THUMB_ADDR (pc
);
4879 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4881 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4883 do_cleanups (old_chain
);
4886 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
4887 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
4888 is found, attempt to step through it. A breakpoint is placed at the end of
4892 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
4894 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4895 struct address_space
*aspace
= get_frame_address_space (frame
);
4896 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4897 CORE_ADDR pc
= get_frame_pc (frame
);
4898 CORE_ADDR breaks
[2] = {-1, -1};
4900 unsigned short insn1
, insn2
;
4903 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4904 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4905 ULONGEST status
, itstate
;
4907 /* We currently do not support atomic sequences within an IT block. */
4908 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4909 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4913 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
4914 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4916 if (thumb_insn_size (insn1
) != 4)
4919 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4921 if (!((insn1
& 0xfff0) == 0xe850
4922 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
4925 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
4927 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
4929 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4932 if (thumb_insn_size (insn1
) != 4)
4934 /* Assume that there is at most one conditional branch in the
4935 atomic sequence. If a conditional branch is found, put a
4936 breakpoint in its destination address. */
4937 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
4939 if (last_breakpoint
> 0)
4940 return 0; /* More than one conditional branch found,
4941 fallback to the standard code. */
4943 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
4947 /* We do not support atomic sequences that use any *other*
4948 instructions but conditional branches to change the PC.
4949 Fall back to standard code to avoid losing control of
4951 else if (thumb_instruction_changes_pc (insn1
))
4956 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4959 /* Assume that there is at most one conditional branch in the
4960 atomic sequence. If a conditional branch is found, put a
4961 breakpoint in its destination address. */
4962 if ((insn1
& 0xf800) == 0xf000
4963 && (insn2
& 0xd000) == 0x8000
4964 && (insn1
& 0x0380) != 0x0380)
4966 int sign
, j1
, j2
, imm1
, imm2
;
4967 unsigned int offset
;
4969 sign
= sbits (insn1
, 10, 10);
4970 imm1
= bits (insn1
, 0, 5);
4971 imm2
= bits (insn2
, 0, 10);
4972 j1
= bit (insn2
, 13);
4973 j2
= bit (insn2
, 11);
4975 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4976 offset
+= (imm1
<< 12) + (imm2
<< 1);
4978 if (last_breakpoint
> 0)
4979 return 0; /* More than one conditional branch found,
4980 fallback to the standard code. */
4982 breaks
[1] = loc
+ offset
;
4986 /* We do not support atomic sequences that use any *other*
4987 instructions but conditional branches to change the PC.
4988 Fall back to standard code to avoid losing control of
4990 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
4993 /* If we find a strex{,b,h,d}, we're done. */
4994 if ((insn1
& 0xfff0) == 0xe840
4995 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5000 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5001 if (insn_count
== atomic_sequence_length
)
5004 /* Insert a breakpoint right after the end of the atomic sequence. */
5007 /* Check for duplicated breakpoints. Check also for a breakpoint
5008 placed (branch instruction's destination) anywhere in sequence. */
5010 && (breaks
[1] == breaks
[0]
5011 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5012 last_breakpoint
= 0;
5014 /* Effectively inserts the breakpoints. */
5015 for (index
= 0; index
<= last_breakpoint
; index
++)
5016 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5017 MAKE_THUMB_ADDR (breaks
[index
]));
5023 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5025 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5026 struct address_space
*aspace
= get_frame_address_space (frame
);
5027 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5028 CORE_ADDR pc
= get_frame_pc (frame
);
5029 CORE_ADDR breaks
[2] = {-1, -1};
5034 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5035 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5037 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5038 Note that we do not currently support conditionally executed atomic
5040 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5042 if ((insn
& 0xff9000f0) != 0xe1900090)
5045 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5047 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5049 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5052 /* Assume that there is at most one conditional branch in the atomic
5053 sequence. If a conditional branch is found, put a breakpoint in
5054 its destination address. */
5055 if (bits (insn
, 24, 27) == 0xa)
5057 if (last_breakpoint
> 0)
5058 return 0; /* More than one conditional branch found, fallback
5059 to the standard single-step code. */
5061 breaks
[1] = BranchDest (loc
- 4, insn
);
5065 /* We do not support atomic sequences that use any *other* instructions
5066 but conditional branches to change the PC. Fall back to standard
5067 code to avoid losing control of execution. */
5068 else if (arm_instruction_changes_pc (insn
))
5071 /* If we find a strex{,b,h,d}, we're done. */
5072 if ((insn
& 0xff9000f0) == 0xe1800090)
5076 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5077 if (insn_count
== atomic_sequence_length
)
5080 /* Insert a breakpoint right after the end of the atomic sequence. */
5083 /* Check for duplicated breakpoints. Check also for a breakpoint
5084 placed (branch instruction's destination) anywhere in sequence. */
5086 && (breaks
[1] == breaks
[0]
5087 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5088 last_breakpoint
= 0;
5090 /* Effectively inserts the breakpoints. */
5091 for (index
= 0; index
<= last_breakpoint
; index
++)
5092 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5098 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5100 if (arm_frame_is_thumb (frame
))
5101 return thumb_deal_with_atomic_sequence_raw (frame
);
5103 return arm_deal_with_atomic_sequence_raw (frame
);
5106 /* single_step() is called just before we want to resume the inferior,
5107 if we want to single-step it but there is no hardware or kernel
5108 single-step support. We find the target of the coming instruction
5109 and breakpoint it. */
5112 arm_software_single_step (struct frame_info
*frame
)
5114 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5115 struct address_space
*aspace
= get_frame_address_space (frame
);
5118 if (arm_deal_with_atomic_sequence (frame
))
5121 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5122 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5127 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5128 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5129 NULL if an error occurs. BUF is freed. */
5132 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5133 int old_len
, int new_len
)
5135 gdb_byte
*new_buf
, *middle
;
5136 int bytes_to_read
= new_len
- old_len
;
5138 new_buf
= xmalloc (new_len
);
5139 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5141 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5149 /* An IT block is at most the 2-byte IT instruction followed by
5150 four 4-byte instructions. The furthest back we must search to
5151 find an IT block that affects the current instruction is thus
5152 2 + 3 * 4 == 14 bytes. */
5153 #define MAX_IT_BLOCK_PREFIX 14
5155 /* Use a quick scan if there are more than this many bytes of
5157 #define IT_SCAN_THRESHOLD 32
5159 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5160 A breakpoint in an IT block may not be hit, depending on the
5163 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5167 CORE_ADDR boundary
, func_start
;
5168 int buf_len
, buf2_len
;
5169 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5170 int i
, any
, last_it
, last_it_count
;
5172 /* If we are using BKPT breakpoints, none of this is necessary. */
5173 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5176 /* ARM mode does not have this problem. */
5177 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5180 /* We are setting a breakpoint in Thumb code that could potentially
5181 contain an IT block. The first step is to find how much Thumb
5182 code there is; we do not need to read outside of known Thumb
5184 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5186 /* Thumb-2 code must have mapping symbols to have a chance. */
5189 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5191 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5192 && func_start
> boundary
)
5193 boundary
= func_start
;
5195 /* Search for a candidate IT instruction. We have to do some fancy
5196 footwork to distinguish a real IT instruction from the second
5197 half of a 32-bit instruction, but there is no need for that if
5198 there's no candidate. */
5199 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5201 /* No room for an IT instruction. */
5204 buf
= xmalloc (buf_len
);
5205 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5208 for (i
= 0; i
< buf_len
; i
+= 2)
5210 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5211 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5223 /* OK, the code bytes before this instruction contain at least one
5224 halfword which resembles an IT instruction. We know that it's
5225 Thumb code, but there are still two possibilities. Either the
5226 halfword really is an IT instruction, or it is the second half of
5227 a 32-bit Thumb instruction. The only way we can tell is to
5228 scan forwards from a known instruction boundary. */
5229 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5233 /* There's a lot of code before this instruction. Start with an
5234 optimistic search; it's easy to recognize halfwords that can
5235 not be the start of a 32-bit instruction, and use that to
5236 lock on to the instruction boundaries. */
5237 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5240 buf_len
= IT_SCAN_THRESHOLD
;
5243 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5245 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5246 if (thumb_insn_size (inst1
) == 2)
5253 /* At this point, if DEFINITE, BUF[I] is the first place we
5254 are sure that we know the instruction boundaries, and it is far
5255 enough from BPADDR that we could not miss an IT instruction
5256 affecting BPADDR. If ! DEFINITE, give up - start from a
5260 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5264 buf_len
= bpaddr
- boundary
;
5270 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5273 buf_len
= bpaddr
- boundary
;
5277 /* Scan forwards. Find the last IT instruction before BPADDR. */
5282 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5284 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5289 else if (inst1
& 0x0002)
5291 else if (inst1
& 0x0004)
5296 i
+= thumb_insn_size (inst1
);
5302 /* There wasn't really an IT instruction after all. */
5305 if (last_it_count
< 1)
5306 /* It was too far away. */
5309 /* This really is a trouble spot. Move the breakpoint to the IT
5311 return bpaddr
- buf_len
+ last_it
;
5314 /* ARM displaced stepping support.
5316 Generally ARM displaced stepping works as follows:
5318 1. When an instruction is to be single-stepped, it is first decoded by
5319 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5320 Depending on the type of instruction, it is then copied to a scratch
5321 location, possibly in a modified form. The copy_* set of functions
5322 performs such modification, as necessary. A breakpoint is placed after
5323 the modified instruction in the scratch space to return control to GDB.
5324 Note in particular that instructions which modify the PC will no longer
5325 do so after modification.
5327 2. The instruction is single-stepped, by setting the PC to the scratch
5328 location address, and resuming. Control returns to GDB when the
5331 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5332 function used for the current instruction. This function's job is to
5333 put the CPU/memory state back to what it would have been if the
5334 instruction had been executed unmodified in its original location. */
5336 /* NOP instruction (mov r0, r0). */
5337 #define ARM_NOP 0xe1a00000
5338 #define THUMB_NOP 0x4600
5340 /* Helper for register reads for displaced stepping. In particular, this
5341 returns the PC as it would be seen by the instruction at its original
5345 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5349 CORE_ADDR from
= dsc
->insn_addr
;
5351 if (regno
== ARM_PC_REGNUM
)
5353 /* Compute pipeline offset:
5354 - When executing an ARM instruction, PC reads as the address of the
5355 current instruction plus 8.
5356 - When executing a Thumb instruction, PC reads as the address of the
5357 current instruction plus 4. */
5364 if (debug_displaced
)
5365 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5366 (unsigned long) from
);
5367 return (ULONGEST
) from
;
5371 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5372 if (debug_displaced
)
5373 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5374 regno
, (unsigned long) ret
);
5380 displaced_in_arm_mode (struct regcache
*regs
)
5383 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5385 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5387 return (ps
& t_bit
) == 0;
5390 /* Write to the PC as from a branch instruction. */
5393 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5397 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5398 architecture versions < 6. */
5399 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5400 val
& ~(ULONGEST
) 0x3);
5402 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5403 val
& ~(ULONGEST
) 0x1);
5406 /* Write to the PC as from a branch-exchange instruction. */
5409 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5412 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5414 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5418 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5419 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5421 else if ((val
& 2) == 0)
5423 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5424 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5428 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5429 mode, align dest to 4 bytes). */
5430 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5431 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5432 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5436 /* Write to the PC as if from a load instruction. */
5439 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5442 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5443 bx_write_pc (regs
, val
);
5445 branch_write_pc (regs
, dsc
, val
);
5448 /* Write to the PC as if from an ALU instruction. */
5451 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5454 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5455 bx_write_pc (regs
, val
);
5457 branch_write_pc (regs
, dsc
, val
);
5460 /* Helper for writing to registers for displaced stepping. Writing to the PC
5461 has a varying effects depending on the instruction which does the write:
5462 this is controlled by the WRITE_PC argument. */
5465 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5466 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5468 if (regno
== ARM_PC_REGNUM
)
5470 if (debug_displaced
)
5471 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5472 (unsigned long) val
);
5475 case BRANCH_WRITE_PC
:
5476 branch_write_pc (regs
, dsc
, val
);
5480 bx_write_pc (regs
, val
);
5484 load_write_pc (regs
, dsc
, val
);
5488 alu_write_pc (regs
, dsc
, val
);
5491 case CANNOT_WRITE_PC
:
5492 warning (_("Instruction wrote to PC in an unexpected way when "
5493 "single-stepping"));
5497 internal_error (__FILE__
, __LINE__
,
5498 _("Invalid argument to displaced_write_reg"));
5501 dsc
->wrote_to_pc
= 1;
5505 if (debug_displaced
)
5506 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5507 regno
, (unsigned long) val
);
5508 regcache_cooked_write_unsigned (regs
, regno
, val
);
5512 /* This function is used to concisely determine if an instruction INSN
5513 references PC. Register fields of interest in INSN should have the
5514 corresponding fields of BITMASK set to 0b1111. The function
5515 returns return 1 if any of these fields in INSN reference the PC
5516 (also 0b1111, r15), else it returns 0. */
5519 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5521 uint32_t lowbit
= 1;
5523 while (bitmask
!= 0)
5527 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5533 mask
= lowbit
* 0xf;
5535 if ((insn
& mask
) == mask
)
5544 /* The simplest copy function. Many instructions have the same effect no
5545 matter what address they are executed at: in those cases, use this. */
5548 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5549 const char *iname
, struct displaced_step_closure
*dsc
)
5551 if (debug_displaced
)
5552 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5553 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5556 dsc
->modinsn
[0] = insn
;
5562 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5563 uint16_t insn2
, const char *iname
,
5564 struct displaced_step_closure
*dsc
)
5566 if (debug_displaced
)
5567 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5568 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5571 dsc
->modinsn
[0] = insn1
;
5572 dsc
->modinsn
[1] = insn2
;
5578 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5581 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5583 struct displaced_step_closure
*dsc
)
5585 if (debug_displaced
)
5586 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5587 "opcode/class '%s' unmodified\n", insn
,
5590 dsc
->modinsn
[0] = insn
;
5595 /* Preload instructions with immediate offset. */
5598 cleanup_preload (struct gdbarch
*gdbarch
,
5599 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5601 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5602 if (!dsc
->u
.preload
.immed
)
5603 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5607 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5608 struct displaced_step_closure
*dsc
, unsigned int rn
)
5611 /* Preload instructions:
5613 {pli/pld} [rn, #+/-imm]
5615 {pli/pld} [r0, #+/-imm]. */
5617 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5618 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5619 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5620 dsc
->u
.preload
.immed
= 1;
5622 dsc
->cleanup
= &cleanup_preload
;
5626 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5627 struct displaced_step_closure
*dsc
)
5629 unsigned int rn
= bits (insn
, 16, 19);
5631 if (!insn_references_pc (insn
, 0x000f0000ul
))
5632 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5634 if (debug_displaced
)
5635 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5636 (unsigned long) insn
);
5638 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5640 install_preload (gdbarch
, regs
, dsc
, rn
);
5646 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5647 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5649 unsigned int rn
= bits (insn1
, 0, 3);
5650 unsigned int u_bit
= bit (insn1
, 7);
5651 int imm12
= bits (insn2
, 0, 11);
5654 if (rn
!= ARM_PC_REGNUM
)
5655 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5657 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5658 PLD (literal) Encoding T1. */
5659 if (debug_displaced
)
5660 fprintf_unfiltered (gdb_stdlog
,
5661 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5662 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5668 /* Rewrite instruction {pli/pld} PC imm12 into:
5669 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5673 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5675 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5676 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5678 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5680 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5681 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5682 dsc
->u
.preload
.immed
= 0;
5684 /* {pli/pld} [r0, r1] */
5685 dsc
->modinsn
[0] = insn1
& 0xfff0;
5686 dsc
->modinsn
[1] = 0xf001;
5689 dsc
->cleanup
= &cleanup_preload
;
5693 /* Preload instructions with register offset. */
5696 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5697 struct displaced_step_closure
*dsc
, unsigned int rn
,
5700 ULONGEST rn_val
, rm_val
;
5702 /* Preload register-offset instructions:
5704 {pli/pld} [rn, rm {, shift}]
5706 {pli/pld} [r0, r1 {, shift}]. */
5708 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5709 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5710 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5711 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5712 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5713 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5714 dsc
->u
.preload
.immed
= 0;
5716 dsc
->cleanup
= &cleanup_preload
;
5720 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5721 struct regcache
*regs
,
5722 struct displaced_step_closure
*dsc
)
5724 unsigned int rn
= bits (insn
, 16, 19);
5725 unsigned int rm
= bits (insn
, 0, 3);
5728 if (!insn_references_pc (insn
, 0x000f000ful
))
5729 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5731 if (debug_displaced
)
5732 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5733 (unsigned long) insn
);
5735 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5737 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5741 /* Copy/cleanup coprocessor load and store instructions. */
5744 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5745 struct regcache
*regs
,
5746 struct displaced_step_closure
*dsc
)
5748 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5750 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5752 if (dsc
->u
.ldst
.writeback
)
5753 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5757 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5758 struct displaced_step_closure
*dsc
,
5759 int writeback
, unsigned int rn
)
5763 /* Coprocessor load/store instructions:
5765 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5767 {stc/stc2} [r0, #+/-imm].
5769 ldc/ldc2 are handled identically. */
5771 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5772 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5773 /* PC should be 4-byte aligned. */
5774 rn_val
= rn_val
& 0xfffffffc;
5775 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5777 dsc
->u
.ldst
.writeback
= writeback
;
5778 dsc
->u
.ldst
.rn
= rn
;
5780 dsc
->cleanup
= &cleanup_copro_load_store
;
5784 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5785 struct regcache
*regs
,
5786 struct displaced_step_closure
*dsc
)
5788 unsigned int rn
= bits (insn
, 16, 19);
5790 if (!insn_references_pc (insn
, 0x000f0000ul
))
5791 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5793 if (debug_displaced
)
5794 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5795 "load/store insn %.8lx\n", (unsigned long) insn
);
5797 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5799 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5805 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5806 uint16_t insn2
, struct regcache
*regs
,
5807 struct displaced_step_closure
*dsc
)
5809 unsigned int rn
= bits (insn1
, 0, 3);
5811 if (rn
!= ARM_PC_REGNUM
)
5812 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
5813 "copro load/store", dsc
);
5815 if (debug_displaced
)
5816 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5817 "load/store insn %.4x%.4x\n", insn1
, insn2
);
5819 dsc
->modinsn
[0] = insn1
& 0xfff0;
5820 dsc
->modinsn
[1] = insn2
;
5823 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5824 doesn't support writeback, so pass 0. */
5825 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
5830 /* Clean up branch instructions (actually perform the branch, by setting
5834 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5835 struct displaced_step_closure
*dsc
)
5837 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5838 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
5839 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
5840 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
5845 if (dsc
->u
.branch
.link
)
5847 /* The value of LR should be the next insn of current one. In order
5848 not to confuse logic hanlding later insn `bx lr', if current insn mode
5849 is Thumb, the bit 0 of LR value should be set to 1. */
5850 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
5853 next_insn_addr
|= 0x1;
5855 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
5859 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
5862 /* Copy B/BL/BLX instructions with immediate destinations. */
5865 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5866 struct displaced_step_closure
*dsc
,
5867 unsigned int cond
, int exchange
, int link
, long offset
)
5869 /* Implement "BL<cond> <label>" as:
5871 Preparation: cond <- instruction condition
5872 Insn: mov r0, r0 (nop)
5873 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5875 B<cond> similar, but don't set r14 in cleanup. */
5877 dsc
->u
.branch
.cond
= cond
;
5878 dsc
->u
.branch
.link
= link
;
5879 dsc
->u
.branch
.exchange
= exchange
;
5881 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
5882 if (link
&& exchange
)
5883 /* For BLX, offset is computed from the Align (PC, 4). */
5884 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5887 dsc
->u
.branch
.dest
+= 4 + offset
;
5889 dsc
->u
.branch
.dest
+= 8 + offset
;
5891 dsc
->cleanup
= &cleanup_branch
;
5894 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5895 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5897 unsigned int cond
= bits (insn
, 28, 31);
5898 int exchange
= (cond
== 0xf);
5899 int link
= exchange
|| bit (insn
, 24);
5902 if (debug_displaced
)
5903 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5904 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5905 (unsigned long) insn
);
5907 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5908 then arrange the switch into Thumb mode. */
5909 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5911 offset
= bits (insn
, 0, 23) << 2;
5913 if (bit (offset
, 25))
5914 offset
= offset
| ~0x3ffffff;
5916 dsc
->modinsn
[0] = ARM_NOP
;
5918 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5923 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5924 uint16_t insn2
, struct regcache
*regs
,
5925 struct displaced_step_closure
*dsc
)
5927 int link
= bit (insn2
, 14);
5928 int exchange
= link
&& !bit (insn2
, 12);
5931 int j1
= bit (insn2
, 13);
5932 int j2
= bit (insn2
, 11);
5933 int s
= sbits (insn1
, 10, 10);
5934 int i1
= !(j1
^ bit (insn1
, 10));
5935 int i2
= !(j2
^ bit (insn1
, 10));
5937 if (!link
&& !exchange
) /* B */
5939 offset
= (bits (insn2
, 0, 10) << 1);
5940 if (bit (insn2
, 12)) /* Encoding T4 */
5942 offset
|= (bits (insn1
, 0, 9) << 12)
5948 else /* Encoding T3 */
5950 offset
|= (bits (insn1
, 0, 5) << 12)
5954 cond
= bits (insn1
, 6, 9);
5959 offset
= (bits (insn1
, 0, 9) << 12);
5960 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5961 offset
|= exchange
?
5962 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5965 if (debug_displaced
)
5966 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5967 "%.4x %.4x with offset %.8lx\n",
5968 link
? (exchange
) ? "blx" : "bl" : "b",
5969 insn1
, insn2
, offset
);
5971 dsc
->modinsn
[0] = THUMB_NOP
;
5973 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5977 /* Copy B Thumb instructions. */
5979 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
5980 struct displaced_step_closure
*dsc
)
5982 unsigned int cond
= 0;
5984 unsigned short bit_12_15
= bits (insn
, 12, 15);
5985 CORE_ADDR from
= dsc
->insn_addr
;
5987 if (bit_12_15
== 0xd)
5989 /* offset = SignExtend (imm8:0, 32) */
5990 offset
= sbits ((insn
<< 1), 0, 8);
5991 cond
= bits (insn
, 8, 11);
5993 else if (bit_12_15
== 0xe) /* Encoding T2 */
5995 offset
= sbits ((insn
<< 1), 0, 11);
5999 if (debug_displaced
)
6000 fprintf_unfiltered (gdb_stdlog
,
6001 "displaced: copying b immediate insn %.4x "
6002 "with offset %d\n", insn
, offset
);
6004 dsc
->u
.branch
.cond
= cond
;
6005 dsc
->u
.branch
.link
= 0;
6006 dsc
->u
.branch
.exchange
= 0;
6007 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6009 dsc
->modinsn
[0] = THUMB_NOP
;
6011 dsc
->cleanup
= &cleanup_branch
;
6016 /* Copy BX/BLX with register-specified destinations. */
6019 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6020 struct displaced_step_closure
*dsc
, int link
,
6021 unsigned int cond
, unsigned int rm
)
6023 /* Implement {BX,BLX}<cond> <reg>" as:
6025 Preparation: cond <- instruction condition
6026 Insn: mov r0, r0 (nop)
6027 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6029 Don't set r14 in cleanup for BX. */
6031 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6033 dsc
->u
.branch
.cond
= cond
;
6034 dsc
->u
.branch
.link
= link
;
6036 dsc
->u
.branch
.exchange
= 1;
6038 dsc
->cleanup
= &cleanup_branch
;
6042 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6043 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6045 unsigned int cond
= bits (insn
, 28, 31);
6048 int link
= bit (insn
, 5);
6049 unsigned int rm
= bits (insn
, 0, 3);
6051 if (debug_displaced
)
6052 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6053 (unsigned long) insn
);
6055 dsc
->modinsn
[0] = ARM_NOP
;
6057 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6062 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6063 struct regcache
*regs
,
6064 struct displaced_step_closure
*dsc
)
6066 int link
= bit (insn
, 7);
6067 unsigned int rm
= bits (insn
, 3, 6);
6069 if (debug_displaced
)
6070 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6071 (unsigned short) insn
);
6073 dsc
->modinsn
[0] = THUMB_NOP
;
6075 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6081 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6084 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6085 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6087 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6088 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6089 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6090 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6094 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6095 struct displaced_step_closure
*dsc
)
6097 unsigned int rn
= bits (insn
, 16, 19);
6098 unsigned int rd
= bits (insn
, 12, 15);
6099 unsigned int op
= bits (insn
, 21, 24);
6100 int is_mov
= (op
== 0xd);
6101 ULONGEST rd_val
, rn_val
;
6103 if (!insn_references_pc (insn
, 0x000ff000ul
))
6104 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6106 if (debug_displaced
)
6107 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6108 "%.8lx\n", is_mov
? "move" : "ALU",
6109 (unsigned long) insn
);
6111 /* Instruction is of form:
6113 <op><cond> rd, [rn,] #imm
6117 Preparation: tmp1, tmp2 <- r0, r1;
6119 Insn: <op><cond> r0, r1, #imm
6120 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6123 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6124 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6125 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6126 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6127 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6128 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6132 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6134 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6136 dsc
->cleanup
= &cleanup_alu_imm
;
6142 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6143 uint16_t insn2
, struct regcache
*regs
,
6144 struct displaced_step_closure
*dsc
)
6146 unsigned int op
= bits (insn1
, 5, 8);
6147 unsigned int rn
, rm
, rd
;
6148 ULONGEST rd_val
, rn_val
;
6150 rn
= bits (insn1
, 0, 3); /* Rn */
6151 rm
= bits (insn2
, 0, 3); /* Rm */
6152 rd
= bits (insn2
, 8, 11); /* Rd */
6154 /* This routine is only called for instruction MOV. */
6155 gdb_assert (op
== 0x2 && rn
== 0xf);
6157 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6158 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6160 if (debug_displaced
)
6161 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6162 "ALU", insn1
, insn2
);
6164 /* Instruction is of form:
6166 <op><cond> rd, [rn,] #imm
6170 Preparation: tmp1, tmp2 <- r0, r1;
6172 Insn: <op><cond> r0, r1, #imm
6173 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6176 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6177 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6178 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6179 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6180 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6181 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6184 dsc
->modinsn
[0] = insn1
;
6185 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6188 dsc
->cleanup
= &cleanup_alu_imm
;
6193 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6196 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6197 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6202 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6204 for (i
= 0; i
< 3; i
++)
6205 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6207 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6211 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6212 struct displaced_step_closure
*dsc
,
6213 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6215 ULONGEST rd_val
, rn_val
, rm_val
;
6217 /* Instruction is of form:
6219 <op><cond> rd, [rn,] rm [, <shift>]
6223 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6224 r0, r1, r2 <- rd, rn, rm
6225 Insn: <op><cond> r0, r1, r2 [, <shift>]
6226 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6229 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6230 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6231 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6232 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6233 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6234 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6235 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6236 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6237 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6240 dsc
->cleanup
= &cleanup_alu_reg
;
6244 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6245 struct displaced_step_closure
*dsc
)
6247 unsigned int op
= bits (insn
, 21, 24);
6248 int is_mov
= (op
== 0xd);
6250 if (!insn_references_pc (insn
, 0x000ff00ful
))
6251 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6253 if (debug_displaced
)
6254 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6255 is_mov
? "move" : "ALU", (unsigned long) insn
);
6258 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6260 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6262 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6268 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6269 struct regcache
*regs
,
6270 struct displaced_step_closure
*dsc
)
6272 unsigned rn
, rm
, rd
;
6274 rd
= bits (insn
, 3, 6);
6275 rn
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6278 if (rd
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6279 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6281 if (debug_displaced
)
6282 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x\n",
6283 "ALU", (unsigned short) insn
);
6285 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x08);
6287 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
);
6292 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6295 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6296 struct regcache
*regs
,
6297 struct displaced_step_closure
*dsc
)
6299 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6302 for (i
= 0; i
< 4; i
++)
6303 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6305 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6309 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6310 struct displaced_step_closure
*dsc
,
6311 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6315 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6317 /* Instruction is of form:
6319 <op><cond> rd, [rn,] rm, <shift> rs
6323 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6324 r0, r1, r2, r3 <- rd, rn, rm, rs
6325 Insn: <op><cond> r0, r1, r2, <shift> r3
6327 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6331 for (i
= 0; i
< 4; i
++)
6332 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6334 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6335 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6336 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6337 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6338 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6339 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6340 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6341 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6343 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6347 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6348 struct regcache
*regs
,
6349 struct displaced_step_closure
*dsc
)
6351 unsigned int op
= bits (insn
, 21, 24);
6352 int is_mov
= (op
== 0xd);
6353 unsigned int rd
, rn
, rm
, rs
;
6355 if (!insn_references_pc (insn
, 0x000fff0ful
))
6356 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6358 if (debug_displaced
)
6359 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6360 "%.8lx\n", is_mov
? "move" : "ALU",
6361 (unsigned long) insn
);
6363 rn
= bits (insn
, 16, 19);
6364 rm
= bits (insn
, 0, 3);
6365 rs
= bits (insn
, 8, 11);
6366 rd
= bits (insn
, 12, 15);
6369 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6371 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6373 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6378 /* Clean up load instructions. */
6381 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6382 struct displaced_step_closure
*dsc
)
6384 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6386 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6387 if (dsc
->u
.ldst
.xfersize
== 8)
6388 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6389 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6391 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6392 if (dsc
->u
.ldst
.xfersize
> 4)
6393 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6394 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6395 if (!dsc
->u
.ldst
.immed
)
6396 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6398 /* Handle register writeback. */
6399 if (dsc
->u
.ldst
.writeback
)
6400 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6401 /* Put result in right place. */
6402 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6403 if (dsc
->u
.ldst
.xfersize
== 8)
6404 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6407 /* Clean up store instructions. */
6410 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6411 struct displaced_step_closure
*dsc
)
6413 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6415 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6416 if (dsc
->u
.ldst
.xfersize
> 4)
6417 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6418 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6419 if (!dsc
->u
.ldst
.immed
)
6420 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6421 if (!dsc
->u
.ldst
.restore_r4
)
6422 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6425 if (dsc
->u
.ldst
.writeback
)
6426 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6429 /* Copy "extra" load/store instructions. These are halfword/doubleword
6430 transfers, which have a different encoding to byte/word transfers. */
6433 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6434 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6436 unsigned int op1
= bits (insn
, 20, 24);
6437 unsigned int op2
= bits (insn
, 5, 6);
6438 unsigned int rt
= bits (insn
, 12, 15);
6439 unsigned int rn
= bits (insn
, 16, 19);
6440 unsigned int rm
= bits (insn
, 0, 3);
6441 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6442 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6443 int immed
= (op1
& 0x4) != 0;
6445 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6447 if (!insn_references_pc (insn
, 0x000ff00ful
))
6448 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6450 if (debug_displaced
)
6451 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6452 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6453 (unsigned long) insn
);
6455 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6458 internal_error (__FILE__
, __LINE__
,
6459 _("copy_extra_ld_st: instruction decode error"));
6461 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6462 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6463 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6465 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6467 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6468 if (bytesize
[opcode
] == 8)
6469 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6470 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6472 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6474 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6475 if (bytesize
[opcode
] == 8)
6476 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6477 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6479 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6482 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6483 dsc
->u
.ldst
.rn
= rn
;
6484 dsc
->u
.ldst
.immed
= immed
;
6485 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6486 dsc
->u
.ldst
.restore_r4
= 0;
6489 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6491 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6492 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6494 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6496 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6497 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6499 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6504 /* Copy byte/half word/word loads and stores. */
6507 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6508 struct displaced_step_closure
*dsc
, int load
,
6509 int immed
, int writeback
, int size
, int usermode
,
6510 int rt
, int rm
, int rn
)
6512 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6514 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6515 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6517 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6519 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6521 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6522 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6524 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6526 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6527 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6529 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6531 dsc
->u
.ldst
.xfersize
= size
;
6532 dsc
->u
.ldst
.rn
= rn
;
6533 dsc
->u
.ldst
.immed
= immed
;
6534 dsc
->u
.ldst
.writeback
= writeback
;
6536 /* To write PC we can do:
6538 Before this sequence of instructions:
6539 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6540 r2 is the Rn value got from dispalced_read_reg.
6542 Insn1: push {pc} Write address of STR instruction + offset on stack
6543 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6544 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6545 = addr(Insn1) + offset - addr(Insn3) - 8
6547 Insn4: add r4, r4, #8 r4 = offset - 8
6548 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6550 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6552 Otherwise we don't know what value to write for PC, since the offset is
6553 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6554 of this can be found in Section "Saving from r15" in
6555 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6557 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6562 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6563 uint16_t insn2
, struct regcache
*regs
,
6564 struct displaced_step_closure
*dsc
, int size
)
6566 unsigned int u_bit
= bit (insn1
, 7);
6567 unsigned int rt
= bits (insn2
, 12, 15);
6568 int imm12
= bits (insn2
, 0, 11);
6571 if (debug_displaced
)
6572 fprintf_unfiltered (gdb_stdlog
,
6573 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6574 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6580 /* Rewrite instruction LDR Rt imm12 into:
6582 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6586 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6589 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6590 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6591 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6593 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6595 pc_val
= pc_val
& 0xfffffffc;
6597 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6598 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6602 dsc
->u
.ldst
.xfersize
= size
;
6603 dsc
->u
.ldst
.immed
= 0;
6604 dsc
->u
.ldst
.writeback
= 0;
6605 dsc
->u
.ldst
.restore_r4
= 0;
6607 /* LDR R0, R2, R3 */
6608 dsc
->modinsn
[0] = 0xf852;
6609 dsc
->modinsn
[1] = 0x3;
6612 dsc
->cleanup
= &cleanup_load
;
6618 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6619 uint16_t insn2
, struct regcache
*regs
,
6620 struct displaced_step_closure
*dsc
,
6621 int writeback
, int immed
)
6623 unsigned int rt
= bits (insn2
, 12, 15);
6624 unsigned int rn
= bits (insn1
, 0, 3);
6625 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6626 /* In LDR (register), there is also a register Rm, which is not allowed to
6627 be PC, so we don't have to check it. */
6629 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6630 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6633 if (debug_displaced
)
6634 fprintf_unfiltered (gdb_stdlog
,
6635 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6636 rt
, rn
, insn1
, insn2
);
6638 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6641 dsc
->u
.ldst
.restore_r4
= 0;
6644 /* ldr[b]<cond> rt, [rn, #imm], etc.
6646 ldr[b]<cond> r0, [r2, #imm]. */
6648 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6649 dsc
->modinsn
[1] = insn2
& 0x0fff;
6652 /* ldr[b]<cond> rt, [rn, rm], etc.
6654 ldr[b]<cond> r0, [r2, r3]. */
6656 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6657 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6667 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6668 struct regcache
*regs
,
6669 struct displaced_step_closure
*dsc
,
6670 int load
, int size
, int usermode
)
6672 int immed
= !bit (insn
, 25);
6673 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6674 unsigned int rt
= bits (insn
, 12, 15);
6675 unsigned int rn
= bits (insn
, 16, 19);
6676 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6678 if (!insn_references_pc (insn
, 0x000ff00ful
))
6679 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6681 if (debug_displaced
)
6682 fprintf_unfiltered (gdb_stdlog
,
6683 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6684 load
? (size
== 1 ? "ldrb" : "ldr")
6685 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6687 (unsigned long) insn
);
6689 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6690 usermode
, rt
, rm
, rn
);
6692 if (load
|| rt
!= ARM_PC_REGNUM
)
6694 dsc
->u
.ldst
.restore_r4
= 0;
6697 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6699 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6700 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6702 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6704 {ldr,str}[b]<cond> r0, [r2, r3]. */
6705 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6709 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6710 dsc
->u
.ldst
.restore_r4
= 1;
6711 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6712 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6713 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6714 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6715 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6719 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6721 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6726 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6731 /* Cleanup LDM instructions with fully-populated register list. This is an
6732 unfortunate corner case: it's impossible to implement correctly by modifying
6733 the instruction. The issue is as follows: we have an instruction,
6737 which we must rewrite to avoid loading PC. A possible solution would be to
6738 do the load in two halves, something like (with suitable cleanup
6742 ldm[id][ab] r8!, {r0-r7}
6744 ldm[id][ab] r8, {r7-r14}
6747 but at present there's no suitable place for <temp>, since the scratch space
6748 is overwritten before the cleanup routine is called. For now, we simply
6749 emulate the instruction. */
6752 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6753 struct displaced_step_closure
*dsc
)
6755 int inc
= dsc
->u
.block
.increment
;
6756 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6757 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6758 uint32_t regmask
= dsc
->u
.block
.regmask
;
6759 int regno
= inc
? 0 : 15;
6760 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6761 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6762 && (regmask
& 0x8000) != 0;
6763 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6764 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6765 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6770 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6771 sensible we can do here. Complain loudly. */
6772 if (exception_return
)
6773 error (_("Cannot single-step exception return"));
6775 /* We don't handle any stores here for now. */
6776 gdb_assert (dsc
->u
.block
.load
!= 0);
6778 if (debug_displaced
)
6779 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6780 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6781 dsc
->u
.block
.increment
? "inc" : "dec",
6782 dsc
->u
.block
.before
? "before" : "after");
6789 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6792 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6795 xfer_addr
+= bump_before
;
6797 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6798 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6800 xfer_addr
+= bump_after
;
6802 regmask
&= ~(1 << regno
);
6805 if (dsc
->u
.block
.writeback
)
6806 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6810 /* Clean up an STM which included the PC in the register list. */
6813 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6814 struct displaced_step_closure
*dsc
)
6816 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6817 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6818 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
6819 CORE_ADDR stm_insn_addr
;
6822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6824 /* If condition code fails, there's nothing else to do. */
6825 if (!store_executed
)
6828 if (dsc
->u
.block
.increment
)
6830 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
6832 if (dsc
->u
.block
.before
)
6837 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
6839 if (dsc
->u
.block
.before
)
6843 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
6844 stm_insn_addr
= dsc
->scratch_base
;
6845 offset
= pc_val
- stm_insn_addr
;
6847 if (debug_displaced
)
6848 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
6849 "STM instruction\n", offset
);
6851 /* Rewrite the stored PC to the proper value for the non-displaced original
6853 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
6854 dsc
->insn_addr
+ offset
);
6857 /* Clean up an LDM which includes the PC in the register list. We clumped all
6858 the registers in the transferred list into a contiguous range r0...rX (to
6859 avoid loading PC directly and losing control of the debugged program), so we
6860 must undo that here. */
6863 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
6864 struct regcache
*regs
,
6865 struct displaced_step_closure
*dsc
)
6867 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6868 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
6869 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
6870 unsigned int regs_loaded
= bitcount (mask
);
6871 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
6873 /* The method employed here will fail if the register list is fully populated
6874 (we need to avoid loading PC directly). */
6875 gdb_assert (num_to_shuffle
< 16);
6880 clobbered
= (1 << num_to_shuffle
) - 1;
6882 while (num_to_shuffle
> 0)
6884 if ((mask
& (1 << write_reg
)) != 0)
6886 unsigned int read_reg
= num_to_shuffle
- 1;
6888 if (read_reg
!= write_reg
)
6890 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6891 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6892 if (debug_displaced
)
6893 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6894 "loaded register r%d to r%d\n"), read_reg
,
6897 else if (debug_displaced
)
6898 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6899 "r%d already in the right place\n"),
6902 clobbered
&= ~(1 << write_reg
);
6910 /* Restore any registers we scribbled over. */
6911 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6913 if ((clobbered
& (1 << write_reg
)) != 0)
6915 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6917 if (debug_displaced
)
6918 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6919 "clobbered register r%d\n"), write_reg
);
6920 clobbered
&= ~(1 << write_reg
);
6924 /* Perform register writeback manually. */
6925 if (dsc
->u
.block
.writeback
)
6927 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6929 if (dsc
->u
.block
.increment
)
6930 new_rn_val
+= regs_loaded
* 4;
6932 new_rn_val
-= regs_loaded
* 4;
6934 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6939 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6940 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6943 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6944 struct regcache
*regs
,
6945 struct displaced_step_closure
*dsc
)
6947 int load
= bit (insn
, 20);
6948 int user
= bit (insn
, 22);
6949 int increment
= bit (insn
, 23);
6950 int before
= bit (insn
, 24);
6951 int writeback
= bit (insn
, 21);
6952 int rn
= bits (insn
, 16, 19);
6954 /* Block transfers which don't mention PC can be run directly
6956 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6957 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6959 if (rn
== ARM_PC_REGNUM
)
6961 warning (_("displaced: Unpredictable LDM or STM with "
6962 "base register r15"));
6963 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6966 if (debug_displaced
)
6967 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6968 "%.8lx\n", (unsigned long) insn
);
6970 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6971 dsc
->u
.block
.rn
= rn
;
6973 dsc
->u
.block
.load
= load
;
6974 dsc
->u
.block
.user
= user
;
6975 dsc
->u
.block
.increment
= increment
;
6976 dsc
->u
.block
.before
= before
;
6977 dsc
->u
.block
.writeback
= writeback
;
6978 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6980 dsc
->u
.block
.regmask
= insn
& 0xffff;
6984 if ((insn
& 0xffff) == 0xffff)
6986 /* LDM with a fully-populated register list. This case is
6987 particularly tricky. Implement for now by fully emulating the
6988 instruction (which might not behave perfectly in all cases, but
6989 these instructions should be rare enough for that not to matter
6991 dsc
->modinsn
[0] = ARM_NOP
;
6993 dsc
->cleanup
= &cleanup_block_load_all
;
6997 /* LDM of a list of registers which includes PC. Implement by
6998 rewriting the list of registers to be transferred into a
6999 contiguous chunk r0...rX before doing the transfer, then shuffling
7000 registers into the correct places in the cleanup routine. */
7001 unsigned int regmask
= insn
& 0xffff;
7002 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7003 unsigned int to
= 0, from
= 0, i
, new_rn
;
7005 for (i
= 0; i
< num_in_list
; i
++)
7006 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7008 /* Writeback makes things complicated. We need to avoid clobbering
7009 the base register with one of the registers in our modified
7010 register list, but just using a different register can't work in
7013 ldm r14!, {r0-r13,pc}
7015 which would need to be rewritten as:
7019 but that can't work, because there's no free register for N.
7021 Solve this by turning off the writeback bit, and emulating
7022 writeback manually in the cleanup routine. */
7027 new_regmask
= (1 << num_in_list
) - 1;
7029 if (debug_displaced
)
7030 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7031 "{..., pc}: original reg list %.4x, modified "
7032 "list %.4x\n"), rn
, writeback
? "!" : "",
7033 (int) insn
& 0xffff, new_regmask
);
7035 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7037 dsc
->cleanup
= &cleanup_block_load_pc
;
7042 /* STM of a list of registers which includes PC. Run the instruction
7043 as-is, but out of line: this will store the wrong value for the PC,
7044 so we must manually fix up the memory in the cleanup routine.
7045 Doing things this way has the advantage that we can auto-detect
7046 the offset of the PC write (which is architecture-dependent) in
7047 the cleanup routine. */
7048 dsc
->modinsn
[0] = insn
;
7050 dsc
->cleanup
= &cleanup_block_store_pc
;
7057 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7058 struct regcache
*regs
,
7059 struct displaced_step_closure
*dsc
)
7061 int rn
= bits (insn1
, 0, 3);
7062 int load
= bit (insn1
, 4);
7063 int writeback
= bit (insn1
, 5);
7065 /* Block transfers which don't mention PC can be run directly
7067 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7068 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7070 if (rn
== ARM_PC_REGNUM
)
7072 warning (_("displaced: Unpredictable LDM or STM with "
7073 "base register r15"));
7074 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7075 "unpredictable ldm/stm", dsc
);
7078 if (debug_displaced
)
7079 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7080 "%.4x%.4x\n", insn1
, insn2
);
7082 /* Clear bit 13, since it should be always zero. */
7083 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7084 dsc
->u
.block
.rn
= rn
;
7086 dsc
->u
.block
.load
= load
;
7087 dsc
->u
.block
.user
= 0;
7088 dsc
->u
.block
.increment
= bit (insn1
, 7);
7089 dsc
->u
.block
.before
= bit (insn1
, 8);
7090 dsc
->u
.block
.writeback
= writeback
;
7091 dsc
->u
.block
.cond
= INST_AL
;
7092 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7096 if (dsc
->u
.block
.regmask
== 0xffff)
7098 /* This branch is impossible to happen. */
7103 unsigned int regmask
= dsc
->u
.block
.regmask
;
7104 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7105 unsigned int to
= 0, from
= 0, i
, new_rn
;
7107 for (i
= 0; i
< num_in_list
; i
++)
7108 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7113 new_regmask
= (1 << num_in_list
) - 1;
7115 if (debug_displaced
)
7116 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7117 "{..., pc}: original reg list %.4x, modified "
7118 "list %.4x\n"), rn
, writeback
? "!" : "",
7119 (int) dsc
->u
.block
.regmask
, new_regmask
);
7121 dsc
->modinsn
[0] = insn1
;
7122 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7125 dsc
->cleanup
= &cleanup_block_load_pc
;
7130 dsc
->modinsn
[0] = insn1
;
7131 dsc
->modinsn
[1] = insn2
;
7133 dsc
->cleanup
= &cleanup_block_store_pc
;
7138 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7139 for Linux, where some SVC instructions must be treated specially. */
7142 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7143 struct displaced_step_closure
*dsc
)
7145 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7147 if (debug_displaced
)
7148 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7149 "%.8lx\n", (unsigned long) resume_addr
);
7151 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7155 /* Common copy routine for svc instruciton. */
7158 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7159 struct displaced_step_closure
*dsc
)
7161 /* Preparation: none.
7162 Insn: unmodified svc.
7163 Cleanup: pc <- insn_addr + insn_size. */
7165 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7167 dsc
->wrote_to_pc
= 1;
7169 /* Allow OS-specific code to override SVC handling. */
7170 if (dsc
->u
.svc
.copy_svc_os
)
7171 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7174 dsc
->cleanup
= &cleanup_svc
;
7180 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7181 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7184 if (debug_displaced
)
7185 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7186 (unsigned long) insn
);
7188 dsc
->modinsn
[0] = insn
;
7190 return install_svc (gdbarch
, regs
, dsc
);
7194 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7195 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7198 if (debug_displaced
)
7199 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7202 dsc
->modinsn
[0] = insn
;
7204 return install_svc (gdbarch
, regs
, dsc
);
7207 /* Copy undefined instructions. */
7210 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7211 struct displaced_step_closure
*dsc
)
7213 if (debug_displaced
)
7214 fprintf_unfiltered (gdb_stdlog
,
7215 "displaced: copying undefined insn %.8lx\n",
7216 (unsigned long) insn
);
7218 dsc
->modinsn
[0] = insn
;
7224 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7225 struct displaced_step_closure
*dsc
)
7228 if (debug_displaced
)
7229 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7230 "%.4x %.4x\n", (unsigned short) insn1
,
7231 (unsigned short) insn2
);
7233 dsc
->modinsn
[0] = insn1
;
7234 dsc
->modinsn
[1] = insn2
;
7240 /* Copy unpredictable instructions. */
7243 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7244 struct displaced_step_closure
*dsc
)
7246 if (debug_displaced
)
7247 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7248 "%.8lx\n", (unsigned long) insn
);
7250 dsc
->modinsn
[0] = insn
;
7255 /* The decode_* functions are instruction decoding helpers. They mostly follow
7256 the presentation in the ARM ARM. */
7259 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7260 struct regcache
*regs
,
7261 struct displaced_step_closure
*dsc
)
7263 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7264 unsigned int rn
= bits (insn
, 16, 19);
7266 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7267 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7268 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7269 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7270 else if ((op1
& 0x60) == 0x20)
7271 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7272 else if ((op1
& 0x71) == 0x40)
7273 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7275 else if ((op1
& 0x77) == 0x41)
7276 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7277 else if ((op1
& 0x77) == 0x45)
7278 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7279 else if ((op1
& 0x77) == 0x51)
7282 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7284 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7286 else if ((op1
& 0x77) == 0x55)
7287 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7288 else if (op1
== 0x57)
7291 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7292 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7293 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7294 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7295 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7297 else if ((op1
& 0x63) == 0x43)
7298 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7299 else if ((op2
& 0x1) == 0x0)
7300 switch (op1
& ~0x80)
7303 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7305 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7306 case 0x71: case 0x75:
7308 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7309 case 0x63: case 0x67: case 0x73: case 0x77:
7310 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7312 return arm_copy_undef (gdbarch
, insn
, dsc
);
7315 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7319 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7320 struct regcache
*regs
,
7321 struct displaced_step_closure
*dsc
)
7323 if (bit (insn
, 27) == 0)
7324 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7325 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7326 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7329 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7332 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7334 case 0x4: case 0x5: case 0x6: case 0x7:
7335 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7338 switch ((insn
& 0xe00000) >> 21)
7340 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7342 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7345 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7348 return arm_copy_undef (gdbarch
, insn
, dsc
);
7353 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7354 switch ((insn
& 0xe00000) >> 21)
7357 /* ldc/ldc2 imm (undefined for rn == pc). */
7358 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7359 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7362 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7364 case 0x4: case 0x5: case 0x6: case 0x7:
7365 /* ldc/ldc2 lit (undefined for rn != pc). */
7366 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7367 : arm_copy_undef (gdbarch
, insn
, dsc
);
7370 return arm_copy_undef (gdbarch
, insn
, dsc
);
7375 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7378 if (bits (insn
, 16, 19) == 0xf)
7380 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7382 return arm_copy_undef (gdbarch
, insn
, dsc
);
7386 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7388 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7392 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7394 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7397 return arm_copy_undef (gdbarch
, insn
, dsc
);
7401 /* Decode miscellaneous instructions in dp/misc encoding space. */
7404 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7405 struct regcache
*regs
,
7406 struct displaced_step_closure
*dsc
)
7408 unsigned int op2
= bits (insn
, 4, 6);
7409 unsigned int op
= bits (insn
, 21, 22);
7410 unsigned int op1
= bits (insn
, 16, 19);
7415 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7418 if (op
== 0x1) /* bx. */
7419 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7421 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7423 return arm_copy_undef (gdbarch
, insn
, dsc
);
7427 /* Not really supported. */
7428 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7430 return arm_copy_undef (gdbarch
, insn
, dsc
);
7434 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7435 regs
, dsc
); /* blx register. */
7437 return arm_copy_undef (gdbarch
, insn
, dsc
);
7440 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7444 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7446 /* Not really supported. */
7447 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7450 return arm_copy_undef (gdbarch
, insn
, dsc
);
7455 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7456 struct regcache
*regs
,
7457 struct displaced_step_closure
*dsc
)
7460 switch (bits (insn
, 20, 24))
7463 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7466 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7468 case 0x12: case 0x16:
7469 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7472 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7476 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7478 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7479 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7480 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7481 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7482 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7483 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7484 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7485 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7486 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7487 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7488 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7489 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7490 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7491 /* 2nd arg means "unpriveleged". */
7492 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7496 /* Should be unreachable. */
7501 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7502 struct regcache
*regs
,
7503 struct displaced_step_closure
*dsc
)
7505 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7506 uint32_t op1
= bits (insn
, 20, 24);
7507 int rn_f
= bits (insn
, 16, 19) == 0xf;
7509 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7510 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7511 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7512 else if ((!a
&& (op1
& 0x17) == 0x02)
7513 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7514 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7515 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7516 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7517 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7518 else if ((!a
&& (op1
& 0x17) == 0x03)
7519 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7520 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7521 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7522 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7523 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7524 else if ((!a
&& (op1
& 0x17) == 0x06)
7525 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7526 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7527 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7528 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7529 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7530 else if ((!a
&& (op1
& 0x17) == 0x07)
7531 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7532 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7534 /* Should be unreachable. */
7539 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7540 struct displaced_step_closure
*dsc
)
7542 switch (bits (insn
, 20, 24))
7544 case 0x00: case 0x01: case 0x02: case 0x03:
7545 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7547 case 0x04: case 0x05: case 0x06: case 0x07:
7548 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7550 case 0x08: case 0x09: case 0x0a: case 0x0b:
7551 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7552 return arm_copy_unmodified (gdbarch
, insn
,
7553 "decode/pack/unpack/saturate/reverse", dsc
);
7556 if (bits (insn
, 5, 7) == 0) /* op2. */
7558 if (bits (insn
, 12, 15) == 0xf)
7559 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7561 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7564 return arm_copy_undef (gdbarch
, insn
, dsc
);
7566 case 0x1a: case 0x1b:
7567 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7568 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7570 return arm_copy_undef (gdbarch
, insn
, dsc
);
7572 case 0x1c: case 0x1d:
7573 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7575 if (bits (insn
, 0, 3) == 0xf)
7576 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7578 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7581 return arm_copy_undef (gdbarch
, insn
, dsc
);
7583 case 0x1e: case 0x1f:
7584 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7585 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7587 return arm_copy_undef (gdbarch
, insn
, dsc
);
7590 /* Should be unreachable. */
7595 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7596 struct regcache
*regs
,
7597 struct displaced_step_closure
*dsc
)
7600 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7602 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7606 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7607 struct regcache
*regs
,
7608 struct displaced_step_closure
*dsc
)
7610 unsigned int opcode
= bits (insn
, 20, 24);
7614 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7615 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7617 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7618 case 0x12: case 0x16:
7619 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7621 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7622 case 0x13: case 0x17:
7623 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7625 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7626 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7627 /* Note: no writeback for these instructions. Bit 25 will always be
7628 zero though (via caller), so the following works OK. */
7629 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7632 /* Should be unreachable. */
7636 /* Decode shifted register instructions. */
7639 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7640 uint16_t insn2
, struct regcache
*regs
,
7641 struct displaced_step_closure
*dsc
)
7643 /* PC is only allowed to be used in instruction MOV. */
7645 unsigned int op
= bits (insn1
, 5, 8);
7646 unsigned int rn
= bits (insn1
, 0, 3);
7648 if (op
== 0x2 && rn
== 0xf) /* MOV */
7649 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7651 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7652 "dp (shift reg)", dsc
);
7656 /* Decode extension register load/store. Exactly the same as
7657 arm_decode_ext_reg_ld_st. */
7660 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7661 uint16_t insn2
, struct regcache
*regs
,
7662 struct displaced_step_closure
*dsc
)
7664 unsigned int opcode
= bits (insn1
, 4, 8);
7668 case 0x04: case 0x05:
7669 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7670 "vfp/neon vmov", dsc
);
7672 case 0x08: case 0x0c: /* 01x00 */
7673 case 0x0a: case 0x0e: /* 01x10 */
7674 case 0x12: case 0x16: /* 10x10 */
7675 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7676 "vfp/neon vstm/vpush", dsc
);
7678 case 0x09: case 0x0d: /* 01x01 */
7679 case 0x0b: case 0x0f: /* 01x11 */
7680 case 0x13: case 0x17: /* 10x11 */
7681 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7682 "vfp/neon vldm/vpop", dsc
);
7684 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7685 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7687 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7688 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7691 /* Should be unreachable. */
7696 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7697 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7699 unsigned int op1
= bits (insn
, 20, 25);
7700 int op
= bit (insn
, 4);
7701 unsigned int coproc
= bits (insn
, 8, 11);
7702 unsigned int rn
= bits (insn
, 16, 19);
7704 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7705 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7706 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7707 && (coproc
& 0xe) != 0xa)
7709 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7710 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7711 && (coproc
& 0xe) != 0xa)
7712 /* ldc/ldc2 imm/lit. */
7713 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7714 else if ((op1
& 0x3e) == 0x00)
7715 return arm_copy_undef (gdbarch
, insn
, dsc
);
7716 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7717 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7718 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7719 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7720 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7721 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7722 else if ((op1
& 0x30) == 0x20 && !op
)
7724 if ((coproc
& 0xe) == 0xa)
7725 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7727 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7729 else if ((op1
& 0x30) == 0x20 && op
)
7730 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7731 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7732 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7733 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7734 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7735 else if ((op1
& 0x30) == 0x30)
7736 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7738 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7742 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7743 uint16_t insn2
, struct regcache
*regs
,
7744 struct displaced_step_closure
*dsc
)
7746 unsigned int coproc
= bits (insn2
, 8, 11);
7747 unsigned int op1
= bits (insn1
, 4, 9);
7748 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7749 unsigned int bit_9
= bit (insn1
, 9);
7750 unsigned int bit_4
= bit (insn1
, 4);
7751 unsigned int rn
= bits (insn1
, 0, 3);
7756 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7757 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7759 else if (bit_5_8
== 0) /* UNDEFINED. */
7760 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7763 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7764 if ((coproc
& 0xe) == 0xa)
7765 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7767 else /* coproc is not 101x. */
7769 if (bit_4
== 0) /* STC/STC2. */
7770 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7772 else /* LDC/LDC2 {literal, immeidate}. */
7773 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7779 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7785 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7786 struct displaced_step_closure
*dsc
, int rd
)
7792 Preparation: Rd <- PC
7798 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7799 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7803 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7804 struct displaced_step_closure
*dsc
,
7805 int rd
, unsigned int imm
)
7808 /* Encoding T2: ADDS Rd, #imm */
7809 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7811 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7817 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7818 struct regcache
*regs
,
7819 struct displaced_step_closure
*dsc
)
7821 unsigned int rd
= bits (insn
, 8, 10);
7822 unsigned int imm8
= bits (insn
, 0, 7);
7824 if (debug_displaced
)
7825 fprintf_unfiltered (gdb_stdlog
,
7826 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7829 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7833 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7834 uint16_t insn2
, struct regcache
*regs
,
7835 struct displaced_step_closure
*dsc
)
7837 unsigned int rd
= bits (insn2
, 8, 11);
7838 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7839 extract raw immediate encoding rather than computing immediate. When
7840 generating ADD or SUB instruction, we can simply perform OR operation to
7841 set immediate into ADD. */
7842 unsigned int imm_3_8
= insn2
& 0x70ff;
7843 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7845 if (debug_displaced
)
7846 fprintf_unfiltered (gdb_stdlog
,
7847 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7848 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7850 if (bit (insn1
, 7)) /* Encoding T2 */
7852 /* Encoding T3: SUB Rd, Rd, #imm */
7853 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7854 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7856 else /* Encoding T3 */
7858 /* Encoding T3: ADD Rd, Rd, #imm */
7859 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7860 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7864 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7870 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
7871 struct regcache
*regs
,
7872 struct displaced_step_closure
*dsc
)
7874 unsigned int rt
= bits (insn1
, 8, 10);
7876 int imm8
= (bits (insn1
, 0, 7) << 2);
7877 CORE_ADDR from
= dsc
->insn_addr
;
7883 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7885 Insn: LDR R0, [R2, R3];
7886 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7888 if (debug_displaced
)
7889 fprintf_unfiltered (gdb_stdlog
,
7890 "displaced: copying thumb ldr r%d [pc #%d]\n"
7893 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7894 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7895 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7896 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7897 /* The assembler calculates the required value of the offset from the
7898 Align(PC,4) value of this instruction to the label. */
7899 pc
= pc
& 0xfffffffc;
7901 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7902 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7905 dsc
->u
.ldst
.xfersize
= 4;
7907 dsc
->u
.ldst
.immed
= 0;
7908 dsc
->u
.ldst
.writeback
= 0;
7909 dsc
->u
.ldst
.restore_r4
= 0;
7911 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7913 dsc
->cleanup
= &cleanup_load
;
7918 /* Copy Thumb cbnz/cbz insruction. */
7921 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7922 struct regcache
*regs
,
7923 struct displaced_step_closure
*dsc
)
7925 int non_zero
= bit (insn1
, 11);
7926 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7927 CORE_ADDR from
= dsc
->insn_addr
;
7928 int rn
= bits (insn1
, 0, 2);
7929 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7931 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7932 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7933 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7934 condition is false, let it be, cleanup_branch will do nothing. */
7935 if (dsc
->u
.branch
.cond
)
7937 dsc
->u
.branch
.cond
= INST_AL
;
7938 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7941 dsc
->u
.branch
.dest
= from
+ 2;
7943 dsc
->u
.branch
.link
= 0;
7944 dsc
->u
.branch
.exchange
= 0;
7946 if (debug_displaced
)
7947 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7948 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7949 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7951 dsc
->modinsn
[0] = THUMB_NOP
;
7953 dsc
->cleanup
= &cleanup_branch
;
7957 /* Copy Table Branch Byte/Halfword */
7959 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7960 uint16_t insn2
, struct regcache
*regs
,
7961 struct displaced_step_closure
*dsc
)
7963 ULONGEST rn_val
, rm_val
;
7964 int is_tbh
= bit (insn2
, 4);
7965 CORE_ADDR halfwords
= 0;
7966 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7968 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7969 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7975 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7976 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7982 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7983 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7986 if (debug_displaced
)
7987 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7988 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7989 (unsigned int) rn_val
, (unsigned int) rm_val
,
7990 (unsigned int) halfwords
);
7992 dsc
->u
.branch
.cond
= INST_AL
;
7993 dsc
->u
.branch
.link
= 0;
7994 dsc
->u
.branch
.exchange
= 0;
7995 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7997 dsc
->cleanup
= &cleanup_branch
;
8003 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8004 struct displaced_step_closure
*dsc
)
8007 int val
= displaced_read_reg (regs
, dsc
, 7);
8008 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8011 val
= displaced_read_reg (regs
, dsc
, 8);
8012 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8015 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8020 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8021 struct regcache
*regs
,
8022 struct displaced_step_closure
*dsc
)
8024 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8026 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8029 (1) register list is full, that is, r0-r7 are used.
8030 Prepare: tmp[0] <- r8
8032 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8033 MOV r8, r7; Move value of r7 to r8;
8034 POP {r7}; Store PC value into r7.
8036 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8038 (2) register list is not full, supposing there are N registers in
8039 register list (except PC, 0 <= N <= 7).
8040 Prepare: for each i, 0 - N, tmp[i] <- ri.
8042 POP {r0, r1, ...., rN};
8044 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8045 from tmp[] properly.
8047 if (debug_displaced
)
8048 fprintf_unfiltered (gdb_stdlog
,
8049 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8050 dsc
->u
.block
.regmask
, insn1
);
8052 if (dsc
->u
.block
.regmask
== 0xff)
8054 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8056 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8057 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8058 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8061 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8065 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8066 unsigned int new_regmask
, bit
= 1;
8067 unsigned int to
= 0, from
= 0, i
, new_rn
;
8069 for (i
= 0; i
< num_in_list
+ 1; i
++)
8070 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8072 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8074 if (debug_displaced
)
8075 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8076 "{..., pc}: original reg list %.4x,"
8077 " modified list %.4x\n"),
8078 (int) dsc
->u
.block
.regmask
, new_regmask
);
8080 dsc
->u
.block
.regmask
|= 0x8000;
8081 dsc
->u
.block
.writeback
= 0;
8082 dsc
->u
.block
.cond
= INST_AL
;
8084 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8086 dsc
->cleanup
= &cleanup_block_load_pc
;
8093 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8094 struct regcache
*regs
,
8095 struct displaced_step_closure
*dsc
)
8097 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8098 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8101 /* 16-bit thumb instructions. */
8102 switch (op_bit_12_15
)
8104 /* Shift (imme), add, subtract, move and compare. */
8105 case 0: case 1: case 2: case 3:
8106 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8107 "shift/add/sub/mov/cmp",
8111 switch (op_bit_10_11
)
8113 case 0: /* Data-processing */
8114 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8118 case 1: /* Special data instructions and branch and exchange. */
8120 unsigned short op
= bits (insn1
, 7, 9);
8121 if (op
== 6 || op
== 7) /* BX or BLX */
8122 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8123 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8124 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8126 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8130 default: /* LDR (literal) */
8131 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8134 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8135 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8138 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8139 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8140 else /* Generate SP-relative address */
8141 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8143 case 11: /* Misc 16-bit instructions */
8145 switch (bits (insn1
, 8, 11))
8147 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8148 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8150 case 12: case 13: /* POP */
8151 if (bit (insn1
, 8)) /* PC is in register list. */
8152 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8154 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8156 case 15: /* If-Then, and hints */
8157 if (bits (insn1
, 0, 3))
8158 /* If-Then makes up to four following instructions conditional.
8159 IT instruction itself is not conditional, so handle it as a
8160 common unmodified instruction. */
8161 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8164 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8167 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8172 if (op_bit_10_11
< 2) /* Store multiple registers */
8173 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8174 else /* Load multiple registers */
8175 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8177 case 13: /* Conditional branch and supervisor call */
8178 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8179 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8181 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8183 case 14: /* Unconditional branch */
8184 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8191 internal_error (__FILE__
, __LINE__
,
8192 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8196 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8197 uint16_t insn1
, uint16_t insn2
,
8198 struct regcache
*regs
,
8199 struct displaced_step_closure
*dsc
)
8201 int rt
= bits (insn2
, 12, 15);
8202 int rn
= bits (insn1
, 0, 3);
8203 int op1
= bits (insn1
, 7, 8);
8206 switch (bits (insn1
, 5, 6))
8208 case 0: /* Load byte and memory hints */
8209 if (rt
== 0xf) /* PLD/PLI */
8212 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8213 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8215 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8220 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8221 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8224 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8225 "ldrb{reg, immediate}/ldrbt",
8230 case 1: /* Load halfword and memory hints. */
8231 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8232 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8233 "pld/unalloc memhint", dsc
);
8237 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8240 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8244 case 2: /* Load word */
8246 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8249 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8250 else if (op1
== 0x1) /* Encoding T3 */
8251 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8253 else /* op1 == 0x0 */
8255 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8256 /* LDR (immediate) */
8257 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8258 dsc
, bit (insn2
, 8), 1);
8259 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8260 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8263 /* LDR (register) */
8264 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8270 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8277 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8278 uint16_t insn2
, struct regcache
*regs
,
8279 struct displaced_step_closure
*dsc
)
8282 unsigned short op
= bit (insn2
, 15);
8283 unsigned int op1
= bits (insn1
, 11, 12);
8289 switch (bits (insn1
, 9, 10))
8294 /* Load/store {dual, execlusive}, table branch. */
8295 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8296 && bits (insn2
, 5, 7) == 0)
8297 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8300 /* PC is not allowed to use in load/store {dual, exclusive}
8302 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8303 "load/store dual/ex", dsc
);
8305 else /* load/store multiple */
8307 switch (bits (insn1
, 7, 8))
8309 case 0: case 3: /* SRS, RFE */
8310 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8313 case 1: case 2: /* LDM/STM/PUSH/POP */
8314 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8321 /* Data-processing (shift register). */
8322 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8325 default: /* Coprocessor instructions. */
8326 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8331 case 2: /* op1 = 2 */
8332 if (op
) /* Branch and misc control. */
8334 if (bit (insn2
, 14) /* BLX/BL */
8335 || bit (insn2
, 12) /* Unconditional branch */
8336 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8337 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8339 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8344 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8346 int op
= bits (insn1
, 4, 8);
8347 int rn
= bits (insn1
, 0, 3);
8348 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8349 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8352 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8355 else /* Data processing (modified immeidate) */
8356 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8360 case 3: /* op1 = 3 */
8361 switch (bits (insn1
, 9, 10))
8365 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8367 else /* NEON Load/Store and Store single data item */
8368 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8369 "neon elt/struct load/store",
8372 case 1: /* op1 = 3, bits (9, 10) == 1 */
8373 switch (bits (insn1
, 7, 8))
8375 case 0: case 1: /* Data processing (register) */
8376 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8379 case 2: /* Multiply and absolute difference */
8380 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8381 "mul/mua/diff", dsc
);
8383 case 3: /* Long multiply and divide */
8384 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8389 default: /* Coprocessor instructions */
8390 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8399 internal_error (__FILE__
, __LINE__
,
8400 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8405 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8406 CORE_ADDR to
, struct regcache
*regs
,
8407 struct displaced_step_closure
*dsc
)
8409 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8411 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8413 if (debug_displaced
)
8414 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8415 "at %.8lx\n", insn1
, (unsigned long) from
);
8418 dsc
->insn_size
= thumb_insn_size (insn1
);
8419 if (thumb_insn_size (insn1
) == 4)
8422 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8423 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8426 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8430 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8431 CORE_ADDR to
, struct regcache
*regs
,
8432 struct displaced_step_closure
*dsc
)
8435 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8438 /* Most displaced instructions use a 1-instruction scratch space, so set this
8439 here and override below if/when necessary. */
8441 dsc
->insn_addr
= from
;
8442 dsc
->scratch_base
= to
;
8443 dsc
->cleanup
= NULL
;
8444 dsc
->wrote_to_pc
= 0;
8446 if (!displaced_in_arm_mode (regs
))
8447 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8451 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8452 if (debug_displaced
)
8453 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8454 "at %.8lx\n", (unsigned long) insn
,
8455 (unsigned long) from
);
8457 if ((insn
& 0xf0000000) == 0xf0000000)
8458 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8459 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8461 case 0x0: case 0x1: case 0x2: case 0x3:
8462 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8465 case 0x4: case 0x5: case 0x6:
8466 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8470 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8473 case 0x8: case 0x9: case 0xa: case 0xb:
8474 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8477 case 0xc: case 0xd: case 0xe: case 0xf:
8478 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8483 internal_error (__FILE__
, __LINE__
,
8484 _("arm_process_displaced_insn: Instruction decode error"));
8487 /* Actually set up the scratch space for a displaced instruction. */
8490 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8491 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8493 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8494 unsigned int i
, len
, offset
;
8495 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8496 int size
= dsc
->is_thumb
? 2 : 4;
8497 const unsigned char *bkp_insn
;
8500 /* Poke modified instruction(s). */
8501 for (i
= 0; i
< dsc
->numinsns
; i
++)
8503 if (debug_displaced
)
8505 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8507 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8510 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8511 (unsigned short)dsc
->modinsn
[i
]);
8513 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8514 (unsigned long) to
+ offset
);
8517 write_memory_unsigned_integer (to
+ offset
, size
,
8518 byte_order_for_code
,
8523 /* Choose the correct breakpoint instruction. */
8526 bkp_insn
= tdep
->thumb_breakpoint
;
8527 len
= tdep
->thumb_breakpoint_size
;
8531 bkp_insn
= tdep
->arm_breakpoint
;
8532 len
= tdep
->arm_breakpoint_size
;
8535 /* Put breakpoint afterwards. */
8536 write_memory (to
+ offset
, bkp_insn
, len
);
8538 if (debug_displaced
)
8539 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8540 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8543 /* Entry point for copying an instruction into scratch space for displaced
8546 struct displaced_step_closure
*
8547 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8548 CORE_ADDR from
, CORE_ADDR to
,
8549 struct regcache
*regs
)
8551 struct displaced_step_closure
*dsc
8552 = xmalloc (sizeof (struct displaced_step_closure
));
8553 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8554 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8559 /* Entry point for cleaning things up after a displaced instruction has been
8563 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8564 struct displaced_step_closure
*dsc
,
8565 CORE_ADDR from
, CORE_ADDR to
,
8566 struct regcache
*regs
)
8569 dsc
->cleanup (gdbarch
, regs
, dsc
);
8571 if (!dsc
->wrote_to_pc
)
8572 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8573 dsc
->insn_addr
+ dsc
->insn_size
);
8577 #include "bfd-in2.h"
8578 #include "libcoff.h"
8581 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8583 struct gdbarch
*gdbarch
= info
->application_data
;
8585 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8587 static asymbol
*asym
;
8588 static combined_entry_type ce
;
8589 static struct coff_symbol_struct csym
;
8590 static struct bfd fake_bfd
;
8591 static bfd_target fake_target
;
8593 if (csym
.native
== NULL
)
8595 /* Create a fake symbol vector containing a Thumb symbol.
8596 This is solely so that the code in print_insn_little_arm()
8597 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8598 the presence of a Thumb symbol and switch to decoding
8599 Thumb instructions. */
8601 fake_target
.flavour
= bfd_target_coff_flavour
;
8602 fake_bfd
.xvec
= &fake_target
;
8603 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8605 csym
.symbol
.the_bfd
= &fake_bfd
;
8606 csym
.symbol
.name
= "fake";
8607 asym
= (asymbol
*) & csym
;
8610 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8611 info
->symbols
= &asym
;
8614 info
->symbols
= NULL
;
8616 if (info
->endian
== BFD_ENDIAN_BIG
)
8617 return print_insn_big_arm (memaddr
, info
);
8619 return print_insn_little_arm (memaddr
, info
);
8622 /* The following define instruction sequences that will cause ARM
8623 cpu's to take an undefined instruction trap. These are used to
8624 signal a breakpoint to GDB.
8626 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8627 modes. A different instruction is required for each mode. The ARM
8628 cpu's can also be big or little endian. Thus four different
8629 instructions are needed to support all cases.
8631 Note: ARMv4 defines several new instructions that will take the
8632 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8633 not in fact add the new instructions. The new undefined
8634 instructions in ARMv4 are all instructions that had no defined
8635 behaviour in earlier chips. There is no guarantee that they will
8636 raise an exception, but may be treated as NOP's. In practice, it
8637 may only safe to rely on instructions matching:
8639 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8640 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8641 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8643 Even this may only true if the condition predicate is true. The
8644 following use a condition predicate of ALWAYS so it is always TRUE.
8646 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8647 and NetBSD all use a software interrupt rather than an undefined
8648 instruction to force a trap. This can be handled by by the
8649 abi-specific code during establishment of the gdbarch vector. */
8651 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8652 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8653 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8654 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8656 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8657 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8658 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8659 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8661 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8662 the program counter value to determine whether a 16-bit or 32-bit
8663 breakpoint should be used. It returns a pointer to a string of
8664 bytes that encode a breakpoint instruction, stores the length of
8665 the string to *lenptr, and adjusts the program counter (if
8666 necessary) to point to the actual memory location where the
8667 breakpoint should be inserted. */
8669 static const unsigned char *
8670 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8672 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8673 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8675 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8677 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8679 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8680 check whether we are replacing a 32-bit instruction. */
8681 if (tdep
->thumb2_breakpoint
!= NULL
)
8684 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8686 unsigned short inst1
;
8687 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8688 if (thumb_insn_size (inst1
) == 4)
8690 *lenptr
= tdep
->thumb2_breakpoint_size
;
8691 return tdep
->thumb2_breakpoint
;
8696 *lenptr
= tdep
->thumb_breakpoint_size
;
8697 return tdep
->thumb_breakpoint
;
8701 *lenptr
= tdep
->arm_breakpoint_size
;
8702 return tdep
->arm_breakpoint
;
8707 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8710 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8712 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8714 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8715 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8716 that this is not confused with a 32-bit ARM breakpoint. */
8720 /* Extract from an array REGBUF containing the (raw) register state a
8721 function return value of type TYPE, and copy that, in virtual
8722 format, into VALBUF. */
8725 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8728 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8729 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8731 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8733 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8737 /* The value is in register F0 in internal format. We need to
8738 extract the raw value and then convert it to the desired
8740 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8742 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8743 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8744 valbuf
, gdbarch_byte_order (gdbarch
));
8748 case ARM_FLOAT_SOFT_FPA
:
8749 case ARM_FLOAT_SOFT_VFP
:
8750 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8751 not using the VFP ABI code. */
8753 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8754 if (TYPE_LENGTH (type
) > 4)
8755 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8756 valbuf
+ INT_REGISTER_SIZE
);
8760 internal_error (__FILE__
, __LINE__
,
8761 _("arm_extract_return_value: "
8762 "Floating point model not supported"));
8766 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8767 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8768 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8769 || TYPE_CODE (type
) == TYPE_CODE_PTR
8770 || TYPE_CODE (type
) == TYPE_CODE_REF
8771 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8773 /* If the type is a plain integer, then the access is
8774 straight-forward. Otherwise we have to play around a bit
8776 int len
= TYPE_LENGTH (type
);
8777 int regno
= ARM_A1_REGNUM
;
8782 /* By using store_unsigned_integer we avoid having to do
8783 anything special for small big-endian values. */
8784 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8785 store_unsigned_integer (valbuf
,
8786 (len
> INT_REGISTER_SIZE
8787 ? INT_REGISTER_SIZE
: len
),
8789 len
-= INT_REGISTER_SIZE
;
8790 valbuf
+= INT_REGISTER_SIZE
;
8795 /* For a structure or union the behaviour is as if the value had
8796 been stored to word-aligned memory and then loaded into
8797 registers with 32-bit load instruction(s). */
8798 int len
= TYPE_LENGTH (type
);
8799 int regno
= ARM_A1_REGNUM
;
8800 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8804 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8805 memcpy (valbuf
, tmpbuf
,
8806 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8807 len
-= INT_REGISTER_SIZE
;
8808 valbuf
+= INT_REGISTER_SIZE
;
8814 /* Will a function return an aggregate type in memory or in a
8815 register? Return 0 if an aggregate type can be returned in a
8816 register, 1 if it must be returned in memory. */
8819 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8822 enum type_code code
;
8824 CHECK_TYPEDEF (type
);
8826 /* In the ARM ABI, "integer" like aggregate types are returned in
8827 registers. For an aggregate type to be integer like, its size
8828 must be less than or equal to INT_REGISTER_SIZE and the
8829 offset of each addressable subfield must be zero. Note that bit
8830 fields are not addressable, and all addressable subfields of
8831 unions always start at offset zero.
8833 This function is based on the behaviour of GCC 2.95.1.
8834 See: gcc/arm.c: arm_return_in_memory() for details.
8836 Note: All versions of GCC before GCC 2.95.2 do not set up the
8837 parameters correctly for a function returning the following
8838 structure: struct { float f;}; This should be returned in memory,
8839 not a register. Richard Earnshaw sent me a patch, but I do not
8840 know of any way to detect if a function like the above has been
8841 compiled with the correct calling convention. */
8843 /* All aggregate types that won't fit in a register must be returned
8845 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8850 /* The AAPCS says all aggregates not larger than a word are returned
8852 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8855 /* The only aggregate types that can be returned in a register are
8856 structs and unions. Arrays must be returned in memory. */
8857 code
= TYPE_CODE (type
);
8858 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
8863 /* Assume all other aggregate types can be returned in a register.
8864 Run a check for structures, unions and arrays. */
8867 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8870 /* Need to check if this struct/union is "integer" like. For
8871 this to be true, its size must be less than or equal to
8872 INT_REGISTER_SIZE and the offset of each addressable
8873 subfield must be zero. Note that bit fields are not
8874 addressable, and unions always start at offset zero. If any
8875 of the subfields is a floating point type, the struct/union
8876 cannot be an integer type. */
8878 /* For each field in the object, check:
8879 1) Is it FP? --> yes, nRc = 1;
8880 2) Is it addressable (bitpos != 0) and
8881 not packed (bitsize == 0)?
8885 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8887 enum type_code field_type_code
;
8888 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8891 /* Is it a floating point type field? */
8892 if (field_type_code
== TYPE_CODE_FLT
)
8898 /* If bitpos != 0, then we have to care about it. */
8899 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8901 /* Bitfields are not addressable. If the field bitsize is
8902 zero, then the field is not packed. Hence it cannot be
8903 a bitfield or any other packed type. */
8904 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8916 /* Write into appropriate registers a function return value of type
8917 TYPE, given in virtual format. */
8920 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8921 const gdb_byte
*valbuf
)
8923 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8924 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8926 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8928 char buf
[MAX_REGISTER_SIZE
];
8930 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8934 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8935 gdbarch_byte_order (gdbarch
));
8936 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8939 case ARM_FLOAT_SOFT_FPA
:
8940 case ARM_FLOAT_SOFT_VFP
:
8941 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8942 not using the VFP ABI code. */
8944 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8945 if (TYPE_LENGTH (type
) > 4)
8946 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8947 valbuf
+ INT_REGISTER_SIZE
);
8951 internal_error (__FILE__
, __LINE__
,
8952 _("arm_store_return_value: Floating "
8953 "point model not supported"));
8957 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8958 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8959 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8960 || TYPE_CODE (type
) == TYPE_CODE_PTR
8961 || TYPE_CODE (type
) == TYPE_CODE_REF
8962 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8964 if (TYPE_LENGTH (type
) <= 4)
8966 /* Values of one word or less are zero/sign-extended and
8968 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8969 LONGEST val
= unpack_long (type
, valbuf
);
8971 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8972 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8976 /* Integral values greater than one word are stored in consecutive
8977 registers starting with r0. This will always be a multiple of
8978 the regiser size. */
8979 int len
= TYPE_LENGTH (type
);
8980 int regno
= ARM_A1_REGNUM
;
8984 regcache_cooked_write (regs
, regno
++, valbuf
);
8985 len
-= INT_REGISTER_SIZE
;
8986 valbuf
+= INT_REGISTER_SIZE
;
8992 /* For a structure or union the behaviour is as if the value had
8993 been stored to word-aligned memory and then loaded into
8994 registers with 32-bit load instruction(s). */
8995 int len
= TYPE_LENGTH (type
);
8996 int regno
= ARM_A1_REGNUM
;
8997 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9001 memcpy (tmpbuf
, valbuf
,
9002 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9003 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9004 len
-= INT_REGISTER_SIZE
;
9005 valbuf
+= INT_REGISTER_SIZE
;
9011 /* Handle function return values. */
9013 static enum return_value_convention
9014 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
9015 struct type
*valtype
, struct regcache
*regcache
,
9016 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9018 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9019 enum arm_vfp_cprc_base_type vfp_base_type
;
9022 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9023 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9025 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9026 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9028 for (i
= 0; i
< vfp_base_count
; i
++)
9030 if (reg_char
== 'q')
9033 arm_neon_quad_write (gdbarch
, regcache
, i
,
9034 writebuf
+ i
* unit_length
);
9037 arm_neon_quad_read (gdbarch
, regcache
, i
,
9038 readbuf
+ i
* unit_length
);
9045 sprintf (name_buf
, "%c%d", reg_char
, i
);
9046 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9049 regcache_cooked_write (regcache
, regnum
,
9050 writebuf
+ i
* unit_length
);
9052 regcache_cooked_read (regcache
, regnum
,
9053 readbuf
+ i
* unit_length
);
9056 return RETURN_VALUE_REGISTER_CONVENTION
;
9059 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9060 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9061 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9063 if (tdep
->struct_return
== pcc_struct_return
9064 || arm_return_in_memory (gdbarch
, valtype
))
9065 return RETURN_VALUE_STRUCT_CONVENTION
;
9068 /* AAPCS returns complex types longer than a register in memory. */
9069 if (tdep
->arm_abi
!= ARM_ABI_APCS
9070 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9071 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9072 return RETURN_VALUE_STRUCT_CONVENTION
;
9075 arm_store_return_value (valtype
, regcache
, writebuf
);
9078 arm_extract_return_value (valtype
, regcache
, readbuf
);
9080 return RETURN_VALUE_REGISTER_CONVENTION
;
9085 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9087 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9088 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9089 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9091 char buf
[INT_REGISTER_SIZE
];
9093 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9095 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9099 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9103 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9104 return the target PC. Otherwise return 0. */
9107 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9111 CORE_ADDR start_addr
;
9113 /* Find the starting address and name of the function containing the PC. */
9114 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9117 /* If PC is in a Thumb call or return stub, return the address of the
9118 target PC, which is in a register. The thunk functions are called
9119 _call_via_xx, where x is the register name. The possible names
9120 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9121 functions, named __ARM_call_via_r[0-7]. */
9122 if (strncmp (name
, "_call_via_", 10) == 0
9123 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9125 /* Use the name suffix to determine which register contains the
9127 static char *table
[15] =
9128 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9129 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9132 int offset
= strlen (name
) - 2;
9134 for (regno
= 0; regno
<= 14; regno
++)
9135 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9136 return get_frame_register_unsigned (frame
, regno
);
9139 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9140 non-interworking calls to foo. We could decode the stubs
9141 to find the target but it's easier to use the symbol table. */
9142 namelen
= strlen (name
);
9143 if (name
[0] == '_' && name
[1] == '_'
9144 && ((namelen
> 2 + strlen ("_from_thumb")
9145 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
9146 strlen ("_from_thumb")) == 0)
9147 || (namelen
> 2 + strlen ("_from_arm")
9148 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
9149 strlen ("_from_arm")) == 0)))
9152 int target_len
= namelen
- 2;
9153 struct minimal_symbol
*minsym
;
9154 struct objfile
*objfile
;
9155 struct obj_section
*sec
;
9157 if (name
[namelen
- 1] == 'b')
9158 target_len
-= strlen ("_from_thumb");
9160 target_len
-= strlen ("_from_arm");
9162 target_name
= alloca (target_len
+ 1);
9163 memcpy (target_name
, name
+ 2, target_len
);
9164 target_name
[target_len
] = '\0';
9166 sec
= find_pc_section (pc
);
9167 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9168 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9170 return SYMBOL_VALUE_ADDRESS (minsym
);
9175 return 0; /* not a stub */
9179 set_arm_command (char *args
, int from_tty
)
9181 printf_unfiltered (_("\
9182 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9183 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9187 show_arm_command (char *args
, int from_tty
)
9189 cmd_show_list (showarmcmdlist
, from_tty
, "");
9193 arm_update_current_architecture (void)
9195 struct gdbarch_info info
;
9197 /* If the current architecture is not ARM, we have nothing to do. */
9198 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
9201 /* Update the architecture. */
9202 gdbarch_info_init (&info
);
9204 if (!gdbarch_update_p (info
))
9205 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9209 set_fp_model_sfunc (char *args
, int from_tty
,
9210 struct cmd_list_element
*c
)
9212 enum arm_float_model fp_model
;
9214 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9215 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9217 arm_fp_model
= fp_model
;
9221 if (fp_model
== ARM_FLOAT_LAST
)
9222 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9225 arm_update_current_architecture ();
9229 show_fp_model (struct ui_file
*file
, int from_tty
,
9230 struct cmd_list_element
*c
, const char *value
)
9232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
9234 if (arm_fp_model
== ARM_FLOAT_AUTO
9235 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
9236 fprintf_filtered (file
, _("\
9237 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9238 fp_model_strings
[tdep
->fp_model
]);
9240 fprintf_filtered (file
, _("\
9241 The current ARM floating point model is \"%s\".\n"),
9242 fp_model_strings
[arm_fp_model
]);
9246 arm_set_abi (char *args
, int from_tty
,
9247 struct cmd_list_element
*c
)
9249 enum arm_abi_kind arm_abi
;
9251 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9252 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9254 arm_abi_global
= arm_abi
;
9258 if (arm_abi
== ARM_ABI_LAST
)
9259 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9262 arm_update_current_architecture ();
9266 arm_show_abi (struct ui_file
*file
, int from_tty
,
9267 struct cmd_list_element
*c
, const char *value
)
9269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
9271 if (arm_abi_global
== ARM_ABI_AUTO
9272 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
9273 fprintf_filtered (file
, _("\
9274 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9275 arm_abi_strings
[tdep
->arm_abi
]);
9277 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9282 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9283 struct cmd_list_element
*c
, const char *value
)
9285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
9287 fprintf_filtered (file
,
9288 _("The current execution mode assumed "
9289 "(when symbols are unavailable) is \"%s\".\n"),
9290 arm_fallback_mode_string
);
9294 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9295 struct cmd_list_element
*c
, const char *value
)
9297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
9299 fprintf_filtered (file
,
9300 _("The current execution mode assumed "
9301 "(even when symbols are available) is \"%s\".\n"),
9302 arm_force_mode_string
);
9305 /* If the user changes the register disassembly style used for info
9306 register and other commands, we have to also switch the style used
9307 in opcodes for disassembly output. This function is run in the "set
9308 arm disassembly" command, and does that. */
9311 set_disassembly_style_sfunc (char *args
, int from_tty
,
9312 struct cmd_list_element
*c
)
9314 set_disassembly_style ();
9317 /* Return the ARM register name corresponding to register I. */
9319 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9321 const int num_regs
= gdbarch_num_regs (gdbarch
);
9323 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9324 && i
>= num_regs
&& i
< num_regs
+ 32)
9326 static const char *const vfp_pseudo_names
[] = {
9327 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9328 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9329 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9330 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9333 return vfp_pseudo_names
[i
- num_regs
];
9336 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9337 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9339 static const char *const neon_pseudo_names
[] = {
9340 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9341 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9344 return neon_pseudo_names
[i
- num_regs
- 32];
9347 if (i
>= ARRAY_SIZE (arm_register_names
))
9348 /* These registers are only supported on targets which supply
9349 an XML description. */
9352 return arm_register_names
[i
];
9356 set_disassembly_style (void)
9360 /* Find the style that the user wants. */
9361 for (current
= 0; current
< num_disassembly_options
; current
++)
9362 if (disassembly_style
== valid_disassembly_styles
[current
])
9364 gdb_assert (current
< num_disassembly_options
);
9366 /* Synchronize the disassembler. */
9367 set_arm_regname_option (current
);
9370 /* Test whether the coff symbol specific value corresponds to a Thumb
9374 coff_sym_is_thumb (int val
)
9376 return (val
== C_THUMBEXT
9377 || val
== C_THUMBSTAT
9378 || val
== C_THUMBEXTFUNC
9379 || val
== C_THUMBSTATFUNC
9380 || val
== C_THUMBLABEL
);
9383 /* arm_coff_make_msymbol_special()
9384 arm_elf_make_msymbol_special()
9386 These functions test whether the COFF or ELF symbol corresponds to
9387 an address in thumb code, and set a "special" bit in a minimal
9388 symbol to indicate that it does. */
9391 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9393 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9394 == ST_BRANCH_TO_THUMB
)
9395 MSYMBOL_SET_SPECIAL (msym
);
9399 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9401 if (coff_sym_is_thumb (val
))
9402 MSYMBOL_SET_SPECIAL (msym
);
9406 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9408 struct arm_per_objfile
*data
= arg
;
9411 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9412 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9416 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9419 const char *name
= bfd_asymbol_name (sym
);
9420 struct arm_per_objfile
*data
;
9421 VEC(arm_mapping_symbol_s
) **map_p
;
9422 struct arm_mapping_symbol new_map_sym
;
9424 gdb_assert (name
[0] == '$');
9425 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9428 data
= objfile_data (objfile
, arm_objfile_data_key
);
9431 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9432 struct arm_per_objfile
);
9433 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9434 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9435 objfile
->obfd
->section_count
,
9436 VEC(arm_mapping_symbol_s
) *);
9438 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9440 new_map_sym
.value
= sym
->value
;
9441 new_map_sym
.type
= name
[1];
9443 /* Assume that most mapping symbols appear in order of increasing
9444 value. If they were randomly distributed, it would be faster to
9445 always push here and then sort at first use. */
9446 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9448 struct arm_mapping_symbol
*prev_map_sym
;
9450 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9451 if (prev_map_sym
->value
>= sym
->value
)
9454 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9455 arm_compare_mapping_symbols
);
9456 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9461 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9465 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9467 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9468 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9470 /* If necessary, set the T bit. */
9473 ULONGEST val
, t_bit
;
9474 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9475 t_bit
= arm_psr_thumb_bit (gdbarch
);
9476 if (arm_pc_is_thumb (gdbarch
, pc
))
9477 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9480 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9485 /* Read the contents of a NEON quad register, by reading from two
9486 double registers. This is used to implement the quad pseudo
9487 registers, and for argument passing in case the quad registers are
9488 missing; vectors are passed in quad registers when using the VFP
9489 ABI, even if a NEON unit is not present. REGNUM is the index of
9490 the quad register, in [0, 15]. */
9492 static enum register_status
9493 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9494 int regnum
, gdb_byte
*buf
)
9497 gdb_byte reg_buf
[8];
9498 int offset
, double_regnum
;
9499 enum register_status status
;
9501 sprintf (name_buf
, "d%d", regnum
<< 1);
9502 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9505 /* d0 is always the least significant half of q0. */
9506 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9511 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9512 if (status
!= REG_VALID
)
9514 memcpy (buf
+ offset
, reg_buf
, 8);
9516 offset
= 8 - offset
;
9517 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9518 if (status
!= REG_VALID
)
9520 memcpy (buf
+ offset
, reg_buf
, 8);
9525 static enum register_status
9526 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9527 int regnum
, gdb_byte
*buf
)
9529 const int num_regs
= gdbarch_num_regs (gdbarch
);
9531 gdb_byte reg_buf
[8];
9532 int offset
, double_regnum
;
9534 gdb_assert (regnum
>= num_regs
);
9537 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9538 /* Quad-precision register. */
9539 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9542 enum register_status status
;
9544 /* Single-precision register. */
9545 gdb_assert (regnum
< 32);
9547 /* s0 is always the least significant half of d0. */
9548 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9549 offset
= (regnum
& 1) ? 0 : 4;
9551 offset
= (regnum
& 1) ? 4 : 0;
9553 sprintf (name_buf
, "d%d", regnum
>> 1);
9554 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9557 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9558 if (status
== REG_VALID
)
9559 memcpy (buf
, reg_buf
+ offset
, 4);
9564 /* Store the contents of BUF to a NEON quad register, by writing to
9565 two double registers. This is used to implement the quad pseudo
9566 registers, and for argument passing in case the quad registers are
9567 missing; vectors are passed in quad registers when using the VFP
9568 ABI, even if a NEON unit is not present. REGNUM is the index
9569 of the quad register, in [0, 15]. */
9572 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9573 int regnum
, const gdb_byte
*buf
)
9576 gdb_byte reg_buf
[8];
9577 int offset
, double_regnum
;
9579 sprintf (name_buf
, "d%d", regnum
<< 1);
9580 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9583 /* d0 is always the least significant half of q0. */
9584 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9589 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9590 offset
= 8 - offset
;
9591 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9595 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9596 int regnum
, const gdb_byte
*buf
)
9598 const int num_regs
= gdbarch_num_regs (gdbarch
);
9600 gdb_byte reg_buf
[8];
9601 int offset
, double_regnum
;
9603 gdb_assert (regnum
>= num_regs
);
9606 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9607 /* Quad-precision register. */
9608 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9611 /* Single-precision register. */
9612 gdb_assert (regnum
< 32);
9614 /* s0 is always the least significant half of d0. */
9615 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9616 offset
= (regnum
& 1) ? 0 : 4;
9618 offset
= (regnum
& 1) ? 4 : 0;
9620 sprintf (name_buf
, "d%d", regnum
>> 1);
9621 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9624 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9625 memcpy (reg_buf
+ offset
, buf
, 4);
9626 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9630 static struct value
*
9631 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9633 const int *reg_p
= baton
;
9634 return value_of_register (*reg_p
, frame
);
9637 static enum gdb_osabi
9638 arm_elf_osabi_sniffer (bfd
*abfd
)
9640 unsigned int elfosabi
;
9641 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9643 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9645 if (elfosabi
== ELFOSABI_ARM
)
9646 /* GNU tools use this value. Check note sections in this case,
9648 bfd_map_over_sections (abfd
,
9649 generic_elf_osabi_sniff_abi_tag_sections
,
9652 /* Anything else will be handled by the generic ELF sniffer. */
9657 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9658 struct reggroup
*group
)
9660 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9661 this, FPS register belongs to save_regroup, restore_reggroup, and
9662 all_reggroup, of course. */
9663 if (regnum
== ARM_FPS_REGNUM
)
9664 return (group
== float_reggroup
9665 || group
== save_reggroup
9666 || group
== restore_reggroup
9667 || group
== all_reggroup
);
9669 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9673 /* For backward-compatibility we allow two 'g' packet lengths with
9674 the remote protocol depending on whether FPA registers are
9675 supplied. M-profile targets do not have FPA registers, but some
9676 stubs already exist in the wild which use a 'g' packet which
9677 supplies them albeit with dummy values. The packet format which
9678 includes FPA registers should be considered deprecated for
9679 M-profile targets. */
9682 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9684 if (gdbarch_tdep (gdbarch
)->is_m
)
9686 /* If we know from the executable this is an M-profile target,
9687 cater for remote targets whose register set layout is the
9688 same as the FPA layout. */
9689 register_remote_g_packet_guess (gdbarch
,
9690 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9691 (16 * INT_REGISTER_SIZE
)
9692 + (8 * FP_REGISTER_SIZE
)
9693 + (2 * INT_REGISTER_SIZE
),
9694 tdesc_arm_with_m_fpa_layout
);
9696 /* The regular M-profile layout. */
9697 register_remote_g_packet_guess (gdbarch
,
9698 /* r0-r12,sp,lr,pc; xpsr */
9699 (16 * INT_REGISTER_SIZE
)
9700 + INT_REGISTER_SIZE
,
9703 /* M-profile plus M4F VFP. */
9704 register_remote_g_packet_guess (gdbarch
,
9705 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9706 (16 * INT_REGISTER_SIZE
)
9707 + (16 * VFP_REGISTER_SIZE
)
9708 + (2 * INT_REGISTER_SIZE
),
9709 tdesc_arm_with_m_vfp_d16
);
9712 /* Otherwise we don't have a useful guess. */
9716 /* Initialize the current architecture based on INFO. If possible,
9717 re-use an architecture from ARCHES, which is a list of
9718 architectures already created during this debugging session.
9720 Called e.g. at program startup, when reading a core file, and when
9721 reading a binary file. */
9723 static struct gdbarch
*
9724 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9726 struct gdbarch_tdep
*tdep
;
9727 struct gdbarch
*gdbarch
;
9728 struct gdbarch_list
*best_arch
;
9729 enum arm_abi_kind arm_abi
= arm_abi_global
;
9730 enum arm_float_model fp_model
= arm_fp_model
;
9731 struct tdesc_arch_data
*tdesc_data
= NULL
;
9733 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9735 int have_fpa_registers
= 1;
9736 const struct target_desc
*tdesc
= info
.target_desc
;
9738 /* If we have an object to base this architecture on, try to determine
9741 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9743 int ei_osabi
, e_flags
;
9745 switch (bfd_get_flavour (info
.abfd
))
9747 case bfd_target_aout_flavour
:
9748 /* Assume it's an old APCS-style ABI. */
9749 arm_abi
= ARM_ABI_APCS
;
9752 case bfd_target_coff_flavour
:
9753 /* Assume it's an old APCS-style ABI. */
9755 arm_abi
= ARM_ABI_APCS
;
9758 case bfd_target_elf_flavour
:
9759 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9760 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9762 if (ei_osabi
== ELFOSABI_ARM
)
9764 /* GNU tools used to use this value, but do not for EABI
9765 objects. There's nowhere to tag an EABI version
9766 anyway, so assume APCS. */
9767 arm_abi
= ARM_ABI_APCS
;
9769 else if (ei_osabi
== ELFOSABI_NONE
)
9771 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9772 int attr_arch
, attr_profile
;
9776 case EF_ARM_EABI_UNKNOWN
:
9777 /* Assume GNU tools. */
9778 arm_abi
= ARM_ABI_APCS
;
9781 case EF_ARM_EABI_VER4
:
9782 case EF_ARM_EABI_VER5
:
9783 arm_abi
= ARM_ABI_AAPCS
;
9784 /* EABI binaries default to VFP float ordering.
9785 They may also contain build attributes that can
9786 be used to identify if the VFP argument-passing
9788 if (fp_model
== ARM_FLOAT_AUTO
)
9791 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9796 /* "The user intended FP parameter/result
9797 passing to conform to AAPCS, base
9799 fp_model
= ARM_FLOAT_SOFT_VFP
;
9802 /* "The user intended FP parameter/result
9803 passing to conform to AAPCS, VFP
9805 fp_model
= ARM_FLOAT_VFP
;
9808 /* "The user intended FP parameter/result
9809 passing to conform to tool chain-specific
9810 conventions" - we don't know any such
9811 conventions, so leave it as "auto". */
9814 /* Attribute value not mentioned in the
9815 October 2008 ABI, so leave it as
9820 fp_model
= ARM_FLOAT_SOFT_VFP
;
9826 /* Leave it as "auto". */
9827 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9832 /* Detect M-profile programs. This only works if the
9833 executable file includes build attributes; GCC does
9834 copy them to the executable, but e.g. RealView does
9836 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9838 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9840 Tag_CPU_arch_profile
);
9841 /* GCC specifies the profile for v6-M; RealView only
9842 specifies the profile for architectures starting with
9843 V7 (as opposed to architectures with a tag
9844 numerically greater than TAG_CPU_ARCH_V7). */
9845 if (!tdesc_has_registers (tdesc
)
9846 && (attr_arch
== TAG_CPU_ARCH_V6_M
9847 || attr_arch
== TAG_CPU_ARCH_V6S_M
9848 || attr_profile
== 'M'))
9853 if (fp_model
== ARM_FLOAT_AUTO
)
9855 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9857 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9860 /* Leave it as "auto". Strictly speaking this case
9861 means FPA, but almost nobody uses that now, and
9862 many toolchains fail to set the appropriate bits
9863 for the floating-point model they use. */
9865 case EF_ARM_SOFT_FLOAT
:
9866 fp_model
= ARM_FLOAT_SOFT_FPA
;
9868 case EF_ARM_VFP_FLOAT
:
9869 fp_model
= ARM_FLOAT_VFP
;
9871 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9872 fp_model
= ARM_FLOAT_SOFT_VFP
;
9877 if (e_flags
& EF_ARM_BE8
)
9878 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9883 /* Leave it as "auto". */
9888 /* Check any target description for validity. */
9889 if (tdesc_has_registers (tdesc
))
9891 /* For most registers we require GDB's default names; but also allow
9892 the numeric names for sp / lr / pc, as a convenience. */
9893 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9894 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9895 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9897 const struct tdesc_feature
*feature
;
9900 feature
= tdesc_find_feature (tdesc
,
9901 "org.gnu.gdb.arm.core");
9902 if (feature
== NULL
)
9904 feature
= tdesc_find_feature (tdesc
,
9905 "org.gnu.gdb.arm.m-profile");
9906 if (feature
== NULL
)
9912 tdesc_data
= tdesc_data_alloc ();
9915 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9916 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9917 arm_register_names
[i
]);
9918 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9921 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9924 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9928 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9929 ARM_PS_REGNUM
, "xpsr");
9931 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9932 ARM_PS_REGNUM
, "cpsr");
9936 tdesc_data_cleanup (tdesc_data
);
9940 feature
= tdesc_find_feature (tdesc
,
9941 "org.gnu.gdb.arm.fpa");
9942 if (feature
!= NULL
)
9945 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9946 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9947 arm_register_names
[i
]);
9950 tdesc_data_cleanup (tdesc_data
);
9955 have_fpa_registers
= 0;
9957 feature
= tdesc_find_feature (tdesc
,
9958 "org.gnu.gdb.xscale.iwmmxt");
9959 if (feature
!= NULL
)
9961 static const char *const iwmmxt_names
[] = {
9962 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9963 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9964 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9965 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9969 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9971 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9972 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9974 /* Check for the control registers, but do not fail if they
9976 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9977 tdesc_numbered_register (feature
, tdesc_data
, i
,
9978 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9980 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9982 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9983 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9987 tdesc_data_cleanup (tdesc_data
);
9992 /* If we have a VFP unit, check whether the single precision registers
9993 are present. If not, then we will synthesize them as pseudo
9995 feature
= tdesc_find_feature (tdesc
,
9996 "org.gnu.gdb.arm.vfp");
9997 if (feature
!= NULL
)
9999 static const char *const vfp_double_names
[] = {
10000 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10001 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10002 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10003 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10006 /* Require the double precision registers. There must be either
10009 for (i
= 0; i
< 32; i
++)
10011 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10013 vfp_double_names
[i
]);
10017 if (!valid_p
&& i
== 16)
10020 /* Also require FPSCR. */
10021 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10022 ARM_FPSCR_REGNUM
, "fpscr");
10025 tdesc_data_cleanup (tdesc_data
);
10029 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10030 have_vfp_pseudos
= 1;
10032 have_vfp_registers
= 1;
10034 /* If we have VFP, also check for NEON. The architecture allows
10035 NEON without VFP (integer vector operations only), but GDB
10036 does not support that. */
10037 feature
= tdesc_find_feature (tdesc
,
10038 "org.gnu.gdb.arm.neon");
10039 if (feature
!= NULL
)
10041 /* NEON requires 32 double-precision registers. */
10044 tdesc_data_cleanup (tdesc_data
);
10048 /* If there are quad registers defined by the stub, use
10049 their type; otherwise (normally) provide them with
10050 the default type. */
10051 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10052 have_neon_pseudos
= 1;
10059 /* If there is already a candidate, use it. */
10060 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10062 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10064 if (arm_abi
!= ARM_ABI_AUTO
10065 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10068 if (fp_model
!= ARM_FLOAT_AUTO
10069 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10072 /* There are various other properties in tdep that we do not
10073 need to check here: those derived from a target description,
10074 since gdbarches with a different target description are
10075 automatically disqualified. */
10077 /* Do check is_m, though, since it might come from the binary. */
10078 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10081 /* Found a match. */
10085 if (best_arch
!= NULL
)
10087 if (tdesc_data
!= NULL
)
10088 tdesc_data_cleanup (tdesc_data
);
10089 return best_arch
->gdbarch
;
10092 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
10093 gdbarch
= gdbarch_alloc (&info
, tdep
);
10095 /* Record additional information about the architecture we are defining.
10096 These are gdbarch discriminators, like the OSABI. */
10097 tdep
->arm_abi
= arm_abi
;
10098 tdep
->fp_model
= fp_model
;
10100 tdep
->have_fpa_registers
= have_fpa_registers
;
10101 tdep
->have_vfp_registers
= have_vfp_registers
;
10102 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10103 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10104 tdep
->have_neon
= have_neon
;
10106 arm_register_g_packet_guesses (gdbarch
);
10109 switch (info
.byte_order_for_code
)
10111 case BFD_ENDIAN_BIG
:
10112 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10113 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10114 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10115 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10119 case BFD_ENDIAN_LITTLE
:
10120 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10121 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10122 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10123 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10128 internal_error (__FILE__
, __LINE__
,
10129 _("arm_gdbarch_init: bad byte order for float format"));
10132 /* On ARM targets char defaults to unsigned. */
10133 set_gdbarch_char_signed (gdbarch
, 0);
10135 /* Note: for displaced stepping, this includes the breakpoint, and one word
10136 of additional scratch space. This setting isn't used for anything beside
10137 displaced stepping at present. */
10138 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10140 /* This should be low enough for everything. */
10141 tdep
->lowest_pc
= 0x20;
10142 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10144 /* The default, for both APCS and AAPCS, is to return small
10145 structures in registers. */
10146 tdep
->struct_return
= reg_struct_return
;
10148 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10149 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10151 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10153 /* Frame handling. */
10154 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10155 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10156 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10158 frame_base_set_default (gdbarch
, &arm_normal_base
);
10160 /* Address manipulation. */
10161 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
10162 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10164 /* Advance PC across function entry code. */
10165 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10167 /* Detect whether PC is in function epilogue. */
10168 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
10170 /* Skip trampolines. */
10171 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10173 /* The stack grows downward. */
10174 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10176 /* Breakpoint manipulation. */
10177 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10178 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10179 arm_remote_breakpoint_from_pc
);
10181 /* Information about registers, etc. */
10182 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10183 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10184 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10185 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10186 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10188 /* This "info float" is FPA-specific. Use the generic version if we
10189 do not have FPA. */
10190 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10191 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10193 /* Internal <-> external register number maps. */
10194 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10195 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10197 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10199 /* Returning results. */
10200 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10203 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10205 /* Minsymbol frobbing. */
10206 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10207 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10208 arm_coff_make_msymbol_special
);
10209 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10211 /* Thumb-2 IT block support. */
10212 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10213 arm_adjust_breakpoint_address
);
10215 /* Virtual tables. */
10216 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10218 /* Hook in the ABI-specific overrides, if they have been registered. */
10219 gdbarch_init_osabi (info
, gdbarch
);
10221 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10223 /* Add some default predicates. */
10224 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10225 dwarf2_append_unwinders (gdbarch
);
10226 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10227 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10229 /* Now we have tuned the configuration, set a few final things,
10230 based on what the OS ABI has told us. */
10232 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10233 binaries are always marked. */
10234 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10235 tdep
->arm_abi
= ARM_ABI_APCS
;
10237 /* Watchpoints are not steppable. */
10238 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10240 /* We used to default to FPA for generic ARM, but almost nobody
10241 uses that now, and we now provide a way for the user to force
10242 the model. So default to the most useful variant. */
10243 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10244 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10246 if (tdep
->jb_pc
>= 0)
10247 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10249 /* Floating point sizes and format. */
10250 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10251 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10253 set_gdbarch_double_format
10254 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10255 set_gdbarch_long_double_format
10256 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10260 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10261 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10264 if (have_vfp_pseudos
)
10266 /* NOTE: These are the only pseudo registers used by
10267 the ARM target at the moment. If more are added, a
10268 little more care in numbering will be needed. */
10270 int num_pseudos
= 32;
10271 if (have_neon_pseudos
)
10273 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10274 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10275 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10280 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10282 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10284 /* Override tdesc_register_type to adjust the types of VFP
10285 registers for NEON. */
10286 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10289 /* Add standard register aliases. We add aliases even for those
10290 nanes which are used by the current architecture - it's simpler,
10291 and does no harm, since nothing ever lists user registers. */
10292 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10293 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10294 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10300 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10307 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10308 (unsigned long) tdep
->lowest_pc
);
10311 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10314 _initialize_arm_tdep (void)
10316 struct ui_file
*stb
;
10318 struct cmd_list_element
*new_set
, *new_show
;
10319 const char *setname
;
10320 const char *setdesc
;
10321 const char *const *regnames
;
10323 static char *helptext
;
10324 char regdesc
[1024], *rdptr
= regdesc
;
10325 size_t rest
= sizeof (regdesc
);
10327 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10329 arm_objfile_data_key
10330 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10332 /* Add ourselves to objfile event chain. */
10333 observer_attach_new_objfile (arm_exidx_new_objfile
);
10335 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10337 /* Register an ELF OS ABI sniffer for ARM binaries. */
10338 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10339 bfd_target_elf_flavour
,
10340 arm_elf_osabi_sniffer
);
10342 /* Initialize the standard target descriptions. */
10343 initialize_tdesc_arm_with_m ();
10344 initialize_tdesc_arm_with_m_fpa_layout ();
10345 initialize_tdesc_arm_with_m_vfp_d16 ();
10346 initialize_tdesc_arm_with_iwmmxt ();
10347 initialize_tdesc_arm_with_vfpv2 ();
10348 initialize_tdesc_arm_with_vfpv3 ();
10349 initialize_tdesc_arm_with_neon ();
10351 /* Get the number of possible sets of register names defined in opcodes. */
10352 num_disassembly_options
= get_arm_regname_num_options ();
10354 /* Add root prefix command for all "set arm"/"show arm" commands. */
10355 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10356 _("Various ARM-specific commands."),
10357 &setarmcmdlist
, "set arm ", 0, &setlist
);
10359 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10360 _("Various ARM-specific commands."),
10361 &showarmcmdlist
, "show arm ", 0, &showlist
);
10363 /* Sync the opcode insn printer with our register viewer. */
10364 parse_arm_disassembler_option ("reg-names-std");
10366 /* Initialize the array that will be passed to
10367 add_setshow_enum_cmd(). */
10368 valid_disassembly_styles
10369 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
10370 for (i
= 0; i
< num_disassembly_options
; i
++)
10372 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10373 valid_disassembly_styles
[i
] = setname
;
10374 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10377 /* When we find the default names, tell the disassembler to use
10379 if (!strcmp (setname
, "std"))
10381 disassembly_style
= setname
;
10382 set_arm_regname_option (i
);
10385 /* Mark the end of valid options. */
10386 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10388 /* Create the help text. */
10389 stb
= mem_fileopen ();
10390 fprintf_unfiltered (stb
, "%s%s%s",
10391 _("The valid values are:\n"),
10393 _("The default is \"std\"."));
10394 helptext
= ui_file_xstrdup (stb
, NULL
);
10395 ui_file_delete (stb
);
10397 add_setshow_enum_cmd("disassembler", no_class
,
10398 valid_disassembly_styles
, &disassembly_style
,
10399 _("Set the disassembly style."),
10400 _("Show the disassembly style."),
10402 set_disassembly_style_sfunc
,
10403 NULL
, /* FIXME: i18n: The disassembly style is
10405 &setarmcmdlist
, &showarmcmdlist
);
10407 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10408 _("Set usage of ARM 32-bit mode."),
10409 _("Show usage of ARM 32-bit mode."),
10410 _("When off, a 26-bit PC will be used."),
10412 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10414 &setarmcmdlist
, &showarmcmdlist
);
10416 /* Add a command to allow the user to force the FPU model. */
10417 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10418 _("Set the floating point type."),
10419 _("Show the floating point type."),
10420 _("auto - Determine the FP typefrom the OS-ABI.\n\
10421 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10422 fpa - FPA co-processor (GCC compiled).\n\
10423 softvfp - Software FP with pure-endian doubles.\n\
10424 vfp - VFP co-processor."),
10425 set_fp_model_sfunc
, show_fp_model
,
10426 &setarmcmdlist
, &showarmcmdlist
);
10428 /* Add a command to allow the user to force the ABI. */
10429 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10431 _("Show the ABI."),
10432 NULL
, arm_set_abi
, arm_show_abi
,
10433 &setarmcmdlist
, &showarmcmdlist
);
10435 /* Add two commands to allow the user to force the assumed
10437 add_setshow_enum_cmd ("fallback-mode", class_support
,
10438 arm_mode_strings
, &arm_fallback_mode_string
,
10439 _("Set the mode assumed when symbols are unavailable."),
10440 _("Show the mode assumed when symbols are unavailable."),
10441 NULL
, NULL
, arm_show_fallback_mode
,
10442 &setarmcmdlist
, &showarmcmdlist
);
10443 add_setshow_enum_cmd ("force-mode", class_support
,
10444 arm_mode_strings
, &arm_force_mode_string
,
10445 _("Set the mode assumed even when symbols are available."),
10446 _("Show the mode assumed even when symbols are available."),
10447 NULL
, NULL
, arm_show_force_mode
,
10448 &setarmcmdlist
, &showarmcmdlist
);
10450 /* Debugging flag. */
10451 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10452 _("Set ARM debugging."),
10453 _("Show ARM debugging."),
10454 _("When on, arm-specific debugging is enabled."),
10456 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10457 &setdebuglist
, &showdebuglist
);
10460 /* ARM-reversible process record data structures. */
10462 #define ARM_INSN_SIZE_BYTES 4
10463 #define THUMB_INSN_SIZE_BYTES 2
10464 #define THUMB2_INSN_SIZE_BYTES 4
10467 #define INSN_S_L_BIT_NUM 20
10469 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10472 unsigned int reg_len = LENGTH; \
10475 REGS = XNEWVEC (uint32_t, reg_len); \
10476 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10481 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10484 unsigned int mem_len = LENGTH; \
10487 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10488 memcpy(&MEMS->len, &RECORD_BUF[0], \
10489 sizeof(struct arm_mem_r) * LENGTH); \
10494 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10495 #define INSN_RECORDED(ARM_RECORD) \
10496 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10498 /* ARM memory record structure. */
10501 uint32_t len
; /* Record length. */
10502 CORE_ADDR addr
; /* Memory address. */
10505 /* ARM instruction record contains opcode of current insn
10506 and execution state (before entry to decode_insn()),
10507 contains list of to-be-modified registers and
10508 memory blocks (on return from decode_insn()). */
10510 typedef struct insn_decode_record_t
10512 struct gdbarch
*gdbarch
;
10513 struct regcache
*regcache
;
10514 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10515 uint32_t arm_insn
; /* Should accommodate thumb. */
10516 uint32_t cond
; /* Condition code. */
10517 uint32_t opcode
; /* Insn opcode. */
10518 uint32_t decode
; /* Insn decode bits. */
10519 uint32_t mem_rec_count
; /* No of mem records. */
10520 uint32_t reg_rec_count
; /* No of reg records. */
10521 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10522 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10523 } insn_decode_record
;
10526 /* Checks ARM SBZ and SBO mandatory fields. */
10529 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10531 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10554 } arm_record_strx_t
;
10565 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10566 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10569 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10570 ULONGEST u_regval
[2]= {0};
10572 uint32_t reg_src1
= 0, reg_src2
= 0;
10573 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10574 uint32_t opcode1
= 0;
10576 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10577 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10578 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10581 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10583 /* 1) Handle misc store, immediate offset. */
10584 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10585 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10586 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10587 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10589 if (ARM_PC_REGNUM
== reg_src1
)
10591 /* If R15 was used as Rn, hence current PC+8. */
10592 u_regval
[0] = u_regval
[0] + 8;
10594 offset_8
= (immed_high
<< 4) | immed_low
;
10595 /* Calculate target store address. */
10596 if (14 == arm_insn_r
->opcode
)
10598 tgt_mem_addr
= u_regval
[0] + offset_8
;
10602 tgt_mem_addr
= u_regval
[0] - offset_8
;
10604 if (ARM_RECORD_STRH
== str_type
)
10606 record_buf_mem
[0] = 2;
10607 record_buf_mem
[1] = tgt_mem_addr
;
10608 arm_insn_r
->mem_rec_count
= 1;
10610 else if (ARM_RECORD_STRD
== str_type
)
10612 record_buf_mem
[0] = 4;
10613 record_buf_mem
[1] = tgt_mem_addr
;
10614 record_buf_mem
[2] = 4;
10615 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10616 arm_insn_r
->mem_rec_count
= 2;
10619 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10621 /* 2) Store, register offset. */
10623 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10625 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10626 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10627 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10628 if (15 == reg_src2
)
10630 /* If R15 was used as Rn, hence current PC+8. */
10631 u_regval
[0] = u_regval
[0] + 8;
10633 /* Calculate target store address, Rn +/- Rm, register offset. */
10634 if (12 == arm_insn_r
->opcode
)
10636 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10640 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10642 if (ARM_RECORD_STRH
== str_type
)
10644 record_buf_mem
[0] = 2;
10645 record_buf_mem
[1] = tgt_mem_addr
;
10646 arm_insn_r
->mem_rec_count
= 1;
10648 else if (ARM_RECORD_STRD
== str_type
)
10650 record_buf_mem
[0] = 4;
10651 record_buf_mem
[1] = tgt_mem_addr
;
10652 record_buf_mem
[2] = 4;
10653 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10654 arm_insn_r
->mem_rec_count
= 2;
10657 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10658 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10660 /* 3) Store, immediate pre-indexed. */
10661 /* 5) Store, immediate post-indexed. */
10662 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10663 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10664 offset_8
= (immed_high
<< 4) | immed_low
;
10665 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10666 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10667 /* Calculate target store address, Rn +/- Rm, register offset. */
10668 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10670 tgt_mem_addr
= u_regval
[0] + offset_8
;
10674 tgt_mem_addr
= u_regval
[0] - offset_8
;
10676 if (ARM_RECORD_STRH
== str_type
)
10678 record_buf_mem
[0] = 2;
10679 record_buf_mem
[1] = tgt_mem_addr
;
10680 arm_insn_r
->mem_rec_count
= 1;
10682 else if (ARM_RECORD_STRD
== str_type
)
10684 record_buf_mem
[0] = 4;
10685 record_buf_mem
[1] = tgt_mem_addr
;
10686 record_buf_mem
[2] = 4;
10687 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10688 arm_insn_r
->mem_rec_count
= 2;
10690 /* Record Rn also as it changes. */
10691 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10692 arm_insn_r
->reg_rec_count
= 1;
10694 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10695 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10697 /* 4) Store, register pre-indexed. */
10698 /* 6) Store, register post -indexed. */
10699 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10700 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10701 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10702 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10703 /* Calculate target store address, Rn +/- Rm, register offset. */
10704 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10706 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10710 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10712 if (ARM_RECORD_STRH
== str_type
)
10714 record_buf_mem
[0] = 2;
10715 record_buf_mem
[1] = tgt_mem_addr
;
10716 arm_insn_r
->mem_rec_count
= 1;
10718 else if (ARM_RECORD_STRD
== str_type
)
10720 record_buf_mem
[0] = 4;
10721 record_buf_mem
[1] = tgt_mem_addr
;
10722 record_buf_mem
[2] = 4;
10723 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10724 arm_insn_r
->mem_rec_count
= 2;
10726 /* Record Rn also as it changes. */
10727 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10728 arm_insn_r
->reg_rec_count
= 1;
10733 /* Handling ARM extension space insns. */
10736 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10738 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10739 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10740 uint32_t record_buf
[8], record_buf_mem
[8];
10741 uint32_t reg_src1
= 0;
10742 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10743 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10744 ULONGEST u_regval
= 0;
10746 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10747 /* Handle unconditional insn extension space. */
10749 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10750 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10751 if (arm_insn_r
->cond
)
10753 /* PLD has no affect on architectural state, it just affects
10755 if (5 == ((opcode1
& 0xE0) >> 5))
10758 record_buf
[0] = ARM_PS_REGNUM
;
10759 record_buf
[1] = ARM_LR_REGNUM
;
10760 arm_insn_r
->reg_rec_count
= 2;
10762 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10766 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10767 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10770 /* Undefined instruction on ARM V5; need to handle if later
10771 versions define it. */
10774 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10775 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10776 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10778 /* Handle arithmetic insn extension space. */
10779 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10780 && !INSN_RECORDED(arm_insn_r
))
10782 /* Handle MLA(S) and MUL(S). */
10783 if (0 <= insn_op1
&& 3 >= insn_op1
)
10785 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10786 record_buf
[1] = ARM_PS_REGNUM
;
10787 arm_insn_r
->reg_rec_count
= 2;
10789 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10791 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10792 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10793 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10794 record_buf
[2] = ARM_PS_REGNUM
;
10795 arm_insn_r
->reg_rec_count
= 3;
10799 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10800 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10801 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10803 /* Handle control insn extension space. */
10805 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10806 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10808 if (!bit (arm_insn_r
->arm_insn
,25))
10810 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10812 if ((0 == insn_op1
) || (2 == insn_op1
))
10815 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10816 arm_insn_r
->reg_rec_count
= 1;
10818 else if (1 == insn_op1
)
10820 /* CSPR is going to be changed. */
10821 record_buf
[0] = ARM_PS_REGNUM
;
10822 arm_insn_r
->reg_rec_count
= 1;
10824 else if (3 == insn_op1
)
10826 /* SPSR is going to be changed. */
10827 /* We need to get SPSR value, which is yet to be done. */
10828 printf_unfiltered (_("Process record does not support "
10829 "instruction 0x%0x at address %s.\n"),
10830 arm_insn_r
->arm_insn
,
10831 paddress (arm_insn_r
->gdbarch
,
10832 arm_insn_r
->this_addr
));
10836 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10841 record_buf
[0] = ARM_PS_REGNUM
;
10842 arm_insn_r
->reg_rec_count
= 1;
10844 else if (3 == insn_op1
)
10847 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10848 arm_insn_r
->reg_rec_count
= 1;
10851 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10854 record_buf
[0] = ARM_PS_REGNUM
;
10855 record_buf
[1] = ARM_LR_REGNUM
;
10856 arm_insn_r
->reg_rec_count
= 2;
10858 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10860 /* QADD, QSUB, QDADD, QDSUB */
10861 record_buf
[0] = ARM_PS_REGNUM
;
10862 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10863 arm_insn_r
->reg_rec_count
= 2;
10865 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10868 record_buf
[0] = ARM_PS_REGNUM
;
10869 record_buf
[1] = ARM_LR_REGNUM
;
10870 arm_insn_r
->reg_rec_count
= 2;
10872 /* Save SPSR also;how? */
10873 printf_unfiltered (_("Process record does not support "
10874 "instruction 0x%0x at address %s.\n"),
10875 arm_insn_r
->arm_insn
,
10876 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
10879 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10880 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10881 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10882 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10885 if (0 == insn_op1
|| 1 == insn_op1
)
10887 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10888 /* We dont do optimization for SMULW<y> where we
10890 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10891 record_buf
[1] = ARM_PS_REGNUM
;
10892 arm_insn_r
->reg_rec_count
= 2;
10894 else if (2 == insn_op1
)
10897 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10898 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10899 arm_insn_r
->reg_rec_count
= 2;
10901 else if (3 == insn_op1
)
10904 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10905 arm_insn_r
->reg_rec_count
= 1;
10911 /* MSR : immediate form. */
10914 /* CSPR is going to be changed. */
10915 record_buf
[0] = ARM_PS_REGNUM
;
10916 arm_insn_r
->reg_rec_count
= 1;
10918 else if (3 == insn_op1
)
10920 /* SPSR is going to be changed. */
10921 /* we need to get SPSR value, which is yet to be done */
10922 printf_unfiltered (_("Process record does not support "
10923 "instruction 0x%0x at address %s.\n"),
10924 arm_insn_r
->arm_insn
,
10925 paddress (arm_insn_r
->gdbarch
,
10926 arm_insn_r
->this_addr
));
10932 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10933 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10934 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10936 /* Handle load/store insn extension space. */
10938 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10939 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10940 && !INSN_RECORDED(arm_insn_r
))
10945 /* These insn, changes register and memory as well. */
10946 /* SWP or SWPB insn. */
10947 /* Get memory address given by Rn. */
10948 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10949 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10950 /* SWP insn ?, swaps word. */
10951 if (8 == arm_insn_r
->opcode
)
10953 record_buf_mem
[0] = 4;
10957 /* SWPB insn, swaps only byte. */
10958 record_buf_mem
[0] = 1;
10960 record_buf_mem
[1] = u_regval
;
10961 arm_insn_r
->mem_rec_count
= 1;
10962 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10963 arm_insn_r
->reg_rec_count
= 1;
10965 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10968 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10971 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10974 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10975 record_buf
[1] = record_buf
[0] + 1;
10976 arm_insn_r
->reg_rec_count
= 2;
10978 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10981 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10984 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10986 /* LDRH, LDRSB, LDRSH. */
10987 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10988 arm_insn_r
->reg_rec_count
= 1;
10993 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10994 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10995 && !INSN_RECORDED(arm_insn_r
))
10998 /* Handle coprocessor insn extension space. */
11001 /* To be done for ARMv5 and later; as of now we return -1. */
11003 printf_unfiltered (_("Process record does not support instruction x%0x "
11004 "at address %s.\n"),arm_insn_r
->arm_insn
,
11005 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11008 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11009 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11014 /* Handling opcode 000 insns. */
11017 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11019 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11020 uint32_t record_buf
[8], record_buf_mem
[8];
11021 ULONGEST u_regval
[2] = {0};
11023 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11024 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11025 uint32_t opcode1
= 0;
11027 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11028 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11029 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11031 /* Data processing insn /multiply insn. */
11032 if (9 == arm_insn_r
->decode
11033 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11034 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11036 /* Handle multiply instructions. */
11037 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11038 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11040 /* Handle MLA and MUL. */
11041 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11042 record_buf
[1] = ARM_PS_REGNUM
;
11043 arm_insn_r
->reg_rec_count
= 2;
11045 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11047 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11048 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11049 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11050 record_buf
[2] = ARM_PS_REGNUM
;
11051 arm_insn_r
->reg_rec_count
= 3;
11054 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11055 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11057 /* Handle misc load insns, as 20th bit (L = 1). */
11058 /* LDR insn has a capability to do branching, if
11059 MOV LR, PC is precceded by LDR insn having Rn as R15
11060 in that case, it emulates branch and link insn, and hence we
11061 need to save CSPR and PC as well. I am not sure this is right
11062 place; as opcode = 010 LDR insn make this happen, if R15 was
11064 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11065 if (15 != reg_dest
)
11067 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11068 arm_insn_r
->reg_rec_count
= 1;
11072 record_buf
[0] = reg_dest
;
11073 record_buf
[1] = ARM_PS_REGNUM
;
11074 arm_insn_r
->reg_rec_count
= 2;
11077 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11078 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11079 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11080 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11082 /* Handle MSR insn. */
11083 if (9 == arm_insn_r
->opcode
)
11085 /* CSPR is going to be changed. */
11086 record_buf
[0] = ARM_PS_REGNUM
;
11087 arm_insn_r
->reg_rec_count
= 1;
11091 /* SPSR is going to be changed. */
11092 /* How to read SPSR value? */
11093 printf_unfiltered (_("Process record does not support instruction "
11094 "0x%0x at address %s.\n"),
11095 arm_insn_r
->arm_insn
,
11096 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11100 else if (9 == arm_insn_r
->decode
11101 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11102 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11104 /* Handling SWP, SWPB. */
11105 /* These insn, changes register and memory as well. */
11106 /* SWP or SWPB insn. */
11108 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11109 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11110 /* SWP insn ?, swaps word. */
11111 if (8 == arm_insn_r
->opcode
)
11113 record_buf_mem
[0] = 4;
11117 /* SWPB insn, swaps only byte. */
11118 record_buf_mem
[0] = 1;
11120 record_buf_mem
[1] = u_regval
[0];
11121 arm_insn_r
->mem_rec_count
= 1;
11122 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11123 arm_insn_r
->reg_rec_count
= 1;
11125 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11126 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11128 /* Handle BLX, branch and link/exchange. */
11129 if (9 == arm_insn_r
->opcode
)
11131 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11132 and R14 stores the return address. */
11133 record_buf
[0] = ARM_PS_REGNUM
;
11134 record_buf
[1] = ARM_LR_REGNUM
;
11135 arm_insn_r
->reg_rec_count
= 2;
11138 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11140 /* Handle enhanced software breakpoint insn, BKPT. */
11141 /* CPSR is changed to be executed in ARM state, disabling normal
11142 interrupts, entering abort mode. */
11143 /* According to high vector configuration PC is set. */
11144 /* user hit breakpoint and type reverse, in
11145 that case, we need to go back with previous CPSR and
11146 Program Counter. */
11147 record_buf
[0] = ARM_PS_REGNUM
;
11148 record_buf
[1] = ARM_LR_REGNUM
;
11149 arm_insn_r
->reg_rec_count
= 2;
11151 /* Save SPSR also; how? */
11152 printf_unfiltered (_("Process record does not support instruction "
11153 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11154 paddress (arm_insn_r
->gdbarch
,
11155 arm_insn_r
->this_addr
));
11158 else if (11 == arm_insn_r
->decode
11159 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11161 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11163 /* Handle str(x) insn */
11164 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11167 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11168 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11170 /* Handle BX, branch and link/exchange. */
11171 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11172 record_buf
[0] = ARM_PS_REGNUM
;
11173 arm_insn_r
->reg_rec_count
= 1;
11175 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11176 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11177 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11179 /* Count leading zeros: CLZ. */
11180 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11181 arm_insn_r
->reg_rec_count
= 1;
11183 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11184 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11185 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11186 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11189 /* Handle MRS insn. */
11190 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11191 arm_insn_r
->reg_rec_count
= 1;
11193 else if (arm_insn_r
->opcode
<= 15)
11195 /* Normal data processing insns. */
11196 /* Out of 11 shifter operands mode, all the insn modifies destination
11197 register, which is specified by 13-16 decode. */
11198 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11199 record_buf
[1] = ARM_PS_REGNUM
;
11200 arm_insn_r
->reg_rec_count
= 2;
11207 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11208 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11212 /* Handling opcode 001 insns. */
11215 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11217 uint32_t record_buf
[8], record_buf_mem
[8];
11219 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11220 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11222 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11223 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11224 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11227 /* Handle MSR insn. */
11228 if (9 == arm_insn_r
->opcode
)
11230 /* CSPR is going to be changed. */
11231 record_buf
[0] = ARM_PS_REGNUM
;
11232 arm_insn_r
->reg_rec_count
= 1;
11236 /* SPSR is going to be changed. */
11239 else if (arm_insn_r
->opcode
<= 15)
11241 /* Normal data processing insns. */
11242 /* Out of 11 shifter operands mode, all the insn modifies destination
11243 register, which is specified by 13-16 decode. */
11244 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11245 record_buf
[1] = ARM_PS_REGNUM
;
11246 arm_insn_r
->reg_rec_count
= 2;
11253 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11254 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11258 /* Handling opcode 010 insns. */
11261 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11263 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11265 uint32_t reg_src1
= 0 , reg_dest
= 0;
11266 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11267 uint32_t record_buf
[8], record_buf_mem
[8];
11269 ULONGEST u_regval
= 0;
11271 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11272 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11274 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11276 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11277 /* LDR insn has a capability to do branching, if
11278 MOV LR, PC is precedded by LDR insn having Rn as R15
11279 in that case, it emulates branch and link insn, and hence we
11280 need to save CSPR and PC as well. */
11281 if (ARM_PC_REGNUM
!= reg_dest
)
11283 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11284 arm_insn_r
->reg_rec_count
= 1;
11288 record_buf
[0] = reg_dest
;
11289 record_buf
[1] = ARM_PS_REGNUM
;
11290 arm_insn_r
->reg_rec_count
= 2;
11295 /* Store, immediate offset, immediate pre-indexed,
11296 immediate post-indexed. */
11297 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11298 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11299 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11301 if (bit (arm_insn_r
->arm_insn
, 23))
11303 tgt_mem_addr
= u_regval
+ offset_12
;
11307 tgt_mem_addr
= u_regval
- offset_12
;
11310 switch (arm_insn_r
->opcode
)
11324 record_buf_mem
[0] = 4;
11339 record_buf_mem
[0] = 1;
11343 gdb_assert_not_reached ("no decoding pattern found");
11346 record_buf_mem
[1] = tgt_mem_addr
;
11347 arm_insn_r
->mem_rec_count
= 1;
11349 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11350 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11351 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11352 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11353 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11354 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11357 /* We are handling pre-indexed mode; post-indexed mode;
11358 where Rn is going to be changed. */
11359 record_buf
[0] = reg_src1
;
11360 arm_insn_r
->reg_rec_count
= 1;
11364 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11365 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11369 /* Handling opcode 011 insns. */
11372 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11374 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11376 uint32_t shift_imm
= 0;
11377 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11378 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11379 uint32_t record_buf
[8], record_buf_mem
[8];
11382 ULONGEST u_regval
[2];
11384 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11385 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11387 /* Handle enhanced store insns and LDRD DSP insn,
11388 order begins according to addressing modes for store insns
11392 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11394 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11395 /* LDR insn has a capability to do branching, if
11396 MOV LR, PC is precedded by LDR insn having Rn as R15
11397 in that case, it emulates branch and link insn, and hence we
11398 need to save CSPR and PC as well. */
11399 if (15 != reg_dest
)
11401 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11402 arm_insn_r
->reg_rec_count
= 1;
11406 record_buf
[0] = reg_dest
;
11407 record_buf
[1] = ARM_PS_REGNUM
;
11408 arm_insn_r
->reg_rec_count
= 2;
11413 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11415 /* Store insn, register offset and register pre-indexed,
11416 register post-indexed. */
11418 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11420 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11421 regcache_raw_read_unsigned (reg_cache
, reg_src1
11423 regcache_raw_read_unsigned (reg_cache
, reg_src2
11425 if (15 == reg_src2
)
11427 /* If R15 was used as Rn, hence current PC+8. */
11428 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11429 u_regval
[0] = u_regval
[0] + 8;
11431 /* Calculate target store address, Rn +/- Rm, register offset. */
11433 if (bit (arm_insn_r
->arm_insn
, 23))
11435 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11439 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11442 switch (arm_insn_r
->opcode
)
11456 record_buf_mem
[0] = 4;
11471 record_buf_mem
[0] = 1;
11475 gdb_assert_not_reached ("no decoding pattern found");
11478 record_buf_mem
[1] = tgt_mem_addr
;
11479 arm_insn_r
->mem_rec_count
= 1;
11481 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11482 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11483 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11484 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11485 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11486 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11489 /* Rn is going to be changed in pre-indexed mode and
11490 post-indexed mode as well. */
11491 record_buf
[0] = reg_src2
;
11492 arm_insn_r
->reg_rec_count
= 1;
11497 /* Store insn, scaled register offset; scaled pre-indexed. */
11498 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11500 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11502 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11503 /* Get shift_imm. */
11504 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11505 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11506 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11507 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11508 /* Offset_12 used as shift. */
11512 /* Offset_12 used as index. */
11513 offset_12
= u_regval
[0] << shift_imm
;
11517 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11523 if (bit (u_regval
[0], 31))
11525 offset_12
= 0xFFFFFFFF;
11534 /* This is arithmetic shift. */
11535 offset_12
= s_word
>> shift_imm
;
11542 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11544 /* Get C flag value and shift it by 31. */
11545 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11546 | (u_regval
[0]) >> 1);
11550 offset_12
= (u_regval
[0] >> shift_imm
) \
11552 (sizeof(uint32_t) - shift_imm
));
11557 gdb_assert_not_reached ("no decoding pattern found");
11561 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11563 if (bit (arm_insn_r
->arm_insn
, 23))
11565 tgt_mem_addr
= u_regval
[1] + offset_12
;
11569 tgt_mem_addr
= u_regval
[1] - offset_12
;
11572 switch (arm_insn_r
->opcode
)
11586 record_buf_mem
[0] = 4;
11601 record_buf_mem
[0] = 1;
11605 gdb_assert_not_reached ("no decoding pattern found");
11608 record_buf_mem
[1] = tgt_mem_addr
;
11609 arm_insn_r
->mem_rec_count
= 1;
11611 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11612 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11613 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11614 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11615 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11616 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11619 /* Rn is going to be changed in register scaled pre-indexed
11620 mode,and scaled post indexed mode. */
11621 record_buf
[0] = reg_src2
;
11622 arm_insn_r
->reg_rec_count
= 1;
11627 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11628 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11632 /* Handling opcode 100 insns. */
11635 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11637 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11639 uint32_t register_list
[16] = {0}, register_count
= 0, register_bits
= 0;
11640 uint32_t reg_src1
= 0, addr_mode
= 0, no_of_regs
= 0;
11641 uint32_t start_address
= 0, index
= 0;
11642 uint32_t record_buf
[24], record_buf_mem
[48];
11644 ULONGEST u_regval
[2] = {0};
11646 /* This mode is exclusively for load and store multiple. */
11647 /* Handle incremenrt after/before and decrment after.before mode;
11648 Rn is changing depending on W bit, but as of now we store Rn too
11649 without optimization. */
11651 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11653 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11655 if (bit (arm_insn_r
->arm_insn
, 20) && !bit (arm_insn_r
->arm_insn
, 22))
11657 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11662 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 14);
11666 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11667 while (register_bits
)
11669 if (register_bits
& 0x00000001)
11670 register_list
[register_count
++] = 1;
11671 register_bits
= register_bits
>> 1;
11674 /* Extra space for Base Register and CPSR; wihtout optimization. */
11675 record_buf
[register_count
] = reg_src1
;
11676 record_buf
[register_count
+ 1] = ARM_PS_REGNUM
;
11677 arm_insn_r
->reg_rec_count
= register_count
+ 2;
11679 for (register_count
= 0; register_count
< no_of_regs
; register_count
++)
11681 if (register_list
[register_count
])
11683 /* Register_count gives total no of registers
11684 and dually working as reg number. */
11685 record_buf
[index
] = register_count
;
11693 /* It handles both STM(1) and STM(2). */
11694 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11696 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11698 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11699 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11700 while (register_bits
)
11702 if (register_bits
& 0x00000001)
11704 register_bits
= register_bits
>> 1;
11709 /* Decrement after. */
11711 start_address
= (u_regval
[0]) - (register_count
* 4) + 4;
11712 arm_insn_r
->mem_rec_count
= register_count
;
11713 while (register_count
)
11715 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11716 record_buf_mem
[(register_count
* 2) - 2] = 4;
11717 start_address
= start_address
+ 4;
11722 /* Increment after. */
11724 start_address
= u_regval
[0];
11725 arm_insn_r
->mem_rec_count
= register_count
;
11726 while (register_count
)
11728 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11729 record_buf_mem
[(register_count
* 2) - 2] = 4;
11730 start_address
= start_address
+ 4;
11735 /* Decrement before. */
11738 start_address
= (u_regval
[0]) - (register_count
* 4);
11739 arm_insn_r
->mem_rec_count
= register_count
;
11740 while (register_count
)
11742 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11743 record_buf_mem
[(register_count
* 2) - 2] = 4;
11744 start_address
= start_address
+ 4;
11749 /* Increment before. */
11751 start_address
= u_regval
[0] + 4;
11752 arm_insn_r
->mem_rec_count
= register_count
;
11753 while (register_count
)
11755 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11756 record_buf_mem
[(register_count
* 2) - 2] = 4;
11757 start_address
= start_address
+ 4;
11763 gdb_assert_not_reached ("no decoding pattern found");
11767 /* Base register also changes; based on condition and W bit. */
11768 /* We save it anyway without optimization. */
11769 record_buf
[0] = reg_src1
;
11770 arm_insn_r
->reg_rec_count
= 1;
11773 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11774 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11778 /* Handling opcode 101 insns. */
11781 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11783 uint32_t record_buf
[8];
11785 /* Handle B, BL, BLX(1) insns. */
11786 /* B simply branches so we do nothing here. */
11787 /* Note: BLX(1) doesnt fall here but instead it falls into
11788 extension space. */
11789 if (bit (arm_insn_r
->arm_insn
, 24))
11791 record_buf
[0] = ARM_LR_REGNUM
;
11792 arm_insn_r
->reg_rec_count
= 1;
11795 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11800 /* Handling opcode 110 insns. */
11803 arm_record_coproc (insn_decode_record
*arm_insn_r
)
11805 printf_unfiltered (_("Process record does not support instruction "
11806 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11807 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11812 /* Handling opcode 111 insns. */
11815 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11817 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11818 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11819 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
11821 /* Handle SWI insn; system call would be handled over here. */
11823 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11824 if (15 == arm_insn_r
->opcode
)
11826 /* Handle arm syscall insn. */
11827 if (tdep
->arm_swi_record
!= NULL
)
11829 ret
= tdep
->arm_swi_record(reg_cache
);
11833 printf_unfiltered (_("no syscall record support\n"));
11838 printf_unfiltered (_("Process record does not support instruction "
11839 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11840 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11844 /* Handling opcode 000 insns. */
11847 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11849 uint32_t record_buf
[8];
11850 uint32_t reg_src1
= 0;
11852 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11854 record_buf
[0] = ARM_PS_REGNUM
;
11855 record_buf
[1] = reg_src1
;
11856 thumb_insn_r
->reg_rec_count
= 2;
11858 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11864 /* Handling opcode 001 insns. */
11867 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11869 uint32_t record_buf
[8];
11870 uint32_t reg_src1
= 0;
11872 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11874 record_buf
[0] = ARM_PS_REGNUM
;
11875 record_buf
[1] = reg_src1
;
11876 thumb_insn_r
->reg_rec_count
= 2;
11878 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11883 /* Handling opcode 010 insns. */
11886 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11888 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11889 uint32_t record_buf
[8], record_buf_mem
[8];
11891 uint32_t reg_src1
= 0, reg_src2
= 0;
11892 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11894 ULONGEST u_regval
[2] = {0};
11896 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11898 if (bit (thumb_insn_r
->arm_insn
, 12))
11900 /* Handle load/store register offset. */
11901 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11902 if (opcode2
>= 12 && opcode2
<= 15)
11904 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11905 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11906 record_buf
[0] = reg_src1
;
11907 thumb_insn_r
->reg_rec_count
= 1;
11909 else if (opcode2
>= 8 && opcode2
<= 10)
11911 /* STR(2), STRB(2), STRH(2) . */
11912 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11913 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11914 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11915 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11917 record_buf_mem
[0] = 4; /* STR (2). */
11918 else if (10 == opcode2
)
11919 record_buf_mem
[0] = 1; /* STRB (2). */
11920 else if (9 == opcode2
)
11921 record_buf_mem
[0] = 2; /* STRH (2). */
11922 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11923 thumb_insn_r
->mem_rec_count
= 1;
11926 else if (bit (thumb_insn_r
->arm_insn
, 11))
11928 /* Handle load from literal pool. */
11930 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11931 record_buf
[0] = reg_src1
;
11932 thumb_insn_r
->reg_rec_count
= 1;
11936 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11937 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11938 if ((3 == opcode2
) && (!opcode3
))
11940 /* Branch with exchange. */
11941 record_buf
[0] = ARM_PS_REGNUM
;
11942 thumb_insn_r
->reg_rec_count
= 1;
11946 /* Format 8; special data processing insns. */
11947 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11948 record_buf
[0] = ARM_PS_REGNUM
;
11949 record_buf
[1] = reg_src1
;
11950 thumb_insn_r
->reg_rec_count
= 2;
11955 /* Format 5; data processing insns. */
11956 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11957 if (bit (thumb_insn_r
->arm_insn
, 7))
11959 reg_src1
= reg_src1
+ 8;
11961 record_buf
[0] = ARM_PS_REGNUM
;
11962 record_buf
[1] = reg_src1
;
11963 thumb_insn_r
->reg_rec_count
= 2;
11966 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11967 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11973 /* Handling opcode 001 insns. */
11976 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11978 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11979 uint32_t record_buf
[8], record_buf_mem
[8];
11981 uint32_t reg_src1
= 0;
11982 uint32_t opcode
= 0, immed_5
= 0;
11984 ULONGEST u_regval
= 0;
11986 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11991 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11992 record_buf
[0] = reg_src1
;
11993 thumb_insn_r
->reg_rec_count
= 1;
11998 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11999 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12000 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12001 record_buf_mem
[0] = 4;
12002 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12003 thumb_insn_r
->mem_rec_count
= 1;
12006 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12007 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12013 /* Handling opcode 100 insns. */
12016 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12018 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12019 uint32_t record_buf
[8], record_buf_mem
[8];
12021 uint32_t reg_src1
= 0;
12022 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12024 ULONGEST u_regval
= 0;
12026 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12031 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12032 record_buf
[0] = reg_src1
;
12033 thumb_insn_r
->reg_rec_count
= 1;
12035 else if (1 == opcode
)
12038 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12039 record_buf
[0] = reg_src1
;
12040 thumb_insn_r
->reg_rec_count
= 1;
12042 else if (2 == opcode
)
12045 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12046 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12047 record_buf_mem
[0] = 4;
12048 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12049 thumb_insn_r
->mem_rec_count
= 1;
12051 else if (0 == opcode
)
12054 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12055 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12056 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12057 record_buf_mem
[0] = 2;
12058 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12059 thumb_insn_r
->mem_rec_count
= 1;
12062 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12063 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12069 /* Handling opcode 101 insns. */
12072 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12074 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12076 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12077 uint32_t register_bits
= 0, register_count
= 0;
12078 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12079 uint32_t record_buf
[24], record_buf_mem
[48];
12082 ULONGEST u_regval
= 0;
12084 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12085 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12086 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12091 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12092 while (register_bits
)
12094 if (register_bits
& 0x00000001)
12095 register_list
[register_count
++] = 1;
12096 register_bits
= register_bits
>> 1;
12098 record_buf
[register_count
] = ARM_PS_REGNUM
;
12099 record_buf
[register_count
+ 1] = ARM_SP_REGNUM
;
12100 thumb_insn_r
->reg_rec_count
= register_count
+ 2;
12101 for (register_count
= 0; register_count
< 8; register_count
++)
12103 if (register_list
[register_count
])
12105 record_buf
[index
] = register_count
;
12110 else if (10 == opcode2
)
12113 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12114 regcache_raw_read_unsigned (reg_cache
, ARM_PC_REGNUM
, &u_regval
);
12115 while (register_bits
)
12117 if (register_bits
& 0x00000001)
12119 register_bits
= register_bits
>> 1;
12121 start_address
= u_regval
- \
12122 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12123 thumb_insn_r
->mem_rec_count
= register_count
;
12124 while (register_count
)
12126 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12127 record_buf_mem
[(register_count
* 2) - 2] = 4;
12128 start_address
= start_address
+ 4;
12131 record_buf
[0] = ARM_SP_REGNUM
;
12132 thumb_insn_r
->reg_rec_count
= 1;
12134 else if (0x1E == opcode1
)
12137 /* Handle enhanced software breakpoint insn, BKPT. */
12138 /* CPSR is changed to be executed in ARM state, disabling normal
12139 interrupts, entering abort mode. */
12140 /* According to high vector configuration PC is set. */
12141 /* User hits breakpoint and type reverse, in that case, we need to go back with
12142 previous CPSR and Program Counter. */
12143 record_buf
[0] = ARM_PS_REGNUM
;
12144 record_buf
[1] = ARM_LR_REGNUM
;
12145 thumb_insn_r
->reg_rec_count
= 2;
12146 /* We need to save SPSR value, which is not yet done. */
12147 printf_unfiltered (_("Process record does not support instruction "
12148 "0x%0x at address %s.\n"),
12149 thumb_insn_r
->arm_insn
,
12150 paddress (thumb_insn_r
->gdbarch
,
12151 thumb_insn_r
->this_addr
));
12154 else if ((0 == opcode
) || (1 == opcode
))
12156 /* ADD(5), ADD(6). */
12157 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12158 record_buf
[0] = reg_src1
;
12159 thumb_insn_r
->reg_rec_count
= 1;
12161 else if (2 == opcode
)
12163 /* ADD(7), SUB(4). */
12164 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12165 record_buf
[0] = ARM_SP_REGNUM
;
12166 thumb_insn_r
->reg_rec_count
= 1;
12169 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12170 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12176 /* Handling opcode 110 insns. */
12179 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12181 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12182 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12184 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12185 uint32_t reg_src1
= 0;
12186 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12187 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12188 uint32_t record_buf
[24], record_buf_mem
[48];
12190 ULONGEST u_regval
= 0;
12192 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12193 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12199 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12201 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12202 while (register_bits
)
12204 if (register_bits
& 0x00000001)
12205 register_list
[register_count
++] = 1;
12206 register_bits
= register_bits
>> 1;
12208 record_buf
[register_count
] = reg_src1
;
12209 thumb_insn_r
->reg_rec_count
= register_count
+ 1;
12210 for (register_count
= 0; register_count
< 8; register_count
++)
12212 if (register_list
[register_count
])
12214 record_buf
[index
] = register_count
;
12219 else if (0 == opcode2
)
12221 /* It handles both STMIA. */
12222 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12224 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12225 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12226 while (register_bits
)
12228 if (register_bits
& 0x00000001)
12230 register_bits
= register_bits
>> 1;
12232 start_address
= u_regval
;
12233 thumb_insn_r
->mem_rec_count
= register_count
;
12234 while (register_count
)
12236 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12237 record_buf_mem
[(register_count
* 2) - 2] = 4;
12238 start_address
= start_address
+ 4;
12242 else if (0x1F == opcode1
)
12244 /* Handle arm syscall insn. */
12245 if (tdep
->arm_swi_record
!= NULL
)
12247 ret
= tdep
->arm_swi_record(reg_cache
);
12251 printf_unfiltered (_("no syscall record support\n"));
12256 /* B (1), conditional branch is automatically taken care in process_record,
12257 as PC is saved there. */
12259 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12260 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12266 /* Handling opcode 111 insns. */
12269 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12271 uint32_t record_buf
[8];
12272 uint32_t bits_h
= 0;
12274 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12276 if (2 == bits_h
|| 3 == bits_h
)
12279 record_buf
[0] = ARM_LR_REGNUM
;
12280 thumb_insn_r
->reg_rec_count
= 1;
12282 else if (1 == bits_h
)
12285 record_buf
[0] = ARM_PS_REGNUM
;
12286 record_buf
[1] = ARM_LR_REGNUM
;
12287 thumb_insn_r
->reg_rec_count
= 2;
12290 /* B(2) is automatically taken care in process_record, as PC is
12293 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12299 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12300 and positive val on fauilure. */
12303 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12305 gdb_byte buf
[insn_size
];
12307 memset (&buf
[0], 0, insn_size
);
12309 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12311 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12313 gdbarch_byte_order (insn_record
->gdbarch
));
12317 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12319 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12323 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12324 uint32_t insn_size
)
12327 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12328 static const sti_arm_hdl_fp_t
const arm_handle_insn
[8] =
12330 arm_record_data_proc_misc_ld_str
, /* 000. */
12331 arm_record_data_proc_imm
, /* 001. */
12332 arm_record_ld_st_imm_offset
, /* 010. */
12333 arm_record_ld_st_reg_offset
, /* 011. */
12334 arm_record_ld_st_multiple
, /* 100. */
12335 arm_record_b_bl
, /* 101. */
12336 arm_record_coproc
, /* 110. */
12337 arm_record_coproc_data_proc
/* 111. */
12340 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12341 static const sti_arm_hdl_fp_t
const thumb_handle_insn
[8] =
12343 thumb_record_shift_add_sub
, /* 000. */
12344 thumb_record_add_sub_cmp_mov
, /* 001. */
12345 thumb_record_ld_st_reg_offset
, /* 010. */
12346 thumb_record_ld_st_imm_offset
, /* 011. */
12347 thumb_record_ld_st_stack
, /* 100. */
12348 thumb_record_misc
, /* 101. */
12349 thumb_record_ldm_stm_swi
, /* 110. */
12350 thumb_record_branch
/* 111. */
12353 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12354 uint32_t insn_id
= 0;
12356 if (extract_arm_insn (arm_record
, insn_size
))
12360 printf_unfiltered (_("Process record: error reading memory at "
12361 "addr %s len = %d.\n"),
12362 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
12366 else if (ARM_RECORD
== record_type
)
12368 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12369 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12370 ret
= arm_record_extension_space (arm_record
);
12371 /* If this insn has fallen into extension space
12372 then we need not decode it anymore. */
12373 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
12375 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12378 else if (THUMB_RECORD
== record_type
)
12380 /* As thumb does not have condition codes, we set negative. */
12381 arm_record
->cond
= -1;
12382 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12383 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12385 else if (THUMB2_RECORD
== record_type
)
12387 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12388 "0x%0x at address %s.\n"),arm_record
->arm_insn
,
12389 paddress (arm_record
->gdbarch
,
12390 arm_record
->this_addr
));
12395 /* Throw assertion. */
12396 gdb_assert_not_reached ("not a valid instruction, could not decode");
12403 /* Cleans up local record registers and memory allocations. */
12406 deallocate_reg_mem (insn_decode_record
*record
)
12408 xfree (record
->arm_regs
);
12409 xfree (record
->arm_mems
);
12413 /* Parse the current instruction and record the values of the registers and
12414 memory that will be changed in current instruction to record_arch_list".
12415 Return -1 if something is wrong. */
12418 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
12419 CORE_ADDR insn_addr
)
12422 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
12423 uint32_t no_of_rec
= 0;
12424 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
12425 ULONGEST t_bit
= 0, insn_id
= 0;
12427 ULONGEST u_regval
= 0;
12429 insn_decode_record arm_record
;
12431 memset (&arm_record
, 0, sizeof (insn_decode_record
));
12432 arm_record
.regcache
= regcache
;
12433 arm_record
.this_addr
= insn_addr
;
12434 arm_record
.gdbarch
= gdbarch
;
12437 if (record_debug
> 1)
12439 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
12441 paddress (gdbarch
, arm_record
.this_addr
));
12444 if (extract_arm_insn (&arm_record
, 2))
12448 printf_unfiltered (_("Process record: error reading memory at "
12449 "addr %s len = %d.\n"),
12450 paddress (arm_record
.gdbarch
,
12451 arm_record
.this_addr
), 2);
12456 /* Check the insn, whether it is thumb or arm one. */
12458 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
12459 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
12462 if (!(u_regval
& t_bit
))
12464 /* We are decoding arm insn. */
12465 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
12469 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
12470 /* is it thumb2 insn? */
12471 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
12473 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
12474 THUMB2_INSN_SIZE_BYTES
);
12478 /* We are decoding thumb insn. */
12479 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
12485 /* Record registers. */
12486 record_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
12487 if (arm_record
.arm_regs
)
12489 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
12491 if (record_arch_list_add_reg (arm_record
.regcache
,
12492 arm_record
.arm_regs
[no_of_rec
]))
12496 /* Record memories. */
12497 if (arm_record
.arm_mems
)
12499 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
12501 if (record_arch_list_add_mem
12502 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
12503 arm_record
.arm_mems
[no_of_rec
].len
))
12508 if (record_arch_list_add_end ())
12513 deallocate_reg_mem (&arm_record
);