1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
41 #include "coff/internal.h"
44 /* Each OS has a different mechanism for accessing the various
45 registers stored in the sigcontext structure.
47 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
48 function pointer) which may be used to determine the addresses
49 of the various saved registers in the sigcontext structure.
51 For the ARM target, there are three parameters to this function.
52 The first is the pc value of the frame under consideration, the
53 second the stack pointer of this frame, and the last is the
54 register number to fetch.
56 If the tm.h file does not define this macro, then it's assumed that
57 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
60 When it comes time to multi-arching this code, see the identically
61 named machinery in ia64-tdep.c for an example of how it could be
62 done. It should not be necessary to modify the code below where
63 this macro is used. */
65 #ifdef SIGCONTEXT_REGISTER_ADDRESS
66 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
67 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
70 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
71 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
74 /* Macros for setting and testing a bit in a minimal symbol that marks
75 it as Thumb function. The MSB of the minimal symbol's "info" field
76 is used for this purpose. This field is already being used to store
77 the symbol size, so the assumption is that the symbol size cannot
80 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
81 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
82 MSYMBOL_SIZE Returns the size of the minimal symbol,
83 i.e. the "info" field with the "special" bit
86 #define MSYMBOL_SET_SPECIAL(msym) \
87 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
90 #define MSYMBOL_IS_SPECIAL(msym) \
91 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
93 #define MSYMBOL_SIZE(msym) \
94 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
96 /* This table matches the indicees assigned to enum arm_abi.
99 static const char * const arm_abi_names
[] =
102 "ARM EABI (version 1)",
103 "ARM EABI (version 2)",
113 /* Number of different reg name sets (options). */
114 static int num_flavor_options
;
116 /* We have more registers than the disassembler as gdb can print the value
117 of special registers as well.
118 The general register names are overwritten by whatever is being used by
119 the disassembler at the moment. We also adjust the case of cpsr and fps. */
121 /* Initial value: Register names used in ARM's ISA documentation. */
122 static char * arm_register_name_strings
[] =
123 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
124 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
125 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
126 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
127 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
128 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
129 "fps", "cpsr" }; /* 24 25 */
130 static char **arm_register_names
= arm_register_name_strings
;
132 /* Valid register name flavors. */
133 static const char **valid_flavors
;
135 /* Disassembly flavor to use. Default to "std" register names. */
136 static const char *disassembly_flavor
;
137 /* Index to that option in the opcodes table. */
138 static int current_option
;
140 /* This is used to keep the bfd arch_info in sync with the disassembly
142 static void set_disassembly_flavor_sfunc(char *, int,
143 struct cmd_list_element
*);
144 static void set_disassembly_flavor (void);
146 static void convert_from_extended (void *ptr
, void *dbl
);
148 /* Define other aspects of the stack frame. We keep the offsets of
149 all saved registers, 'cause we need 'em a lot! We also keep the
150 current size of the stack frame, and the offset of the frame
151 pointer from the stack pointer (for frameless functions, and when
152 we're still in the prologue of a function with a frame). */
154 struct frame_extra_info
161 /* Addresses for calling Thumb functions have the bit 0 set.
162 Here are some macros to test, set, or clear bit 0 of addresses. */
163 #define IS_THUMB_ADDR(addr) ((addr) & 1)
164 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
165 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
168 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
170 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
173 /* Set to true if the 32-bit mode is in use. */
177 /* Flag set by arm_fix_call_dummy that tells whether the target
178 function is a Thumb function. This flag is checked by
179 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
180 its use in valops.c) to pass the function address as an additional
183 static int target_is_thumb
;
185 /* Flag set by arm_fix_call_dummy that tells whether the calling
186 function is a Thumb function. This flag is checked by
187 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
189 static int caller_is_thumb
;
191 /* Determine if the program counter specified in MEMADDR is in a Thumb
195 arm_pc_is_thumb (CORE_ADDR memaddr
)
197 struct minimal_symbol
*sym
;
199 /* If bit 0 of the address is set, assume this is a Thumb address. */
200 if (IS_THUMB_ADDR (memaddr
))
203 /* Thumb functions have a "special" bit set in minimal symbols. */
204 sym
= lookup_minimal_symbol_by_pc (memaddr
);
207 return (MSYMBOL_IS_SPECIAL (sym
));
215 /* Determine if the program counter specified in MEMADDR is in a call
216 dummy being called from a Thumb function. */
219 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
221 CORE_ADDR sp
= read_sp ();
223 /* FIXME: Until we switch for the new call dummy macros, this heuristic
224 is the best we can do. We are trying to determine if the pc is on
225 the stack, which (hopefully) will only happen in a call dummy.
226 We hope the current stack pointer is not so far alway from the dummy
227 frame location (true if we have not pushed large data structures or
228 gone too many levels deep) and that our 1024 is not enough to consider
229 code regions as part of the stack (true for most practical purposes). */
230 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
231 return caller_is_thumb
;
236 /* Remove useless bits from addresses in a running program. */
238 arm_addr_bits_remove (CORE_ADDR val
)
240 if (arm_pc_is_thumb (val
))
241 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
243 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
246 /* When reading symbols, we need to zap the low bit of the address,
247 which may be set to 1 for Thumb functions. */
249 arm_smash_text_address (CORE_ADDR val
)
254 /* Immediately after a function call, return the saved pc. Can't
255 always go through the frames for this because on some machines the
256 new frame is not set up until the new function executes some
260 arm_saved_pc_after_call (struct frame_info
*frame
)
262 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
265 /* Determine whether the function invocation represented by FI has a
266 frame on the stack associated with it. If it does return zero,
267 otherwise return 1. */
270 arm_frameless_function_invocation (struct frame_info
*fi
)
272 CORE_ADDR func_start
, after_prologue
;
275 /* Sometimes we have functions that do a little setup (like saving the
276 vN registers with the stmdb instruction, but DO NOT set up a frame.
277 The symbol table will report this as a prologue. However, it is
278 important not to try to parse these partial frames as frames, or we
279 will get really confused.
281 So I will demand 3 instructions between the start & end of the
282 prologue before I call it a real prologue, i.e. at least
287 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
288 after_prologue
= SKIP_PROLOGUE (func_start
);
290 /* There are some frameless functions whose first two instructions
291 follow the standard APCS form, in which case after_prologue will
292 be func_start + 8. */
294 frameless
= (after_prologue
< func_start
+ 12);
298 /* The address of the arguments in the frame. */
300 arm_frame_args_address (struct frame_info
*fi
)
305 /* The address of the local variables in the frame. */
307 arm_frame_locals_address (struct frame_info
*fi
)
312 /* The number of arguments being passed in the frame. */
314 arm_frame_num_args (struct frame_info
*fi
)
316 /* We have no way of knowing. */
320 /* A typical Thumb prologue looks like this:
324 Sometimes the latter instruction may be replaced by:
332 or, on tpcs, like this:
339 There is always one instruction of three classes:
344 When we have found at least one of each class we are done with the prolog.
345 Note that the "sub sp, #NN" before the push does not count.
349 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
351 CORE_ADDR current_pc
;
353 bit 0 - push { rlist }
354 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
355 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
359 for (current_pc
= pc
;
360 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
363 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
365 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
367 findmask
|= 1; /* push found */
369 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
372 if ((findmask
& 1) == 0) /* before push ? */
375 findmask
|= 4; /* add/sub sp found */
377 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
379 findmask
|= 2; /* setting of r7 found */
381 else if (insn
== 0x466f) /* mov r7, sp */
383 findmask
|= 2; /* setting of r7 found */
385 else if (findmask
== (4+2+1))
387 /* We have found one of each type of prologue instruction */
391 /* Something in the prolog that we don't care about or some
392 instruction from outside the prolog scheduled here for
400 /* Advance the PC across any function entry prologue instructions to
401 reach some "real" code.
403 The APCS (ARM Procedure Call Standard) defines the following
407 [stmfd sp!, {a1,a2,a3,a4}]
408 stmfd sp!, {...,fp,ip,lr,pc}
409 [stfe f7, [sp, #-12]!]
410 [stfe f6, [sp, #-12]!]
411 [stfe f5, [sp, #-12]!]
412 [stfe f4, [sp, #-12]!]
413 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
416 arm_skip_prologue (CORE_ADDR pc
)
420 CORE_ADDR func_addr
, func_end
;
422 struct symtab_and_line sal
;
424 /* See what the symbol table says. */
426 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
430 /* Found a function. */
431 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
432 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
434 /* Don't use this trick for assembly source files. */
435 sal
= find_pc_line (func_addr
, 0);
436 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
441 /* Check if this is Thumb code. */
442 if (arm_pc_is_thumb (pc
))
443 return thumb_skip_prologue (pc
, func_end
);
445 /* Can't find the prologue end in the symbol table, try it the hard way
446 by disassembling the instructions. */
448 inst
= read_memory_integer (skip_pc
, 4);
449 /* "mov ip, sp" is no longer a required part of the prologue. */
450 if (inst
== 0xe1a0c00d) /* mov ip, sp */
453 inst
= read_memory_integer (skip_pc
, 4);
456 /* Some prologues begin with "str lr, [sp, #-4]!". */
457 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
460 inst
= read_memory_integer (skip_pc
, 4);
463 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
466 inst
= read_memory_integer (skip_pc
, 4);
469 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
472 inst
= read_memory_integer (skip_pc
, 4);
475 /* Any insns after this point may float into the code, if it makes
476 for better instruction scheduling, so we skip them only if we
477 find them, but still consider the function to be frame-ful. */
479 /* We may have either one sfmfd instruction here, or several stfe
480 insns, depending on the version of floating point code we
482 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
485 inst
= read_memory_integer (skip_pc
, 4);
489 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
492 inst
= read_memory_integer (skip_pc
, 4);
496 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
499 inst
= read_memory_integer (skip_pc
, 4);
502 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
505 inst
= read_memory_integer (skip_pc
, 4);
508 while ((inst
& 0xffffcfc0) == 0xe50b0000) /* str r(0123), [r11, #-nn] */
511 inst
= read_memory_integer (skip_pc
, 4);
518 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
519 This function decodes a Thumb function prologue to determine:
520 1) the size of the stack frame
521 2) which registers are saved on it
522 3) the offsets of saved regs
523 4) the offset from the stack pointer to the frame pointer
524 This information is stored in the "extra" fields of the frame_info.
526 A typical Thumb function prologue would create this stack frame
527 (offsets relative to FP)
528 old SP -> 24 stack parameters
531 R7 -> 0 local variables (16 bytes)
532 SP -> -12 additional stack space (12 bytes)
533 The frame size would thus be 36 bytes, and the frame offset would be
534 12 bytes. The frame register is R7.
536 The comments for thumb_skip_prolog() describe the algorithm we use
537 to detect the end of the prolog. */
541 thumb_scan_prologue (struct frame_info
*fi
)
543 CORE_ADDR prologue_start
;
544 CORE_ADDR prologue_end
;
545 CORE_ADDR current_pc
;
546 /* Which register has been copied to register n? */
549 bit 0 - push { rlist }
550 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
551 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
556 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
558 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
560 if (sal
.line
== 0) /* no line info, use current PC */
561 prologue_end
= fi
->pc
;
562 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
563 prologue_end
= sal
.end
; /* (probably means no prologue) */
566 /* We're in the boondocks: allow for
567 16 pushes, an add, and "mv fp,sp". */
568 prologue_end
= prologue_start
+ 40;
570 prologue_end
= min (prologue_end
, fi
->pc
);
572 /* Initialize the saved register map. When register H is copied to
573 register L, we will put H in saved_reg[L]. */
574 for (i
= 0; i
< 16; i
++)
577 /* Search the prologue looking for instructions that set up the
578 frame pointer, adjust the stack pointer, and save registers.
579 Do this until all basic prolog instructions are found. */
581 fi
->extra_info
->framesize
= 0;
582 for (current_pc
= prologue_start
;
583 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
590 insn
= read_memory_unsigned_integer (current_pc
, 2);
592 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
595 findmask
|= 1; /* push found */
596 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
597 whether to save LR (R14). */
598 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
600 /* Calculate offsets of saved R0-R7 and LR. */
601 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
602 if (mask
& (1 << regno
))
604 fi
->extra_info
->framesize
+= 4;
605 fi
->saved_regs
[saved_reg
[regno
]] =
606 -(fi
->extra_info
->framesize
);
607 /* Reset saved register map. */
608 saved_reg
[regno
] = regno
;
611 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
614 if ((findmask
& 1) == 0) /* before push? */
617 findmask
|= 4; /* add/sub sp found */
619 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
620 if (insn
& 0x80) /* is it signed? (==subtracting) */
622 fi
->extra_info
->frameoffset
+= offset
;
625 fi
->extra_info
->framesize
-= offset
;
627 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
629 findmask
|= 2; /* setting of r7 found */
630 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
631 /* get scaled offset */
632 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
634 else if (insn
== 0x466f) /* mov r7, sp */
636 findmask
|= 2; /* setting of r7 found */
637 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
638 fi
->extra_info
->frameoffset
= 0;
639 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
641 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
643 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
644 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
645 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
648 /* Something in the prolog that we don't care about or some
649 instruction from outside the prolog scheduled here for
655 /* Check if prologue for this frame's PC has already been scanned. If
656 it has, copy the relevant information about that prologue and
657 return non-zero. Otherwise do not copy anything and return zero.
659 The information saved in the cache includes:
660 * the frame register number;
661 * the size of the stack frame;
662 * the offsets of saved regs (relative to the old SP); and
663 * the offset from the stack pointer to the frame pointer
665 The cache contains only one entry, since this is adequate for the
666 typical sequence of prologue scan requests we get. When performing
667 a backtrace, GDB will usually ask to scan the same function twice
668 in a row (once to get the frame chain, and once to fill in the
669 extra frame information). */
671 static struct frame_info prologue_cache
;
674 check_prologue_cache (struct frame_info
*fi
)
678 if (fi
->pc
== prologue_cache
.pc
)
680 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
681 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
682 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
683 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
684 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
692 /* Copy the prologue information from fi to the prologue cache. */
695 save_prologue_cache (struct frame_info
*fi
)
699 prologue_cache
.pc
= fi
->pc
;
700 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
701 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
702 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
704 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
705 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
709 /* This function decodes an ARM function prologue to determine:
710 1) the size of the stack frame
711 2) which registers are saved on it
712 3) the offsets of saved regs
713 4) the offset from the stack pointer to the frame pointer
714 This information is stored in the "extra" fields of the frame_info.
716 There are two basic forms for the ARM prologue. The fixed argument
717 function call will look like:
720 stmfd sp!, {fp, ip, lr, pc}
724 Which would create this stack frame (offsets relative to FP):
725 IP -> 4 (caller's stack)
726 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
727 -4 LR (return address in caller)
728 -8 IP (copy of caller's SP)
730 SP -> -28 Local variables
732 The frame size would thus be 32 bytes, and the frame offset would be
733 28 bytes. The stmfd call can also save any of the vN registers it
734 plans to use, which increases the frame size accordingly.
736 Note: The stored PC is 8 off of the STMFD instruction that stored it
737 because the ARM Store instructions always store PC + 8 when you read
740 A variable argument function call will look like:
743 stmfd sp!, {a1, a2, a3, a4}
744 stmfd sp!, {fp, ip, lr, pc}
747 Which would create this stack frame (offsets relative to FP):
748 IP -> 20 (caller's stack)
753 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
754 -4 LR (return address in caller)
755 -8 IP (copy of caller's SP)
757 SP -> -28 Local variables
759 The frame size would thus be 48 bytes, and the frame offset would be
762 There is another potential complication, which is that the optimizer
763 will try to separate the store of fp in the "stmfd" instruction from
764 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
765 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
767 Also, note, the original version of the ARM toolchain claimed that there
770 instruction at the end of the prologue. I have never seen GCC produce
771 this, and the ARM docs don't mention it. We still test for it below in
777 arm_scan_prologue (struct frame_info
*fi
)
779 int regno
, sp_offset
, fp_offset
;
780 LONGEST return_value
;
781 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
783 /* Check if this function is already in the cache of frame information. */
784 if (check_prologue_cache (fi
))
787 /* Assume there is no frame until proven otherwise. */
788 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
789 fi
->extra_info
->framesize
= 0;
790 fi
->extra_info
->frameoffset
= 0;
792 /* Check for Thumb prologue. */
793 if (arm_pc_is_thumb (fi
->pc
))
795 thumb_scan_prologue (fi
);
796 save_prologue_cache (fi
);
800 /* Find the function prologue. If we can't find the function in
801 the symbol table, peek in the stack frame to find the PC. */
802 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
804 /* One way to find the end of the prologue (which works well
805 for unoptimized code) is to do the following:
807 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
810 prologue_end = fi->pc;
811 else if (sal.end < prologue_end)
812 prologue_end = sal.end;
814 This mechanism is very accurate so long as the optimizer
815 doesn't move any instructions from the function body into the
816 prologue. If this happens, sal.end will be the last
817 instruction in the first hunk of prologue code just before
818 the first instruction that the scheduler has moved from
819 the body to the prologue.
821 In order to make sure that we scan all of the prologue
822 instructions, we use a slightly less accurate mechanism which
823 may scan more than necessary. To help compensate for this
824 lack of accuracy, the prologue scanning loop below contains
825 several clauses which'll cause the loop to terminate early if
826 an implausible prologue instruction is encountered.
832 is a suitable endpoint since it accounts for the largest
833 possible prologue plus up to five instructions inserted by
836 if (prologue_end
> prologue_start
+ 64)
838 prologue_end
= prologue_start
+ 64; /* See above. */
843 /* Get address of the stmfd in the prologue of the callee;
844 the saved PC is the address of the stmfd + 8. */
845 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
849 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
850 prologue_end
= prologue_start
+ 64; /* See above. */
854 /* Now search the prologue looking for instructions that set up the
855 frame pointer, adjust the stack pointer, and save registers.
857 Be careful, however, and if it doesn't look like a prologue,
858 don't try to scan it. If, for instance, a frameless function
859 begins with stmfd sp!, then we will tell ourselves there is
860 a frame, which will confuse stack traceback, as well ad"finish"
861 and other operations that rely on a knowledge of the stack
864 In the APCS, the prologue should start with "mov ip, sp" so
865 if we don't see this as the first insn, we will stop.
867 [Note: This doesn't seem to be true any longer, so it's now an
868 optional part of the prologue. - Kevin Buettner, 2001-11-20]
870 [Note further: The "mov ip,sp" only seems to be missing in
871 frameless functions at optimization level "-O2" or above,
872 in which case it is often (but not always) replaced by
873 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
875 sp_offset
= fp_offset
= 0;
877 for (current_pc
= prologue_start
;
878 current_pc
< prologue_end
;
881 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
883 if (insn
== 0xe1a0c00d) /* mov ip, sp */
887 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
889 /* Function is frameless: extra_info defaults OK? */
892 else if ((insn
& 0xffff0000) == 0xe92d0000)
893 /* stmfd sp!, {..., fp, ip, lr, pc}
895 stmfd sp!, {a1, a2, a3, a4} */
897 int mask
= insn
& 0xffff;
899 /* Calculate offsets of saved registers. */
900 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
901 if (mask
& (1 << regno
))
904 fi
->saved_regs
[regno
] = sp_offset
;
907 else if ((insn
& 0xffffcfc0) == 0xe50b0000) /* str rx, [r11, -n] */
909 /* No need to add this to saved_regs -- it's just an arg reg. */
912 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
914 unsigned imm
= insn
& 0xff; /* immediate value */
915 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
916 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
918 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
920 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
922 unsigned imm
= insn
& 0xff; /* immediate value */
923 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
924 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
927 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
930 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
931 fi
->saved_regs
[regno
] = sp_offset
;
933 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
936 unsigned int fp_start_reg
, fp_bound_reg
;
938 if ((insn
& 0x800) == 0x800) /* N0 is set */
940 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
947 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
953 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
954 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
955 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
958 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
961 else if ((insn
& 0xf0000000) != 0xe0000000)
962 break; /* Condition not true, exit early */
963 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
964 break; /* Don't scan past a block load */
966 /* The optimizer might shove anything into the prologue,
967 so we just skip what we don't recognize. */
971 /* The frame size is just the negative of the offset (from the
972 original SP) of the last thing thing we pushed on the stack.
973 The frame offset is [new FP] - [new SP]. */
974 fi
->extra_info
->framesize
= -sp_offset
;
975 if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
)
976 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
978 fi
->extra_info
->frameoffset
= 0;
980 save_prologue_cache (fi
);
983 /* Find REGNUM on the stack. Otherwise, it's in an active register.
984 One thing we might want to do here is to check REGNUM against the
985 clobber mask, and somehow flag it as invalid if it isn't saved on
986 the stack somewhere. This would provide a graceful failure mode
987 when trying to get the value of caller-saves registers for an inner
991 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
993 for (; fi
; fi
= fi
->next
)
995 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
996 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
997 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1000 if (fi
->saved_regs
[regnum
] != 0)
1001 return read_memory_integer (fi
->saved_regs
[regnum
],
1002 REGISTER_RAW_SIZE (regnum
));
1003 return read_register (regnum
);
1005 /* Function: frame_chain Given a GDB frame, determine the address of
1006 the calling function's frame. This will be used to create a new
1007 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1008 will be called for the new frame. For ARM, we save the frame size
1009 when we initialize the frame_info. */
1012 arm_frame_chain (struct frame_info
*fi
)
1014 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1015 CORE_ADDR fn_start
, callers_pc
, fp
;
1017 /* Is this a dummy frame? */
1018 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1019 return fi
->frame
; /* dummy frame same as caller's frame */
1021 /* Is caller-of-this a dummy frame? */
1022 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
1023 fp
= arm_find_callers_reg (fi
, ARM_FP_REGNUM
);
1024 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
1025 return fp
; /* dummy frame's frame may bear no relation to ours */
1027 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
1028 if (fn_start
== entry_point_address ())
1029 return 0; /* in _start fn, don't chain further */
1031 CORE_ADDR caller_pc
, fn_start
;
1032 int framereg
= fi
->extra_info
->framereg
;
1034 if (fi
->pc
< LOWEST_PC
)
1037 /* If the caller is the startup code, we're at the end of the chain. */
1038 caller_pc
= FRAME_SAVED_PC (fi
);
1039 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
1040 if (fn_start
== entry_point_address ())
1043 /* If the caller is Thumb and the caller is ARM, or vice versa,
1044 the frame register of the caller is different from ours.
1045 So we must scan the prologue of the caller to determine its
1046 frame register number. */
1047 /* XXX Fixme, we should try to do this without creating a temporary
1049 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1051 struct frame_info caller_fi
;
1052 struct cleanup
*old_chain
;
1054 /* Create a temporary frame suitable for scanning the caller's
1056 memset (&caller_fi
, 0, sizeof (caller_fi
));
1057 caller_fi
.extra_info
= (struct frame_extra_info
*)
1058 xcalloc (1, sizeof (struct frame_extra_info
));
1059 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1060 caller_fi
.saved_regs
= (CORE_ADDR
*)
1061 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1062 make_cleanup (xfree
, caller_fi
.saved_regs
);
1064 /* Now, scan the prologue and obtain the frame register. */
1065 caller_fi
.pc
= caller_pc
;
1066 arm_scan_prologue (&caller_fi
);
1067 framereg
= caller_fi
.extra_info
->framereg
;
1069 /* Deallocate the storage associated with the temporary frame
1071 do_cleanups (old_chain
);
1074 /* If the caller used a frame register, return its value.
1075 Otherwise, return the caller's stack pointer. */
1076 if (framereg
== ARM_FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1077 return arm_find_callers_reg (fi
, framereg
);
1079 return fi
->frame
+ fi
->extra_info
->framesize
;
1082 /* This function actually figures out the frame address for a given pc
1083 and sp. This is tricky because we sometimes don't use an explicit
1084 frame pointer, and the previous stack pointer isn't necessarily
1085 recorded on the stack. The only reliable way to get this info is
1086 to examine the prologue. FROMLEAF is a little confusing, it means
1087 this is the next frame up the chain AFTER a frameless function. If
1088 this is true, then the frame value for this frame is still in the
1092 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1097 if (fi
->saved_regs
== NULL
)
1098 frame_saved_regs_zalloc (fi
);
1100 fi
->extra_info
= (struct frame_extra_info
*)
1101 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1103 fi
->extra_info
->framesize
= 0;
1104 fi
->extra_info
->frameoffset
= 0;
1105 fi
->extra_info
->framereg
= 0;
1108 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1110 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1112 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1113 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1115 /* We need to setup fi->frame here because run_stack_dummy gets
1116 it wrong by assuming it's always FP. */
1117 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1119 fi
->extra_info
->framesize
= 0;
1120 fi
->extra_info
->frameoffset
= 0;
1126 /* Compute stack pointer for this frame. We use this value for both
1127 the sigtramp and call dummy cases. */
1131 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1132 + fi
->next
->extra_info
->framesize
);
1134 /* Determine whether or not we're in a sigtramp frame.
1135 Unfortunately, it isn't sufficient to test
1136 fi->signal_handler_caller because this value is sometimes set
1137 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1138 fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we
1139 need to use the sigcontext addresses for the saved registers.
1141 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1142 against the name of the function, the code below will have to be
1143 changed to first fetch the name of the function and then pass
1144 this name to PC_IN_SIGTRAMP. */
1146 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1147 && (fi
->signal_handler_caller
|| PC_IN_SIGTRAMP (fi
->pc
, (char *)0)))
1149 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1150 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1152 /* FIXME: What about thumb mode? */
1153 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
1155 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1156 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1157 fi
->extra_info
->framesize
= 0;
1158 fi
->extra_info
->frameoffset
= 0;
1161 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1164 CORE_ADDR callers_sp
;
1166 /* Set rp point at the high end of the saved registers. */
1167 rp
= fi
->frame
- REGISTER_SIZE
;
1169 /* Fill in addresses of saved registers. */
1170 fi
->saved_regs
[ARM_PS_REGNUM
] = rp
;
1171 rp
-= REGISTER_RAW_SIZE (ARM_PS_REGNUM
);
1172 for (reg
= ARM_PC_REGNUM
; reg
>= 0; reg
--)
1174 fi
->saved_regs
[reg
] = rp
;
1175 rp
-= REGISTER_RAW_SIZE (reg
);
1178 callers_sp
= read_memory_integer (fi
->saved_regs
[ARM_SP_REGNUM
],
1179 REGISTER_RAW_SIZE (ARM_SP_REGNUM
));
1180 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
1181 fi
->extra_info
->framesize
= callers_sp
- sp
;
1182 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1186 arm_scan_prologue (fi
);
1189 /* This is the innermost frame? */
1190 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1191 else if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
1192 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1194 /* not the innermost frame */
1195 /* If we have an FP, the callee saved it. */
1196 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1198 read_memory_integer (fi
->next
1199 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1201 /* If we were called by a frameless fn. then our frame is
1202 still in the frame pointer register on the board... */
1203 fi
->frame
= read_fp ();
1206 /* Calculate actual addresses of saved registers using offsets
1207 determined by arm_scan_prologue. */
1208 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1209 if (fi
->saved_regs
[reg
] != 0)
1210 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1211 - fi
->extra_info
->frameoffset
);
1216 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1217 is saved in the stack anywhere, otherwise we get it from the
1220 The old definition of this function was a macro:
1221 #define FRAME_SAVED_PC(FRAME) \
1222 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1225 arm_frame_saved_pc (struct frame_info
*fi
)
1227 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1228 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1229 return generic_read_register_dummy (fi
->pc
, fi
->frame
, ARM_PC_REGNUM
);
1232 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1235 return read_memory_integer (fi
->saved_regs
[ARM_PC_REGNUM
],
1236 REGISTER_RAW_SIZE (ARM_PC_REGNUM
));
1240 CORE_ADDR pc
= arm_find_callers_reg (fi
, ARM_LR_REGNUM
);
1241 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1245 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1246 Examine the Program Status Register to decide which state we're in. */
1251 if (read_register (ARM_PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1252 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1254 return read_register (ARM_FP_REGNUM
); /* R11 if ARM */
1257 /* Store into a struct frame_saved_regs the addresses of the saved
1258 registers of frame described by FRAME_INFO. This includes special
1259 registers such as PC and FP saved in special ways in the stack
1260 frame. SP is even more special: the address we return for it IS
1261 the sp for the next frame. */
1264 arm_frame_init_saved_regs (struct frame_info
*fip
)
1267 if (fip
->saved_regs
)
1270 arm_init_extra_frame_info (0, fip
);
1273 /* Push an empty stack frame, to record the current PC, etc. */
1276 arm_push_dummy_frame (void)
1278 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1279 CORE_ADDR sp
= old_sp
;
1280 CORE_ADDR fp
, prologue_start
;
1283 /* Push the two dummy prologue instructions in reverse order,
1284 so that they'll be in the correct low-to-high order in memory. */
1285 /* sub fp, ip, #4 */
1286 sp
= push_word (sp
, 0xe24cb004);
1287 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1288 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1290 /* Push a pointer to the dummy prologue + 12, because when stm
1291 instruction stores the PC, it stores the address of the stm
1292 instruction itself plus 12. */
1293 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1295 /* Push the processor status. */
1296 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1298 /* Push all 16 registers starting with r15. */
1299 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1300 sp
= push_word (sp
, read_register (regnum
));
1302 /* Update fp (for both Thumb and ARM) and sp. */
1303 write_register (ARM_FP_REGNUM
, fp
);
1304 write_register (THUMB_FP_REGNUM
, fp
);
1305 write_register (ARM_SP_REGNUM
, sp
);
1308 /* CALL_DUMMY_WORDS:
1309 This sequence of words is the instructions
1315 Note this is 12 bytes. */
1317 static LONGEST arm_call_dummy_words
[] =
1319 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1322 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1323 breakpoint to the proper address in the call dummy, so that
1324 `finish' after a stop in a call dummy works.
1326 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1327 optimal solution, but the call to arm_fix_call_dummy is immediately
1328 followed by a call to run_stack_dummy, which is the only function
1329 where call_dummy_breakpoint_offset is actually used. */
1333 arm_set_call_dummy_breakpoint_offset (void)
1335 if (caller_is_thumb
)
1336 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1338 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1341 /* Fix up the call dummy, based on whether the processor is currently
1342 in Thumb or ARM mode, and whether the target function is Thumb or
1343 ARM. There are three different situations requiring three
1346 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1347 been copied into the dummy parameter to this function.
1348 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1349 "mov pc,r4" instruction patched to be a "bx r4" instead.
1350 * Thumb calling anything: uses the Thumb dummy defined below, which
1351 works for calling both ARM and Thumb functions.
1353 All three call dummies expect to receive the target function
1354 address in R4, with the low bit set if it's a Thumb function. */
1357 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1358 struct value
**args
, struct type
*type
, int gcc_p
)
1360 static short thumb_dummy
[4] =
1362 0xf000, 0xf801, /* bl label */
1363 0xdf18, /* swi 24 */
1364 0x4720, /* label: bx r4 */
1366 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1368 /* Set flag indicating whether the current PC is in a Thumb function. */
1369 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1370 arm_set_call_dummy_breakpoint_offset ();
1372 /* If the target function is Thumb, set the low bit of the function
1373 address. And if the CPU is currently in ARM mode, patch the
1374 second instruction of call dummy to use a BX instruction to
1375 switch to Thumb mode. */
1376 target_is_thumb
= arm_pc_is_thumb (fun
);
1377 if (target_is_thumb
)
1380 if (!caller_is_thumb
)
1381 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1384 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1385 instead of the ARM one that's already been copied. This will
1386 work for both Thumb and ARM target functions. */
1387 if (caller_is_thumb
)
1391 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1393 for (i
= 0; i
< len
; i
++)
1395 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1396 p
+= sizeof (thumb_dummy
[0]);
1400 /* Put the target address in r4; the call dummy will copy this to
1402 write_register (4, fun
);
1407 This function does not support passing parameters using the FPA
1408 variant of the APCS. It passes any floating point arguments in the
1409 general registers and/or on the stack. */
1412 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1413 int struct_return
, CORE_ADDR struct_addr
)
1416 int argnum
, argreg
, nstack_size
;
1418 /* Walk through the list of args and determine how large a temporary
1419 stack is required. Need to take care here as structs may be
1420 passed on the stack, and we have to to push them. */
1421 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1422 if (struct_return
) /* The struct address goes in A1. */
1423 nstack_size
+= REGISTER_SIZE
;
1425 /* Walk through the arguments and add their size to nstack_size. */
1426 for (argnum
= 0; argnum
< nargs
; argnum
++)
1429 struct type
*arg_type
;
1431 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1432 len
= TYPE_LENGTH (arg_type
);
1437 /* Allocate room on the stack, and initialize our stack frame
1440 if (nstack_size
> 0)
1446 /* Initialize the integer argument register pointer. */
1447 argreg
= ARM_A1_REGNUM
;
1449 /* The struct_return pointer occupies the first parameter passing
1452 write_register (argreg
++, struct_addr
);
1454 /* Process arguments from left to right. Store as many as allowed
1455 in the parameter passing registers (A1-A4), and save the rest on
1456 the temporary stack. */
1457 for (argnum
= 0; argnum
< nargs
; argnum
++)
1462 enum type_code typecode
;
1463 struct type
*arg_type
, *target_type
;
1465 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1466 target_type
= TYPE_TARGET_TYPE (arg_type
);
1467 len
= TYPE_LENGTH (arg_type
);
1468 typecode
= TYPE_CODE (arg_type
);
1469 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1472 /* I don't know why this code was disable. The only logical use
1473 for a function pointer is to call that function, so setting
1474 the mode bit is perfectly fine. FN */
1475 /* If the argument is a pointer to a function, and it is a Thumb
1476 function, set the low bit of the pointer. */
1477 if (TYPE_CODE_PTR
== typecode
1478 && NULL
!= target_type
1479 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1481 CORE_ADDR regval
= extract_address (val
, len
);
1482 if (arm_pc_is_thumb (regval
))
1483 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1486 /* Copy the argument to general registers or the stack in
1487 register-sized pieces. Large arguments are split between
1488 registers and stack. */
1491 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1493 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1495 /* It's an argument being passed in a general register. */
1496 regval
= extract_address (val
, partial_len
);
1497 write_register (argreg
++, regval
);
1501 /* Push the arguments onto the stack. */
1502 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1503 fp
+= REGISTER_SIZE
;
1511 /* Return adjusted stack pointer. */
1515 /* Pop the current frame. So long as the frame info has been
1516 initialized properly (see arm_init_extra_frame_info), this code
1517 works for dummy frames as well as regular frames. I.e, there's no
1518 need to have a special case for dummy frames. */
1520 arm_pop_frame (void)
1523 struct frame_info
*frame
= get_current_frame ();
1524 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1525 + frame
->extra_info
->framesize
);
1527 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1528 if (frame
->saved_regs
[regnum
] != 0)
1529 write_register (regnum
,
1530 read_memory_integer (frame
->saved_regs
[regnum
],
1531 REGISTER_RAW_SIZE (regnum
)));
1533 write_register (ARM_PC_REGNUM
, FRAME_SAVED_PC (frame
));
1534 write_register (ARM_SP_REGNUM
, old_SP
);
1536 flush_cached_frames ();
1540 print_fpu_flags (int flags
)
1542 if (flags
& (1 << 0))
1543 fputs ("IVO ", stdout
);
1544 if (flags
& (1 << 1))
1545 fputs ("DVZ ", stdout
);
1546 if (flags
& (1 << 2))
1547 fputs ("OFL ", stdout
);
1548 if (flags
& (1 << 3))
1549 fputs ("UFL ", stdout
);
1550 if (flags
& (1 << 4))
1551 fputs ("INX ", stdout
);
1555 /* Print interesting information about the floating point processor
1556 (if present) or emulator. */
1558 arm_print_float_info (void)
1560 register unsigned long status
= read_register (ARM_FPS_REGNUM
);
1563 type
= (status
>> 24) & 127;
1564 printf ("%s FPU type %d\n",
1565 (status
& (1 << 31)) ? "Hardware" : "Software",
1567 fputs ("mask: ", stdout
);
1568 print_fpu_flags (status
>> 16);
1569 fputs ("flags: ", stdout
);
1570 print_fpu_flags (status
);
1573 /* Return the GDB type object for the "standard" data type of data in
1576 static struct type
*
1577 arm_register_type (int regnum
)
1579 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1581 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1582 return builtin_type_arm_ext_big
;
1584 return builtin_type_arm_ext_littlebyte_bigword
;
1587 return builtin_type_int32
;
1590 /* Index within `registers' of the first byte of the space for
1594 arm_register_byte (int regnum
)
1596 if (regnum
< ARM_F0_REGNUM
)
1597 return regnum
* INT_REGISTER_RAW_SIZE
;
1598 else if (regnum
< ARM_PS_REGNUM
)
1599 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1600 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1602 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1603 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1604 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1607 /* Number of bytes of storage in the actual machine representation for
1608 register N. All registers are 4 bytes, except fp0 - fp7, which are
1609 12 bytes in length. */
1612 arm_register_raw_size (int regnum
)
1614 if (regnum
< ARM_F0_REGNUM
)
1615 return INT_REGISTER_RAW_SIZE
;
1616 else if (regnum
< ARM_FPS_REGNUM
)
1617 return FP_REGISTER_RAW_SIZE
;
1619 return STATUS_REGISTER_SIZE
;
1622 /* Number of bytes of storage in a program's representation
1625 arm_register_virtual_size (int regnum
)
1627 if (regnum
< ARM_F0_REGNUM
)
1628 return INT_REGISTER_VIRTUAL_SIZE
;
1629 else if (regnum
< ARM_FPS_REGNUM
)
1630 return FP_REGISTER_VIRTUAL_SIZE
;
1632 return STATUS_REGISTER_SIZE
;
1636 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1637 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1638 It is thought that this is is the floating-point register format on
1639 little-endian systems. */
1642 convert_from_extended (void *ptr
, void *dbl
)
1645 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1646 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1648 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1650 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1654 convert_to_extended (void *dbl
, void *ptr
)
1657 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1658 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1659 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1661 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1666 condition_true (unsigned long cond
, unsigned long status_reg
)
1668 if (cond
== INST_AL
|| cond
== INST_NV
)
1674 return ((status_reg
& FLAG_Z
) != 0);
1676 return ((status_reg
& FLAG_Z
) == 0);
1678 return ((status_reg
& FLAG_C
) != 0);
1680 return ((status_reg
& FLAG_C
) == 0);
1682 return ((status_reg
& FLAG_N
) != 0);
1684 return ((status_reg
& FLAG_N
) == 0);
1686 return ((status_reg
& FLAG_V
) != 0);
1688 return ((status_reg
& FLAG_V
) == 0);
1690 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1692 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1694 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1696 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1698 return (((status_reg
& FLAG_Z
) == 0) &&
1699 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1701 return (((status_reg
& FLAG_Z
) != 0) ||
1702 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1707 /* Support routines for single stepping. Calculate the next PC value. */
1708 #define submask(x) ((1L << ((x) + 1)) - 1)
1709 #define bit(obj,st) (((obj) >> (st)) & 1)
1710 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1711 #define sbits(obj,st,fn) \
1712 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1713 #define BranchDest(addr,instr) \
1714 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1717 static unsigned long
1718 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1719 unsigned long status_reg
)
1721 unsigned long res
, shift
;
1722 int rm
= bits (inst
, 0, 3);
1723 unsigned long shifttype
= bits (inst
, 5, 6);
1727 int rs
= bits (inst
, 8, 11);
1728 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1731 shift
= bits (inst
, 7, 11);
1734 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1735 + (bit (inst
, 4) ? 12 : 8))
1736 : read_register (rm
));
1741 res
= shift
>= 32 ? 0 : res
<< shift
;
1745 res
= shift
>= 32 ? 0 : res
>> shift
;
1751 res
= ((res
& 0x80000000L
)
1752 ? ~((~res
) >> shift
) : res
>> shift
);
1755 case 3: /* ROR/RRX */
1758 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1760 res
= (res
>> shift
) | (res
<< (32 - shift
));
1764 return res
& 0xffffffff;
1767 /* Return number of 1-bits in VAL. */
1770 bitcount (unsigned long val
)
1773 for (nbits
= 0; val
!= 0; nbits
++)
1774 val
&= val
- 1; /* delete rightmost 1-bit in val */
1779 thumb_get_next_pc (CORE_ADDR pc
)
1781 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1782 unsigned short inst1
= read_memory_integer (pc
, 2);
1783 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1784 unsigned long offset
;
1786 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1790 /* Fetch the saved PC from the stack. It's stored above
1791 all of the other registers. */
1792 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1793 sp
= read_register (ARM_SP_REGNUM
);
1794 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1795 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1797 error ("Infinite loop detected");
1799 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1801 unsigned long status
= read_register (ARM_PS_REGNUM
);
1802 unsigned long cond
= bits (inst1
, 8, 11);
1803 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1804 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1806 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1808 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1810 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1812 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1813 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1814 nextpc
= pc_val
+ offset
;
1821 arm_get_next_pc (CORE_ADDR pc
)
1823 unsigned long pc_val
;
1824 unsigned long this_instr
;
1825 unsigned long status
;
1828 if (arm_pc_is_thumb (pc
))
1829 return thumb_get_next_pc (pc
);
1831 pc_val
= (unsigned long) pc
;
1832 this_instr
= read_memory_integer (pc
, 4);
1833 status
= read_register (ARM_PS_REGNUM
);
1834 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1836 if (condition_true (bits (this_instr
, 28, 31), status
))
1838 switch (bits (this_instr
, 24, 27))
1841 case 0x1: /* data processing */
1845 unsigned long operand1
, operand2
, result
= 0;
1849 if (bits (this_instr
, 12, 15) != 15)
1852 if (bits (this_instr
, 22, 25) == 0
1853 && bits (this_instr
, 4, 7) == 9) /* multiply */
1854 error ("Illegal update to pc in instruction");
1856 /* Multiply into PC */
1857 c
= (status
& FLAG_C
) ? 1 : 0;
1858 rn
= bits (this_instr
, 16, 19);
1859 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1861 if (bit (this_instr
, 25))
1863 unsigned long immval
= bits (this_instr
, 0, 7);
1864 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1865 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1868 else /* operand 2 is a shifted register */
1869 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1871 switch (bits (this_instr
, 21, 24))
1874 result
= operand1
& operand2
;
1878 result
= operand1
^ operand2
;
1882 result
= operand1
- operand2
;
1886 result
= operand2
- operand1
;
1890 result
= operand1
+ operand2
;
1894 result
= operand1
+ operand2
+ c
;
1898 result
= operand1
- operand2
+ c
;
1902 result
= operand2
- operand1
+ c
;
1908 case 0xb: /* tst, teq, cmp, cmn */
1909 result
= (unsigned long) nextpc
;
1913 result
= operand1
| operand2
;
1917 /* Always step into a function. */
1922 result
= operand1
& ~operand2
;
1929 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1932 error ("Infinite loop detected");
1937 case 0x5: /* data transfer */
1940 if (bit (this_instr
, 20))
1943 if (bits (this_instr
, 12, 15) == 15)
1949 if (bit (this_instr
, 22))
1950 error ("Illegal update to pc in instruction");
1952 /* byte write to PC */
1953 rn
= bits (this_instr
, 16, 19);
1954 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1955 if (bit (this_instr
, 24))
1958 int c
= (status
& FLAG_C
) ? 1 : 0;
1959 unsigned long offset
=
1960 (bit (this_instr
, 25)
1961 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1962 : bits (this_instr
, 0, 11));
1964 if (bit (this_instr
, 23))
1969 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1972 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1975 error ("Infinite loop detected");
1981 case 0x9: /* block transfer */
1982 if (bit (this_instr
, 20))
1985 if (bit (this_instr
, 15))
1990 if (bit (this_instr
, 23))
1993 unsigned long reglist
= bits (this_instr
, 0, 14);
1994 offset
= bitcount (reglist
) * 4;
1995 if (bit (this_instr
, 24)) /* pre */
1998 else if (bit (this_instr
, 24))
2002 unsigned long rn_val
=
2003 read_register (bits (this_instr
, 16, 19));
2005 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2009 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2011 error ("Infinite loop detected");
2016 case 0xb: /* branch & link */
2017 case 0xa: /* branch */
2019 nextpc
= BranchDest (pc
, this_instr
);
2021 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2023 error ("Infinite loop detected");
2029 case 0xe: /* coproc ops */
2034 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2042 /* single_step() is called just before we want to resume the inferior,
2043 if we want to single-step it but there is no hardware or kernel
2044 single-step support. We find the target of the coming instruction
2047 single_step() is also called just after the inferior stops. If we
2048 had set up a simulated single-step, we undo our damage. */
2051 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2053 static int next_pc
; /* State between setting and unsetting. */
2054 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2058 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2059 target_insert_breakpoint (next_pc
, break_mem
);
2062 target_remove_breakpoint (next_pc
, break_mem
);
2065 #include "bfd-in2.h"
2066 #include "libcoff.h"
2069 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2071 if (arm_pc_is_thumb (memaddr
))
2073 static asymbol
*asym
;
2074 static combined_entry_type ce
;
2075 static struct coff_symbol_struct csym
;
2076 static struct _bfd fake_bfd
;
2077 static bfd_target fake_target
;
2079 if (csym
.native
== NULL
)
2081 /* Create a fake symbol vector containing a Thumb symbol.
2082 This is solely so that the code in print_insn_little_arm()
2083 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2084 the presence of a Thumb symbol and switch to decoding
2085 Thumb instructions. */
2087 fake_target
.flavour
= bfd_target_coff_flavour
;
2088 fake_bfd
.xvec
= &fake_target
;
2089 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2091 csym
.symbol
.the_bfd
= &fake_bfd
;
2092 csym
.symbol
.name
= "fake";
2093 asym
= (asymbol
*) & csym
;
2096 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2097 info
->symbols
= &asym
;
2100 info
->symbols
= NULL
;
2102 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2103 return print_insn_big_arm (memaddr
, info
);
2105 return print_insn_little_arm (memaddr
, info
);
2108 /* The following define instruction sequences that will cause ARM
2109 cpu's to take an undefined instruction trap. These are used to
2110 signal a breakpoint to GDB.
2112 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2113 modes. A different instruction is required for each mode. The ARM
2114 cpu's can also be big or little endian. Thus four different
2115 instructions are needed to support all cases.
2117 Note: ARMv4 defines several new instructions that will take the
2118 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2119 not in fact add the new instructions. The new undefined
2120 instructions in ARMv4 are all instructions that had no defined
2121 behaviour in earlier chips. There is no guarantee that they will
2122 raise an exception, but may be treated as NOP's. In practice, it
2123 may only safe to rely on instructions matching:
2125 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2126 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2127 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2129 Even this may only true if the condition predicate is true. The
2130 following use a condition predicate of ALWAYS so it is always TRUE.
2132 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2133 and NetBSD all use a software interrupt rather than an undefined
2134 instruction to force a trap. This can be handled by by the
2135 abi-specific code during establishment of the gdbarch vector. */
2138 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2139 override these definitions. */
2140 #ifndef ARM_LE_BREAKPOINT
2141 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2143 #ifndef ARM_BE_BREAKPOINT
2144 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2146 #ifndef THUMB_LE_BREAKPOINT
2147 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2149 #ifndef THUMB_BE_BREAKPOINT
2150 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2153 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2154 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2155 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2156 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2158 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2159 the program counter value to determine whether a 16-bit or 32-bit
2160 breakpoint should be used. It returns a pointer to a string of
2161 bytes that encode a breakpoint instruction, stores the length of
2162 the string to *lenptr, and adjusts the program counter (if
2163 necessary) to point to the actual memory location where the
2164 breakpoint should be inserted. */
2166 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2167 breakpoints and storing their handles instread of what was in
2168 memory. It is nice that this is the same size as a handle -
2169 otherwise remote-rdp will have to change. */
2171 static const unsigned char *
2172 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2176 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2178 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2179 *lenptr
= tdep
->thumb_breakpoint_size
;
2180 return tdep
->thumb_breakpoint
;
2184 *lenptr
= tdep
->arm_breakpoint_size
;
2185 return tdep
->arm_breakpoint
;
2189 /* Extract from an array REGBUF containing the (raw) register state a
2190 function return value of type TYPE, and copy that, in virtual
2191 format, into VALBUF. */
2194 arm_extract_return_value (struct type
*type
,
2195 char regbuf
[REGISTER_BYTES
],
2198 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2202 switch (tdep
->fp_model
)
2205 convert_from_extended (®buf
[REGISTER_BYTE (ARM_F0_REGNUM
)],
2209 case ARM_FLOAT_SOFT
:
2210 case ARM_FLOAT_SOFT_VFP
:
2211 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2212 TYPE_LENGTH (type
));
2217 (__FILE__
, __LINE__
,
2218 "arm_extract_return_value: Floating point model not supported");
2223 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2224 TYPE_LENGTH (type
));
2227 /* Extract from an array REGBUF containing the (raw) register state
2228 the address in which a function should return its structure value. */
2231 arm_extract_struct_value_address (char *regbuf
)
2233 return extract_address (regbuf
, REGISTER_RAW_SIZE(ARM_A1_REGNUM
));
2236 /* Will a function return an aggregate type in memory or in a
2237 register? Return 0 if an aggregate type can be returned in a
2238 register, 1 if it must be returned in memory. */
2241 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2244 register enum type_code code
;
2246 /* In the ARM ABI, "integer" like aggregate types are returned in
2247 registers. For an aggregate type to be integer like, its size
2248 must be less than or equal to REGISTER_SIZE and the offset of
2249 each addressable subfield must be zero. Note that bit fields are
2250 not addressable, and all addressable subfields of unions always
2251 start at offset zero.
2253 This function is based on the behaviour of GCC 2.95.1.
2254 See: gcc/arm.c: arm_return_in_memory() for details.
2256 Note: All versions of GCC before GCC 2.95.2 do not set up the
2257 parameters correctly for a function returning the following
2258 structure: struct { float f;}; This should be returned in memory,
2259 not a register. Richard Earnshaw sent me a patch, but I do not
2260 know of any way to detect if a function like the above has been
2261 compiled with the correct calling convention. */
2263 /* All aggregate types that won't fit in a register must be returned
2265 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
2270 /* The only aggregate types that can be returned in a register are
2271 structs and unions. Arrays must be returned in memory. */
2272 code
= TYPE_CODE (type
);
2273 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2278 /* Assume all other aggregate types can be returned in a register.
2279 Run a check for structures, unions and arrays. */
2282 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2285 /* Need to check if this struct/union is "integer" like. For
2286 this to be true, its size must be less than or equal to
2287 REGISTER_SIZE and the offset of each addressable subfield
2288 must be zero. Note that bit fields are not addressable, and
2289 unions always start at offset zero. If any of the subfields
2290 is a floating point type, the struct/union cannot be an
2293 /* For each field in the object, check:
2294 1) Is it FP? --> yes, nRc = 1;
2295 2) Is it addressable (bitpos != 0) and
2296 not packed (bitsize == 0)?
2300 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2302 enum type_code field_type_code
;
2303 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2305 /* Is it a floating point type field? */
2306 if (field_type_code
== TYPE_CODE_FLT
)
2312 /* If bitpos != 0, then we have to care about it. */
2313 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2315 /* Bitfields are not addressable. If the field bitsize is
2316 zero, then the field is not packed. Hence it cannot be
2317 a bitfield or any other packed type. */
2318 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2330 /* Write into appropriate registers a function return value of type
2331 TYPE, given in virtual format. */
2334 arm_store_return_value (struct type
*type
, char *valbuf
)
2336 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2338 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2339 char buf
[MAX_REGISTER_RAW_SIZE
];
2341 switch (tdep
->fp_model
)
2345 convert_to_extended (valbuf
, buf
);
2346 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM
), buf
,
2347 MAX_REGISTER_RAW_SIZE
);
2350 case ARM_FLOAT_SOFT
:
2351 case ARM_FLOAT_SOFT_VFP
:
2352 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2357 (__FILE__
, __LINE__
,
2358 "arm_store_return_value: Floating point model not supported");
2363 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2366 /* Store the address of the place in which to copy the structure the
2367 subroutine will return. This is called from call_function. */
2370 arm_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2372 write_register (ARM_A1_REGNUM
, addr
);
2376 arm_get_longjmp_target (CORE_ADDR
*pc
)
2379 char buf
[INT_REGISTER_RAW_SIZE
];
2380 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2382 jb_addr
= read_register (ARM_A1_REGNUM
);
2384 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2385 INT_REGISTER_RAW_SIZE
))
2388 *pc
= extract_address (buf
, INT_REGISTER_RAW_SIZE
);
2392 /* Return non-zero if the PC is inside a thumb call thunk. */
2395 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2397 CORE_ADDR start_addr
;
2399 /* Find the starting address of the function containing the PC. If
2400 the caller didn't give us a name, look it up at the same time. */
2401 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2405 return strncmp (name
, "_call_via_r", 11) == 0;
2408 /* If PC is in a Thumb call or return stub, return the address of the
2409 target PC, which is in a register. The thunk functions are called
2410 _called_via_xx, where x is the register name. The possible names
2411 are r0-r9, sl, fp, ip, sp, and lr. */
2414 arm_skip_stub (CORE_ADDR pc
)
2417 CORE_ADDR start_addr
;
2419 /* Find the starting address and name of the function containing the PC. */
2420 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2423 /* Call thunks always start with "_call_via_". */
2424 if (strncmp (name
, "_call_via_", 10) == 0)
2426 /* Use the name suffix to determine which register contains the
2428 static char *table
[15] =
2429 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2430 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2434 for (regno
= 0; regno
<= 14; regno
++)
2435 if (strcmp (&name
[10], table
[regno
]) == 0)
2436 return read_register (regno
);
2439 return 0; /* not a stub */
2442 /* If the user changes the register disassembly flavor used for info
2443 register and other commands, we have to also switch the flavor used
2444 in opcodes for disassembly output. This function is run in the set
2445 disassembly_flavor command, and does that. */
2448 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2449 struct cmd_list_element
*c
)
2451 set_disassembly_flavor ();
2454 /* Return the ARM register name corresponding to register I. */
2456 arm_register_name (int i
)
2458 return arm_register_names
[i
];
2462 set_disassembly_flavor (void)
2464 const char *setname
, *setdesc
, **regnames
;
2467 /* Find the flavor that the user wants in the opcodes table. */
2469 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2470 while ((disassembly_flavor
!= setname
)
2471 && (current
< num_flavor_options
))
2472 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2473 current_option
= current
;
2475 /* Fill our copy. */
2476 for (j
= 0; j
< numregs
; j
++)
2477 arm_register_names
[j
] = (char *) regnames
[j
];
2480 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2482 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2483 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2487 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2488 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2491 /* Synchronize the disassembler. */
2492 set_arm_regname_option (current
);
2495 /* arm_othernames implements the "othernames" command. This is kind
2496 of hacky, and I prefer the set-show disassembly-flavor which is
2497 also used for the x86 gdb. I will keep this around, however, in
2498 case anyone is actually using it. */
2501 arm_othernames (char *names
, int n
)
2503 /* Circle through the various flavors. */
2504 current_option
= (current_option
+ 1) % num_flavor_options
;
2506 disassembly_flavor
= valid_flavors
[current_option
];
2507 set_disassembly_flavor ();
2510 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2511 for ARM linux targets using the struct offsets defined in <link.h>.
2512 Note, however, that link.h is not actually referred to in this file.
2513 Instead, the relevant structs offsets were obtained from examining
2514 link.h. (We can't refer to link.h from this file because the host
2515 system won't necessarily have it, or if it does, the structs which
2516 it defines will refer to the host system, not the target). */
2518 struct link_map_offsets
*
2519 arm_linux_svr4_fetch_link_map_offsets (void)
2521 static struct link_map_offsets lmo
;
2522 static struct link_map_offsets
*lmp
= 0;
2528 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2531 lmo
.r_map_offset
= 4;
2534 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2537 lmo
.l_addr_offset
= 0;
2538 lmo
.l_addr_size
= 4;
2540 lmo
.l_name_offset
= 4;
2541 lmo
.l_name_size
= 4;
2543 lmo
.l_next_offset
= 12;
2544 lmo
.l_next_size
= 4;
2546 lmo
.l_prev_offset
= 16;
2547 lmo
.l_prev_size
= 4;
2553 /* Test whether the coff symbol specific value corresponds to a Thumb
2557 coff_sym_is_thumb (int val
)
2559 return (val
== C_THUMBEXT
||
2560 val
== C_THUMBSTAT
||
2561 val
== C_THUMBEXTFUNC
||
2562 val
== C_THUMBSTATFUNC
||
2563 val
== C_THUMBLABEL
);
2566 /* arm_coff_make_msymbol_special()
2567 arm_elf_make_msymbol_special()
2569 These functions test whether the COFF or ELF symbol corresponds to
2570 an address in thumb code, and set a "special" bit in a minimal
2571 symbol to indicate that it does. */
2574 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2576 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2578 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2580 MSYMBOL_SET_SPECIAL (msym
);
2584 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2586 if (coff_sym_is_thumb (val
))
2587 MSYMBOL_SET_SPECIAL (msym
);
2592 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
2594 enum arm_abi
*os_ident_ptr
= obj
;
2596 unsigned int sectsize
;
2598 name
= bfd_get_section_name (abfd
, sect
);
2599 sectsize
= bfd_section_size (abfd
, sect
);
2601 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
2603 unsigned int name_length
, data_length
, note_type
;
2606 /* If the section is larger than this, it's probably not what we are
2611 note
= alloca (sectsize
);
2613 bfd_get_section_contents (abfd
, sect
, note
,
2614 (file_ptr
) 0, (bfd_size_type
) sectsize
);
2616 name_length
= bfd_h_get_32 (abfd
, note
);
2617 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
2618 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
2620 if (name_length
== 4 && data_length
== 16 && note_type
== 1
2621 && strcmp (note
+ 12, "GNU") == 0)
2623 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
2625 /* The case numbers are from abi-tags in glibc. */
2629 *os_ident_ptr
= ARM_ABI_LINUX
;
2634 (__FILE__
, __LINE__
,
2635 "process_note_abi_sections: Hurd objects not supported");
2640 (__FILE__
, __LINE__
,
2641 "process_note_abi_sections: Solaris objects not supported");
2646 (__FILE__
, __LINE__
,
2647 "process_note_abi_sections: unknown OS number %d",
2653 /* NetBSD uses a similar trick. */
2654 else if (strcmp (name
, ".note.netbsd.ident") == 0 && sectsize
> 0)
2656 unsigned int name_length
, desc_length
, note_type
;
2659 /* If the section is larger than this, it's probably not what we are
2664 note
= alloca (sectsize
);
2666 bfd_get_section_contents (abfd
, sect
, note
,
2667 (file_ptr
) 0, (bfd_size_type
) sectsize
);
2669 name_length
= bfd_h_get_32 (abfd
, note
);
2670 desc_length
= bfd_h_get_32 (abfd
, note
+ 4);
2671 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
2673 if (name_length
== 7 && desc_length
== 4 && note_type
== 1
2674 && strcmp (note
+ 12, "NetBSD") == 0)
2675 /* XXX Should we check the version here?
2676 Probably not necessary yet. */
2677 *os_ident_ptr
= ARM_ABI_NETBSD_ELF
;
2681 /* Return one of the ELFOSABI_ constants for BFDs representing ELF
2682 executables. If it's not an ELF executable or if the OS/ABI couldn't
2683 be determined, simply return -1. */
2686 get_elfosabi (bfd
*abfd
)
2689 enum arm_abi arm_abi
= ARM_ABI_UNKNOWN
;
2691 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2693 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
2694 that we're on a SYSV system. However, GNU/Linux uses a note section
2695 to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we
2696 have to check the note sections too.
2698 GNU/ARM tools set the EI_OSABI field to ELFOSABI_ARM, so handle that
2700 if (elfosabi
== 0 || elfosabi
== ELFOSABI_ARM
)
2702 bfd_map_over_sections (abfd
,
2703 process_note_abi_tag_sections
,
2707 if (arm_abi
!= ARM_ABI_UNKNOWN
)
2713 /* Existing ARM Tools don't set this field, so look at the EI_FLAGS
2714 field for more information. */
2716 switch (EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
))
2718 case EF_ARM_EABI_VER1
:
2719 return ARM_ABI_EABI_V1
;
2721 case EF_ARM_EABI_VER2
:
2722 return ARM_ABI_EABI_V2
;
2724 case EF_ARM_EABI_UNKNOWN
:
2725 /* Assume GNU tools. */
2726 return ARM_ABI_APCS
;
2729 internal_error (__FILE__
, __LINE__
,
2730 "get_elfosabi: Unknown ARM EABI version 0x%lx",
2731 EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
));
2736 case ELFOSABI_NETBSD
:
2737 return ARM_ABI_NETBSD_ELF
;
2739 case ELFOSABI_FREEBSD
:
2740 return ARM_ABI_FREEBSD
;
2742 case ELFOSABI_LINUX
:
2743 return ARM_ABI_LINUX
;
2746 /* Assume GNU tools with the old APCS abi. */
2747 return ARM_ABI_APCS
;
2752 return ARM_ABI_UNKNOWN
;
2755 struct arm_abi_handler
2757 struct arm_abi_handler
*next
;
2759 void (*init_abi
)(struct gdbarch_info
, struct gdbarch
*);
2762 struct arm_abi_handler
*arm_abi_handler_list
= NULL
;
2765 arm_gdbarch_register_os_abi (enum arm_abi abi
,
2766 void (*init_abi
)(struct gdbarch_info
,
2769 struct arm_abi_handler
**handler_p
;
2771 for (handler_p
= &arm_abi_handler_list
; *handler_p
!= NULL
;
2772 handler_p
= &(*handler_p
)->next
)
2774 if ((*handler_p
)->abi
== abi
)
2777 (__FILE__
, __LINE__
,
2778 "arm_gdbarch_register_os_abi: A handler for this ABI variant (%d)"
2779 " has already been registered", (int)abi
);
2780 /* If user wants to continue, override previous definition. */
2781 (*handler_p
)->init_abi
= init_abi
;
2787 = (struct arm_abi_handler
*) xmalloc (sizeof (struct arm_abi_handler
));
2788 (*handler_p
)->next
= NULL
;
2789 (*handler_p
)->abi
= abi
;
2790 (*handler_p
)->init_abi
= init_abi
;
2793 /* Initialize the current architecture based on INFO. If possible,
2794 re-use an architecture from ARCHES, which is a list of
2795 architectures already created during this debugging session.
2797 Called e.g. at program startup, when reading a core file, and when
2798 reading a binary file. */
2800 static struct gdbarch
*
2801 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2803 struct gdbarch_tdep
*tdep
;
2804 struct gdbarch
*gdbarch
;
2805 enum arm_abi arm_abi
= ARM_ABI_UNKNOWN
;
2806 struct arm_abi_handler
*abi_handler
;
2808 /* Try to deterimine the ABI of the object we are loading. */
2810 if (info
.abfd
!= NULL
)
2812 switch (bfd_get_flavour (info
.abfd
))
2814 case bfd_target_elf_flavour
:
2815 arm_abi
= get_elfosabi (info
.abfd
);
2818 case bfd_target_aout_flavour
:
2819 if (strcmp (bfd_get_target(info
.abfd
), "a.out-arm-netbsd") == 0)
2820 arm_abi
= ARM_ABI_NETBSD_AOUT
;
2822 /* Assume it's an old APCS-style ABI. */
2823 arm_abi
= ARM_ABI_APCS
;
2826 case bfd_target_coff_flavour
:
2827 /* Assume it's an old APCS-style ABI. */
2829 arm_abi
= ARM_ABI_APCS
;
2833 /* Not sure what to do here, leave the ABI as unknown. */
2838 /* Find a candidate among extant architectures. */
2839 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2841 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2843 /* Make sure the ABI selection matches. */
2844 tdep
= gdbarch_tdep (arches
->gdbarch
);
2845 if (tdep
&& tdep
->arm_abi
== arm_abi
)
2846 return arches
->gdbarch
;
2849 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2850 gdbarch
= gdbarch_alloc (&info
, tdep
);
2852 tdep
->arm_abi
= arm_abi
;
2853 if (arm_abi
< ARM_ABI_INVALID
)
2854 tdep
->abi_name
= arm_abi_names
[arm_abi
];
2857 internal_error (__FILE__
, __LINE__
, "Invalid setting of arm_abi %d",
2859 tdep
->abi_name
= "<invalid>";
2862 /* This is the way it has always defaulted. */
2863 tdep
->fp_model
= ARM_FLOAT_FPA
;
2866 switch (info
.byte_order
)
2868 case BFD_ENDIAN_BIG
:
2869 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2870 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2871 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2872 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2876 case BFD_ENDIAN_LITTLE
:
2877 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2878 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2879 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2880 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2885 internal_error (__FILE__
, __LINE__
,
2886 "arm_gdbarch_init: bad byte order for float format");
2889 /* On ARM targets char defaults to unsigned. */
2890 set_gdbarch_char_signed (gdbarch
, 0);
2892 /* This should be low enough for everything. */
2893 tdep
->lowest_pc
= 0x20;
2894 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2896 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2898 /* Call dummy code. */
2899 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2900 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2901 /* We have to give this a value now, even though we will re-set it
2902 during each call to arm_fix_call_dummy. */
2903 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8);
2904 set_gdbarch_call_dummy_p (gdbarch
, 1);
2905 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2907 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2908 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (arm_call_dummy_words
));
2909 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2910 set_gdbarch_call_dummy_length (gdbarch
, 0);
2912 set_gdbarch_fix_call_dummy (gdbarch
, arm_fix_call_dummy
);
2914 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2916 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2917 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2918 set_gdbarch_coerce_float_to_double (gdbarch
,
2919 standard_coerce_float_to_double
);
2921 /* Frame handling. */
2922 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2923 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2924 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2925 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2926 set_gdbarch_frameless_function_invocation
2927 (gdbarch
, arm_frameless_function_invocation
);
2928 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2929 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2930 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2931 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2932 set_gdbarch_frame_args_skip (gdbarch
, 0);
2933 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2934 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2935 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2937 /* Address manipulation. */
2938 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2939 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2941 /* Offset from address of function to start of its code. */
2942 set_gdbarch_function_start_offset (gdbarch
, 0);
2944 /* Advance PC across function entry code. */
2945 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2947 /* Get the PC when a frame might not be available. */
2948 set_gdbarch_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2950 /* The stack grows downward. */
2951 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2953 /* Breakpoint manipulation. */
2954 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2955 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2957 /* Information about registers, etc. */
2958 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2959 set_gdbarch_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2960 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2961 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2962 set_gdbarch_register_byte (gdbarch
, arm_register_byte
);
2963 set_gdbarch_register_bytes (gdbarch
,
2964 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2965 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2966 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2967 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2968 set_gdbarch_register_raw_size (gdbarch
, arm_register_raw_size
);
2969 set_gdbarch_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2970 set_gdbarch_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2971 set_gdbarch_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2972 set_gdbarch_register_virtual_type (gdbarch
, arm_register_type
);
2974 /* Integer registers are 4 bytes. */
2975 set_gdbarch_register_size (gdbarch
, 4);
2976 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2978 /* Returning results. */
2979 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2980 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2981 set_gdbarch_store_struct_return (gdbarch
, arm_store_struct_return
);
2982 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2983 set_gdbarch_extract_struct_value_address (gdbarch
,
2984 arm_extract_struct_value_address
);
2986 /* Single stepping. */
2987 /* XXX For an RDI target we should ask the target if it can single-step. */
2988 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2990 /* Minsymbol frobbing. */
2991 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2992 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2993 arm_coff_make_msymbol_special
);
2995 /* Hook in the ABI-specific overrides, if they have been registered. */
2996 if (arm_abi
== ARM_ABI_UNKNOWN
)
2998 /* Don't complain about not knowing the ABI variant if we don't
2999 have an inferior. */
3002 (gdb_stderr
, "GDB doesn't recognize the ABI of the inferior. "
3003 "Attempting to continue with the default ARM settings");
3007 for (abi_handler
= arm_abi_handler_list
; abi_handler
!= NULL
;
3008 abi_handler
= abi_handler
->next
)
3009 if (abi_handler
->abi
== arm_abi
)
3013 abi_handler
->init_abi (info
, gdbarch
);
3016 /* We assume that if GDB_MULTI_ARCH is less than
3017 GDB_MULTI_ARCH_TM that an ABI variant can be supported by
3018 overriding definitions in this file. */
3019 if (GDB_MULTI_ARCH
> GDB_MULTI_ARCH_PARTIAL
)
3022 "A handler for the ABI variant \"%s\" is not built into this "
3023 "configuration of GDB. "
3024 "Attempting to continue with the default ARM settings",
3025 arm_abi_names
[arm_abi
]);
3029 /* Now we have tuned the configuration, set a few final things,
3030 based on what the OS ABI has told us. */
3032 if (tdep
->jb_pc
>= 0)
3033 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3035 /* Floating point sizes and format. */
3036 switch (info
.byte_order
)
3038 case BFD_ENDIAN_BIG
:
3039 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
3040 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
3041 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
3045 case BFD_ENDIAN_LITTLE
:
3046 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
3047 if (tdep
->fp_model
== ARM_FLOAT_VFP
3048 || tdep
->fp_model
== ARM_FLOAT_SOFT_VFP
)
3050 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
3051 set_gdbarch_long_double_format (gdbarch
,
3052 &floatformat_ieee_double_little
);
3056 set_gdbarch_double_format
3057 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
3058 set_gdbarch_long_double_format
3059 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
3064 internal_error (__FILE__
, __LINE__
,
3065 "arm_gdbarch_init: bad byte order for float format");
3068 /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
3069 references the old architecture vector, not the one we are
3071 if (prologue_cache
.saved_regs
!= NULL
)
3072 xfree (prologue_cache
.saved_regs
);
3074 /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
3075 references the old architecture vector, not the one we are
3077 prologue_cache
.saved_regs
= (CORE_ADDR
*)
3078 xcalloc (1, (sizeof (CORE_ADDR
)
3079 * (gdbarch_num_regs (gdbarch
)
3080 + gdbarch_num_pseudo_regs (gdbarch
))));
3086 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3088 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3093 if (tdep
->abi_name
!= NULL
)
3094 fprintf_unfiltered (file
, "arm_dump_tdep: ABI = %s\n", tdep
->abi_name
);
3096 internal_error (__FILE__
, __LINE__
,
3097 "arm_dump_tdep: illegal setting of tdep->arm_abi (%d)",
3098 (int) tdep
->arm_abi
);
3100 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
3101 (unsigned long) tdep
->lowest_pc
);
3105 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
3106 struct gdbarch
*gdbarch
)
3112 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
3113 struct gdbarch
*gdbarch
)
3119 arm_init_abi_apcs (struct gdbarch_info info
,
3120 struct gdbarch
*gdbarch
)
3126 _initialize_arm_tdep (void)
3128 struct ui_file
*stb
;
3130 struct cmd_list_element
*new_cmd
;
3131 const char *setname
;
3132 const char *setdesc
;
3133 const char **regnames
;
3135 static char *helptext
;
3138 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3140 /* Register some ABI variants for embedded systems. */
3141 arm_gdbarch_register_os_abi (ARM_ABI_EABI_V1
, arm_init_abi_eabi_v1
);
3142 arm_gdbarch_register_os_abi (ARM_ABI_EABI_V2
, arm_init_abi_eabi_v2
);
3143 arm_gdbarch_register_os_abi (ARM_ABI_APCS
, arm_init_abi_apcs
);
3145 tm_print_insn
= gdb_print_insn_arm
;
3147 /* Get the number of possible sets of register names defined in opcodes. */
3148 num_flavor_options
= get_arm_regname_num_options ();
3150 /* Sync the opcode insn printer with our register viewer. */
3151 parse_arm_disassembler_option ("reg-names-std");
3153 /* Begin creating the help text. */
3154 stb
= mem_fileopen ();
3155 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
3156 The valid values are:\n");
3158 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3159 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
3160 for (i
= 0; i
< num_flavor_options
; i
++)
3162 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3163 valid_flavors
[i
] = setname
;
3164 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3166 /* Copy the default names (if found) and synchronize disassembler. */
3167 if (!strcmp (setname
, "std"))
3169 disassembly_flavor
= setname
;
3171 for (j
= 0; j
< numregs
; j
++)
3172 arm_register_names
[j
] = (char *) regnames
[j
];
3173 set_arm_regname_option (i
);
3176 /* Mark the end of valid options. */
3177 valid_flavors
[num_flavor_options
] = NULL
;
3179 /* Finish the creation of the help text. */
3180 fprintf_unfiltered (stb
, "The default is \"std\".");
3181 helptext
= ui_file_xstrdup (stb
, &length
);
3182 ui_file_delete (stb
);
3184 /* Add the disassembly-flavor command. */
3185 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3187 &disassembly_flavor
,
3190 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
3191 add_show_from_set (new_cmd
, &showlist
);
3193 /* ??? Maybe this should be a boolean. */
3194 add_show_from_set (add_set_cmd ("apcs32", no_class
,
3195 var_zinteger
, (char *) &arm_apcs_32
,
3196 "Set usage of ARM 32-bit mode.\n", &setlist
),
3199 /* Add the deprecated "othernames" command. */
3201 add_com ("othernames", class_obscure
, arm_othernames
,
3202 "Switch to the next set of register names.");
3204 /* Fill in the prologue_cache fields. */
3205 prologue_cache
.saved_regs
= NULL
;
3206 prologue_cache
.extra_info
= (struct frame_extra_info
*)
3207 xcalloc (1, sizeof (struct frame_extra_info
));