1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
41 #include "coff/internal.h"
43 /* Each OS has a different mechanism for accessing the various
44 registers stored in the sigcontext structure.
46 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
47 function pointer) which may be used to determine the addresses
48 of the various saved registers in the sigcontext structure.
50 For the ARM target, there are three parameters to this function.
51 The first is the pc value of the frame under consideration, the
52 second the stack pointer of this frame, and the last is the
53 register number to fetch.
55 If the tm.h file does not define this macro, then it's assumed that
56 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
59 When it comes time to multi-arching this code, see the identically
60 named machinery in ia64-tdep.c for an example of how it could be
61 done. It should not be necessary to modify the code below where
62 this macro is used. */
64 #ifdef SIGCONTEXT_REGISTER_ADDRESS
65 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
66 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
69 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
70 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose. This field is already being used to store
76 the symbol size, so the assumption is that the symbol size cannot
79 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
80 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
81 MSYMBOL_SIZE Returns the size of the minimal symbol,
82 i.e. the "info" field with the "special" bit
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
89 #define MSYMBOL_IS_SPECIAL(msym) \
90 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
92 #define MSYMBOL_SIZE(msym) \
93 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
95 /* Number of different reg name sets (options). */
96 static int num_flavor_options
;
98 /* We have more registers than the disassembler as gdb can print the value
99 of special registers as well.
100 The general register names are overwritten by whatever is being used by
101 the disassembler at the moment. We also adjust the case of cpsr and fps. */
103 /* Initial value: Register names used in ARM's ISA documentation. */
104 static char * arm_register_name_strings
[] =
105 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
106 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
107 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
108 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
109 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
110 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
111 "fps", "cpsr" }; /* 24 25 */
112 static char **arm_register_names
= arm_register_name_strings
;
114 /* Valid register name flavors. */
115 static const char **valid_flavors
;
117 /* Disassembly flavor to use. Default to "std" register names. */
118 static const char *disassembly_flavor
;
119 static int current_option
; /* Index to that option in the opcodes table. */
121 /* This is used to keep the bfd arch_info in sync with the disassembly
123 static void set_disassembly_flavor_sfunc(char *, int,
124 struct cmd_list_element
*);
125 static void set_disassembly_flavor (void);
127 static void convert_from_extended (void *ptr
, void *dbl
);
129 /* Define other aspects of the stack frame. We keep the offsets of
130 all saved registers, 'cause we need 'em a lot! We also keep the
131 current size of the stack frame, and the offset of the frame
132 pointer from the stack pointer (for frameless functions, and when
133 we're still in the prologue of a function with a frame) */
135 struct frame_extra_info
142 /* Addresses for calling Thumb functions have the bit 0 set.
143 Here are some macros to test, set, or clear bit 0 of addresses. */
144 #define IS_THUMB_ADDR(addr) ((addr) & 1)
145 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
146 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
148 /* Will a function return an aggregate type in memory or in a
149 register? Return 0 if an aggregate type can be returned in a
150 register, 1 if it must be returned in memory. */
153 arm_use_struct_convention (int gcc_p
, struct type
*type
)
156 register enum type_code code
;
158 /* In the ARM ABI, "integer" like aggregate types are returned in
159 registers. For an aggregate type to be integer like, its size
160 must be less than or equal to REGISTER_SIZE and the offset of
161 each addressable subfield must be zero. Note that bit fields are
162 not addressable, and all addressable subfields of unions always
163 start at offset zero.
165 This function is based on the behaviour of GCC 2.95.1.
166 See: gcc/arm.c: arm_return_in_memory() for details.
168 Note: All versions of GCC before GCC 2.95.2 do not set up the
169 parameters correctly for a function returning the following
170 structure: struct { float f;}; This should be returned in memory,
171 not a register. Richard Earnshaw sent me a patch, but I do not
172 know of any way to detect if a function like the above has been
173 compiled with the correct calling convention. */
175 /* All aggregate types that won't fit in a register must be returned
177 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
182 /* The only aggregate types that can be returned in a register are
183 structs and unions. Arrays must be returned in memory. */
184 code
= TYPE_CODE (type
);
185 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
190 /* Assume all other aggregate types can be returned in a register.
191 Run a check for structures, unions and arrays. */
194 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
197 /* Need to check if this struct/union is "integer" like. For
198 this to be true, its size must be less than or equal to
199 REGISTER_SIZE and the offset of each addressable subfield
200 must be zero. Note that bit fields are not addressable, and
201 unions always start at offset zero. If any of the subfields
202 is a floating point type, the struct/union cannot be an
205 /* For each field in the object, check:
206 1) Is it FP? --> yes, nRc = 1;
207 2) Is it addressable (bitpos != 0) and
208 not packed (bitsize == 0)?
212 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
214 enum type_code field_type_code
;
215 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
217 /* Is it a floating point type field? */
218 if (field_type_code
== TYPE_CODE_FLT
)
224 /* If bitpos != 0, then we have to care about it. */
225 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
227 /* Bitfields are not addressable. If the field bitsize is
228 zero, then the field is not packed. Hence it cannot be
229 a bitfield or any other packed type. */
230 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
243 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
245 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
248 /* Set to true if the 32-bit mode is in use. */
252 /* Flag set by arm_fix_call_dummy that tells whether the target
253 function is a Thumb function. This flag is checked by
254 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
255 its use in valops.c) to pass the function address as an additional
258 static int target_is_thumb
;
260 /* Flag set by arm_fix_call_dummy that tells whether the calling
261 function is a Thumb function. This flag is checked by
262 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
264 static int caller_is_thumb
;
266 /* Determine if the program counter specified in MEMADDR is in a Thumb
270 arm_pc_is_thumb (CORE_ADDR memaddr
)
272 struct minimal_symbol
*sym
;
274 /* If bit 0 of the address is set, assume this is a Thumb address. */
275 if (IS_THUMB_ADDR (memaddr
))
278 /* Thumb functions have a "special" bit set in minimal symbols. */
279 sym
= lookup_minimal_symbol_by_pc (memaddr
);
282 return (MSYMBOL_IS_SPECIAL (sym
));
290 /* Determine if the program counter specified in MEMADDR is in a call
291 dummy being called from a Thumb function. */
294 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
296 CORE_ADDR sp
= read_sp ();
298 /* FIXME: Until we switch for the new call dummy macros, this heuristic
299 is the best we can do. We are trying to determine if the pc is on
300 the stack, which (hopefully) will only happen in a call dummy.
301 We hope the current stack pointer is not so far alway from the dummy
302 frame location (true if we have not pushed large data structures or
303 gone too many levels deep) and that our 1024 is not enough to consider
304 code regions as part of the stack (true for most practical purposes) */
305 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
306 return caller_is_thumb
;
311 /* Remove useless bits from addresses in a running program. */
313 arm_addr_bits_remove (CORE_ADDR val
)
315 if (arm_pc_is_thumb (val
))
316 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
318 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
321 /* When reading symbols, we need to zap the low bit of the address,
322 which may be set to 1 for Thumb functions. */
324 arm_smash_text_address (CORE_ADDR val
)
329 /* Immediately after a function call, return the saved pc. Can't
330 always go through the frames for this because on some machines the
331 new frame is not set up until the new function executes some
335 arm_saved_pc_after_call (struct frame_info
*frame
)
337 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
340 /* Determine whether the function invocation represented by FI has a
341 frame on the stack associated with it. If it does return zero,
342 otherwise return 1. */
345 arm_frameless_function_invocation (struct frame_info
*fi
)
347 CORE_ADDR func_start
, after_prologue
;
350 /* Sometimes we have functions that do a little setup (like saving the
351 vN registers with the stmdb instruction, but DO NOT set up a frame.
352 The symbol table will report this as a prologue. However, it is
353 important not to try to parse these partial frames as frames, or we
354 will get really confused.
356 So I will demand 3 instructions between the start & end of the
357 prologue before I call it a real prologue, i.e. at least
362 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
363 after_prologue
= SKIP_PROLOGUE (func_start
);
365 /* There are some frameless functions whose first two instructions
366 follow the standard APCS form, in which case after_prologue will
367 be func_start + 8. */
369 frameless
= (after_prologue
< func_start
+ 12);
373 /* The address of the arguments in the frame. */
375 arm_frame_args_address (struct frame_info
*fi
)
380 /* The address of the local variables in the frame. */
382 arm_frame_locals_address (struct frame_info
*fi
)
387 /* The number of arguments being passed in the frame. */
389 arm_frame_num_args (struct frame_info
*fi
)
391 /* We have no way of knowing. */
395 /* A typical Thumb prologue looks like this:
399 Sometimes the latter instruction may be replaced by:
407 or, on tpcs, like this:
414 There is always one instruction of three classes:
419 When we have found at least one of each class we are done with the prolog.
420 Note that the "sub sp, #NN" before the push does not count.
424 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
426 CORE_ADDR current_pc
;
427 int findmask
= 0; /* findmask:
428 bit 0 - push { rlist }
429 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
430 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
433 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
435 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
437 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
439 findmask
|= 1; /* push found */
441 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
443 if ((findmask
& 1) == 0) /* before push ? */
446 findmask
|= 4; /* add/sub sp found */
448 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
450 findmask
|= 2; /* setting of r7 found */
452 else if (insn
== 0x466f) /* mov r7, sp */
454 findmask
|= 2; /* setting of r7 found */
456 else if (findmask
== (4+2+1))
458 break; /* We have found one of each type of prologue instruction */
461 continue; /* something in the prolog that we don't care about or some
462 instruction from outside the prolog scheduled here for optimization */
468 /* Advance the PC across any function entry prologue instructions to reach
471 The APCS (ARM Procedure Call Standard) defines the following
475 [stmfd sp!, {a1,a2,a3,a4}]
476 stmfd sp!, {...,fp,ip,lr,pc}
477 [stfe f7, [sp, #-12]!]
478 [stfe f6, [sp, #-12]!]
479 [stfe f5, [sp, #-12]!]
480 [stfe f4, [sp, #-12]!]
481 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
484 arm_skip_prologue (CORE_ADDR pc
)
488 CORE_ADDR func_addr
, func_end
;
490 struct symtab_and_line sal
;
492 /* See what the symbol table says. */
494 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
498 /* Found a function. */
499 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
500 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
502 /* Don't use this trick for assembly source files. */
503 sal
= find_pc_line (func_addr
, 0);
504 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
509 /* Check if this is Thumb code. */
510 if (arm_pc_is_thumb (pc
))
511 return thumb_skip_prologue (pc
, func_end
);
513 /* Can't find the prologue end in the symbol table, try it the hard way
514 by disassembling the instructions. */
516 inst
= read_memory_integer (skip_pc
, 4);
517 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
521 inst
= read_memory_integer (skip_pc
, 4);
522 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
525 inst
= read_memory_integer (skip_pc
, 4);
528 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
532 inst
= read_memory_integer (skip_pc
, 4);
534 /* Any insns after this point may float into the code, if it makes
535 for better instruction scheduling, so we skip them only if we
536 find them, but still consdier the function to be frame-ful. */
538 /* We may have either one sfmfd instruction here, or several stfe
539 insns, depending on the version of floating point code we
541 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
544 inst
= read_memory_integer (skip_pc
, 4);
548 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
551 inst
= read_memory_integer (skip_pc
, 4);
555 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
561 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
562 This function decodes a Thumb function prologue to determine:
563 1) the size of the stack frame
564 2) which registers are saved on it
565 3) the offsets of saved regs
566 4) the offset from the stack pointer to the frame pointer
567 This information is stored in the "extra" fields of the frame_info.
569 A typical Thumb function prologue would create this stack frame
570 (offsets relative to FP)
571 old SP -> 24 stack parameters
574 R7 -> 0 local variables (16 bytes)
575 SP -> -12 additional stack space (12 bytes)
576 The frame size would thus be 36 bytes, and the frame offset would be
577 12 bytes. The frame register is R7.
579 The comments for thumb_skip_prolog() describe the algorithm we use to detect
580 the end of the prolog */
584 thumb_scan_prologue (struct frame_info
*fi
)
586 CORE_ADDR prologue_start
;
587 CORE_ADDR prologue_end
;
588 CORE_ADDR current_pc
;
589 int saved_reg
[16]; /* which register has been copied to register n? */
590 int findmask
= 0; /* findmask:
591 bit 0 - push { rlist }
592 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
593 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
597 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
599 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
601 if (sal
.line
== 0) /* no line info, use current PC */
602 prologue_end
= fi
->pc
;
603 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
604 prologue_end
= sal
.end
; /* (probably means no prologue) */
607 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
608 /* 16 pushes, an add, and "mv fp,sp" */
610 prologue_end
= min (prologue_end
, fi
->pc
);
612 /* Initialize the saved register map. When register H is copied to
613 register L, we will put H in saved_reg[L]. */
614 for (i
= 0; i
< 16; i
++)
617 /* Search the prologue looking for instructions that set up the
618 frame pointer, adjust the stack pointer, and save registers.
619 Do this until all basic prolog instructions are found. */
621 fi
->extra_info
->framesize
= 0;
622 for (current_pc
= prologue_start
;
623 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
630 insn
= read_memory_unsigned_integer (current_pc
, 2);
632 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
635 findmask
|= 1; /* push found */
636 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
637 whether to save LR (R14). */
638 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
640 /* Calculate offsets of saved R0-R7 and LR. */
641 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
642 if (mask
& (1 << regno
))
644 fi
->extra_info
->framesize
+= 4;
645 fi
->saved_regs
[saved_reg
[regno
]] =
646 -(fi
->extra_info
->framesize
);
647 saved_reg
[regno
] = regno
; /* reset saved register map */
650 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
652 if ((findmask
& 1) == 0) /* before push ? */
655 findmask
|= 4; /* add/sub sp found */
657 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
658 if (insn
& 0x80) /* is it signed? (==subtracting) */
660 fi
->extra_info
->frameoffset
+= offset
;
663 fi
->extra_info
->framesize
-= offset
;
665 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
667 findmask
|= 2; /* setting of r7 found */
668 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
669 /* get scaled offset */
670 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
672 else if (insn
== 0x466f) /* mov r7, sp */
674 findmask
|= 2; /* setting of r7 found */
675 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
676 fi
->extra_info
->frameoffset
= 0;
677 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
679 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
681 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
682 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
683 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
686 continue; /* something in the prolog that we don't care about or some
687 instruction from outside the prolog scheduled here for optimization */
691 /* Check if prologue for this frame's PC has already been scanned. If
692 it has, copy the relevant information about that prologue and
693 return non-zero. Otherwise do not copy anything and return zero.
695 The information saved in the cache includes:
696 * the frame register number;
697 * the size of the stack frame;
698 * the offsets of saved regs (relative to the old SP); and
699 * the offset from the stack pointer to the frame pointer
701 The cache contains only one entry, since this is adequate for the
702 typical sequence of prologue scan requests we get. When performing
703 a backtrace, GDB will usually ask to scan the same function twice
704 in a row (once to get the frame chain, and once to fill in the
705 extra frame information). */
707 static struct frame_info prologue_cache
;
710 check_prologue_cache (struct frame_info
*fi
)
714 if (fi
->pc
== prologue_cache
.pc
)
716 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
717 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
718 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
719 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
720 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
728 /* Copy the prologue information from fi to the prologue cache. */
731 save_prologue_cache (struct frame_info
*fi
)
735 prologue_cache
.pc
= fi
->pc
;
736 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
737 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
738 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
740 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
741 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
745 /* This function decodes an ARM function prologue to determine:
746 1) the size of the stack frame
747 2) which registers are saved on it
748 3) the offsets of saved regs
749 4) the offset from the stack pointer to the frame pointer
750 This information is stored in the "extra" fields of the frame_info.
752 There are two basic forms for the ARM prologue. The fixed argument
753 function call will look like:
756 stmfd sp!, {fp, ip, lr, pc}
760 Which would create this stack frame (offsets relative to FP):
761 IP -> 4 (caller's stack)
762 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
763 -4 LR (return address in caller)
764 -8 IP (copy of caller's SP)
766 SP -> -28 Local variables
768 The frame size would thus be 32 bytes, and the frame offset would be
769 28 bytes. The stmfd call can also save any of the vN registers it
770 plans to use, which increases the frame size accordingly.
772 Note: The stored PC is 8 off of the STMFD instruction that stored it
773 because the ARM Store instructions always store PC + 8 when you read
776 A variable argument function call will look like:
779 stmfd sp!, {a1, a2, a3, a4}
780 stmfd sp!, {fp, ip, lr, pc}
783 Which would create this stack frame (offsets relative to FP):
784 IP -> 20 (caller's stack)
789 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
790 -4 LR (return address in caller)
791 -8 IP (copy of caller's SP)
793 SP -> -28 Local variables
795 The frame size would thus be 48 bytes, and the frame offset would be
798 There is another potential complication, which is that the optimizer
799 will try to separate the store of fp in the "stmfd" instruction from
800 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
801 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
803 Also, note, the original version of the ARM toolchain claimed that there
806 instruction at the end of the prologue. I have never seen GCC produce
807 this, and the ARM docs don't mention it. We still test for it below in
813 arm_scan_prologue (struct frame_info
*fi
)
815 int regno
, sp_offset
, fp_offset
;
816 LONGEST return_value
;
817 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
819 /* Check if this function is already in the cache of frame information. */
820 if (check_prologue_cache (fi
))
823 /* Assume there is no frame until proven otherwise. */
824 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
825 fi
->extra_info
->framesize
= 0;
826 fi
->extra_info
->frameoffset
= 0;
828 /* Check for Thumb prologue. */
829 if (arm_pc_is_thumb (fi
->pc
))
831 thumb_scan_prologue (fi
);
832 save_prologue_cache (fi
);
836 /* Find the function prologue. If we can't find the function in
837 the symbol table, peek in the stack frame to find the PC. */
838 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
840 /* One way to find the end of the prologue (which works well
841 for unoptimized code) is to do the following:
843 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
846 prologue_end = fi->pc;
847 else if (sal.end < prologue_end)
848 prologue_end = sal.end;
850 This mechanism is very accurate so long as the optimizer
851 doesn't move any instructions from the function body into the
852 prologue. If this happens, sal.end will be the last
853 instruction in the first hunk of prologue code just before
854 the first instruction that the scheduler has moved from
855 the body to the prologue.
857 In order to make sure that we scan all of the prologue
858 instructions, we use a slightly less accurate mechanism which
859 may scan more than necessary. To help compensate for this
860 lack of accuracy, the prologue scanning loop below contains
861 several clauses which'll cause the loop to terminate early if
862 an implausible prologue instruction is encountered.
868 is a suitable endpoint since it accounts for the largest
869 possible prologue plus up to five instructions inserted by
872 if (prologue_end
> prologue_start
+ 64)
874 prologue_end
= prologue_start
+ 64; /* See above. */
879 /* Get address of the stmfd in the prologue of the callee; the saved
880 PC is the address of the stmfd + 8. */
881 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
885 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
886 prologue_end
= prologue_start
+ 64; /* See above. */
890 /* Now search the prologue looking for instructions that set up the
891 frame pointer, adjust the stack pointer, and save registers.
893 Be careful, however, and if it doesn't look like a prologue,
894 don't try to scan it. If, for instance, a frameless function
895 begins with stmfd sp!, then we will tell ourselves there is
896 a frame, which will confuse stack traceback, as well ad"finish"
897 and other operations that rely on a knowledge of the stack
900 In the APCS, the prologue should start with "mov ip, sp" so
901 if we don't see this as the first insn, we will stop. [Note:
902 This doesn't seem to be true any longer, so it's now an optional
903 part of the prologue. - Kevin Buettner, 2001-11-20] */
905 sp_offset
= fp_offset
= 0;
907 if (read_memory_unsigned_integer (prologue_start
, 4)
908 == 0xe1a0c00d) /* mov ip, sp */
909 current_pc
= prologue_start
+ 4;
911 current_pc
= prologue_start
;
913 for (; current_pc
< prologue_end
; current_pc
+= 4)
915 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
917 if ((insn
& 0xffff0000) == 0xe92d0000)
918 /* stmfd sp!, {..., fp, ip, lr, pc}
920 stmfd sp!, {a1, a2, a3, a4} */
922 int mask
= insn
& 0xffff;
924 /* Calculate offsets of saved registers. */
925 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
926 if (mask
& (1 << regno
))
929 fi
->saved_regs
[regno
] = sp_offset
;
932 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
934 unsigned imm
= insn
& 0xff; /* immediate value */
935 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
936 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
938 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
940 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
942 unsigned imm
= insn
& 0xff; /* immediate value */
943 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
944 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
947 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
950 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
951 fi
->saved_regs
[regno
] = sp_offset
;
953 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
956 unsigned int fp_start_reg
, fp_bound_reg
;
958 if ((insn
& 0x800) == 0x800) /* N0 is set */
960 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
967 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
973 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
974 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
975 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
978 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
981 else if ((insn
& 0xf0000000) != 0xe0000000)
982 break; /* Condition not true, exit early */
983 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
984 break; /* Don't scan past a block load */
986 /* The optimizer might shove anything into the prologue,
987 so we just skip what we don't recognize. */
991 /* The frame size is just the negative of the offset (from the original SP)
992 of the last thing thing we pushed on the stack. The frame offset is
993 [new FP] - [new SP]. */
994 fi
->extra_info
->framesize
= -sp_offset
;
995 if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
)
996 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
998 fi
->extra_info
->frameoffset
= 0;
1000 save_prologue_cache (fi
);
1003 /* Find REGNUM on the stack. Otherwise, it's in an active register.
1004 One thing we might want to do here is to check REGNUM against the
1005 clobber mask, and somehow flag it as invalid if it isn't saved on
1006 the stack somewhere. This would provide a graceful failure mode
1007 when trying to get the value of caller-saves registers for an inner
1011 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
1013 for (; fi
; fi
= fi
->next
)
1015 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1016 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1017 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1020 if (fi
->saved_regs
[regnum
] != 0)
1021 return read_memory_integer (fi
->saved_regs
[regnum
],
1022 REGISTER_RAW_SIZE (regnum
));
1023 return read_register (regnum
);
1025 /* Function: frame_chain Given a GDB frame, determine the address of
1026 the calling function's frame. This will be used to create a new
1027 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1028 will be called for the new frame. For ARM, we save the frame size
1029 when we initialize the frame_info. */
1032 arm_frame_chain (struct frame_info
*fi
)
1034 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1035 CORE_ADDR fn_start
, callers_pc
, fp
;
1037 /* is this a dummy frame? */
1038 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1039 return fi
->frame
; /* dummy frame same as caller's frame */
1041 /* is caller-of-this a dummy frame? */
1042 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
1043 fp
= arm_find_callers_reg (fi
, ARM_FP_REGNUM
);
1044 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
1045 return fp
; /* dummy frame's frame may bear no relation to ours */
1047 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
1048 if (fn_start
== entry_point_address ())
1049 return 0; /* in _start fn, don't chain further */
1051 CORE_ADDR caller_pc
, fn_start
;
1052 int framereg
= fi
->extra_info
->framereg
;
1054 if (fi
->pc
< LOWEST_PC
)
1057 /* If the caller is the startup code, we're at the end of the chain. */
1058 caller_pc
= FRAME_SAVED_PC (fi
);
1059 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
1060 if (fn_start
== entry_point_address ())
1063 /* If the caller is Thumb and the caller is ARM, or vice versa,
1064 the frame register of the caller is different from ours.
1065 So we must scan the prologue of the caller to determine its
1066 frame register number. */
1067 /* XXX Fixme, we should try to do this without creating a temporary
1069 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1071 struct frame_info caller_fi
;
1072 struct cleanup
*old_chain
;
1074 /* Create a temporary frame suitable for scanning the caller's
1076 memset (&caller_fi
, 0, sizeof (caller_fi
));
1077 caller_fi
.extra_info
= (struct frame_extra_info
*)
1078 xcalloc (1, sizeof (struct frame_extra_info
));
1079 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1080 caller_fi
.saved_regs
= (CORE_ADDR
*)
1081 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1082 make_cleanup (xfree
, caller_fi
.saved_regs
);
1084 /* Now, scan the prologue and obtain the frame register. */
1085 caller_fi
.pc
= caller_pc
;
1086 arm_scan_prologue (&caller_fi
);
1087 framereg
= caller_fi
.extra_info
->framereg
;
1089 /* Deallocate the storage associated with the temporary frame
1091 do_cleanups (old_chain
);
1094 /* If the caller used a frame register, return its value.
1095 Otherwise, return the caller's stack pointer. */
1096 if (framereg
== ARM_FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1097 return arm_find_callers_reg (fi
, framereg
);
1099 return fi
->frame
+ fi
->extra_info
->framesize
;
1102 /* This function actually figures out the frame address for a given pc
1103 and sp. This is tricky because we sometimes don't use an explicit
1104 frame pointer, and the previous stack pointer isn't necessarily
1105 recorded on the stack. The only reliable way to get this info is
1106 to examine the prologue. FROMLEAF is a little confusing, it means
1107 this is the next frame up the chain AFTER a frameless function. If
1108 this is true, then the frame value for this frame is still in the
1112 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1117 if (fi
->saved_regs
== NULL
)
1118 frame_saved_regs_zalloc (fi
);
1120 fi
->extra_info
= (struct frame_extra_info
*)
1121 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1123 fi
->extra_info
->framesize
= 0;
1124 fi
->extra_info
->frameoffset
= 0;
1125 fi
->extra_info
->framereg
= 0;
1128 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1130 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1132 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1133 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1135 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1136 by assuming it's always FP. */
1137 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1139 fi
->extra_info
->framesize
= 0;
1140 fi
->extra_info
->frameoffset
= 0;
1146 /* Compute stack pointer for this frame. We use this value for both the
1147 sigtramp and call dummy cases. */
1151 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1152 + fi
->next
->extra_info
->framesize
);
1154 /* Determine whether or not we're in a sigtramp frame.
1155 Unfortunately, it isn't sufficient to test
1156 fi->signal_handler_caller because this value is sometimes set
1157 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1158 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1159 to use the sigcontext addresses for the saved registers.
1161 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1162 the name of the function, the code below will have to be changed
1163 to first fetch the name of the function and then pass this name
1166 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1167 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, (char *)0)))
1169 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1170 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1172 /* FIXME: What about thumb mode? */
1173 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
1175 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1176 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1177 fi
->extra_info
->framesize
= 0;
1178 fi
->extra_info
->frameoffset
= 0;
1181 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1184 CORE_ADDR callers_sp
;
1186 /* Set rp point at the high end of the saved registers. */
1187 rp
= fi
->frame
- REGISTER_SIZE
;
1189 /* Fill in addresses of saved registers. */
1190 fi
->saved_regs
[ARM_PS_REGNUM
] = rp
;
1191 rp
-= REGISTER_RAW_SIZE (ARM_PS_REGNUM
);
1192 for (reg
= ARM_PC_REGNUM
; reg
>= 0; reg
--)
1194 fi
->saved_regs
[reg
] = rp
;
1195 rp
-= REGISTER_RAW_SIZE (reg
);
1198 callers_sp
= read_memory_integer (fi
->saved_regs
[ARM_SP_REGNUM
],
1199 REGISTER_RAW_SIZE (ARM_SP_REGNUM
));
1200 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
1201 fi
->extra_info
->framesize
= callers_sp
- sp
;
1202 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1206 arm_scan_prologue (fi
);
1209 /* this is the innermost frame? */
1210 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1211 else if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
1212 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1214 /* not the innermost frame */
1215 /* If we have an FP, the callee saved it. */
1216 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1218 read_memory_integer (fi
->next
1219 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1221 /* If we were called by a frameless fn. then our frame is
1222 still in the frame pointer register on the board... */
1223 fi
->frame
= read_fp ();
1226 /* Calculate actual addresses of saved registers using offsets
1227 determined by arm_scan_prologue. */
1228 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1229 if (fi
->saved_regs
[reg
] != 0)
1230 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1231 - fi
->extra_info
->frameoffset
);
1236 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1237 is saved in the stack anywhere, otherwise we get it from the
1240 The old definition of this function was a macro:
1241 #define FRAME_SAVED_PC(FRAME) \
1242 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1245 arm_frame_saved_pc (struct frame_info
*fi
)
1247 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1248 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1249 return generic_read_register_dummy (fi
->pc
, fi
->frame
, ARM_PC_REGNUM
);
1252 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1255 return read_memory_integer (fi
->saved_regs
[ARM_PC_REGNUM
],
1256 REGISTER_RAW_SIZE (ARM_PC_REGNUM
));
1260 CORE_ADDR pc
= arm_find_callers_reg (fi
, ARM_LR_REGNUM
);
1261 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1265 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1266 Examine the Program Status Register to decide which state we're in. */
1271 if (read_register (ARM_PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1272 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1274 return read_register (ARM_FP_REGNUM
); /* R11 if ARM */
1277 /* Store into a struct frame_saved_regs the addresses of the saved
1278 registers of frame described by FRAME_INFO. This includes special
1279 registers such as PC and FP saved in special ways in the stack
1280 frame. SP is even more special: the address we return for it IS
1281 the sp for the next frame. */
1284 arm_frame_init_saved_regs (struct frame_info
*fip
)
1287 if (fip
->saved_regs
)
1290 arm_init_extra_frame_info (0, fip
);
1293 /* Push an empty stack frame, to record the current PC, etc. */
1296 arm_push_dummy_frame (void)
1298 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1299 CORE_ADDR sp
= old_sp
;
1300 CORE_ADDR fp
, prologue_start
;
1303 /* Push the two dummy prologue instructions in reverse order,
1304 so that they'll be in the correct low-to-high order in memory. */
1305 /* sub fp, ip, #4 */
1306 sp
= push_word (sp
, 0xe24cb004);
1307 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1308 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1310 /* Push a pointer to the dummy prologue + 12, because when stm
1311 instruction stores the PC, it stores the address of the stm
1312 instruction itself plus 12. */
1313 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1315 /* Push the processor status. */
1316 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1318 /* Push all 16 registers starting with r15. */
1319 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1320 sp
= push_word (sp
, read_register (regnum
));
1322 /* Update fp (for both Thumb and ARM) and sp. */
1323 write_register (ARM_FP_REGNUM
, fp
);
1324 write_register (THUMB_FP_REGNUM
, fp
);
1325 write_register (ARM_SP_REGNUM
, sp
);
1328 /* CALL_DUMMY_WORDS:
1329 This sequence of words is the instructions
1335 Note this is 12 bytes. */
1337 static LONGEST arm_call_dummy_words
[] =
1339 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1342 /* Fix up the call dummy, based on whether the processor is currently
1343 in Thumb or ARM mode, and whether the target function is Thumb or
1344 ARM. There are three different situations requiring three
1347 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1348 been copied into the dummy parameter to this function.
1349 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1350 "mov pc,r4" instruction patched to be a "bx r4" instead.
1351 * Thumb calling anything: uses the Thumb dummy defined below, which
1352 works for calling both ARM and Thumb functions.
1354 All three call dummies expect to receive the target function
1355 address in R4, with the low bit set if it's a Thumb function. */
1358 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1359 struct value
**args
, struct type
*type
, int gcc_p
)
1361 static short thumb_dummy
[4] =
1363 0xf000, 0xf801, /* bl label */
1364 0xdf18, /* swi 24 */
1365 0x4720, /* label: bx r4 */
1367 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1369 /* Set flag indicating whether the current PC is in a Thumb function. */
1370 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1372 /* If the target function is Thumb, set the low bit of the function
1373 address. And if the CPU is currently in ARM mode, patch the
1374 second instruction of call dummy to use a BX instruction to
1375 switch to Thumb mode. */
1376 target_is_thumb
= arm_pc_is_thumb (fun
);
1377 if (target_is_thumb
)
1380 if (!caller_is_thumb
)
1381 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1384 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1385 instead of the ARM one that's already been copied. This will
1386 work for both Thumb and ARM target functions. */
1387 if (caller_is_thumb
)
1391 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1393 for (i
= 0; i
< len
; i
++)
1395 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1396 p
+= sizeof (thumb_dummy
[0]);
1400 /* Put the target address in r4; the call dummy will copy this to
1402 write_register (4, fun
);
1405 /* Return the offset in the call dummy of the instruction that needs
1406 to have a breakpoint placed on it. This is the offset of the 'swi
1407 24' instruction, which is no longer actually used, but simply acts
1408 as a place-holder now.
1410 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1413 arm_call_dummy_breakpoint_offset (void)
1415 if (caller_is_thumb
)
1423 This function does not support passing parameters using the FPA
1424 variant of the APCS. It passes any floating point arguments in the
1425 general registers and/or on the stack. */
1428 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1429 int struct_return
, CORE_ADDR struct_addr
)
1432 int argnum
, argreg
, nstack_size
;
1434 /* Walk through the list of args and determine how large a temporary
1435 stack is required. Need to take care here as structs may be
1436 passed on the stack, and we have to to push them. */
1437 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1438 if (struct_return
) /* The struct address goes in A1. */
1439 nstack_size
+= REGISTER_SIZE
;
1441 /* Walk through the arguments and add their size to nstack_size. */
1442 for (argnum
= 0; argnum
< nargs
; argnum
++)
1445 struct type
*arg_type
;
1447 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1448 len
= TYPE_LENGTH (arg_type
);
1450 /* ANSI C code passes float arguments as integers, K&R code
1451 passes float arguments as doubles. Correct for this here. */
1452 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1453 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1458 /* Allocate room on the stack, and initialize our stack frame
1461 if (nstack_size
> 0)
1467 /* Initialize the integer argument register pointer. */
1468 argreg
= ARM_A1_REGNUM
;
1470 /* The struct_return pointer occupies the first parameter passing
1473 write_register (argreg
++, struct_addr
);
1475 /* Process arguments from left to right. Store as many as allowed
1476 in the parameter passing registers (A1-A4), and save the rest on
1477 the temporary stack. */
1478 for (argnum
= 0; argnum
< nargs
; argnum
++)
1483 enum type_code typecode
;
1484 struct type
*arg_type
, *target_type
;
1486 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1487 target_type
= TYPE_TARGET_TYPE (arg_type
);
1488 len
= TYPE_LENGTH (arg_type
);
1489 typecode
= TYPE_CODE (arg_type
);
1490 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1492 /* ANSI C code passes float arguments as integers, K&R code
1493 passes float arguments as doubles. The .stabs record for
1494 for ANSI prototype floating point arguments records the
1495 type as FP_INTEGER, while a K&R style (no prototype)
1496 .stabs records the type as FP_FLOAT. In this latter case
1497 the compiler converts the float arguments to double before
1498 calling the function. */
1499 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1502 dblval
= extract_floating (val
, len
);
1503 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1505 store_floating (val
, len
, dblval
);
1508 /* I don't know why this code was disable. The only logical use
1509 for a function pointer is to call that function, so setting
1510 the mode bit is perfectly fine. FN */
1511 /* If the argument is a pointer to a function, and it is a Thumb
1512 function, set the low bit of the pointer. */
1513 if (TYPE_CODE_PTR
== typecode
1514 && NULL
!= target_type
1515 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1517 CORE_ADDR regval
= extract_address (val
, len
);
1518 if (arm_pc_is_thumb (regval
))
1519 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1522 /* Copy the argument to general registers or the stack in
1523 register-sized pieces. Large arguments are split between
1524 registers and stack. */
1527 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1529 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1531 /* It's an argument being passed in a general register. */
1532 regval
= extract_address (val
, partial_len
);
1533 write_register (argreg
++, regval
);
1537 /* Push the arguments onto the stack. */
1538 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1539 fp
+= REGISTER_SIZE
;
1547 /* Return adjusted stack pointer. */
1551 /* Pop the current frame. So long as the frame info has been initialized
1552 properly (see arm_init_extra_frame_info), this code works for dummy frames
1553 as well as regular frames. I.e, there's no need to have a special case
1554 for dummy frames. */
1556 arm_pop_frame (void)
1559 struct frame_info
*frame
= get_current_frame ();
1560 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1561 + frame
->extra_info
->framesize
);
1563 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1564 if (frame
->saved_regs
[regnum
] != 0)
1565 write_register (regnum
,
1566 read_memory_integer (frame
->saved_regs
[regnum
],
1567 REGISTER_RAW_SIZE (regnum
)));
1569 write_register (ARM_PC_REGNUM
, FRAME_SAVED_PC (frame
));
1570 write_register (ARM_SP_REGNUM
, old_SP
);
1572 flush_cached_frames ();
1576 print_fpu_flags (int flags
)
1578 if (flags
& (1 << 0))
1579 fputs ("IVO ", stdout
);
1580 if (flags
& (1 << 1))
1581 fputs ("DVZ ", stdout
);
1582 if (flags
& (1 << 2))
1583 fputs ("OFL ", stdout
);
1584 if (flags
& (1 << 3))
1585 fputs ("UFL ", stdout
);
1586 if (flags
& (1 << 4))
1587 fputs ("INX ", stdout
);
1591 /* Print interesting information about the floating point processor
1592 (if present) or emulator. */
1594 arm_print_float_info (void)
1596 register unsigned long status
= read_register (ARM_FPS_REGNUM
);
1599 type
= (status
>> 24) & 127;
1600 printf ("%s FPU type %d\n",
1601 (status
& (1 << 31)) ? "Hardware" : "Software",
1603 fputs ("mask: ", stdout
);
1604 print_fpu_flags (status
>> 16);
1605 fputs ("flags: ", stdout
);
1606 print_fpu_flags (status
);
1609 /* Return the GDB type object for the "standard" data type of data in
1612 static struct type
*
1613 arm_register_type (int regnum
)
1615 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1617 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1618 return builtin_type_arm_ext_big
;
1620 return builtin_type_arm_ext_littlebyte_bigword
;
1623 return builtin_type_int32
;
1626 /* Index within `registers' of the first byte of the space for
1630 arm_register_byte (int regnum
)
1632 if (regnum
< ARM_F0_REGNUM
)
1633 return regnum
* INT_REGISTER_RAW_SIZE
;
1634 else if (regnum
< ARM_PS_REGNUM
)
1635 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1636 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1638 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1639 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1640 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1643 /* Number of bytes of storage in the actual machine representation for
1644 register N. All registers are 4 bytes, except fp0 - fp7, which are
1645 12 bytes in length. */
1648 arm_register_raw_size (int regnum
)
1650 if (regnum
< ARM_F0_REGNUM
)
1651 return INT_REGISTER_RAW_SIZE
;
1652 else if (regnum
< ARM_FPS_REGNUM
)
1653 return FP_REGISTER_RAW_SIZE
;
1655 return STATUS_REGISTER_SIZE
;
1658 /* Number of bytes of storage in a program's representation
1661 arm_register_virtual_size (int regnum
)
1663 if (regnum
< ARM_F0_REGNUM
)
1664 return INT_REGISTER_VIRTUAL_SIZE
;
1665 else if (regnum
< ARM_FPS_REGNUM
)
1666 return FP_REGISTER_VIRTUAL_SIZE
;
1668 return STATUS_REGISTER_SIZE
;
1672 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1673 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1674 It is thought that this is is the floating-point register format on
1675 little-endian systems. */
1678 convert_from_extended (void *ptr
, void *dbl
)
1681 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1682 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1684 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1686 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1690 convert_to_extended (void *dbl
, void *ptr
)
1693 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1694 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1695 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1697 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1702 condition_true (unsigned long cond
, unsigned long status_reg
)
1704 if (cond
== INST_AL
|| cond
== INST_NV
)
1710 return ((status_reg
& FLAG_Z
) != 0);
1712 return ((status_reg
& FLAG_Z
) == 0);
1714 return ((status_reg
& FLAG_C
) != 0);
1716 return ((status_reg
& FLAG_C
) == 0);
1718 return ((status_reg
& FLAG_N
) != 0);
1720 return ((status_reg
& FLAG_N
) == 0);
1722 return ((status_reg
& FLAG_V
) != 0);
1724 return ((status_reg
& FLAG_V
) == 0);
1726 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1728 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1730 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1732 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1734 return (((status_reg
& FLAG_Z
) == 0) &&
1735 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1737 return (((status_reg
& FLAG_Z
) != 0) ||
1738 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1743 /* Support routines for single stepping. Calculate the next PC value. */
1744 #define submask(x) ((1L << ((x) + 1)) - 1)
1745 #define bit(obj,st) (((obj) >> (st)) & 1)
1746 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1747 #define sbits(obj,st,fn) \
1748 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1749 #define BranchDest(addr,instr) \
1750 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1753 static unsigned long
1754 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1755 unsigned long status_reg
)
1757 unsigned long res
, shift
;
1758 int rm
= bits (inst
, 0, 3);
1759 unsigned long shifttype
= bits (inst
, 5, 6);
1763 int rs
= bits (inst
, 8, 11);
1764 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1767 shift
= bits (inst
, 7, 11);
1770 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1771 + (bit (inst
, 4) ? 12 : 8))
1772 : read_register (rm
));
1777 res
= shift
>= 32 ? 0 : res
<< shift
;
1781 res
= shift
>= 32 ? 0 : res
>> shift
;
1787 res
= ((res
& 0x80000000L
)
1788 ? ~((~res
) >> shift
) : res
>> shift
);
1791 case 3: /* ROR/RRX */
1794 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1796 res
= (res
>> shift
) | (res
<< (32 - shift
));
1800 return res
& 0xffffffff;
1803 /* Return number of 1-bits in VAL. */
1806 bitcount (unsigned long val
)
1809 for (nbits
= 0; val
!= 0; nbits
++)
1810 val
&= val
- 1; /* delete rightmost 1-bit in val */
1815 thumb_get_next_pc (CORE_ADDR pc
)
1817 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1818 unsigned short inst1
= read_memory_integer (pc
, 2);
1819 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1820 unsigned long offset
;
1822 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1826 /* Fetch the saved PC from the stack. It's stored above
1827 all of the other registers. */
1828 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1829 sp
= read_register (ARM_SP_REGNUM
);
1830 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1831 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1833 error ("Infinite loop detected");
1835 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1837 unsigned long status
= read_register (ARM_PS_REGNUM
);
1838 unsigned long cond
= bits (inst1
, 8, 11);
1839 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1840 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1842 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1844 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1846 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1848 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1849 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1850 nextpc
= pc_val
+ offset
;
1857 arm_get_next_pc (CORE_ADDR pc
)
1859 unsigned long pc_val
;
1860 unsigned long this_instr
;
1861 unsigned long status
;
1864 if (arm_pc_is_thumb (pc
))
1865 return thumb_get_next_pc (pc
);
1867 pc_val
= (unsigned long) pc
;
1868 this_instr
= read_memory_integer (pc
, 4);
1869 status
= read_register (ARM_PS_REGNUM
);
1870 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1872 if (condition_true (bits (this_instr
, 28, 31), status
))
1874 switch (bits (this_instr
, 24, 27))
1877 case 0x1: /* data processing */
1881 unsigned long operand1
, operand2
, result
= 0;
1885 if (bits (this_instr
, 12, 15) != 15)
1888 if (bits (this_instr
, 22, 25) == 0
1889 && bits (this_instr
, 4, 7) == 9) /* multiply */
1890 error ("Illegal update to pc in instruction");
1892 /* Multiply into PC */
1893 c
= (status
& FLAG_C
) ? 1 : 0;
1894 rn
= bits (this_instr
, 16, 19);
1895 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1897 if (bit (this_instr
, 25))
1899 unsigned long immval
= bits (this_instr
, 0, 7);
1900 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1901 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1904 else /* operand 2 is a shifted register */
1905 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1907 switch (bits (this_instr
, 21, 24))
1910 result
= operand1
& operand2
;
1914 result
= operand1
^ operand2
;
1918 result
= operand1
- operand2
;
1922 result
= operand2
- operand1
;
1926 result
= operand1
+ operand2
;
1930 result
= operand1
+ operand2
+ c
;
1934 result
= operand1
- operand2
+ c
;
1938 result
= operand2
- operand1
+ c
;
1944 case 0xb: /* tst, teq, cmp, cmn */
1945 result
= (unsigned long) nextpc
;
1949 result
= operand1
| operand2
;
1953 /* Always step into a function. */
1958 result
= operand1
& ~operand2
;
1965 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1968 error ("Infinite loop detected");
1973 case 0x5: /* data transfer */
1976 if (bit (this_instr
, 20))
1979 if (bits (this_instr
, 12, 15) == 15)
1985 if (bit (this_instr
, 22))
1986 error ("Illegal update to pc in instruction");
1988 /* byte write to PC */
1989 rn
= bits (this_instr
, 16, 19);
1990 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1991 if (bit (this_instr
, 24))
1994 int c
= (status
& FLAG_C
) ? 1 : 0;
1995 unsigned long offset
=
1996 (bit (this_instr
, 25)
1997 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1998 : bits (this_instr
, 0, 11));
2000 if (bit (this_instr
, 23))
2005 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2008 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2011 error ("Infinite loop detected");
2017 case 0x9: /* block transfer */
2018 if (bit (this_instr
, 20))
2021 if (bit (this_instr
, 15))
2026 if (bit (this_instr
, 23))
2029 unsigned long reglist
= bits (this_instr
, 0, 14);
2030 offset
= bitcount (reglist
) * 4;
2031 if (bit (this_instr
, 24)) /* pre */
2034 else if (bit (this_instr
, 24))
2038 unsigned long rn_val
=
2039 read_register (bits (this_instr
, 16, 19));
2041 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2045 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2047 error ("Infinite loop detected");
2052 case 0xb: /* branch & link */
2053 case 0xa: /* branch */
2055 nextpc
= BranchDest (pc
, this_instr
);
2057 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2059 error ("Infinite loop detected");
2065 case 0xe: /* coproc ops */
2070 fprintf (stderr
, "Bad bit-field extraction\n");
2078 /* single_step() is called just before we want to resume the inferior,
2079 if we want to single-step it but there is no hardware or kernel
2080 single-step support. We find the target of the coming instruction
2083 single_step is also called just after the inferior stops. If we had
2084 set up a simulated single-step, we undo our damage. */
2087 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2089 static int next_pc
; /* State between setting and unsetting. */
2090 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2094 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2095 target_insert_breakpoint (next_pc
, break_mem
);
2098 target_remove_breakpoint (next_pc
, break_mem
);
2101 #include "bfd-in2.h"
2102 #include "libcoff.h"
2105 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2107 if (arm_pc_is_thumb (memaddr
))
2109 static asymbol
*asym
;
2110 static combined_entry_type ce
;
2111 static struct coff_symbol_struct csym
;
2112 static struct _bfd fake_bfd
;
2113 static bfd_target fake_target
;
2115 if (csym
.native
== NULL
)
2117 /* Create a fake symbol vector containing a Thumb symbol. This is
2118 solely so that the code in print_insn_little_arm() and
2119 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
2120 of a Thumb symbol and switch to decoding Thumb instructions. */
2122 fake_target
.flavour
= bfd_target_coff_flavour
;
2123 fake_bfd
.xvec
= &fake_target
;
2124 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2126 csym
.symbol
.the_bfd
= &fake_bfd
;
2127 csym
.symbol
.name
= "fake";
2128 asym
= (asymbol
*) & csym
;
2131 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2132 info
->symbols
= &asym
;
2135 info
->symbols
= NULL
;
2137 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2138 return print_insn_big_arm (memaddr
, info
);
2140 return print_insn_little_arm (memaddr
, info
);
2143 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2144 the program counter value to determine whether a 16-bit or 32-bit
2145 breakpoint should be used. It returns a pointer to a string of
2146 bytes that encode a breakpoint instruction, stores the length of
2147 the string to *lenptr, and adjusts the program counter (if
2148 necessary) to point to the actual memory location where the
2149 breakpoint should be inserted. */
2151 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2152 breakpoints and storing their handles instread of what was in
2153 memory. It is nice that this is the same size as a handle -
2154 otherwise remote-rdp will have to change. */
2157 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2159 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2161 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2163 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2164 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2165 *lenptr
= sizeof (thumb_breakpoint
);
2166 return thumb_breakpoint
;
2170 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2171 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2172 *lenptr
= sizeof (thumb_breakpoint
);
2173 return thumb_breakpoint
;
2178 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2180 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
2181 *lenptr
= sizeof (arm_breakpoint
);
2182 return arm_breakpoint
;
2186 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
2187 *lenptr
= sizeof (arm_breakpoint
);
2188 return arm_breakpoint
;
2193 /* Extract from an array REGBUF containing the (raw) register state a
2194 function return value of type TYPE, and copy that, in virtual
2195 format, into VALBUF. */
2198 arm_extract_return_value (struct type
*type
,
2199 char regbuf
[REGISTER_BYTES
],
2202 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2203 convert_from_extended (®buf
[REGISTER_BYTE (ARM_F0_REGNUM
)], valbuf
);
2205 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2206 TYPE_LENGTH (type
));
2209 /* Write into appropriate registers a function return value of type
2210 TYPE, given in virtual format. */
2213 arm_store_return_value (struct type
*type
, char *valbuf
)
2215 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2217 char buf
[MAX_REGISTER_RAW_SIZE
];
2219 convert_to_extended (valbuf
, buf
);
2220 /* XXX Is this correct for soft-float? */
2221 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM
), buf
,
2222 MAX_REGISTER_RAW_SIZE
);
2225 write_register_bytes (0, valbuf
, TYPE_LENGTH (type
));
2228 /* Store the address of the place in which to copy the structure the
2229 subroutine will return. This is called from call_function. */
2232 arm_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2234 write_register (ARM_A1_REGNUM
, addr
);
2237 /* Return non-zero if the PC is inside a thumb call thunk. */
2240 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2242 CORE_ADDR start_addr
;
2244 /* Find the starting address of the function containing the PC. If
2245 the caller didn't give us a name, look it up at the same time. */
2246 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2249 return strncmp (name
, "_call_via_r", 11) == 0;
2252 /* If PC is in a Thumb call or return stub, return the address of the
2253 target PC, which is in a register. The thunk functions are called
2254 _called_via_xx, where x is the register name. The possible names
2255 are r0-r9, sl, fp, ip, sp, and lr. */
2258 arm_skip_stub (CORE_ADDR pc
)
2261 CORE_ADDR start_addr
;
2263 /* Find the starting address and name of the function containing the PC. */
2264 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2267 /* Call thunks always start with "_call_via_". */
2268 if (strncmp (name
, "_call_via_", 10) == 0)
2270 /* Use the name suffix to determine which register contains the
2272 static char *table
[15] =
2273 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2274 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2278 for (regno
= 0; regno
<= 14; regno
++)
2279 if (strcmp (&name
[10], table
[regno
]) == 0)
2280 return read_register (regno
);
2283 return 0; /* not a stub */
2286 /* If the user changes the register disassembly flavor used for info register
2287 and other commands, we have to also switch the flavor used in opcodes
2288 for disassembly output.
2289 This function is run in the set disassembly_flavor command, and does that. */
2292 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2293 struct cmd_list_element
*c
)
2295 set_disassembly_flavor ();
2298 /* Return the ARM register name corresponding to register I. */
2300 arm_register_name (int i
)
2302 return arm_register_names
[i
];
2306 set_disassembly_flavor (void)
2308 const char *setname
, *setdesc
, **regnames
;
2311 /* Find the flavor that the user wants in the opcodes table. */
2313 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2314 while ((disassembly_flavor
!= setname
)
2315 && (current
< num_flavor_options
))
2316 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2317 current_option
= current
;
2319 /* Fill our copy. */
2320 for (j
= 0; j
< numregs
; j
++)
2321 arm_register_names
[j
] = (char *) regnames
[j
];
2324 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2326 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2327 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2331 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2332 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2335 /* Synchronize the disassembler. */
2336 set_arm_regname_option (current
);
2339 /* arm_othernames implements the "othernames" command. This is kind
2340 of hacky, and I prefer the set-show disassembly-flavor which is
2341 also used for the x86 gdb. I will keep this around, however, in
2342 case anyone is actually using it. */
2345 arm_othernames (char *names
, int n
)
2347 /* Circle through the various flavors. */
2348 current_option
= (current_option
+ 1) % num_flavor_options
;
2350 disassembly_flavor
= valid_flavors
[current_option
];
2351 set_disassembly_flavor ();
2354 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2355 for ARM linux targets using the struct offsets defined in <link.h>.
2356 Note, however, that link.h is not actually referred to in this file.
2357 Instead, the relevant structs offsets were obtained from examining
2358 link.h. (We can't refer to link.h from this file because the host
2359 system won't necessarily have it, or if it does, the structs which
2360 it defines will refer to the host system, not the target.) */
2362 struct link_map_offsets
*
2363 arm_linux_svr4_fetch_link_map_offsets (void)
2365 static struct link_map_offsets lmo
;
2366 static struct link_map_offsets
*lmp
= 0;
2372 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2375 lmo
.r_map_offset
= 4;
2378 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2381 lmo
.l_addr_offset
= 0;
2382 lmo
.l_addr_size
= 4;
2384 lmo
.l_name_offset
= 4;
2385 lmo
.l_name_size
= 4;
2387 lmo
.l_next_offset
= 12;
2388 lmo
.l_next_size
= 4;
2390 lmo
.l_prev_offset
= 16;
2391 lmo
.l_prev_size
= 4;
2397 /* Test whether the coff symbol specific value corresponds to a Thumb
2401 coff_sym_is_thumb (int val
)
2403 return (val
== C_THUMBEXT
||
2404 val
== C_THUMBSTAT
||
2405 val
== C_THUMBEXTFUNC
||
2406 val
== C_THUMBSTATFUNC
||
2407 val
== C_THUMBLABEL
);
2410 /* arm_coff_make_msymbol_special()
2411 arm_elf_make_msymbol_special()
2413 These functions test whether the COFF or ELF symbol corresponds to
2414 an address in thumb code, and set a "special" bit in a minimal
2415 symbol to indicate that it does. */
2418 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2420 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2422 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2424 MSYMBOL_SET_SPECIAL (msym
);
2428 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2430 if (coff_sym_is_thumb (val
))
2431 MSYMBOL_SET_SPECIAL (msym
);
2434 static struct gdbarch
*
2435 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2437 struct gdbarch
*gdbarch
;
2440 return arches
->gdbarch
;
2442 /* XXX We'll probably need to set the tdep field soon. */
2443 gdbarch
= gdbarch_alloc (&info
, NULL
);
2445 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2447 /* Call dummy code. */
2448 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2449 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2450 set_gdbarch_call_dummy_p (gdbarch
, 1);
2451 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2453 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2454 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (arm_call_dummy_words
));
2455 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2457 set_gdbarch_fix_call_dummy (gdbarch
, arm_fix_call_dummy
);
2459 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2461 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2462 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2464 /* Frame handling. */
2465 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2466 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2467 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2468 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2469 set_gdbarch_frameless_function_invocation
2470 (gdbarch
, arm_frameless_function_invocation
);
2471 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2472 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2473 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2474 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2475 set_gdbarch_frame_args_skip (gdbarch
, 0);
2476 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2477 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2478 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2480 /* Address manipulation. */
2481 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2482 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2484 /* Offset from address of function to start of its code. */
2485 set_gdbarch_function_start_offset (gdbarch
, 0);
2487 /* Advance PC across function entry code. */
2488 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2490 /* Get the PC when a frame might not be available. */
2491 set_gdbarch_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2493 /* The stack grows downward. */
2494 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2496 /* Breakpoint manipulation. */
2497 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2498 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2500 /* Information about registers, etc. */
2501 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2502 set_gdbarch_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2503 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2504 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2505 set_gdbarch_register_byte (gdbarch
, arm_register_byte
);
2506 set_gdbarch_register_bytes (gdbarch
,
2507 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2508 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2509 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2510 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2511 set_gdbarch_register_raw_size (gdbarch
, arm_register_raw_size
);
2512 set_gdbarch_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2513 set_gdbarch_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2514 set_gdbarch_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2515 set_gdbarch_register_virtual_type (gdbarch
, arm_register_type
);
2517 /* Integer registers are 4 bytes. */
2518 set_gdbarch_register_size (gdbarch
, 4);
2519 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2521 /* Returning results. */
2522 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2523 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2524 set_gdbarch_store_struct_return (gdbarch
, arm_store_struct_return
);
2526 /* Single stepping. */
2527 /* XXX For an RDI target we should ask the target if it can single-step. */
2528 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2530 /* Minsymbol frobbing. */
2531 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2532 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2533 arm_coff_make_msymbol_special
);
2535 /* XXX We can't do this until NUM_REGS is set for the architecture.
2536 Even then, we can't use SIZEOF_FRAME_SAVED_REGS, since that still
2537 references the old architecture vector, not the one we are
2539 if (prologue_cache
.saved_regs
!= NULL
)
2540 xfree (prologue_cache
.saved_regs
);
2542 prologue_cache
.saved_regs
= (CORE_ADDR
*)
2543 xcalloc (1, (sizeof (CORE_ADDR
)
2544 * (NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
+ NUM_PSEUDO_REGS
)));
2550 _initialize_arm_tdep (void)
2552 struct ui_file
*stb
;
2554 struct cmd_list_element
*new_cmd
;
2555 const char *setname
;
2556 const char *setdesc
;
2557 const char **regnames
;
2559 static char *helptext
;
2562 register_gdbarch_init (bfd_arch_arm
, arm_gdbarch_init
);
2564 tm_print_insn
= gdb_print_insn_arm
;
2566 /* Get the number of possible sets of register names defined in opcodes. */
2567 num_flavor_options
= get_arm_regname_num_options ();
2569 /* Sync the opcode insn printer with our register viewer: */
2570 parse_arm_disassembler_option ("reg-names-std");
2572 /* Begin creating the help text. */
2573 stb
= mem_fileopen ();
2574 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2575 The valid values are:\n");
2577 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2578 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2579 for (i
= 0; i
< num_flavor_options
; i
++)
2581 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2582 valid_flavors
[i
] = setname
;
2583 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2585 /* Copy the default names (if found) and synchronize disassembler. */
2586 if (!strcmp (setname
, "std"))
2588 disassembly_flavor
= setname
;
2590 for (j
= 0; j
< numregs
; j
++)
2591 arm_register_names
[j
] = (char *) regnames
[j
];
2592 set_arm_regname_option (i
);
2595 /* Mark the end of valid options. */
2596 valid_flavors
[num_flavor_options
] = NULL
;
2598 /* Finish the creation of the help text. */
2599 fprintf_unfiltered (stb
, "The default is \"std\".");
2600 helptext
= ui_file_xstrdup (stb
, &length
);
2601 ui_file_delete (stb
);
2603 /* Add the disassembly-flavor command */
2604 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2606 &disassembly_flavor
,
2609 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
2610 add_show_from_set (new_cmd
, &showlist
);
2612 /* ??? Maybe this should be a boolean. */
2613 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2614 var_zinteger
, (char *) &arm_apcs_32
,
2615 "Set usage of ARM 32-bit mode.\n", &setlist
),
2618 /* Add the deprecated "othernames" command */
2620 add_com ("othernames", class_obscure
, arm_othernames
,
2621 "Switch to the next set of register names.");
2623 /* Fill in the prologue_cache fields. */
2624 prologue_cache
.saved_regs
= NULL
;
2625 prologue_cache
.extra_info
= (struct frame_extra_info
*)
2626 xcalloc (1, sizeof (struct frame_extra_info
));