1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
33 #include "target-float.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
47 #include "observable.h"
50 #include "arch/arm-get-next-pcs.h"
52 #include "gdb/sim-arm.h"
55 #include "coff/internal.h"
58 #include "gdbsupport/vec.h"
61 #include "record-full.h"
64 #include "features/arm/arm-with-m.c"
65 #include "features/arm/arm-with-m-fpa-layout.c"
66 #include "features/arm/arm-with-m-vfp-d16.c"
67 #include "features/arm/arm-with-iwmmxt.c"
68 #include "features/arm/arm-with-vfpv2.c"
69 #include "features/arm/arm-with-vfpv3.c"
70 #include "features/arm/arm-with-neon.c"
73 #include "gdbsupport/selftest.h"
78 /* Macros for setting and testing a bit in a minimal symbol that marks
79 it as Thumb function. The MSB of the minimal symbol's "info" field
80 is used for this purpose.
82 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
83 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_TARGET_FLAG_1 (msym) = 1
88 #define MSYMBOL_IS_SPECIAL(msym) \
89 MSYMBOL_TARGET_FLAG_1 (msym)
91 struct arm_mapping_symbol
96 bool operator< (const arm_mapping_symbol
&other
) const
97 { return this->value
< other
.value
; }
100 typedef std::vector
<arm_mapping_symbol
> arm_mapping_symbol_vec
;
102 struct arm_per_objfile
104 explicit arm_per_objfile (size_t num_sections
)
105 : section_maps (new arm_mapping_symbol_vec
[num_sections
]),
106 section_maps_sorted (new bool[num_sections
] ())
109 DISABLE_COPY_AND_ASSIGN (arm_per_objfile
);
111 /* Information about mapping symbols ($a, $d, $t) in the objfile.
113 The format is an array of vectors of arm_mapping_symbols, there is one
114 vector for each section of the objfile (the array is index by BFD section
117 For each section, the vector of arm_mapping_symbol is sorted by
118 symbol value (address). */
119 std::unique_ptr
<arm_mapping_symbol_vec
[]> section_maps
;
121 /* For each corresponding element of section_maps above, is this vector
123 std::unique_ptr
<bool[]> section_maps_sorted
;
126 /* Per-objfile data used for mapping symbols. */
127 static objfile_key
<arm_per_objfile
> arm_objfile_data_key
;
129 /* The list of available "set arm ..." and "show arm ..." commands. */
130 static struct cmd_list_element
*setarmcmdlist
= NULL
;
131 static struct cmd_list_element
*showarmcmdlist
= NULL
;
133 /* The type of floating-point to use. Keep this in sync with enum
134 arm_float_model, and the help string in _initialize_arm_tdep. */
135 static const char *const fp_model_strings
[] =
145 /* A variable that can be configured by the user. */
146 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
147 static const char *current_fp_model
= "auto";
149 /* The ABI to use. Keep this in sync with arm_abi_kind. */
150 static const char *const arm_abi_strings
[] =
158 /* A variable that can be configured by the user. */
159 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
160 static const char *arm_abi_string
= "auto";
162 /* The execution mode to assume. */
163 static const char *const arm_mode_strings
[] =
171 static const char *arm_fallback_mode_string
= "auto";
172 static const char *arm_force_mode_string
= "auto";
174 /* The standard register names, and all the valid aliases for them. Note
175 that `fp', `sp' and `pc' are not added in this alias list, because they
176 have been added as builtin user registers in
177 std-regs.c:_initialize_frame_reg. */
182 } arm_register_aliases
[] = {
183 /* Basic register numbers. */
200 /* Synonyms (argument and variable registers). */
213 /* Other platform-specific names for r9. */
219 /* Names used by GCC (not listed in the ARM EABI). */
221 /* A special name from the older ATPCS. */
225 static const char *const arm_register_names
[] =
226 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
227 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
228 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
229 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
230 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
231 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
232 "fps", "cpsr" }; /* 24 25 */
234 /* Holds the current set of options to be passed to the disassembler. */
235 static char *arm_disassembler_options
;
237 /* Valid register name styles. */
238 static const char **valid_disassembly_styles
;
240 /* Disassembly style to use. Default to "std" register names. */
241 static const char *disassembly_style
;
243 /* All possible arm target descriptors. */
244 static struct target_desc
*tdesc_arm_list
[ARM_FP_TYPE_INVALID
];
245 static struct target_desc
*tdesc_arm_mprofile_list
[ARM_M_TYPE_INVALID
];
247 /* This is used to keep the bfd arch_info in sync with the disassembly
249 static void set_disassembly_style_sfunc (const char *, int,
250 struct cmd_list_element
*);
251 static void show_disassembly_style_sfunc (struct ui_file
*, int,
252 struct cmd_list_element
*,
255 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
256 readable_regcache
*regcache
,
257 int regnum
, gdb_byte
*buf
);
258 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
259 struct regcache
*regcache
,
260 int regnum
, const gdb_byte
*buf
);
263 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
266 /* get_next_pcs operations. */
267 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
268 arm_get_next_pcs_read_memory_unsigned_integer
,
269 arm_get_next_pcs_syscall_next_pc
,
270 arm_get_next_pcs_addr_bits_remove
,
271 arm_get_next_pcs_is_thumb
,
275 struct arm_prologue_cache
277 /* The stack pointer at the time this frame was created; i.e. the
278 caller's stack pointer when this function was called. It is used
279 to identify this frame. */
282 /* The frame base for this frame is just prev_sp - frame size.
283 FRAMESIZE is the distance from the frame pointer to the
284 initial stack pointer. */
288 /* The register used to hold the frame pointer for this frame. */
291 /* Saved register offsets. */
292 struct trad_frame_saved_reg
*saved_regs
;
295 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
296 CORE_ADDR prologue_start
,
297 CORE_ADDR prologue_end
,
298 struct arm_prologue_cache
*cache
);
300 /* Architecture version for displaced stepping. This effects the behaviour of
301 certain instructions, and really should not be hard-wired. */
303 #define DISPLACED_STEPPING_ARCH_VERSION 5
305 /* Set to true if the 32-bit mode is in use. */
309 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
312 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
314 if (gdbarch_tdep (gdbarch
)->is_m
)
320 /* Determine if the processor is currently executing in Thumb mode. */
323 arm_is_thumb (struct regcache
*regcache
)
326 ULONGEST t_bit
= arm_psr_thumb_bit (regcache
->arch ());
328 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
330 return (cpsr
& t_bit
) != 0;
333 /* Determine if FRAME is executing in Thumb mode. */
336 arm_frame_is_thumb (struct frame_info
*frame
)
339 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
341 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
342 directly (from a signal frame or dummy frame) or by interpreting
343 the saved LR (from a prologue or DWARF frame). So consult it and
344 trust the unwinders. */
345 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
347 return (cpsr
& t_bit
) != 0;
350 /* Search for the mapping symbol covering MEMADDR. If one is found,
351 return its type. Otherwise, return 0. If START is non-NULL,
352 set *START to the location of the mapping symbol. */
355 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
357 struct obj_section
*sec
;
359 /* If there are mapping symbols, consult them. */
360 sec
= find_pc_section (memaddr
);
363 arm_per_objfile
*data
= arm_objfile_data_key
.get (sec
->objfile
);
366 unsigned int section_idx
= sec
->the_bfd_section
->index
;
367 arm_mapping_symbol_vec
&map
368 = data
->section_maps
[section_idx
];
370 /* Sort the vector on first use. */
371 if (!data
->section_maps_sorted
[section_idx
])
373 std::sort (map
.begin (), map
.end ());
374 data
->section_maps_sorted
[section_idx
] = true;
377 struct arm_mapping_symbol map_key
378 = { memaddr
- obj_section_addr (sec
), 0 };
379 arm_mapping_symbol_vec::const_iterator it
380 = std::lower_bound (map
.begin (), map
.end (), map_key
);
382 /* std::lower_bound finds the earliest ordered insertion
383 point. If the symbol at this position starts at this exact
384 address, we use that; otherwise, the preceding
385 mapping symbol covers this address. */
388 if (it
->value
== map_key
.value
)
391 *start
= it
->value
+ obj_section_addr (sec
);
396 if (it
> map
.begin ())
398 arm_mapping_symbol_vec::const_iterator prev_it
402 *start
= prev_it
->value
+ obj_section_addr (sec
);
403 return prev_it
->type
;
411 /* Determine if the program counter specified in MEMADDR is in a Thumb
412 function. This function should be called for addresses unrelated to
413 any executing frame; otherwise, prefer arm_frame_is_thumb. */
416 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
418 struct bound_minimal_symbol sym
;
420 arm_displaced_step_closure
*dsc
421 = ((arm_displaced_step_closure
* )
422 get_displaced_step_closure_by_addr (memaddr
));
424 /* If checking the mode of displaced instruction in copy area, the mode
425 should be determined by instruction on the original address. */
429 fprintf_unfiltered (gdb_stdlog
,
430 "displaced: check mode of %.8lx instead of %.8lx\n",
431 (unsigned long) dsc
->insn_addr
,
432 (unsigned long) memaddr
);
433 memaddr
= dsc
->insn_addr
;
436 /* If bit 0 of the address is set, assume this is a Thumb address. */
437 if (IS_THUMB_ADDR (memaddr
))
440 /* If the user wants to override the symbol table, let him. */
441 if (strcmp (arm_force_mode_string
, "arm") == 0)
443 if (strcmp (arm_force_mode_string
, "thumb") == 0)
446 /* ARM v6-M and v7-M are always in Thumb mode. */
447 if (gdbarch_tdep (gdbarch
)->is_m
)
450 /* If there are mapping symbols, consult them. */
451 type
= arm_find_mapping_symbol (memaddr
, NULL
);
455 /* Thumb functions have a "special" bit set in minimal symbols. */
456 sym
= lookup_minimal_symbol_by_pc (memaddr
);
458 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
460 /* If the user wants to override the fallback mode, let them. */
461 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
463 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
466 /* If we couldn't find any symbol, but we're talking to a running
467 target, then trust the current value of $cpsr. This lets
468 "display/i $pc" always show the correct mode (though if there is
469 a symbol table we will not reach here, so it still may not be
470 displayed in the mode it will be executed). */
471 if (target_has_registers
)
472 return arm_frame_is_thumb (get_current_frame ());
474 /* Otherwise we're out of luck; we assume ARM. */
478 /* Determine if the address specified equals any of these magic return
479 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
482 From ARMv6-M Reference Manual B1.5.8
483 Table B1-5 Exception return behavior
485 EXC_RETURN Return To Return Stack
486 0xFFFFFFF1 Handler mode Main
487 0xFFFFFFF9 Thread mode Main
488 0xFFFFFFFD Thread mode Process
490 From ARMv7-M Reference Manual B1.5.8
491 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
493 EXC_RETURN Return To Return Stack
494 0xFFFFFFF1 Handler mode Main
495 0xFFFFFFF9 Thread mode Main
496 0xFFFFFFFD Thread mode Process
498 Table B1-9 EXC_RETURN definition of exception return behavior, with
501 EXC_RETURN Return To Return Stack Frame Type
502 0xFFFFFFE1 Handler mode Main Extended
503 0xFFFFFFE9 Thread mode Main Extended
504 0xFFFFFFED Thread mode Process Extended
505 0xFFFFFFF1 Handler mode Main Basic
506 0xFFFFFFF9 Thread mode Main Basic
507 0xFFFFFFFD Thread mode Process Basic
509 For more details see "B1.5.8 Exception return behavior"
510 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
513 arm_m_addr_is_magic (CORE_ADDR addr
)
517 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
518 the exception return behavior. */
525 /* Address is magic. */
529 /* Address is not magic. */
534 /* Remove useless bits from addresses in a running program. */
536 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
538 /* On M-profile devices, do not strip the low bit from EXC_RETURN
539 (the magic exception return address). */
540 if (gdbarch_tdep (gdbarch
)->is_m
541 && arm_m_addr_is_magic (val
))
545 return UNMAKE_THUMB_ADDR (val
);
547 return (val
& 0x03fffffc);
550 /* Return 1 if PC is the start of a compiler helper function which
551 can be safely ignored during prologue skipping. IS_THUMB is true
552 if the function is known to be a Thumb function due to the way it
555 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
557 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
558 struct bound_minimal_symbol msym
;
560 msym
= lookup_minimal_symbol_by_pc (pc
);
561 if (msym
.minsym
!= NULL
562 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
563 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
565 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
567 /* The GNU linker's Thumb call stub to foo is named
569 if (strstr (name
, "_from_thumb") != NULL
)
572 /* On soft-float targets, __truncdfsf2 is called to convert promoted
573 arguments to their argument types in non-prototyped
575 if (startswith (name
, "__truncdfsf2"))
577 if (startswith (name
, "__aeabi_d2f"))
580 /* Internal functions related to thread-local storage. */
581 if (startswith (name
, "__tls_get_addr"))
583 if (startswith (name
, "__aeabi_read_tp"))
588 /* If we run against a stripped glibc, we may be unable to identify
589 special functions by name. Check for one important case,
590 __aeabi_read_tp, by comparing the *code* against the default
591 implementation (this is hand-written ARM assembler in glibc). */
594 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
595 == 0xe3e00a0f /* mov r0, #0xffff0fff */
596 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
597 == 0xe240f01f) /* sub pc, r0, #31 */
604 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
605 the first 16-bit of instruction, and INSN2 is the second 16-bit of
607 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
608 ((bits ((insn1), 0, 3) << 12) \
609 | (bits ((insn1), 10, 10) << 11) \
610 | (bits ((insn2), 12, 14) << 8) \
611 | bits ((insn2), 0, 7))
613 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
614 the 32-bit instruction. */
615 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
616 ((bits ((insn), 16, 19) << 12) \
617 | bits ((insn), 0, 11))
619 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
622 thumb_expand_immediate (unsigned int imm
)
624 unsigned int count
= imm
>> 7;
632 return (imm
& 0xff) | ((imm
& 0xff) << 16);
634 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
636 return (imm
& 0xff) | ((imm
& 0xff) << 8)
637 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
640 return (0x80 | (imm
& 0x7f)) << (32 - count
);
643 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
644 epilogue, 0 otherwise. */
647 thumb_instruction_restores_sp (unsigned short insn
)
649 return (insn
== 0x46bd /* mov sp, r7 */
650 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
651 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
654 /* Analyze a Thumb prologue, looking for a recognizable stack frame
655 and frame pointer. Scan until we encounter a store that could
656 clobber the stack frame unexpectedly, or an unknown instruction.
657 Return the last address which is definitely safe to skip for an
658 initial breakpoint. */
661 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
662 CORE_ADDR start
, CORE_ADDR limit
,
663 struct arm_prologue_cache
*cache
)
665 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
666 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
670 CORE_ADDR unrecognized_pc
= 0;
672 for (i
= 0; i
< 16; i
++)
673 regs
[i
] = pv_register (i
, 0);
674 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
676 while (start
< limit
)
680 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
682 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
687 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
690 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
691 whether to save LR (R14). */
692 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
694 /* Calculate offsets of saved R0-R7 and LR. */
695 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
696 if (mask
& (1 << regno
))
698 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
700 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
703 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
705 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
706 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
709 else if (thumb_instruction_restores_sp (insn
))
711 /* Don't scan past the epilogue. */
714 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
715 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
717 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
718 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
719 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
721 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
722 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
723 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
725 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
726 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
727 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
728 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
729 regs
[bits (insn
, 6, 8)]);
730 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
731 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
733 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
734 int rm
= bits (insn
, 3, 6);
735 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
737 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
739 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
740 int src_reg
= (insn
& 0x78) >> 3;
741 regs
[dst_reg
] = regs
[src_reg
];
743 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
745 /* Handle stores to the stack. Normally pushes are used,
746 but with GCC -mtpcs-frame, there may be other stores
747 in the prologue to create the frame. */
748 int regno
= (insn
>> 8) & 0x7;
751 offset
= (insn
& 0xff) << 2;
752 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
754 if (stack
.store_would_trash (addr
))
757 stack
.store (addr
, 4, regs
[regno
]);
759 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
761 int rd
= bits (insn
, 0, 2);
762 int rn
= bits (insn
, 3, 5);
765 offset
= bits (insn
, 6, 10) << 2;
766 addr
= pv_add_constant (regs
[rn
], offset
);
768 if (stack
.store_would_trash (addr
))
771 stack
.store (addr
, 4, regs
[rd
]);
773 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
774 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
775 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
776 /* Ignore stores of argument registers to the stack. */
778 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
779 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
780 /* Ignore block loads from the stack, potentially copying
781 parameters from memory. */
783 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
784 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
785 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
786 /* Similarly ignore single loads from the stack. */
788 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
789 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
790 /* Skip register copies, i.e. saves to another register
791 instead of the stack. */
793 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
794 /* Recognize constant loads; even with small stacks these are necessary
796 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
797 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
799 /* Constant pool loads, for the same reason. */
800 unsigned int constant
;
803 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
804 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
805 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
807 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
809 unsigned short inst2
;
811 inst2
= read_code_unsigned_integer (start
+ 2, 2,
812 byte_order_for_code
);
814 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
816 /* BL, BLX. Allow some special function calls when
817 skipping the prologue; GCC generates these before
818 storing arguments to the stack. */
820 int j1
, j2
, imm1
, imm2
;
822 imm1
= sbits (insn
, 0, 10);
823 imm2
= bits (inst2
, 0, 10);
824 j1
= bit (inst2
, 13);
825 j2
= bit (inst2
, 11);
827 offset
= ((imm1
<< 12) + (imm2
<< 1));
828 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
830 nextpc
= start
+ 4 + offset
;
831 /* For BLX make sure to clear the low bits. */
832 if (bit (inst2
, 12) == 0)
833 nextpc
= nextpc
& 0xfffffffc;
835 if (!skip_prologue_function (gdbarch
, nextpc
,
836 bit (inst2
, 12) != 0))
840 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
842 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
844 pv_t addr
= regs
[bits (insn
, 0, 3)];
847 if (stack
.store_would_trash (addr
))
850 /* Calculate offsets of saved registers. */
851 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
852 if (inst2
& (1 << regno
))
854 addr
= pv_add_constant (addr
, -4);
855 stack
.store (addr
, 4, regs
[regno
]);
859 regs
[bits (insn
, 0, 3)] = addr
;
862 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
864 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
866 int regno1
= bits (inst2
, 12, 15);
867 int regno2
= bits (inst2
, 8, 11);
868 pv_t addr
= regs
[bits (insn
, 0, 3)];
870 offset
= inst2
& 0xff;
872 addr
= pv_add_constant (addr
, offset
);
874 addr
= pv_add_constant (addr
, -offset
);
876 if (stack
.store_would_trash (addr
))
879 stack
.store (addr
, 4, regs
[regno1
]);
880 stack
.store (pv_add_constant (addr
, 4),
884 regs
[bits (insn
, 0, 3)] = addr
;
887 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
888 && (inst2
& 0x0c00) == 0x0c00
889 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
891 int regno
= bits (inst2
, 12, 15);
892 pv_t addr
= regs
[bits (insn
, 0, 3)];
894 offset
= inst2
& 0xff;
896 addr
= pv_add_constant (addr
, offset
);
898 addr
= pv_add_constant (addr
, -offset
);
900 if (stack
.store_would_trash (addr
))
903 stack
.store (addr
, 4, regs
[regno
]);
906 regs
[bits (insn
, 0, 3)] = addr
;
909 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
910 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
912 int regno
= bits (inst2
, 12, 15);
915 offset
= inst2
& 0xfff;
916 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
918 if (stack
.store_would_trash (addr
))
921 stack
.store (addr
, 4, regs
[regno
]);
924 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
925 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
926 /* Ignore stores of argument registers to the stack. */
929 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
930 && (inst2
& 0x0d00) == 0x0c00
931 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
932 /* Ignore stores of argument registers to the stack. */
935 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
937 && (inst2
& 0x8000) == 0x0000
938 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
939 /* Ignore block loads from the stack, potentially copying
940 parameters from memory. */
943 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
945 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
946 /* Similarly ignore dual loads from the stack. */
949 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
950 && (inst2
& 0x0d00) == 0x0c00
951 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
952 /* Similarly ignore single loads from the stack. */
955 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
956 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
957 /* Similarly ignore single loads from the stack. */
960 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
961 && (inst2
& 0x8000) == 0x0000)
963 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
964 | (bits (inst2
, 12, 14) << 8)
965 | bits (inst2
, 0, 7));
967 regs
[bits (inst2
, 8, 11)]
968 = pv_add_constant (regs
[bits (insn
, 0, 3)],
969 thumb_expand_immediate (imm
));
972 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
973 && (inst2
& 0x8000) == 0x0000)
975 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
976 | (bits (inst2
, 12, 14) << 8)
977 | bits (inst2
, 0, 7));
979 regs
[bits (inst2
, 8, 11)]
980 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
983 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
984 && (inst2
& 0x8000) == 0x0000)
986 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
987 | (bits (inst2
, 12, 14) << 8)
988 | bits (inst2
, 0, 7));
990 regs
[bits (inst2
, 8, 11)]
991 = pv_add_constant (regs
[bits (insn
, 0, 3)],
992 - (CORE_ADDR
) thumb_expand_immediate (imm
));
995 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
996 && (inst2
& 0x8000) == 0x0000)
998 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
999 | (bits (inst2
, 12, 14) << 8)
1000 | bits (inst2
, 0, 7));
1002 regs
[bits (inst2
, 8, 11)]
1003 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1006 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1008 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1009 | (bits (inst2
, 12, 14) << 8)
1010 | bits (inst2
, 0, 7));
1012 regs
[bits (inst2
, 8, 11)]
1013 = pv_constant (thumb_expand_immediate (imm
));
1016 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1019 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1021 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1024 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1025 && (inst2
& 0xf0f0) == 0)
1027 int dst_reg
= (inst2
& 0x0f00) >> 8;
1028 int src_reg
= inst2
& 0xf;
1029 regs
[dst_reg
] = regs
[src_reg
];
1032 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1034 /* Constant pool loads. */
1035 unsigned int constant
;
1038 offset
= bits (inst2
, 0, 11);
1040 loc
= start
+ 4 + offset
;
1042 loc
= start
+ 4 - offset
;
1044 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1045 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1048 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1050 /* Constant pool loads. */
1051 unsigned int constant
;
1054 offset
= bits (inst2
, 0, 7) << 2;
1056 loc
= start
+ 4 + offset
;
1058 loc
= start
+ 4 - offset
;
1060 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1061 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1063 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1064 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1067 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1069 /* Don't scan past anything that might change control flow. */
1074 /* The optimizer might shove anything into the prologue,
1075 so we just skip what we don't recognize. */
1076 unrecognized_pc
= start
;
1081 else if (thumb_instruction_changes_pc (insn
))
1083 /* Don't scan past anything that might change control flow. */
1088 /* The optimizer might shove anything into the prologue,
1089 so we just skip what we don't recognize. */
1090 unrecognized_pc
= start
;
1097 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1098 paddress (gdbarch
, start
));
1100 if (unrecognized_pc
== 0)
1101 unrecognized_pc
= start
;
1104 return unrecognized_pc
;
1106 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1108 /* Frame pointer is fp. Frame size is constant. */
1109 cache
->framereg
= ARM_FP_REGNUM
;
1110 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1112 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1114 /* Frame pointer is r7. Frame size is constant. */
1115 cache
->framereg
= THUMB_FP_REGNUM
;
1116 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1120 /* Try the stack pointer... this is a bit desperate. */
1121 cache
->framereg
= ARM_SP_REGNUM
;
1122 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1125 for (i
= 0; i
< 16; i
++)
1126 if (stack
.find_reg (gdbarch
, i
, &offset
))
1127 cache
->saved_regs
[i
].addr
= offset
;
1129 return unrecognized_pc
;
1133 /* Try to analyze the instructions starting from PC, which load symbol
1134 __stack_chk_guard. Return the address of instruction after loading this
1135 symbol, set the dest register number to *BASEREG, and set the size of
1136 instructions for loading symbol in OFFSET. Return 0 if instructions are
1140 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1141 unsigned int *destreg
, int *offset
)
1143 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1144 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1145 unsigned int low
, high
, address
;
1150 unsigned short insn1
1151 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1153 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1155 *destreg
= bits (insn1
, 8, 10);
1157 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1158 address
= read_memory_unsigned_integer (address
, 4,
1159 byte_order_for_code
);
1161 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1163 unsigned short insn2
1164 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1166 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1169 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1171 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1173 /* movt Rd, #const */
1174 if ((insn1
& 0xfbc0) == 0xf2c0)
1176 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1177 *destreg
= bits (insn2
, 8, 11);
1179 address
= (high
<< 16 | low
);
1186 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1188 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1190 address
= bits (insn
, 0, 11) + pc
+ 8;
1191 address
= read_memory_unsigned_integer (address
, 4,
1192 byte_order_for_code
);
1194 *destreg
= bits (insn
, 12, 15);
1197 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1199 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1202 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1204 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1206 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1207 *destreg
= bits (insn
, 12, 15);
1209 address
= (high
<< 16 | low
);
1217 /* Try to skip a sequence of instructions used for stack protector. If PC
1218 points to the first instruction of this sequence, return the address of
1219 first instruction after this sequence, otherwise, return original PC.
1221 On arm, this sequence of instructions is composed of mainly three steps,
1222 Step 1: load symbol __stack_chk_guard,
1223 Step 2: load from address of __stack_chk_guard,
1224 Step 3: store it to somewhere else.
1226 Usually, instructions on step 2 and step 3 are the same on various ARM
1227 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1228 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1229 instructions in step 1 vary from different ARM architectures. On ARMv7,
1232 movw Rn, #:lower16:__stack_chk_guard
1233 movt Rn, #:upper16:__stack_chk_guard
1240 .word __stack_chk_guard
1242 Since ldr/str is a very popular instruction, we can't use them as
1243 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1244 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1245 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1248 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1250 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1251 unsigned int basereg
;
1252 struct bound_minimal_symbol stack_chk_guard
;
1254 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1257 /* Try to parse the instructions in Step 1. */
1258 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1263 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1264 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1265 Otherwise, this sequence cannot be for stack protector. */
1266 if (stack_chk_guard
.minsym
== NULL
1267 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1272 unsigned int destreg
;
1274 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1276 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1277 if ((insn
& 0xf800) != 0x6800)
1279 if (bits (insn
, 3, 5) != basereg
)
1281 destreg
= bits (insn
, 0, 2);
1283 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1284 byte_order_for_code
);
1285 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1286 if ((insn
& 0xf800) != 0x6000)
1288 if (destreg
!= bits (insn
, 0, 2))
1293 unsigned int destreg
;
1295 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1297 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1298 if ((insn
& 0x0e500000) != 0x04100000)
1300 if (bits (insn
, 16, 19) != basereg
)
1302 destreg
= bits (insn
, 12, 15);
1303 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1304 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1305 4, byte_order_for_code
);
1306 if ((insn
& 0x0e500000) != 0x04000000)
1308 if (bits (insn
, 12, 15) != destreg
)
1311 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1314 return pc
+ offset
+ 4;
1316 return pc
+ offset
+ 8;
1319 /* Advance the PC across any function entry prologue instructions to
1320 reach some "real" code.
1322 The APCS (ARM Procedure Call Standard) defines the following
1326 [stmfd sp!, {a1,a2,a3,a4}]
1327 stmfd sp!, {...,fp,ip,lr,pc}
1328 [stfe f7, [sp, #-12]!]
1329 [stfe f6, [sp, #-12]!]
1330 [stfe f5, [sp, #-12]!]
1331 [stfe f4, [sp, #-12]!]
1332 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1335 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1337 CORE_ADDR func_addr
, limit_pc
;
1339 /* See if we can determine the end of the prologue via the symbol table.
1340 If so, then return either PC, or the PC after the prologue, whichever
1342 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1344 CORE_ADDR post_prologue_pc
1345 = skip_prologue_using_sal (gdbarch
, func_addr
);
1346 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1348 if (post_prologue_pc
)
1350 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1353 /* GCC always emits a line note before the prologue and another
1354 one after, even if the two are at the same address or on the
1355 same line. Take advantage of this so that we do not need to
1356 know every instruction that might appear in the prologue. We
1357 will have producer information for most binaries; if it is
1358 missing (e.g. for -gstabs), assuming the GNU tools. */
1359 if (post_prologue_pc
1361 || COMPUNIT_PRODUCER (cust
) == NULL
1362 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1363 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1364 return post_prologue_pc
;
1366 if (post_prologue_pc
!= 0)
1368 CORE_ADDR analyzed_limit
;
1370 /* For non-GCC compilers, make sure the entire line is an
1371 acceptable prologue; GDB will round this function's
1372 return value up to the end of the following line so we
1373 can not skip just part of a line (and we do not want to).
1375 RealView does not treat the prologue specially, but does
1376 associate prologue code with the opening brace; so this
1377 lets us skip the first line if we think it is the opening
1379 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1380 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1381 post_prologue_pc
, NULL
);
1383 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1384 post_prologue_pc
, NULL
);
1386 if (analyzed_limit
!= post_prologue_pc
)
1389 return post_prologue_pc
;
1393 /* Can't determine prologue from the symbol table, need to examine
1396 /* Find an upper limit on the function prologue using the debug
1397 information. If the debug information could not be used to provide
1398 that bound, then use an arbitrary large number as the upper bound. */
1399 /* Like arm_scan_prologue, stop no later than pc + 64. */
1400 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1402 limit_pc
= pc
+ 64; /* Magic. */
1405 /* Check if this is Thumb code. */
1406 if (arm_pc_is_thumb (gdbarch
, pc
))
1407 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1409 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1413 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1414 This function decodes a Thumb function prologue to determine:
1415 1) the size of the stack frame
1416 2) which registers are saved on it
1417 3) the offsets of saved regs
1418 4) the offset from the stack pointer to the frame pointer
1420 A typical Thumb function prologue would create this stack frame
1421 (offsets relative to FP)
1422 old SP -> 24 stack parameters
1425 R7 -> 0 local variables (16 bytes)
1426 SP -> -12 additional stack space (12 bytes)
1427 The frame size would thus be 36 bytes, and the frame offset would be
1428 12 bytes. The frame register is R7.
1430 The comments for thumb_skip_prolog() describe the algorithm we use
1431 to detect the end of the prolog. */
1435 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1436 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1438 CORE_ADDR prologue_start
;
1439 CORE_ADDR prologue_end
;
1441 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1444 /* See comment in arm_scan_prologue for an explanation of
1446 if (prologue_end
> prologue_start
+ 64)
1448 prologue_end
= prologue_start
+ 64;
1452 /* We're in the boondocks: we have no idea where the start of the
1456 prologue_end
= std::min (prologue_end
, prev_pc
);
1458 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1461 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1465 arm_instruction_restores_sp (unsigned int insn
)
1467 if (bits (insn
, 28, 31) != INST_NV
)
1469 if ((insn
& 0x0df0f000) == 0x0080d000
1470 /* ADD SP (register or immediate). */
1471 || (insn
& 0x0df0f000) == 0x0040d000
1472 /* SUB SP (register or immediate). */
1473 || (insn
& 0x0ffffff0) == 0x01a0d000
1475 || (insn
& 0x0fff0000) == 0x08bd0000
1477 || (insn
& 0x0fff0000) == 0x049d0000)
1478 /* POP of a single register. */
1485 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1486 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1487 fill it in. Return the first address not recognized as a prologue
1490 We recognize all the instructions typically found in ARM prologues,
1491 plus harmless instructions which can be skipped (either for analysis
1492 purposes, or a more restrictive set that can be skipped when finding
1493 the end of the prologue). */
1496 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1497 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1498 struct arm_prologue_cache
*cache
)
1500 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1502 CORE_ADDR offset
, current_pc
;
1503 pv_t regs
[ARM_FPS_REGNUM
];
1504 CORE_ADDR unrecognized_pc
= 0;
1506 /* Search the prologue looking for instructions that set up the
1507 frame pointer, adjust the stack pointer, and save registers.
1509 Be careful, however, and if it doesn't look like a prologue,
1510 don't try to scan it. If, for instance, a frameless function
1511 begins with stmfd sp!, then we will tell ourselves there is
1512 a frame, which will confuse stack traceback, as well as "finish"
1513 and other operations that rely on a knowledge of the stack
1516 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1517 regs
[regno
] = pv_register (regno
, 0);
1518 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1520 for (current_pc
= prologue_start
;
1521 current_pc
< prologue_end
;
1525 = read_code_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1527 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1529 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1532 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1533 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1535 unsigned imm
= insn
& 0xff; /* immediate value */
1536 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1537 int rd
= bits (insn
, 12, 15);
1538 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1539 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1542 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1543 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1545 unsigned imm
= insn
& 0xff; /* immediate value */
1546 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1547 int rd
= bits (insn
, 12, 15);
1548 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1549 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1552 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1555 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1557 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1558 stack
.store (regs
[ARM_SP_REGNUM
], 4,
1559 regs
[bits (insn
, 12, 15)]);
1562 else if ((insn
& 0xffff0000) == 0xe92d0000)
1563 /* stmfd sp!, {..., fp, ip, lr, pc}
1565 stmfd sp!, {a1, a2, a3, a4} */
1567 int mask
= insn
& 0xffff;
1569 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1572 /* Calculate offsets of saved registers. */
1573 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1574 if (mask
& (1 << regno
))
1577 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1578 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1581 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1582 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1583 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1585 /* No need to add this to saved_regs -- it's just an arg reg. */
1588 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1589 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1590 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1592 /* No need to add this to saved_regs -- it's just an arg reg. */
1595 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1597 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1599 /* No need to add this to saved_regs -- it's just arg regs. */
1602 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1604 unsigned imm
= insn
& 0xff; /* immediate value */
1605 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1606 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1607 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1609 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1611 unsigned imm
= insn
& 0xff; /* immediate value */
1612 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1613 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1614 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1616 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1618 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1620 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1623 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1624 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1625 stack
.store (regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1627 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1629 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1631 int n_saved_fp_regs
;
1632 unsigned int fp_start_reg
, fp_bound_reg
;
1634 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1637 if ((insn
& 0x800) == 0x800) /* N0 is set */
1639 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1640 n_saved_fp_regs
= 3;
1642 n_saved_fp_regs
= 1;
1646 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1647 n_saved_fp_regs
= 2;
1649 n_saved_fp_regs
= 4;
1652 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1653 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1654 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1656 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1657 stack
.store (regs
[ARM_SP_REGNUM
], 12,
1658 regs
[fp_start_reg
++]);
1661 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1663 /* Allow some special function calls when skipping the
1664 prologue; GCC generates these before storing arguments to
1666 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1668 if (skip_prologue_function (gdbarch
, dest
, 0))
1673 else if ((insn
& 0xf0000000) != 0xe0000000)
1674 break; /* Condition not true, exit early. */
1675 else if (arm_instruction_changes_pc (insn
))
1676 /* Don't scan past anything that might change control flow. */
1678 else if (arm_instruction_restores_sp (insn
))
1680 /* Don't scan past the epilogue. */
1683 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1684 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1685 /* Ignore block loads from the stack, potentially copying
1686 parameters from memory. */
1688 else if ((insn
& 0xfc500000) == 0xe4100000
1689 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1690 /* Similarly ignore single loads from the stack. */
1692 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1693 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1694 register instead of the stack. */
1698 /* The optimizer might shove anything into the prologue, if
1699 we build up cache (cache != NULL) from scanning prologue,
1700 we just skip what we don't recognize and scan further to
1701 make cache as complete as possible. However, if we skip
1702 prologue, we'll stop immediately on unrecognized
1704 unrecognized_pc
= current_pc
;
1712 if (unrecognized_pc
== 0)
1713 unrecognized_pc
= current_pc
;
1717 int framereg
, framesize
;
1719 /* The frame size is just the distance from the frame register
1720 to the original stack pointer. */
1721 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1723 /* Frame pointer is fp. */
1724 framereg
= ARM_FP_REGNUM
;
1725 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1729 /* Try the stack pointer... this is a bit desperate. */
1730 framereg
= ARM_SP_REGNUM
;
1731 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1734 cache
->framereg
= framereg
;
1735 cache
->framesize
= framesize
;
1737 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1738 if (stack
.find_reg (gdbarch
, regno
, &offset
))
1739 cache
->saved_regs
[regno
].addr
= offset
;
1743 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1744 paddress (gdbarch
, unrecognized_pc
));
1746 return unrecognized_pc
;
1750 arm_scan_prologue (struct frame_info
*this_frame
,
1751 struct arm_prologue_cache
*cache
)
1753 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1754 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1755 CORE_ADDR prologue_start
, prologue_end
;
1756 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1757 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1759 /* Assume there is no frame until proven otherwise. */
1760 cache
->framereg
= ARM_SP_REGNUM
;
1761 cache
->framesize
= 0;
1763 /* Check for Thumb prologue. */
1764 if (arm_frame_is_thumb (this_frame
))
1766 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1770 /* Find the function prologue. If we can't find the function in
1771 the symbol table, peek in the stack frame to find the PC. */
1772 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1775 /* One way to find the end of the prologue (which works well
1776 for unoptimized code) is to do the following:
1778 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1781 prologue_end = prev_pc;
1782 else if (sal.end < prologue_end)
1783 prologue_end = sal.end;
1785 This mechanism is very accurate so long as the optimizer
1786 doesn't move any instructions from the function body into the
1787 prologue. If this happens, sal.end will be the last
1788 instruction in the first hunk of prologue code just before
1789 the first instruction that the scheduler has moved from
1790 the body to the prologue.
1792 In order to make sure that we scan all of the prologue
1793 instructions, we use a slightly less accurate mechanism which
1794 may scan more than necessary. To help compensate for this
1795 lack of accuracy, the prologue scanning loop below contains
1796 several clauses which'll cause the loop to terminate early if
1797 an implausible prologue instruction is encountered.
1803 is a suitable endpoint since it accounts for the largest
1804 possible prologue plus up to five instructions inserted by
1807 if (prologue_end
> prologue_start
+ 64)
1809 prologue_end
= prologue_start
+ 64; /* See above. */
1814 /* We have no symbol information. Our only option is to assume this
1815 function has a standard stack frame and the normal frame register.
1816 Then, we can find the value of our frame pointer on entrance to
1817 the callee (or at the present moment if this is the innermost frame).
1818 The value stored there should be the address of the stmfd + 8. */
1819 CORE_ADDR frame_loc
;
1820 ULONGEST return_value
;
1822 /* AAPCS does not use a frame register, so we can abort here. */
1823 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_AAPCS
)
1826 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1827 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
1832 prologue_start
= gdbarch_addr_bits_remove
1833 (gdbarch
, return_value
) - 8;
1834 prologue_end
= prologue_start
+ 64; /* See above. */
1838 if (prev_pc
< prologue_end
)
1839 prologue_end
= prev_pc
;
1841 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1844 static struct arm_prologue_cache
*
1845 arm_make_prologue_cache (struct frame_info
*this_frame
)
1848 struct arm_prologue_cache
*cache
;
1849 CORE_ADDR unwound_fp
;
1851 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1852 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1854 arm_scan_prologue (this_frame
, cache
);
1856 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1857 if (unwound_fp
== 0)
1860 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1862 /* Calculate actual addresses of saved registers using offsets
1863 determined by arm_scan_prologue. */
1864 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1865 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1866 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1871 /* Implementation of the stop_reason hook for arm_prologue frames. */
1873 static enum unwind_stop_reason
1874 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1877 struct arm_prologue_cache
*cache
;
1880 if (*this_cache
== NULL
)
1881 *this_cache
= arm_make_prologue_cache (this_frame
);
1882 cache
= (struct arm_prologue_cache
*) *this_cache
;
1884 /* This is meant to halt the backtrace at "_start". */
1885 pc
= get_frame_pc (this_frame
);
1886 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1887 return UNWIND_OUTERMOST
;
1889 /* If we've hit a wall, stop. */
1890 if (cache
->prev_sp
== 0)
1891 return UNWIND_OUTERMOST
;
1893 return UNWIND_NO_REASON
;
1896 /* Our frame ID for a normal frame is the current function's starting PC
1897 and the caller's SP when we were called. */
1900 arm_prologue_this_id (struct frame_info
*this_frame
,
1902 struct frame_id
*this_id
)
1904 struct arm_prologue_cache
*cache
;
1908 if (*this_cache
== NULL
)
1909 *this_cache
= arm_make_prologue_cache (this_frame
);
1910 cache
= (struct arm_prologue_cache
*) *this_cache
;
1912 /* Use function start address as part of the frame ID. If we cannot
1913 identify the start address (due to missing symbol information),
1914 fall back to just using the current PC. */
1915 pc
= get_frame_pc (this_frame
);
1916 func
= get_frame_func (this_frame
);
1920 id
= frame_id_build (cache
->prev_sp
, func
);
1924 static struct value
*
1925 arm_prologue_prev_register (struct frame_info
*this_frame
,
1929 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1930 struct arm_prologue_cache
*cache
;
1932 if (*this_cache
== NULL
)
1933 *this_cache
= arm_make_prologue_cache (this_frame
);
1934 cache
= (struct arm_prologue_cache
*) *this_cache
;
1936 /* If we are asked to unwind the PC, then we need to return the LR
1937 instead. The prologue may save PC, but it will point into this
1938 frame's prologue, not the next frame's resume location. Also
1939 strip the saved T bit. A valid LR may have the low bit set, but
1940 a valid PC never does. */
1941 if (prev_regnum
== ARM_PC_REGNUM
)
1945 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1946 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1947 arm_addr_bits_remove (gdbarch
, lr
));
1950 /* SP is generally not saved to the stack, but this frame is
1951 identified by the next frame's stack pointer at the time of the call.
1952 The value was already reconstructed into PREV_SP. */
1953 if (prev_regnum
== ARM_SP_REGNUM
)
1954 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1956 /* The CPSR may have been changed by the call instruction and by the
1957 called function. The only bit we can reconstruct is the T bit,
1958 by checking the low bit of LR as of the call. This is a reliable
1959 indicator of Thumb-ness except for some ARM v4T pre-interworking
1960 Thumb code, which could get away with a clear low bit as long as
1961 the called function did not use bx. Guess that all other
1962 bits are unchanged; the condition flags are presumably lost,
1963 but the processor status is likely valid. */
1964 if (prev_regnum
== ARM_PS_REGNUM
)
1967 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1969 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1970 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1971 if (IS_THUMB_ADDR (lr
))
1975 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1978 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1982 struct frame_unwind arm_prologue_unwind
= {
1984 arm_prologue_unwind_stop_reason
,
1985 arm_prologue_this_id
,
1986 arm_prologue_prev_register
,
1988 default_frame_sniffer
1991 /* Maintain a list of ARM exception table entries per objfile, similar to the
1992 list of mapping symbols. We only cache entries for standard ARM-defined
1993 personality routines; the cache will contain only the frame unwinding
1994 instructions associated with the entry (not the descriptors). */
1996 struct arm_exidx_entry
2001 bool operator< (const arm_exidx_entry
&other
) const
2003 return addr
< other
.addr
;
2007 struct arm_exidx_data
2009 std::vector
<std::vector
<arm_exidx_entry
>> section_maps
;
2012 static const struct objfile_key
<arm_exidx_data
> arm_exidx_data_key
;
2014 static struct obj_section
*
2015 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2017 struct obj_section
*osect
;
2019 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2020 if (bfd_get_section_flags (objfile
->obfd
,
2021 osect
->the_bfd_section
) & SEC_ALLOC
)
2023 bfd_vma start
, size
;
2024 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2025 size
= bfd_get_section_size (osect
->the_bfd_section
);
2027 if (start
<= vma
&& vma
< start
+ size
)
2034 /* Parse contents of exception table and exception index sections
2035 of OBJFILE, and fill in the exception table entry cache.
2037 For each entry that refers to a standard ARM-defined personality
2038 routine, extract the frame unwinding instructions (from either
2039 the index or the table section). The unwinding instructions
2041 - extracting them from the rest of the table data
2042 - converting to host endianness
2043 - appending the implicit 0xb0 ("Finish") code
2045 The extracted and normalized instructions are stored for later
2046 retrieval by the arm_find_exidx_entry routine. */
2049 arm_exidx_new_objfile (struct objfile
*objfile
)
2051 struct arm_exidx_data
*data
;
2052 asection
*exidx
, *extab
;
2053 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2056 /* If we've already touched this file, do nothing. */
2057 if (!objfile
|| arm_exidx_data_key
.get (objfile
) != NULL
)
2060 /* Read contents of exception table and index. */
2061 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2062 gdb::byte_vector exidx_data
;
2065 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2066 exidx_data
.resize (bfd_get_section_size (exidx
));
2068 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2069 exidx_data
.data (), 0,
2070 exidx_data
.size ()))
2074 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2075 gdb::byte_vector extab_data
;
2078 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2079 extab_data
.resize (bfd_get_section_size (extab
));
2081 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2082 extab_data
.data (), 0,
2083 extab_data
.size ()))
2087 /* Allocate exception table data structure. */
2088 data
= arm_exidx_data_key
.emplace (objfile
);
2089 data
->section_maps
.resize (objfile
->obfd
->section_count
);
2091 /* Fill in exception table. */
2092 for (i
= 0; i
< exidx_data
.size () / 8; i
++)
2094 struct arm_exidx_entry new_exidx_entry
;
2095 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
.data () + i
* 8);
2096 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
,
2097 exidx_data
.data () + i
* 8 + 4);
2098 bfd_vma addr
= 0, word
= 0;
2099 int n_bytes
= 0, n_words
= 0;
2100 struct obj_section
*sec
;
2101 gdb_byte
*entry
= NULL
;
2103 /* Extract address of start of function. */
2104 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2105 idx
+= exidx_vma
+ i
* 8;
2107 /* Find section containing function and compute section offset. */
2108 sec
= arm_obj_section_from_vma (objfile
, idx
);
2111 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2113 /* Determine address of exception table entry. */
2116 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2118 else if ((val
& 0xff000000) == 0x80000000)
2120 /* Exception table entry embedded in .ARM.exidx
2121 -- must be short form. */
2125 else if (!(val
& 0x80000000))
2127 /* Exception table entry in .ARM.extab. */
2128 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2129 addr
+= exidx_vma
+ i
* 8 + 4;
2131 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_data
.size ())
2133 word
= bfd_h_get_32 (objfile
->obfd
,
2134 extab_data
.data () + addr
- extab_vma
);
2137 if ((word
& 0xff000000) == 0x80000000)
2142 else if ((word
& 0xff000000) == 0x81000000
2143 || (word
& 0xff000000) == 0x82000000)
2147 n_words
= ((word
>> 16) & 0xff);
2149 else if (!(word
& 0x80000000))
2152 struct obj_section
*pers_sec
;
2153 int gnu_personality
= 0;
2155 /* Custom personality routine. */
2156 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2157 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2159 /* Check whether we've got one of the variants of the
2160 GNU personality routines. */
2161 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2164 static const char *personality
[] =
2166 "__gcc_personality_v0",
2167 "__gxx_personality_v0",
2168 "__gcj_personality_v0",
2169 "__gnu_objc_personality_v0",
2173 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2176 for (k
= 0; personality
[k
]; k
++)
2177 if (lookup_minimal_symbol_by_pc_name
2178 (pc
, personality
[k
], objfile
))
2180 gnu_personality
= 1;
2185 /* If so, the next word contains a word count in the high
2186 byte, followed by the same unwind instructions as the
2187 pre-defined forms. */
2189 && addr
+ 4 <= extab_vma
+ extab_data
.size ())
2191 word
= bfd_h_get_32 (objfile
->obfd
,
2193 + addr
- extab_vma
));
2196 n_words
= ((word
>> 24) & 0xff);
2202 /* Sanity check address. */
2204 if (addr
< extab_vma
2205 || addr
+ 4 * n_words
> extab_vma
+ extab_data
.size ())
2206 n_words
= n_bytes
= 0;
2208 /* The unwind instructions reside in WORD (only the N_BYTES least
2209 significant bytes are valid), followed by N_WORDS words in the
2210 extab section starting at ADDR. */
2211 if (n_bytes
|| n_words
)
2214 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2215 n_bytes
+ n_words
* 4 + 1);
2218 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2222 word
= bfd_h_get_32 (objfile
->obfd
,
2223 extab_data
.data () + addr
- extab_vma
);
2226 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2227 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2228 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2229 *p
++ = (gdb_byte
) (word
& 0xff);
2232 /* Implied "Finish" to terminate the list. */
2236 /* Push entry onto vector. They are guaranteed to always
2237 appear in order of increasing addresses. */
2238 new_exidx_entry
.addr
= idx
;
2239 new_exidx_entry
.entry
= entry
;
2240 data
->section_maps
[sec
->the_bfd_section
->index
].push_back
2245 /* Search for the exception table entry covering MEMADDR. If one is found,
2246 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2247 set *START to the start of the region covered by this entry. */
2250 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2252 struct obj_section
*sec
;
2254 sec
= find_pc_section (memaddr
);
2257 struct arm_exidx_data
*data
;
2258 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2260 data
= arm_exidx_data_key
.get (sec
->objfile
);
2263 std::vector
<arm_exidx_entry
> &map
2264 = data
->section_maps
[sec
->the_bfd_section
->index
];
2267 auto idx
= std::lower_bound (map
.begin (), map
.end (), map_key
);
2269 /* std::lower_bound finds the earliest ordered insertion
2270 point. If the following symbol starts at this exact
2271 address, we use that; otherwise, the preceding
2272 exception table entry covers this address. */
2273 if (idx
< map
.end ())
2275 if (idx
->addr
== map_key
.addr
)
2278 *start
= idx
->addr
+ obj_section_addr (sec
);
2283 if (idx
> map
.begin ())
2287 *start
= idx
->addr
+ obj_section_addr (sec
);
2297 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2298 instruction list from the ARM exception table entry ENTRY, allocate and
2299 return a prologue cache structure describing how to unwind this frame.
2301 Return NULL if the unwinding instruction list contains a "spare",
2302 "reserved" or "refuse to unwind" instruction as defined in section
2303 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2304 for the ARM Architecture" document. */
2306 static struct arm_prologue_cache
*
2307 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2312 struct arm_prologue_cache
*cache
;
2313 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2314 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2320 /* Whenever we reload SP, we actually have to retrieve its
2321 actual value in the current frame. */
2324 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2326 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2327 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2331 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2332 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2338 /* Decode next unwind instruction. */
2341 if ((insn
& 0xc0) == 0)
2343 int offset
= insn
& 0x3f;
2344 vsp
+= (offset
<< 2) + 4;
2346 else if ((insn
& 0xc0) == 0x40)
2348 int offset
= insn
& 0x3f;
2349 vsp
-= (offset
<< 2) + 4;
2351 else if ((insn
& 0xf0) == 0x80)
2353 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2356 /* The special case of an all-zero mask identifies
2357 "Refuse to unwind". We return NULL to fall back
2358 to the prologue analyzer. */
2362 /* Pop registers r4..r15 under mask. */
2363 for (i
= 0; i
< 12; i
++)
2364 if (mask
& (1 << i
))
2366 cache
->saved_regs
[4 + i
].addr
= vsp
;
2370 /* Special-case popping SP -- we need to reload vsp. */
2371 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2374 else if ((insn
& 0xf0) == 0x90)
2376 int reg
= insn
& 0xf;
2378 /* Reserved cases. */
2379 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2382 /* Set SP from another register and mark VSP for reload. */
2383 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2386 else if ((insn
& 0xf0) == 0xa0)
2388 int count
= insn
& 0x7;
2389 int pop_lr
= (insn
& 0x8) != 0;
2392 /* Pop r4..r[4+count]. */
2393 for (i
= 0; i
<= count
; i
++)
2395 cache
->saved_regs
[4 + i
].addr
= vsp
;
2399 /* If indicated by flag, pop LR as well. */
2402 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2406 else if (insn
== 0xb0)
2408 /* We could only have updated PC by popping into it; if so, it
2409 will show up as address. Otherwise, copy LR into PC. */
2410 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2411 cache
->saved_regs
[ARM_PC_REGNUM
]
2412 = cache
->saved_regs
[ARM_LR_REGNUM
];
2417 else if (insn
== 0xb1)
2419 int mask
= *entry
++;
2422 /* All-zero mask and mask >= 16 is "spare". */
2423 if (mask
== 0 || mask
>= 16)
2426 /* Pop r0..r3 under mask. */
2427 for (i
= 0; i
< 4; i
++)
2428 if (mask
& (1 << i
))
2430 cache
->saved_regs
[i
].addr
= vsp
;
2434 else if (insn
== 0xb2)
2436 ULONGEST offset
= 0;
2441 offset
|= (*entry
& 0x7f) << shift
;
2444 while (*entry
++ & 0x80);
2446 vsp
+= 0x204 + (offset
<< 2);
2448 else if (insn
== 0xb3)
2450 int start
= *entry
>> 4;
2451 int count
= (*entry
++) & 0xf;
2454 /* Only registers D0..D15 are valid here. */
2455 if (start
+ count
>= 16)
2458 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2459 for (i
= 0; i
<= count
; i
++)
2461 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2465 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2468 else if ((insn
& 0xf8) == 0xb8)
2470 int count
= insn
& 0x7;
2473 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2474 for (i
= 0; i
<= count
; i
++)
2476 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2480 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2483 else if (insn
== 0xc6)
2485 int start
= *entry
>> 4;
2486 int count
= (*entry
++) & 0xf;
2489 /* Only registers WR0..WR15 are valid. */
2490 if (start
+ count
>= 16)
2493 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2494 for (i
= 0; i
<= count
; i
++)
2496 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2500 else if (insn
== 0xc7)
2502 int mask
= *entry
++;
2505 /* All-zero mask and mask >= 16 is "spare". */
2506 if (mask
== 0 || mask
>= 16)
2509 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2510 for (i
= 0; i
< 4; i
++)
2511 if (mask
& (1 << i
))
2513 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2517 else if ((insn
& 0xf8) == 0xc0)
2519 int count
= insn
& 0x7;
2522 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2523 for (i
= 0; i
<= count
; i
++)
2525 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2529 else if (insn
== 0xc8)
2531 int start
= *entry
>> 4;
2532 int count
= (*entry
++) & 0xf;
2535 /* Only registers D0..D31 are valid. */
2536 if (start
+ count
>= 16)
2539 /* Pop VFP double-precision registers
2540 D[16+start]..D[16+start+count]. */
2541 for (i
= 0; i
<= count
; i
++)
2543 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2547 else if (insn
== 0xc9)
2549 int start
= *entry
>> 4;
2550 int count
= (*entry
++) & 0xf;
2553 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2554 for (i
= 0; i
<= count
; i
++)
2556 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2560 else if ((insn
& 0xf8) == 0xd0)
2562 int count
= insn
& 0x7;
2565 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2566 for (i
= 0; i
<= count
; i
++)
2568 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2574 /* Everything else is "spare". */
2579 /* If we restore SP from a register, assume this was the frame register.
2580 Otherwise just fall back to SP as frame register. */
2581 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2582 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2584 cache
->framereg
= ARM_SP_REGNUM
;
2586 /* Determine offset to previous frame. */
2588 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2590 /* We already got the previous SP. */
2591 cache
->prev_sp
= vsp
;
2596 /* Unwinding via ARM exception table entries. Note that the sniffer
2597 already computes a filled-in prologue cache, which is then used
2598 with the same arm_prologue_this_id and arm_prologue_prev_register
2599 routines also used for prologue-parsing based unwinding. */
2602 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2603 struct frame_info
*this_frame
,
2604 void **this_prologue_cache
)
2606 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2607 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2608 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2609 struct arm_prologue_cache
*cache
;
2612 /* See if we have an ARM exception table entry covering this address. */
2613 addr_in_block
= get_frame_address_in_block (this_frame
);
2614 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2618 /* The ARM exception table does not describe unwind information
2619 for arbitrary PC values, but is guaranteed to be correct only
2620 at call sites. We have to decide here whether we want to use
2621 ARM exception table information for this frame, or fall back
2622 to using prologue parsing. (Note that if we have DWARF CFI,
2623 this sniffer isn't even called -- CFI is always preferred.)
2625 Before we make this decision, however, we check whether we
2626 actually have *symbol* information for the current frame.
2627 If not, prologue parsing would not work anyway, so we might
2628 as well use the exception table and hope for the best. */
2629 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2633 /* If the next frame is "normal", we are at a call site in this
2634 frame, so exception information is guaranteed to be valid. */
2635 if (get_next_frame (this_frame
)
2636 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2639 /* We also assume exception information is valid if we're currently
2640 blocked in a system call. The system library is supposed to
2641 ensure this, so that e.g. pthread cancellation works. */
2642 if (arm_frame_is_thumb (this_frame
))
2646 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
2647 2, byte_order_for_code
, &insn
)
2648 && (insn
& 0xff00) == 0xdf00 /* svc */)
2655 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
2656 4, byte_order_for_code
, &insn
)
2657 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2661 /* Bail out if we don't know that exception information is valid. */
2665 /* The ARM exception index does not mark the *end* of the region
2666 covered by the entry, and some functions will not have any entry.
2667 To correctly recognize the end of the covered region, the linker
2668 should have inserted dummy records with a CANTUNWIND marker.
2670 Unfortunately, current versions of GNU ld do not reliably do
2671 this, and thus we may have found an incorrect entry above.
2672 As a (temporary) sanity check, we only use the entry if it
2673 lies *within* the bounds of the function. Note that this check
2674 might reject perfectly valid entries that just happen to cover
2675 multiple functions; therefore this check ought to be removed
2676 once the linker is fixed. */
2677 if (func_start
> exidx_region
)
2681 /* Decode the list of unwinding instructions into a prologue cache.
2682 Note that this may fail due to e.g. a "refuse to unwind" code. */
2683 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2687 *this_prologue_cache
= cache
;
2691 struct frame_unwind arm_exidx_unwind
= {
2693 default_frame_unwind_stop_reason
,
2694 arm_prologue_this_id
,
2695 arm_prologue_prev_register
,
2697 arm_exidx_unwind_sniffer
2700 static struct arm_prologue_cache
*
2701 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2703 struct arm_prologue_cache
*cache
;
2706 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2707 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2709 /* Still rely on the offset calculated from prologue. */
2710 arm_scan_prologue (this_frame
, cache
);
2712 /* Since we are in epilogue, the SP has been restored. */
2713 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2715 /* Calculate actual addresses of saved registers using offsets
2716 determined by arm_scan_prologue. */
2717 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2718 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2719 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2724 /* Implementation of function hook 'this_id' in
2725 'struct frame_uwnind' for epilogue unwinder. */
2728 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2730 struct frame_id
*this_id
)
2732 struct arm_prologue_cache
*cache
;
2735 if (*this_cache
== NULL
)
2736 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2737 cache
= (struct arm_prologue_cache
*) *this_cache
;
2739 /* Use function start address as part of the frame ID. If we cannot
2740 identify the start address (due to missing symbol information),
2741 fall back to just using the current PC. */
2742 pc
= get_frame_pc (this_frame
);
2743 func
= get_frame_func (this_frame
);
2747 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2750 /* Implementation of function hook 'prev_register' in
2751 'struct frame_uwnind' for epilogue unwinder. */
2753 static struct value
*
2754 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2755 void **this_cache
, int regnum
)
2757 if (*this_cache
== NULL
)
2758 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2760 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2763 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2765 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2768 /* Implementation of function hook 'sniffer' in
2769 'struct frame_uwnind' for epilogue unwinder. */
2772 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2773 struct frame_info
*this_frame
,
2774 void **this_prologue_cache
)
2776 if (frame_relative_level (this_frame
) == 0)
2778 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2779 CORE_ADDR pc
= get_frame_pc (this_frame
);
2781 if (arm_frame_is_thumb (this_frame
))
2782 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2784 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2790 /* Frame unwinder from epilogue. */
2792 static const struct frame_unwind arm_epilogue_frame_unwind
=
2795 default_frame_unwind_stop_reason
,
2796 arm_epilogue_frame_this_id
,
2797 arm_epilogue_frame_prev_register
,
2799 arm_epilogue_frame_sniffer
,
2802 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2803 trampoline, return the target PC. Otherwise return 0.
2805 void call0a (char c, short s, int i, long l) {}
2809 (*pointer_to_call0a) (c, s, i, l);
2812 Instead of calling a stub library function _call_via_xx (xx is
2813 the register name), GCC may inline the trampoline in the object
2814 file as below (register r2 has the address of call0a).
2817 .type main, %function
2826 The trampoline 'bx r2' doesn't belong to main. */
2829 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2831 /* The heuristics of recognizing such trampoline is that FRAME is
2832 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2833 if (arm_frame_is_thumb (frame
))
2837 if (target_read_memory (pc
, buf
, 2) == 0)
2839 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2840 enum bfd_endian byte_order_for_code
2841 = gdbarch_byte_order_for_code (gdbarch
);
2843 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2845 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2848 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2850 /* Clear the LSB so that gdb core sets step-resume
2851 breakpoint at the right address. */
2852 return UNMAKE_THUMB_ADDR (dest
);
2860 static struct arm_prologue_cache
*
2861 arm_make_stub_cache (struct frame_info
*this_frame
)
2863 struct arm_prologue_cache
*cache
;
2865 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2866 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2868 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2873 /* Our frame ID for a stub frame is the current SP and LR. */
2876 arm_stub_this_id (struct frame_info
*this_frame
,
2878 struct frame_id
*this_id
)
2880 struct arm_prologue_cache
*cache
;
2882 if (*this_cache
== NULL
)
2883 *this_cache
= arm_make_stub_cache (this_frame
);
2884 cache
= (struct arm_prologue_cache
*) *this_cache
;
2886 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2890 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2891 struct frame_info
*this_frame
,
2892 void **this_prologue_cache
)
2894 CORE_ADDR addr_in_block
;
2896 CORE_ADDR pc
, start_addr
;
2899 addr_in_block
= get_frame_address_in_block (this_frame
);
2900 pc
= get_frame_pc (this_frame
);
2901 if (in_plt_section (addr_in_block
)
2902 /* We also use the stub winder if the target memory is unreadable
2903 to avoid having the prologue unwinder trying to read it. */
2904 || target_read_memory (pc
, dummy
, 4) != 0)
2907 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2908 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2914 struct frame_unwind arm_stub_unwind
= {
2916 default_frame_unwind_stop_reason
,
2918 arm_prologue_prev_register
,
2920 arm_stub_unwind_sniffer
2923 /* Put here the code to store, into CACHE->saved_regs, the addresses
2924 of the saved registers of frame described by THIS_FRAME. CACHE is
2927 static struct arm_prologue_cache
*
2928 arm_m_exception_cache (struct frame_info
*this_frame
)
2930 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2931 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2932 struct arm_prologue_cache
*cache
;
2933 CORE_ADDR unwound_sp
;
2936 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2937 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2939 unwound_sp
= get_frame_register_unsigned (this_frame
,
2942 /* The hardware saves eight 32-bit words, comprising xPSR,
2943 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2944 "B1.5.6 Exception entry behavior" in
2945 "ARMv7-M Architecture Reference Manual". */
2946 cache
->saved_regs
[0].addr
= unwound_sp
;
2947 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2948 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2949 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2950 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2951 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2952 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2953 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2955 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2956 aligner between the top of the 32-byte stack frame and the
2957 previous context's stack pointer. */
2958 cache
->prev_sp
= unwound_sp
+ 32;
2959 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2960 && (xpsr
& (1 << 9)) != 0)
2961 cache
->prev_sp
+= 4;
2966 /* Implementation of function hook 'this_id' in
2967 'struct frame_uwnind'. */
2970 arm_m_exception_this_id (struct frame_info
*this_frame
,
2972 struct frame_id
*this_id
)
2974 struct arm_prologue_cache
*cache
;
2976 if (*this_cache
== NULL
)
2977 *this_cache
= arm_m_exception_cache (this_frame
);
2978 cache
= (struct arm_prologue_cache
*) *this_cache
;
2980 /* Our frame ID for a stub frame is the current SP and LR. */
2981 *this_id
= frame_id_build (cache
->prev_sp
,
2982 get_frame_pc (this_frame
));
2985 /* Implementation of function hook 'prev_register' in
2986 'struct frame_uwnind'. */
2988 static struct value
*
2989 arm_m_exception_prev_register (struct frame_info
*this_frame
,
2993 struct arm_prologue_cache
*cache
;
2995 if (*this_cache
== NULL
)
2996 *this_cache
= arm_m_exception_cache (this_frame
);
2997 cache
= (struct arm_prologue_cache
*) *this_cache
;
2999 /* The value was already reconstructed into PREV_SP. */
3000 if (prev_regnum
== ARM_SP_REGNUM
)
3001 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3004 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3008 /* Implementation of function hook 'sniffer' in
3009 'struct frame_uwnind'. */
3012 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3013 struct frame_info
*this_frame
,
3014 void **this_prologue_cache
)
3016 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3018 /* No need to check is_m; this sniffer is only registered for
3019 M-profile architectures. */
3021 /* Check if exception frame returns to a magic PC value. */
3022 return arm_m_addr_is_magic (this_pc
);
3025 /* Frame unwinder for M-profile exceptions. */
3027 struct frame_unwind arm_m_exception_unwind
=
3030 default_frame_unwind_stop_reason
,
3031 arm_m_exception_this_id
,
3032 arm_m_exception_prev_register
,
3034 arm_m_exception_unwind_sniffer
3038 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3040 struct arm_prologue_cache
*cache
;
3042 if (*this_cache
== NULL
)
3043 *this_cache
= arm_make_prologue_cache (this_frame
);
3044 cache
= (struct arm_prologue_cache
*) *this_cache
;
3046 return cache
->prev_sp
- cache
->framesize
;
3049 struct frame_base arm_normal_base
= {
3050 &arm_prologue_unwind
,
3051 arm_normal_frame_base
,
3052 arm_normal_frame_base
,
3053 arm_normal_frame_base
3056 static struct value
*
3057 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3060 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3062 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3067 /* The PC is normally copied from the return column, which
3068 describes saves of LR. However, that version may have an
3069 extra bit set to indicate Thumb state. The bit is not
3071 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3072 return frame_unwind_got_constant (this_frame
, regnum
,
3073 arm_addr_bits_remove (gdbarch
, lr
));
3076 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3077 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3078 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3079 if (IS_THUMB_ADDR (lr
))
3083 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3086 internal_error (__FILE__
, __LINE__
,
3087 _("Unexpected register %d"), regnum
);
3092 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3093 struct dwarf2_frame_state_reg
*reg
,
3094 struct frame_info
*this_frame
)
3100 reg
->how
= DWARF2_FRAME_REG_FN
;
3101 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3104 reg
->how
= DWARF2_FRAME_REG_CFA
;
3109 /* Implement the stack_frame_destroyed_p gdbarch method. */
3112 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3114 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3115 unsigned int insn
, insn2
;
3116 int found_return
= 0, found_stack_adjust
= 0;
3117 CORE_ADDR func_start
, func_end
;
3121 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3124 /* The epilogue is a sequence of instructions along the following lines:
3126 - add stack frame size to SP or FP
3127 - [if frame pointer used] restore SP from FP
3128 - restore registers from SP [may include PC]
3129 - a return-type instruction [if PC wasn't already restored]
3131 In a first pass, we scan forward from the current PC and verify the
3132 instructions we find as compatible with this sequence, ending in a
3135 However, this is not sufficient to distinguish indirect function calls
3136 within a function from indirect tail calls in the epilogue in some cases.
3137 Therefore, if we didn't already find any SP-changing instruction during
3138 forward scan, we add a backward scanning heuristic to ensure we actually
3139 are in the epilogue. */
3142 while (scan_pc
< func_end
&& !found_return
)
3144 if (target_read_memory (scan_pc
, buf
, 2))
3148 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3150 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3152 else if (insn
== 0x46f7) /* mov pc, lr */
3154 else if (thumb_instruction_restores_sp (insn
))
3156 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3159 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3161 if (target_read_memory (scan_pc
, buf
, 2))
3165 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3167 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3169 if (insn2
& 0x8000) /* <registers> include PC. */
3172 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3173 && (insn2
& 0x0fff) == 0x0b04)
3175 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3178 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3179 && (insn2
& 0x0e00) == 0x0a00)
3191 /* Since any instruction in the epilogue sequence, with the possible
3192 exception of return itself, updates the stack pointer, we need to
3193 scan backwards for at most one instruction. Try either a 16-bit or
3194 a 32-bit instruction. This is just a heuristic, so we do not worry
3195 too much about false positives. */
3197 if (pc
- 4 < func_start
)
3199 if (target_read_memory (pc
- 4, buf
, 4))
3202 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3203 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3205 if (thumb_instruction_restores_sp (insn2
))
3206 found_stack_adjust
= 1;
3207 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3208 found_stack_adjust
= 1;
3209 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3210 && (insn2
& 0x0fff) == 0x0b04)
3211 found_stack_adjust
= 1;
3212 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3213 && (insn2
& 0x0e00) == 0x0a00)
3214 found_stack_adjust
= 1;
3216 return found_stack_adjust
;
3220 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3222 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3225 CORE_ADDR func_start
, func_end
;
3227 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3230 /* We are in the epilogue if the previous instruction was a stack
3231 adjustment and the next instruction is a possible return (bx, mov
3232 pc, or pop). We could have to scan backwards to find the stack
3233 adjustment, or forwards to find the return, but this is a decent
3234 approximation. First scan forwards. */
3237 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3238 if (bits (insn
, 28, 31) != INST_NV
)
3240 if ((insn
& 0x0ffffff0) == 0x012fff10)
3243 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3246 else if ((insn
& 0x0fff0000) == 0x08bd0000
3247 && (insn
& 0x0000c000) != 0)
3248 /* POP (LDMIA), including PC or LR. */
3255 /* Scan backwards. This is just a heuristic, so do not worry about
3256 false positives from mode changes. */
3258 if (pc
< func_start
+ 4)
3261 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3262 if (arm_instruction_restores_sp (insn
))
3268 /* Implement the stack_frame_destroyed_p gdbarch method. */
3271 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3273 if (arm_pc_is_thumb (gdbarch
, pc
))
3274 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3276 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3279 /* When arguments must be pushed onto the stack, they go on in reverse
3280 order. The code below implements a FILO (stack) to do this. */
3285 struct stack_item
*prev
;
3289 static struct stack_item
*
3290 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3292 struct stack_item
*si
;
3293 si
= XNEW (struct stack_item
);
3294 si
->data
= (gdb_byte
*) xmalloc (len
);
3297 memcpy (si
->data
, contents
, len
);
3301 static struct stack_item
*
3302 pop_stack_item (struct stack_item
*si
)
3304 struct stack_item
*dead
= si
;
3311 /* Implement the gdbarch type alignment method, overrides the generic
3312 alignment algorithm for anything that is arm specific. */
3315 arm_type_align (gdbarch
*gdbarch
, struct type
*t
)
3317 t
= check_typedef (t
);
3318 if (TYPE_CODE (t
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (t
))
3320 /* Use the natural alignment for vector types (the same for
3321 scalar type), but the maximum alignment is 64-bit. */
3322 if (TYPE_LENGTH (t
) > 8)
3325 return TYPE_LENGTH (t
);
3328 /* Allow the common code to calculate the alignment. */
3332 /* Possible base types for a candidate for passing and returning in
3335 enum arm_vfp_cprc_base_type
3344 /* The length of one element of base type B. */
3347 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3351 case VFP_CPRC_SINGLE
:
3353 case VFP_CPRC_DOUBLE
:
3355 case VFP_CPRC_VEC64
:
3357 case VFP_CPRC_VEC128
:
3360 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3365 /* The character ('s', 'd' or 'q') for the type of VFP register used
3366 for passing base type B. */
3369 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3373 case VFP_CPRC_SINGLE
:
3375 case VFP_CPRC_DOUBLE
:
3377 case VFP_CPRC_VEC64
:
3379 case VFP_CPRC_VEC128
:
3382 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3387 /* Determine whether T may be part of a candidate for passing and
3388 returning in VFP registers, ignoring the limit on the total number
3389 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3390 classification of the first valid component found; if it is not
3391 VFP_CPRC_UNKNOWN, all components must have the same classification
3392 as *BASE_TYPE. If it is found that T contains a type not permitted
3393 for passing and returning in VFP registers, a type differently
3394 classified from *BASE_TYPE, or two types differently classified
3395 from each other, return -1, otherwise return the total number of
3396 base-type elements found (possibly 0 in an empty structure or
3397 array). Vector types are not currently supported, matching the
3398 generic AAPCS support. */
3401 arm_vfp_cprc_sub_candidate (struct type
*t
,
3402 enum arm_vfp_cprc_base_type
*base_type
)
3404 t
= check_typedef (t
);
3405 switch (TYPE_CODE (t
))
3408 switch (TYPE_LENGTH (t
))
3411 if (*base_type
== VFP_CPRC_UNKNOWN
)
3412 *base_type
= VFP_CPRC_SINGLE
;
3413 else if (*base_type
!= VFP_CPRC_SINGLE
)
3418 if (*base_type
== VFP_CPRC_UNKNOWN
)
3419 *base_type
= VFP_CPRC_DOUBLE
;
3420 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3429 case TYPE_CODE_COMPLEX
:
3430 /* Arguments of complex T where T is one of the types float or
3431 double get treated as if they are implemented as:
3440 switch (TYPE_LENGTH (t
))
3443 if (*base_type
== VFP_CPRC_UNKNOWN
)
3444 *base_type
= VFP_CPRC_SINGLE
;
3445 else if (*base_type
!= VFP_CPRC_SINGLE
)
3450 if (*base_type
== VFP_CPRC_UNKNOWN
)
3451 *base_type
= VFP_CPRC_DOUBLE
;
3452 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3461 case TYPE_CODE_ARRAY
:
3463 if (TYPE_VECTOR (t
))
3465 /* A 64-bit or 128-bit containerized vector type are VFP
3467 switch (TYPE_LENGTH (t
))
3470 if (*base_type
== VFP_CPRC_UNKNOWN
)
3471 *base_type
= VFP_CPRC_VEC64
;
3474 if (*base_type
== VFP_CPRC_UNKNOWN
)
3475 *base_type
= VFP_CPRC_VEC128
;
3486 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3490 if (TYPE_LENGTH (t
) == 0)
3492 gdb_assert (count
== 0);
3495 else if (count
== 0)
3497 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3498 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3499 return TYPE_LENGTH (t
) / unitlen
;
3504 case TYPE_CODE_STRUCT
:
3509 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3513 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3514 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3516 if (sub_count
== -1)
3520 if (TYPE_LENGTH (t
) == 0)
3522 gdb_assert (count
== 0);
3525 else if (count
== 0)
3527 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3528 if (TYPE_LENGTH (t
) != unitlen
* count
)
3533 case TYPE_CODE_UNION
:
3538 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3540 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3542 if (sub_count
== -1)
3544 count
= (count
> sub_count
? count
: sub_count
);
3546 if (TYPE_LENGTH (t
) == 0)
3548 gdb_assert (count
== 0);
3551 else if (count
== 0)
3553 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3554 if (TYPE_LENGTH (t
) != unitlen
* count
)
3566 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3567 if passed to or returned from a non-variadic function with the VFP
3568 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3569 *BASE_TYPE to the base type for T and *COUNT to the number of
3570 elements of that base type before returning. */
3573 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3576 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3577 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3578 if (c
<= 0 || c
> 4)
3585 /* Return 1 if the VFP ABI should be used for passing arguments to and
3586 returning values from a function of type FUNC_TYPE, 0
3590 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3592 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3593 /* Variadic functions always use the base ABI. Assume that functions
3594 without debug info are not variadic. */
3595 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3597 /* The VFP ABI is only supported as a variant of AAPCS. */
3598 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3600 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3603 /* We currently only support passing parameters in integer registers, which
3604 conforms with GCC's default model, and VFP argument passing following
3605 the VFP variant of AAPCS. Several other variants exist and
3606 we should probably support some of them based on the selected ABI. */
3609 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3610 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3611 struct value
**args
, CORE_ADDR sp
,
3612 function_call_return_method return_method
,
3613 CORE_ADDR struct_addr
)
3615 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3619 struct stack_item
*si
= NULL
;
3622 unsigned vfp_regs_free
= (1 << 16) - 1;
3624 /* Determine the type of this function and whether the VFP ABI
3626 ftype
= check_typedef (value_type (function
));
3627 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3628 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3629 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3631 /* Set the return address. For the ARM, the return breakpoint is
3632 always at BP_ADDR. */
3633 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3635 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3637 /* Walk through the list of args and determine how large a temporary
3638 stack is required. Need to take care here as structs may be
3639 passed on the stack, and we have to push them. */
3642 argreg
= ARM_A1_REGNUM
;
3645 /* The struct_return pointer occupies the first parameter
3646 passing register. */
3647 if (return_method
== return_method_struct
)
3650 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3651 gdbarch_register_name (gdbarch
, argreg
),
3652 paddress (gdbarch
, struct_addr
));
3653 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3657 for (argnum
= 0; argnum
< nargs
; argnum
++)
3660 struct type
*arg_type
;
3661 struct type
*target_type
;
3662 enum type_code typecode
;
3663 const bfd_byte
*val
;
3665 enum arm_vfp_cprc_base_type vfp_base_type
;
3667 int may_use_core_reg
= 1;
3669 arg_type
= check_typedef (value_type (args
[argnum
]));
3670 len
= TYPE_LENGTH (arg_type
);
3671 target_type
= TYPE_TARGET_TYPE (arg_type
);
3672 typecode
= TYPE_CODE (arg_type
);
3673 val
= value_contents (args
[argnum
]);
3675 align
= type_align (arg_type
);
3676 /* Round alignment up to a whole number of words. */
3677 align
= (align
+ ARM_INT_REGISTER_SIZE
- 1)
3678 & ~(ARM_INT_REGISTER_SIZE
- 1);
3679 /* Different ABIs have different maximum alignments. */
3680 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3682 /* The APCS ABI only requires word alignment. */
3683 align
= ARM_INT_REGISTER_SIZE
;
3687 /* The AAPCS requires at most doubleword alignment. */
3688 if (align
> ARM_INT_REGISTER_SIZE
* 2)
3689 align
= ARM_INT_REGISTER_SIZE
* 2;
3693 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3701 /* Because this is a CPRC it cannot go in a core register or
3702 cause a core register to be skipped for alignment.
3703 Either it goes in VFP registers and the rest of this loop
3704 iteration is skipped for this argument, or it goes on the
3705 stack (and the stack alignment code is correct for this
3707 may_use_core_reg
= 0;
3709 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3710 shift
= unit_length
/ 4;
3711 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3712 for (regno
= 0; regno
< 16; regno
+= shift
)
3713 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3722 vfp_regs_free
&= ~(mask
<< regno
);
3723 reg_scaled
= regno
/ shift
;
3724 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3725 for (i
= 0; i
< vfp_base_count
; i
++)
3729 if (reg_char
== 'q')
3730 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3731 val
+ i
* unit_length
);
3734 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3735 reg_char
, reg_scaled
+ i
);
3736 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3738 regcache
->cooked_write (regnum
, val
+ i
* unit_length
);
3745 /* This CPRC could not go in VFP registers, so all VFP
3746 registers are now marked as used. */
3751 /* Push stack padding for dowubleword alignment. */
3752 if (nstack
& (align
- 1))
3754 si
= push_stack_item (si
, val
, ARM_INT_REGISTER_SIZE
);
3755 nstack
+= ARM_INT_REGISTER_SIZE
;
3758 /* Doubleword aligned quantities must go in even register pairs. */
3759 if (may_use_core_reg
3760 && argreg
<= ARM_LAST_ARG_REGNUM
3761 && align
> ARM_INT_REGISTER_SIZE
3765 /* If the argument is a pointer to a function, and it is a
3766 Thumb function, create a LOCAL copy of the value and set
3767 the THUMB bit in it. */
3768 if (TYPE_CODE_PTR
== typecode
3769 && target_type
!= NULL
3770 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3772 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3773 if (arm_pc_is_thumb (gdbarch
, regval
))
3775 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3776 store_unsigned_integer (copy
, len
, byte_order
,
3777 MAKE_THUMB_ADDR (regval
));
3782 /* Copy the argument to general registers or the stack in
3783 register-sized pieces. Large arguments are split between
3784 registers and stack. */
3787 int partial_len
= len
< ARM_INT_REGISTER_SIZE
3788 ? len
: ARM_INT_REGISTER_SIZE
;
3790 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3792 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3794 /* The argument is being passed in a general purpose
3796 if (byte_order
== BFD_ENDIAN_BIG
)
3797 regval
<<= (ARM_INT_REGISTER_SIZE
- partial_len
) * 8;
3799 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3801 gdbarch_register_name
3803 phex (regval
, ARM_INT_REGISTER_SIZE
));
3804 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3809 gdb_byte buf
[ARM_INT_REGISTER_SIZE
];
3811 memset (buf
, 0, sizeof (buf
));
3812 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3814 /* Push the arguments onto the stack. */
3816 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3818 si
= push_stack_item (si
, buf
, ARM_INT_REGISTER_SIZE
);
3819 nstack
+= ARM_INT_REGISTER_SIZE
;
3826 /* If we have an odd number of words to push, then decrement the stack
3827 by one word now, so first stack argument will be dword aligned. */
3834 write_memory (sp
, si
->data
, si
->len
);
3835 si
= pop_stack_item (si
);
3838 /* Finally, update teh SP register. */
3839 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3845 /* Always align the frame to an 8-byte boundary. This is required on
3846 some platforms and harmless on the rest. */
3849 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3851 /* Align the stack to eight bytes. */
3852 return sp
& ~ (CORE_ADDR
) 7;
3856 print_fpu_flags (struct ui_file
*file
, int flags
)
3858 if (flags
& (1 << 0))
3859 fputs_filtered ("IVO ", file
);
3860 if (flags
& (1 << 1))
3861 fputs_filtered ("DVZ ", file
);
3862 if (flags
& (1 << 2))
3863 fputs_filtered ("OFL ", file
);
3864 if (flags
& (1 << 3))
3865 fputs_filtered ("UFL ", file
);
3866 if (flags
& (1 << 4))
3867 fputs_filtered ("INX ", file
);
3868 fputc_filtered ('\n', file
);
3871 /* Print interesting information about the floating point processor
3872 (if present) or emulator. */
3874 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3875 struct frame_info
*frame
, const char *args
)
3877 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3880 type
= (status
>> 24) & 127;
3881 if (status
& (1 << 31))
3882 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3884 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3885 /* i18n: [floating point unit] mask */
3886 fputs_filtered (_("mask: "), file
);
3887 print_fpu_flags (file
, status
>> 16);
3888 /* i18n: [floating point unit] flags */
3889 fputs_filtered (_("flags: "), file
);
3890 print_fpu_flags (file
, status
);
3893 /* Construct the ARM extended floating point type. */
3894 static struct type
*
3895 arm_ext_type (struct gdbarch
*gdbarch
)
3897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3899 if (!tdep
->arm_ext_type
)
3901 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3902 floatformats_arm_ext
);
3904 return tdep
->arm_ext_type
;
3907 static struct type
*
3908 arm_neon_double_type (struct gdbarch
*gdbarch
)
3910 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3912 if (tdep
->neon_double_type
== NULL
)
3914 struct type
*t
, *elem
;
3916 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3918 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3919 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3920 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3921 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3922 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3923 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3924 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3925 append_composite_type_field (t
, "u64", elem
);
3926 elem
= builtin_type (gdbarch
)->builtin_float
;
3927 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3928 elem
= builtin_type (gdbarch
)->builtin_double
;
3929 append_composite_type_field (t
, "f64", elem
);
3931 TYPE_VECTOR (t
) = 1;
3932 TYPE_NAME (t
) = "neon_d";
3933 tdep
->neon_double_type
= t
;
3936 return tdep
->neon_double_type
;
3939 /* FIXME: The vector types are not correctly ordered on big-endian
3940 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3941 bits of d0 - regardless of what unit size is being held in d0. So
3942 the offset of the first uint8 in d0 is 7, but the offset of the
3943 first float is 4. This code works as-is for little-endian
3946 static struct type
*
3947 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3951 if (tdep
->neon_quad_type
== NULL
)
3953 struct type
*t
, *elem
;
3955 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
3957 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3958 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
3959 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3960 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
3961 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3962 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
3963 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3964 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
3965 elem
= builtin_type (gdbarch
)->builtin_float
;
3966 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
3967 elem
= builtin_type (gdbarch
)->builtin_double
;
3968 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
3970 TYPE_VECTOR (t
) = 1;
3971 TYPE_NAME (t
) = "neon_q";
3972 tdep
->neon_quad_type
= t
;
3975 return tdep
->neon_quad_type
;
3978 /* Return the GDB type object for the "standard" data type of data in
3981 static struct type
*
3982 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
3984 int num_regs
= gdbarch_num_regs (gdbarch
);
3986 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
3987 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
3988 return builtin_type (gdbarch
)->builtin_float
;
3990 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
3991 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
3992 return arm_neon_quad_type (gdbarch
);
3994 /* If the target description has register information, we are only
3995 in this function so that we can override the types of
3996 double-precision registers for NEON. */
3997 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
3999 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4001 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4002 && TYPE_CODE (t
) == TYPE_CODE_FLT
4003 && gdbarch_tdep (gdbarch
)->have_neon
)
4004 return arm_neon_double_type (gdbarch
);
4009 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4011 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4012 return builtin_type (gdbarch
)->builtin_void
;
4014 return arm_ext_type (gdbarch
);
4016 else if (regnum
== ARM_SP_REGNUM
)
4017 return builtin_type (gdbarch
)->builtin_data_ptr
;
4018 else if (regnum
== ARM_PC_REGNUM
)
4019 return builtin_type (gdbarch
)->builtin_func_ptr
;
4020 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4021 /* These registers are only supported on targets which supply
4022 an XML description. */
4023 return builtin_type (gdbarch
)->builtin_int0
;
4025 return builtin_type (gdbarch
)->builtin_uint32
;
4028 /* Map a DWARF register REGNUM onto the appropriate GDB register
4032 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4034 /* Core integer regs. */
4035 if (reg
>= 0 && reg
<= 15)
4038 /* Legacy FPA encoding. These were once used in a way which
4039 overlapped with VFP register numbering, so their use is
4040 discouraged, but GDB doesn't support the ARM toolchain
4041 which used them for VFP. */
4042 if (reg
>= 16 && reg
<= 23)
4043 return ARM_F0_REGNUM
+ reg
- 16;
4045 /* New assignments for the FPA registers. */
4046 if (reg
>= 96 && reg
<= 103)
4047 return ARM_F0_REGNUM
+ reg
- 96;
4049 /* WMMX register assignments. */
4050 if (reg
>= 104 && reg
<= 111)
4051 return ARM_WCGR0_REGNUM
+ reg
- 104;
4053 if (reg
>= 112 && reg
<= 127)
4054 return ARM_WR0_REGNUM
+ reg
- 112;
4056 if (reg
>= 192 && reg
<= 199)
4057 return ARM_WC0_REGNUM
+ reg
- 192;
4059 /* VFP v2 registers. A double precision value is actually
4060 in d1 rather than s2, but the ABI only defines numbering
4061 for the single precision registers. This will "just work"
4062 in GDB for little endian targets (we'll read eight bytes,
4063 starting in s0 and then progressing to s1), but will be
4064 reversed on big endian targets with VFP. This won't
4065 be a problem for the new Neon quad registers; you're supposed
4066 to use DW_OP_piece for those. */
4067 if (reg
>= 64 && reg
<= 95)
4071 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4072 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4076 /* VFP v3 / Neon registers. This range is also used for VFP v2
4077 registers, except that it now describes d0 instead of s0. */
4078 if (reg
>= 256 && reg
<= 287)
4082 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4083 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4090 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4092 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4095 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4097 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4098 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4100 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4101 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4103 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4104 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4106 if (reg
< NUM_GREGS
)
4107 return SIM_ARM_R0_REGNUM
+ reg
;
4110 if (reg
< NUM_FREGS
)
4111 return SIM_ARM_FP0_REGNUM
+ reg
;
4114 if (reg
< NUM_SREGS
)
4115 return SIM_ARM_FPS_REGNUM
+ reg
;
4118 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4121 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4122 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4123 NULL if an error occurs. BUF is freed. */
4126 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4127 int old_len
, int new_len
)
4130 int bytes_to_read
= new_len
- old_len
;
4132 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4133 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4135 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4143 /* An IT block is at most the 2-byte IT instruction followed by
4144 four 4-byte instructions. The furthest back we must search to
4145 find an IT block that affects the current instruction is thus
4146 2 + 3 * 4 == 14 bytes. */
4147 #define MAX_IT_BLOCK_PREFIX 14
4149 /* Use a quick scan if there are more than this many bytes of
4151 #define IT_SCAN_THRESHOLD 32
4153 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4154 A breakpoint in an IT block may not be hit, depending on the
4157 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4161 CORE_ADDR boundary
, func_start
;
4163 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4164 int i
, any
, last_it
, last_it_count
;
4166 /* If we are using BKPT breakpoints, none of this is necessary. */
4167 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4170 /* ARM mode does not have this problem. */
4171 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4174 /* We are setting a breakpoint in Thumb code that could potentially
4175 contain an IT block. The first step is to find how much Thumb
4176 code there is; we do not need to read outside of known Thumb
4178 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4180 /* Thumb-2 code must have mapping symbols to have a chance. */
4183 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4185 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4186 && func_start
> boundary
)
4187 boundary
= func_start
;
4189 /* Search for a candidate IT instruction. We have to do some fancy
4190 footwork to distinguish a real IT instruction from the second
4191 half of a 32-bit instruction, but there is no need for that if
4192 there's no candidate. */
4193 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4195 /* No room for an IT instruction. */
4198 buf
= (gdb_byte
*) xmalloc (buf_len
);
4199 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4202 for (i
= 0; i
< buf_len
; i
+= 2)
4204 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4205 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4218 /* OK, the code bytes before this instruction contain at least one
4219 halfword which resembles an IT instruction. We know that it's
4220 Thumb code, but there are still two possibilities. Either the
4221 halfword really is an IT instruction, or it is the second half of
4222 a 32-bit Thumb instruction. The only way we can tell is to
4223 scan forwards from a known instruction boundary. */
4224 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4228 /* There's a lot of code before this instruction. Start with an
4229 optimistic search; it's easy to recognize halfwords that can
4230 not be the start of a 32-bit instruction, and use that to
4231 lock on to the instruction boundaries. */
4232 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4235 buf_len
= IT_SCAN_THRESHOLD
;
4238 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4240 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4241 if (thumb_insn_size (inst1
) == 2)
4248 /* At this point, if DEFINITE, BUF[I] is the first place we
4249 are sure that we know the instruction boundaries, and it is far
4250 enough from BPADDR that we could not miss an IT instruction
4251 affecting BPADDR. If ! DEFINITE, give up - start from a
4255 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4259 buf_len
= bpaddr
- boundary
;
4265 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4268 buf_len
= bpaddr
- boundary
;
4272 /* Scan forwards. Find the last IT instruction before BPADDR. */
4277 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4279 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4284 else if (inst1
& 0x0002)
4286 else if (inst1
& 0x0004)
4291 i
+= thumb_insn_size (inst1
);
4297 /* There wasn't really an IT instruction after all. */
4300 if (last_it_count
< 1)
4301 /* It was too far away. */
4304 /* This really is a trouble spot. Move the breakpoint to the IT
4306 return bpaddr
- buf_len
+ last_it
;
4309 /* ARM displaced stepping support.
4311 Generally ARM displaced stepping works as follows:
4313 1. When an instruction is to be single-stepped, it is first decoded by
4314 arm_process_displaced_insn. Depending on the type of instruction, it is
4315 then copied to a scratch location, possibly in a modified form. The
4316 copy_* set of functions performs such modification, as necessary. A
4317 breakpoint is placed after the modified instruction in the scratch space
4318 to return control to GDB. Note in particular that instructions which
4319 modify the PC will no longer do so after modification.
4321 2. The instruction is single-stepped, by setting the PC to the scratch
4322 location address, and resuming. Control returns to GDB when the
4325 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4326 function used for the current instruction. This function's job is to
4327 put the CPU/memory state back to what it would have been if the
4328 instruction had been executed unmodified in its original location. */
4330 /* NOP instruction (mov r0, r0). */
4331 #define ARM_NOP 0xe1a00000
4332 #define THUMB_NOP 0x4600
4334 /* Helper for register reads for displaced stepping. In particular, this
4335 returns the PC as it would be seen by the instruction at its original
4339 displaced_read_reg (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4343 CORE_ADDR from
= dsc
->insn_addr
;
4345 if (regno
== ARM_PC_REGNUM
)
4347 /* Compute pipeline offset:
4348 - When executing an ARM instruction, PC reads as the address of the
4349 current instruction plus 8.
4350 - When executing a Thumb instruction, PC reads as the address of the
4351 current instruction plus 4. */
4358 if (debug_displaced
)
4359 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4360 (unsigned long) from
);
4361 return (ULONGEST
) from
;
4365 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4366 if (debug_displaced
)
4367 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4368 regno
, (unsigned long) ret
);
4374 displaced_in_arm_mode (struct regcache
*regs
)
4377 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
4379 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4381 return (ps
& t_bit
) == 0;
4384 /* Write to the PC as from a branch instruction. */
4387 branch_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4391 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4392 architecture versions < 6. */
4393 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4394 val
& ~(ULONGEST
) 0x3);
4396 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4397 val
& ~(ULONGEST
) 0x1);
4400 /* Write to the PC as from a branch-exchange instruction. */
4403 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4406 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
4408 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4412 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4413 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4415 else if ((val
& 2) == 0)
4417 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4418 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4422 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4423 mode, align dest to 4 bytes). */
4424 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4425 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4426 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4430 /* Write to the PC as if from a load instruction. */
4433 load_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4436 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4437 bx_write_pc (regs
, val
);
4439 branch_write_pc (regs
, dsc
, val
);
4442 /* Write to the PC as if from an ALU instruction. */
4445 alu_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4448 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4449 bx_write_pc (regs
, val
);
4451 branch_write_pc (regs
, dsc
, val
);
4454 /* Helper for writing to registers for displaced stepping. Writing to the PC
4455 has a varying effects depending on the instruction which does the write:
4456 this is controlled by the WRITE_PC argument. */
4459 displaced_write_reg (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4460 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4462 if (regno
== ARM_PC_REGNUM
)
4464 if (debug_displaced
)
4465 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4466 (unsigned long) val
);
4469 case BRANCH_WRITE_PC
:
4470 branch_write_pc (regs
, dsc
, val
);
4474 bx_write_pc (regs
, val
);
4478 load_write_pc (regs
, dsc
, val
);
4482 alu_write_pc (regs
, dsc
, val
);
4485 case CANNOT_WRITE_PC
:
4486 warning (_("Instruction wrote to PC in an unexpected way when "
4487 "single-stepping"));
4491 internal_error (__FILE__
, __LINE__
,
4492 _("Invalid argument to displaced_write_reg"));
4495 dsc
->wrote_to_pc
= 1;
4499 if (debug_displaced
)
4500 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4501 regno
, (unsigned long) val
);
4502 regcache_cooked_write_unsigned (regs
, regno
, val
);
4506 /* This function is used to concisely determine if an instruction INSN
4507 references PC. Register fields of interest in INSN should have the
4508 corresponding fields of BITMASK set to 0b1111. The function
4509 returns return 1 if any of these fields in INSN reference the PC
4510 (also 0b1111, r15), else it returns 0. */
4513 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4515 uint32_t lowbit
= 1;
4517 while (bitmask
!= 0)
4521 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4527 mask
= lowbit
* 0xf;
4529 if ((insn
& mask
) == mask
)
4538 /* The simplest copy function. Many instructions have the same effect no
4539 matter what address they are executed at: in those cases, use this. */
4542 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4543 const char *iname
, arm_displaced_step_closure
*dsc
)
4545 if (debug_displaced
)
4546 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4547 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4550 dsc
->modinsn
[0] = insn
;
4556 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4557 uint16_t insn2
, const char *iname
,
4558 arm_displaced_step_closure
*dsc
)
4560 if (debug_displaced
)
4561 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4562 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4565 dsc
->modinsn
[0] = insn1
;
4566 dsc
->modinsn
[1] = insn2
;
4572 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4575 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4577 arm_displaced_step_closure
*dsc
)
4579 if (debug_displaced
)
4580 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4581 "opcode/class '%s' unmodified\n", insn
,
4584 dsc
->modinsn
[0] = insn
;
4589 /* Preload instructions with immediate offset. */
4592 cleanup_preload (struct gdbarch
*gdbarch
,
4593 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4595 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4596 if (!dsc
->u
.preload
.immed
)
4597 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4601 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4602 arm_displaced_step_closure
*dsc
, unsigned int rn
)
4605 /* Preload instructions:
4607 {pli/pld} [rn, #+/-imm]
4609 {pli/pld} [r0, #+/-imm]. */
4611 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4612 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4613 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4614 dsc
->u
.preload
.immed
= 1;
4616 dsc
->cleanup
= &cleanup_preload
;
4620 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4621 arm_displaced_step_closure
*dsc
)
4623 unsigned int rn
= bits (insn
, 16, 19);
4625 if (!insn_references_pc (insn
, 0x000f0000ul
))
4626 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4628 if (debug_displaced
)
4629 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4630 (unsigned long) insn
);
4632 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4634 install_preload (gdbarch
, regs
, dsc
, rn
);
4640 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4641 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4643 unsigned int rn
= bits (insn1
, 0, 3);
4644 unsigned int u_bit
= bit (insn1
, 7);
4645 int imm12
= bits (insn2
, 0, 11);
4648 if (rn
!= ARM_PC_REGNUM
)
4649 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4651 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4652 PLD (literal) Encoding T1. */
4653 if (debug_displaced
)
4654 fprintf_unfiltered (gdb_stdlog
,
4655 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4656 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4662 /* Rewrite instruction {pli/pld} PC imm12 into:
4663 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4667 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4669 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4670 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4672 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4674 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4675 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4676 dsc
->u
.preload
.immed
= 0;
4678 /* {pli/pld} [r0, r1] */
4679 dsc
->modinsn
[0] = insn1
& 0xfff0;
4680 dsc
->modinsn
[1] = 0xf001;
4683 dsc
->cleanup
= &cleanup_preload
;
4687 /* Preload instructions with register offset. */
4690 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4691 arm_displaced_step_closure
*dsc
, unsigned int rn
,
4694 ULONGEST rn_val
, rm_val
;
4696 /* Preload register-offset instructions:
4698 {pli/pld} [rn, rm {, shift}]
4700 {pli/pld} [r0, r1 {, shift}]. */
4702 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4703 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4704 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4705 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4706 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4707 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4708 dsc
->u
.preload
.immed
= 0;
4710 dsc
->cleanup
= &cleanup_preload
;
4714 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4715 struct regcache
*regs
,
4716 arm_displaced_step_closure
*dsc
)
4718 unsigned int rn
= bits (insn
, 16, 19);
4719 unsigned int rm
= bits (insn
, 0, 3);
4722 if (!insn_references_pc (insn
, 0x000f000ful
))
4723 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4725 if (debug_displaced
)
4726 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4727 (unsigned long) insn
);
4729 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4731 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4735 /* Copy/cleanup coprocessor load and store instructions. */
4738 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4739 struct regcache
*regs
,
4740 arm_displaced_step_closure
*dsc
)
4742 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4744 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4746 if (dsc
->u
.ldst
.writeback
)
4747 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4751 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4752 arm_displaced_step_closure
*dsc
,
4753 int writeback
, unsigned int rn
)
4757 /* Coprocessor load/store instructions:
4759 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4761 {stc/stc2} [r0, #+/-imm].
4763 ldc/ldc2 are handled identically. */
4765 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4766 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4767 /* PC should be 4-byte aligned. */
4768 rn_val
= rn_val
& 0xfffffffc;
4769 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4771 dsc
->u
.ldst
.writeback
= writeback
;
4772 dsc
->u
.ldst
.rn
= rn
;
4774 dsc
->cleanup
= &cleanup_copro_load_store
;
4778 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4779 struct regcache
*regs
,
4780 arm_displaced_step_closure
*dsc
)
4782 unsigned int rn
= bits (insn
, 16, 19);
4784 if (!insn_references_pc (insn
, 0x000f0000ul
))
4785 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4787 if (debug_displaced
)
4788 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4789 "load/store insn %.8lx\n", (unsigned long) insn
);
4791 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4793 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4799 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4800 uint16_t insn2
, struct regcache
*regs
,
4801 arm_displaced_step_closure
*dsc
)
4803 unsigned int rn
= bits (insn1
, 0, 3);
4805 if (rn
!= ARM_PC_REGNUM
)
4806 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4807 "copro load/store", dsc
);
4809 if (debug_displaced
)
4810 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4811 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4813 dsc
->modinsn
[0] = insn1
& 0xfff0;
4814 dsc
->modinsn
[1] = insn2
;
4817 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4818 doesn't support writeback, so pass 0. */
4819 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4824 /* Clean up branch instructions (actually perform the branch, by setting
4828 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4829 arm_displaced_step_closure
*dsc
)
4831 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4832 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4833 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4834 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4839 if (dsc
->u
.branch
.link
)
4841 /* The value of LR should be the next insn of current one. In order
4842 not to confuse logic hanlding later insn `bx lr', if current insn mode
4843 is Thumb, the bit 0 of LR value should be set to 1. */
4844 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4847 next_insn_addr
|= 0x1;
4849 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4853 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4856 /* Copy B/BL/BLX instructions with immediate destinations. */
4859 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4860 arm_displaced_step_closure
*dsc
,
4861 unsigned int cond
, int exchange
, int link
, long offset
)
4863 /* Implement "BL<cond> <label>" as:
4865 Preparation: cond <- instruction condition
4866 Insn: mov r0, r0 (nop)
4867 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4869 B<cond> similar, but don't set r14 in cleanup. */
4871 dsc
->u
.branch
.cond
= cond
;
4872 dsc
->u
.branch
.link
= link
;
4873 dsc
->u
.branch
.exchange
= exchange
;
4875 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4876 if (link
&& exchange
)
4877 /* For BLX, offset is computed from the Align (PC, 4). */
4878 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4881 dsc
->u
.branch
.dest
+= 4 + offset
;
4883 dsc
->u
.branch
.dest
+= 8 + offset
;
4885 dsc
->cleanup
= &cleanup_branch
;
4888 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4889 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4891 unsigned int cond
= bits (insn
, 28, 31);
4892 int exchange
= (cond
== 0xf);
4893 int link
= exchange
|| bit (insn
, 24);
4896 if (debug_displaced
)
4897 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
4898 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
4899 (unsigned long) insn
);
4901 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4902 then arrange the switch into Thumb mode. */
4903 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
4905 offset
= bits (insn
, 0, 23) << 2;
4907 if (bit (offset
, 25))
4908 offset
= offset
| ~0x3ffffff;
4910 dsc
->modinsn
[0] = ARM_NOP
;
4912 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
4917 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
4918 uint16_t insn2
, struct regcache
*regs
,
4919 arm_displaced_step_closure
*dsc
)
4921 int link
= bit (insn2
, 14);
4922 int exchange
= link
&& !bit (insn2
, 12);
4925 int j1
= bit (insn2
, 13);
4926 int j2
= bit (insn2
, 11);
4927 int s
= sbits (insn1
, 10, 10);
4928 int i1
= !(j1
^ bit (insn1
, 10));
4929 int i2
= !(j2
^ bit (insn1
, 10));
4931 if (!link
&& !exchange
) /* B */
4933 offset
= (bits (insn2
, 0, 10) << 1);
4934 if (bit (insn2
, 12)) /* Encoding T4 */
4936 offset
|= (bits (insn1
, 0, 9) << 12)
4942 else /* Encoding T3 */
4944 offset
|= (bits (insn1
, 0, 5) << 12)
4948 cond
= bits (insn1
, 6, 9);
4953 offset
= (bits (insn1
, 0, 9) << 12);
4954 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
4955 offset
|= exchange
?
4956 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
4959 if (debug_displaced
)
4960 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
4961 "%.4x %.4x with offset %.8lx\n",
4962 link
? (exchange
) ? "blx" : "bl" : "b",
4963 insn1
, insn2
, offset
);
4965 dsc
->modinsn
[0] = THUMB_NOP
;
4967 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
4971 /* Copy B Thumb instructions. */
4973 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
4974 arm_displaced_step_closure
*dsc
)
4976 unsigned int cond
= 0;
4978 unsigned short bit_12_15
= bits (insn
, 12, 15);
4979 CORE_ADDR from
= dsc
->insn_addr
;
4981 if (bit_12_15
== 0xd)
4983 /* offset = SignExtend (imm8:0, 32) */
4984 offset
= sbits ((insn
<< 1), 0, 8);
4985 cond
= bits (insn
, 8, 11);
4987 else if (bit_12_15
== 0xe) /* Encoding T2 */
4989 offset
= sbits ((insn
<< 1), 0, 11);
4993 if (debug_displaced
)
4994 fprintf_unfiltered (gdb_stdlog
,
4995 "displaced: copying b immediate insn %.4x "
4996 "with offset %d\n", insn
, offset
);
4998 dsc
->u
.branch
.cond
= cond
;
4999 dsc
->u
.branch
.link
= 0;
5000 dsc
->u
.branch
.exchange
= 0;
5001 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5003 dsc
->modinsn
[0] = THUMB_NOP
;
5005 dsc
->cleanup
= &cleanup_branch
;
5010 /* Copy BX/BLX with register-specified destinations. */
5013 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5014 arm_displaced_step_closure
*dsc
, int link
,
5015 unsigned int cond
, unsigned int rm
)
5017 /* Implement {BX,BLX}<cond> <reg>" as:
5019 Preparation: cond <- instruction condition
5020 Insn: mov r0, r0 (nop)
5021 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5023 Don't set r14 in cleanup for BX. */
5025 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5027 dsc
->u
.branch
.cond
= cond
;
5028 dsc
->u
.branch
.link
= link
;
5030 dsc
->u
.branch
.exchange
= 1;
5032 dsc
->cleanup
= &cleanup_branch
;
5036 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5037 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5039 unsigned int cond
= bits (insn
, 28, 31);
5042 int link
= bit (insn
, 5);
5043 unsigned int rm
= bits (insn
, 0, 3);
5045 if (debug_displaced
)
5046 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5047 (unsigned long) insn
);
5049 dsc
->modinsn
[0] = ARM_NOP
;
5051 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5056 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5057 struct regcache
*regs
,
5058 arm_displaced_step_closure
*dsc
)
5060 int link
= bit (insn
, 7);
5061 unsigned int rm
= bits (insn
, 3, 6);
5063 if (debug_displaced
)
5064 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5065 (unsigned short) insn
);
5067 dsc
->modinsn
[0] = THUMB_NOP
;
5069 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5075 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5078 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5079 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5081 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5082 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5083 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5084 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5088 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5089 arm_displaced_step_closure
*dsc
)
5091 unsigned int rn
= bits (insn
, 16, 19);
5092 unsigned int rd
= bits (insn
, 12, 15);
5093 unsigned int op
= bits (insn
, 21, 24);
5094 int is_mov
= (op
== 0xd);
5095 ULONGEST rd_val
, rn_val
;
5097 if (!insn_references_pc (insn
, 0x000ff000ul
))
5098 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5100 if (debug_displaced
)
5101 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5102 "%.8lx\n", is_mov
? "move" : "ALU",
5103 (unsigned long) insn
);
5105 /* Instruction is of form:
5107 <op><cond> rd, [rn,] #imm
5111 Preparation: tmp1, tmp2 <- r0, r1;
5113 Insn: <op><cond> r0, r1, #imm
5114 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5117 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5118 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5119 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5120 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5121 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5122 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5126 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5128 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5130 dsc
->cleanup
= &cleanup_alu_imm
;
5136 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5137 uint16_t insn2
, struct regcache
*regs
,
5138 arm_displaced_step_closure
*dsc
)
5140 unsigned int op
= bits (insn1
, 5, 8);
5141 unsigned int rn
, rm
, rd
;
5142 ULONGEST rd_val
, rn_val
;
5144 rn
= bits (insn1
, 0, 3); /* Rn */
5145 rm
= bits (insn2
, 0, 3); /* Rm */
5146 rd
= bits (insn2
, 8, 11); /* Rd */
5148 /* This routine is only called for instruction MOV. */
5149 gdb_assert (op
== 0x2 && rn
== 0xf);
5151 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5152 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5154 if (debug_displaced
)
5155 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5156 "ALU", insn1
, insn2
);
5158 /* Instruction is of form:
5160 <op><cond> rd, [rn,] #imm
5164 Preparation: tmp1, tmp2 <- r0, r1;
5166 Insn: <op><cond> r0, r1, #imm
5167 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5170 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5171 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5172 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5173 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5174 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5175 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5178 dsc
->modinsn
[0] = insn1
;
5179 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5182 dsc
->cleanup
= &cleanup_alu_imm
;
5187 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5190 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5191 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5196 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5198 for (i
= 0; i
< 3; i
++)
5199 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5201 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5205 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5206 arm_displaced_step_closure
*dsc
,
5207 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5209 ULONGEST rd_val
, rn_val
, rm_val
;
5211 /* Instruction is of form:
5213 <op><cond> rd, [rn,] rm [, <shift>]
5217 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5218 r0, r1, r2 <- rd, rn, rm
5219 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5220 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5223 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5224 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5225 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5226 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5227 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5228 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5229 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5230 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5231 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5234 dsc
->cleanup
= &cleanup_alu_reg
;
5238 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5239 arm_displaced_step_closure
*dsc
)
5241 unsigned int op
= bits (insn
, 21, 24);
5242 int is_mov
= (op
== 0xd);
5244 if (!insn_references_pc (insn
, 0x000ff00ful
))
5245 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5247 if (debug_displaced
)
5248 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5249 is_mov
? "move" : "ALU", (unsigned long) insn
);
5252 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5254 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5256 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5262 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5263 struct regcache
*regs
,
5264 arm_displaced_step_closure
*dsc
)
5268 rm
= bits (insn
, 3, 6);
5269 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5271 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5272 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5274 if (debug_displaced
)
5275 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5276 (unsigned short) insn
);
5278 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5280 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5285 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5288 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5289 struct regcache
*regs
,
5290 arm_displaced_step_closure
*dsc
)
5292 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5295 for (i
= 0; i
< 4; i
++)
5296 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5298 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5302 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5303 arm_displaced_step_closure
*dsc
,
5304 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5308 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5310 /* Instruction is of form:
5312 <op><cond> rd, [rn,] rm, <shift> rs
5316 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5317 r0, r1, r2, r3 <- rd, rn, rm, rs
5318 Insn: <op><cond> r0, r1, r2, <shift> r3
5320 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5324 for (i
= 0; i
< 4; i
++)
5325 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5327 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5328 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5329 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5330 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5331 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5332 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5333 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5334 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5336 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5340 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5341 struct regcache
*regs
,
5342 arm_displaced_step_closure
*dsc
)
5344 unsigned int op
= bits (insn
, 21, 24);
5345 int is_mov
= (op
== 0xd);
5346 unsigned int rd
, rn
, rm
, rs
;
5348 if (!insn_references_pc (insn
, 0x000fff0ful
))
5349 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5351 if (debug_displaced
)
5352 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5353 "%.8lx\n", is_mov
? "move" : "ALU",
5354 (unsigned long) insn
);
5356 rn
= bits (insn
, 16, 19);
5357 rm
= bits (insn
, 0, 3);
5358 rs
= bits (insn
, 8, 11);
5359 rd
= bits (insn
, 12, 15);
5362 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5364 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5366 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5371 /* Clean up load instructions. */
5374 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5375 arm_displaced_step_closure
*dsc
)
5377 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5379 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5380 if (dsc
->u
.ldst
.xfersize
== 8)
5381 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5382 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5384 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5385 if (dsc
->u
.ldst
.xfersize
> 4)
5386 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5387 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5388 if (!dsc
->u
.ldst
.immed
)
5389 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5391 /* Handle register writeback. */
5392 if (dsc
->u
.ldst
.writeback
)
5393 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5394 /* Put result in right place. */
5395 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5396 if (dsc
->u
.ldst
.xfersize
== 8)
5397 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5400 /* Clean up store instructions. */
5403 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5404 arm_displaced_step_closure
*dsc
)
5406 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5408 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5409 if (dsc
->u
.ldst
.xfersize
> 4)
5410 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5411 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5412 if (!dsc
->u
.ldst
.immed
)
5413 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5414 if (!dsc
->u
.ldst
.restore_r4
)
5415 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5418 if (dsc
->u
.ldst
.writeback
)
5419 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5422 /* Copy "extra" load/store instructions. These are halfword/doubleword
5423 transfers, which have a different encoding to byte/word transfers. */
5426 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5427 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5429 unsigned int op1
= bits (insn
, 20, 24);
5430 unsigned int op2
= bits (insn
, 5, 6);
5431 unsigned int rt
= bits (insn
, 12, 15);
5432 unsigned int rn
= bits (insn
, 16, 19);
5433 unsigned int rm
= bits (insn
, 0, 3);
5434 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5435 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5436 int immed
= (op1
& 0x4) != 0;
5438 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5440 if (!insn_references_pc (insn
, 0x000ff00ful
))
5441 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5443 if (debug_displaced
)
5444 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5445 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5446 (unsigned long) insn
);
5448 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5451 internal_error (__FILE__
, __LINE__
,
5452 _("copy_extra_ld_st: instruction decode error"));
5454 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5455 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5456 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5458 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5460 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5461 if (bytesize
[opcode
] == 8)
5462 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5463 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5465 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5467 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5468 if (bytesize
[opcode
] == 8)
5469 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5470 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5472 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5475 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5476 dsc
->u
.ldst
.rn
= rn
;
5477 dsc
->u
.ldst
.immed
= immed
;
5478 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5479 dsc
->u
.ldst
.restore_r4
= 0;
5482 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5484 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5485 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5487 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5489 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5490 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5492 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5497 /* Copy byte/half word/word loads and stores. */
5500 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5501 arm_displaced_step_closure
*dsc
, int load
,
5502 int immed
, int writeback
, int size
, int usermode
,
5503 int rt
, int rm
, int rn
)
5505 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5507 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5508 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5510 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5512 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5514 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5515 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5517 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5519 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5520 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5522 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5524 dsc
->u
.ldst
.xfersize
= size
;
5525 dsc
->u
.ldst
.rn
= rn
;
5526 dsc
->u
.ldst
.immed
= immed
;
5527 dsc
->u
.ldst
.writeback
= writeback
;
5529 /* To write PC we can do:
5531 Before this sequence of instructions:
5532 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5533 r2 is the Rn value got from dispalced_read_reg.
5535 Insn1: push {pc} Write address of STR instruction + offset on stack
5536 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5537 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5538 = addr(Insn1) + offset - addr(Insn3) - 8
5540 Insn4: add r4, r4, #8 r4 = offset - 8
5541 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5543 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5545 Otherwise we don't know what value to write for PC, since the offset is
5546 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5547 of this can be found in Section "Saving from r15" in
5548 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5550 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5555 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5556 uint16_t insn2
, struct regcache
*regs
,
5557 arm_displaced_step_closure
*dsc
, int size
)
5559 unsigned int u_bit
= bit (insn1
, 7);
5560 unsigned int rt
= bits (insn2
, 12, 15);
5561 int imm12
= bits (insn2
, 0, 11);
5564 if (debug_displaced
)
5565 fprintf_unfiltered (gdb_stdlog
,
5566 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5567 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5573 /* Rewrite instruction LDR Rt imm12 into:
5575 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5579 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5582 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5583 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5584 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5586 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5588 pc_val
= pc_val
& 0xfffffffc;
5590 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5591 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5595 dsc
->u
.ldst
.xfersize
= size
;
5596 dsc
->u
.ldst
.immed
= 0;
5597 dsc
->u
.ldst
.writeback
= 0;
5598 dsc
->u
.ldst
.restore_r4
= 0;
5600 /* LDR R0, R2, R3 */
5601 dsc
->modinsn
[0] = 0xf852;
5602 dsc
->modinsn
[1] = 0x3;
5605 dsc
->cleanup
= &cleanup_load
;
5611 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5612 uint16_t insn2
, struct regcache
*regs
,
5613 arm_displaced_step_closure
*dsc
,
5614 int writeback
, int immed
)
5616 unsigned int rt
= bits (insn2
, 12, 15);
5617 unsigned int rn
= bits (insn1
, 0, 3);
5618 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5619 /* In LDR (register), there is also a register Rm, which is not allowed to
5620 be PC, so we don't have to check it. */
5622 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5623 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5626 if (debug_displaced
)
5627 fprintf_unfiltered (gdb_stdlog
,
5628 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5629 rt
, rn
, insn1
, insn2
);
5631 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5634 dsc
->u
.ldst
.restore_r4
= 0;
5637 /* ldr[b]<cond> rt, [rn, #imm], etc.
5639 ldr[b]<cond> r0, [r2, #imm]. */
5641 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5642 dsc
->modinsn
[1] = insn2
& 0x0fff;
5645 /* ldr[b]<cond> rt, [rn, rm], etc.
5647 ldr[b]<cond> r0, [r2, r3]. */
5649 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5650 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5660 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5661 struct regcache
*regs
,
5662 arm_displaced_step_closure
*dsc
,
5663 int load
, int size
, int usermode
)
5665 int immed
= !bit (insn
, 25);
5666 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5667 unsigned int rt
= bits (insn
, 12, 15);
5668 unsigned int rn
= bits (insn
, 16, 19);
5669 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5671 if (!insn_references_pc (insn
, 0x000ff00ful
))
5672 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5674 if (debug_displaced
)
5675 fprintf_unfiltered (gdb_stdlog
,
5676 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5677 load
? (size
== 1 ? "ldrb" : "ldr")
5678 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5680 (unsigned long) insn
);
5682 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5683 usermode
, rt
, rm
, rn
);
5685 if (load
|| rt
!= ARM_PC_REGNUM
)
5687 dsc
->u
.ldst
.restore_r4
= 0;
5690 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5692 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5693 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5695 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5697 {ldr,str}[b]<cond> r0, [r2, r3]. */
5698 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5702 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5703 dsc
->u
.ldst
.restore_r4
= 1;
5704 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5705 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5706 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5707 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5708 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5712 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5714 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5719 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5724 /* Cleanup LDM instructions with fully-populated register list. This is an
5725 unfortunate corner case: it's impossible to implement correctly by modifying
5726 the instruction. The issue is as follows: we have an instruction,
5730 which we must rewrite to avoid loading PC. A possible solution would be to
5731 do the load in two halves, something like (with suitable cleanup
5735 ldm[id][ab] r8!, {r0-r7}
5737 ldm[id][ab] r8, {r7-r14}
5740 but at present there's no suitable place for <temp>, since the scratch space
5741 is overwritten before the cleanup routine is called. For now, we simply
5742 emulate the instruction. */
5745 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5746 arm_displaced_step_closure
*dsc
)
5748 int inc
= dsc
->u
.block
.increment
;
5749 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5750 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5751 uint32_t regmask
= dsc
->u
.block
.regmask
;
5752 int regno
= inc
? 0 : 15;
5753 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5754 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5755 && (regmask
& 0x8000) != 0;
5756 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5757 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5758 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5763 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5764 sensible we can do here. Complain loudly. */
5765 if (exception_return
)
5766 error (_("Cannot single-step exception return"));
5768 /* We don't handle any stores here for now. */
5769 gdb_assert (dsc
->u
.block
.load
!= 0);
5771 if (debug_displaced
)
5772 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5773 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5774 dsc
->u
.block
.increment
? "inc" : "dec",
5775 dsc
->u
.block
.before
? "before" : "after");
5782 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5785 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5788 xfer_addr
+= bump_before
;
5790 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5791 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5793 xfer_addr
+= bump_after
;
5795 regmask
&= ~(1 << regno
);
5798 if (dsc
->u
.block
.writeback
)
5799 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5803 /* Clean up an STM which included the PC in the register list. */
5806 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5807 arm_displaced_step_closure
*dsc
)
5809 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5810 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5811 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5812 CORE_ADDR stm_insn_addr
;
5815 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5817 /* If condition code fails, there's nothing else to do. */
5818 if (!store_executed
)
5821 if (dsc
->u
.block
.increment
)
5823 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5825 if (dsc
->u
.block
.before
)
5830 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5832 if (dsc
->u
.block
.before
)
5836 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5837 stm_insn_addr
= dsc
->scratch_base
;
5838 offset
= pc_val
- stm_insn_addr
;
5840 if (debug_displaced
)
5841 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5842 "STM instruction\n", offset
);
5844 /* Rewrite the stored PC to the proper value for the non-displaced original
5846 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5847 dsc
->insn_addr
+ offset
);
5850 /* Clean up an LDM which includes the PC in the register list. We clumped all
5851 the registers in the transferred list into a contiguous range r0...rX (to
5852 avoid loading PC directly and losing control of the debugged program), so we
5853 must undo that here. */
5856 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5857 struct regcache
*regs
,
5858 arm_displaced_step_closure
*dsc
)
5860 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5861 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5862 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5863 unsigned int regs_loaded
= bitcount (mask
);
5864 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5866 /* The method employed here will fail if the register list is fully populated
5867 (we need to avoid loading PC directly). */
5868 gdb_assert (num_to_shuffle
< 16);
5873 clobbered
= (1 << num_to_shuffle
) - 1;
5875 while (num_to_shuffle
> 0)
5877 if ((mask
& (1 << write_reg
)) != 0)
5879 unsigned int read_reg
= num_to_shuffle
- 1;
5881 if (read_reg
!= write_reg
)
5883 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
5884 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
5885 if (debug_displaced
)
5886 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
5887 "loaded register r%d to r%d\n"), read_reg
,
5890 else if (debug_displaced
)
5891 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
5892 "r%d already in the right place\n"),
5895 clobbered
&= ~(1 << write_reg
);
5903 /* Restore any registers we scribbled over. */
5904 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
5906 if ((clobbered
& (1 << write_reg
)) != 0)
5908 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
5910 if (debug_displaced
)
5911 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
5912 "clobbered register r%d\n"), write_reg
);
5913 clobbered
&= ~(1 << write_reg
);
5917 /* Perform register writeback manually. */
5918 if (dsc
->u
.block
.writeback
)
5920 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
5922 if (dsc
->u
.block
.increment
)
5923 new_rn_val
+= regs_loaded
* 4;
5925 new_rn_val
-= regs_loaded
* 4;
5927 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
5932 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
5933 in user-level code (in particular exception return, ldm rn, {...pc}^). */
5936 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
5937 struct regcache
*regs
,
5938 arm_displaced_step_closure
*dsc
)
5940 int load
= bit (insn
, 20);
5941 int user
= bit (insn
, 22);
5942 int increment
= bit (insn
, 23);
5943 int before
= bit (insn
, 24);
5944 int writeback
= bit (insn
, 21);
5945 int rn
= bits (insn
, 16, 19);
5947 /* Block transfers which don't mention PC can be run directly
5949 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
5950 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
5952 if (rn
== ARM_PC_REGNUM
)
5954 warning (_("displaced: Unpredictable LDM or STM with "
5955 "base register r15"));
5956 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
5959 if (debug_displaced
)
5960 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
5961 "%.8lx\n", (unsigned long) insn
);
5963 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
5964 dsc
->u
.block
.rn
= rn
;
5966 dsc
->u
.block
.load
= load
;
5967 dsc
->u
.block
.user
= user
;
5968 dsc
->u
.block
.increment
= increment
;
5969 dsc
->u
.block
.before
= before
;
5970 dsc
->u
.block
.writeback
= writeback
;
5971 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
5973 dsc
->u
.block
.regmask
= insn
& 0xffff;
5977 if ((insn
& 0xffff) == 0xffff)
5979 /* LDM with a fully-populated register list. This case is
5980 particularly tricky. Implement for now by fully emulating the
5981 instruction (which might not behave perfectly in all cases, but
5982 these instructions should be rare enough for that not to matter
5984 dsc
->modinsn
[0] = ARM_NOP
;
5986 dsc
->cleanup
= &cleanup_block_load_all
;
5990 /* LDM of a list of registers which includes PC. Implement by
5991 rewriting the list of registers to be transferred into a
5992 contiguous chunk r0...rX before doing the transfer, then shuffling
5993 registers into the correct places in the cleanup routine. */
5994 unsigned int regmask
= insn
& 0xffff;
5995 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
5998 for (i
= 0; i
< num_in_list
; i
++)
5999 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6001 /* Writeback makes things complicated. We need to avoid clobbering
6002 the base register with one of the registers in our modified
6003 register list, but just using a different register can't work in
6006 ldm r14!, {r0-r13,pc}
6008 which would need to be rewritten as:
6012 but that can't work, because there's no free register for N.
6014 Solve this by turning off the writeback bit, and emulating
6015 writeback manually in the cleanup routine. */
6020 new_regmask
= (1 << num_in_list
) - 1;
6022 if (debug_displaced
)
6023 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6024 "{..., pc}: original reg list %.4x, modified "
6025 "list %.4x\n"), rn
, writeback
? "!" : "",
6026 (int) insn
& 0xffff, new_regmask
);
6028 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6030 dsc
->cleanup
= &cleanup_block_load_pc
;
6035 /* STM of a list of registers which includes PC. Run the instruction
6036 as-is, but out of line: this will store the wrong value for the PC,
6037 so we must manually fix up the memory in the cleanup routine.
6038 Doing things this way has the advantage that we can auto-detect
6039 the offset of the PC write (which is architecture-dependent) in
6040 the cleanup routine. */
6041 dsc
->modinsn
[0] = insn
;
6043 dsc
->cleanup
= &cleanup_block_store_pc
;
6050 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6051 struct regcache
*regs
,
6052 arm_displaced_step_closure
*dsc
)
6054 int rn
= bits (insn1
, 0, 3);
6055 int load
= bit (insn1
, 4);
6056 int writeback
= bit (insn1
, 5);
6058 /* Block transfers which don't mention PC can be run directly
6060 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6061 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6063 if (rn
== ARM_PC_REGNUM
)
6065 warning (_("displaced: Unpredictable LDM or STM with "
6066 "base register r15"));
6067 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6068 "unpredictable ldm/stm", dsc
);
6071 if (debug_displaced
)
6072 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6073 "%.4x%.4x\n", insn1
, insn2
);
6075 /* Clear bit 13, since it should be always zero. */
6076 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6077 dsc
->u
.block
.rn
= rn
;
6079 dsc
->u
.block
.load
= load
;
6080 dsc
->u
.block
.user
= 0;
6081 dsc
->u
.block
.increment
= bit (insn1
, 7);
6082 dsc
->u
.block
.before
= bit (insn1
, 8);
6083 dsc
->u
.block
.writeback
= writeback
;
6084 dsc
->u
.block
.cond
= INST_AL
;
6085 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6089 if (dsc
->u
.block
.regmask
== 0xffff)
6091 /* This branch is impossible to happen. */
6096 unsigned int regmask
= dsc
->u
.block
.regmask
;
6097 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6100 for (i
= 0; i
< num_in_list
; i
++)
6101 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6106 new_regmask
= (1 << num_in_list
) - 1;
6108 if (debug_displaced
)
6109 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6110 "{..., pc}: original reg list %.4x, modified "
6111 "list %.4x\n"), rn
, writeback
? "!" : "",
6112 (int) dsc
->u
.block
.regmask
, new_regmask
);
6114 dsc
->modinsn
[0] = insn1
;
6115 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6118 dsc
->cleanup
= &cleanup_block_load_pc
;
6123 dsc
->modinsn
[0] = insn1
;
6124 dsc
->modinsn
[1] = insn2
;
6126 dsc
->cleanup
= &cleanup_block_store_pc
;
6131 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6132 This is used to avoid a dependency on BFD's bfd_endian enum. */
6135 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6138 return read_memory_unsigned_integer (memaddr
, len
,
6139 (enum bfd_endian
) byte_order
);
6142 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6145 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6148 return gdbarch_addr_bits_remove (self
->regcache
->arch (), val
);
6151 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6154 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6159 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6162 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6164 return arm_is_thumb (self
->regcache
);
6167 /* single_step() is called just before we want to resume the inferior,
6168 if we want to single-step it but there is no hardware or kernel
6169 single-step support. We find the target of the coming instructions
6170 and breakpoint them. */
6172 std::vector
<CORE_ADDR
>
6173 arm_software_single_step (struct regcache
*regcache
)
6175 struct gdbarch
*gdbarch
= regcache
->arch ();
6176 struct arm_get_next_pcs next_pcs_ctx
;
6178 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6179 &arm_get_next_pcs_ops
,
6180 gdbarch_byte_order (gdbarch
),
6181 gdbarch_byte_order_for_code (gdbarch
),
6185 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6187 for (CORE_ADDR
&pc_ref
: next_pcs
)
6188 pc_ref
= gdbarch_addr_bits_remove (gdbarch
, pc_ref
);
6193 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6194 for Linux, where some SVC instructions must be treated specially. */
6197 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6198 arm_displaced_step_closure
*dsc
)
6200 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6202 if (debug_displaced
)
6203 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6204 "%.8lx\n", (unsigned long) resume_addr
);
6206 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6210 /* Common copy routine for svc instruciton. */
6213 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6214 arm_displaced_step_closure
*dsc
)
6216 /* Preparation: none.
6217 Insn: unmodified svc.
6218 Cleanup: pc <- insn_addr + insn_size. */
6220 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6222 dsc
->wrote_to_pc
= 1;
6224 /* Allow OS-specific code to override SVC handling. */
6225 if (dsc
->u
.svc
.copy_svc_os
)
6226 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6229 dsc
->cleanup
= &cleanup_svc
;
6235 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6236 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6239 if (debug_displaced
)
6240 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6241 (unsigned long) insn
);
6243 dsc
->modinsn
[0] = insn
;
6245 return install_svc (gdbarch
, regs
, dsc
);
6249 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6250 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6253 if (debug_displaced
)
6254 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6257 dsc
->modinsn
[0] = insn
;
6259 return install_svc (gdbarch
, regs
, dsc
);
6262 /* Copy undefined instructions. */
6265 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6266 arm_displaced_step_closure
*dsc
)
6268 if (debug_displaced
)
6269 fprintf_unfiltered (gdb_stdlog
,
6270 "displaced: copying undefined insn %.8lx\n",
6271 (unsigned long) insn
);
6273 dsc
->modinsn
[0] = insn
;
6279 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6280 arm_displaced_step_closure
*dsc
)
6283 if (debug_displaced
)
6284 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6285 "%.4x %.4x\n", (unsigned short) insn1
,
6286 (unsigned short) insn2
);
6288 dsc
->modinsn
[0] = insn1
;
6289 dsc
->modinsn
[1] = insn2
;
6295 /* Copy unpredictable instructions. */
6298 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6299 arm_displaced_step_closure
*dsc
)
6301 if (debug_displaced
)
6302 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6303 "%.8lx\n", (unsigned long) insn
);
6305 dsc
->modinsn
[0] = insn
;
6310 /* The decode_* functions are instruction decoding helpers. They mostly follow
6311 the presentation in the ARM ARM. */
6314 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6315 struct regcache
*regs
,
6316 arm_displaced_step_closure
*dsc
)
6318 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6319 unsigned int rn
= bits (insn
, 16, 19);
6321 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0x1) == 0x0)
6322 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6323 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0x1) == 0x1)
6324 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6325 else if ((op1
& 0x60) == 0x20)
6326 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6327 else if ((op1
& 0x71) == 0x40)
6328 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6330 else if ((op1
& 0x77) == 0x41)
6331 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6332 else if ((op1
& 0x77) == 0x45)
6333 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6334 else if ((op1
& 0x77) == 0x51)
6337 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6339 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6341 else if ((op1
& 0x77) == 0x55)
6342 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6343 else if (op1
== 0x57)
6346 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6347 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6348 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6349 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6350 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6352 else if ((op1
& 0x63) == 0x43)
6353 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6354 else if ((op2
& 0x1) == 0x0)
6355 switch (op1
& ~0x80)
6358 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6360 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6361 case 0x71: case 0x75:
6363 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6364 case 0x63: case 0x67: case 0x73: case 0x77:
6365 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6367 return arm_copy_undef (gdbarch
, insn
, dsc
);
6370 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6374 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6375 struct regcache
*regs
,
6376 arm_displaced_step_closure
*dsc
)
6378 if (bit (insn
, 27) == 0)
6379 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6380 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6381 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6384 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6387 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6389 case 0x4: case 0x5: case 0x6: case 0x7:
6390 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6393 switch ((insn
& 0xe00000) >> 21)
6395 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6397 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6400 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6403 return arm_copy_undef (gdbarch
, insn
, dsc
);
6408 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6409 switch ((insn
& 0xe00000) >> 21)
6412 /* ldc/ldc2 imm (undefined for rn == pc). */
6413 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6414 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6417 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6419 case 0x4: case 0x5: case 0x6: case 0x7:
6420 /* ldc/ldc2 lit (undefined for rn != pc). */
6421 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6422 : arm_copy_undef (gdbarch
, insn
, dsc
);
6425 return arm_copy_undef (gdbarch
, insn
, dsc
);
6430 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6433 if (bits (insn
, 16, 19) == 0xf)
6435 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6437 return arm_copy_undef (gdbarch
, insn
, dsc
);
6441 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6443 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6447 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6449 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6452 return arm_copy_undef (gdbarch
, insn
, dsc
);
6456 /* Decode miscellaneous instructions in dp/misc encoding space. */
6459 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6460 struct regcache
*regs
,
6461 arm_displaced_step_closure
*dsc
)
6463 unsigned int op2
= bits (insn
, 4, 6);
6464 unsigned int op
= bits (insn
, 21, 22);
6469 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6472 if (op
== 0x1) /* bx. */
6473 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6475 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6477 return arm_copy_undef (gdbarch
, insn
, dsc
);
6481 /* Not really supported. */
6482 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6484 return arm_copy_undef (gdbarch
, insn
, dsc
);
6488 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6489 regs
, dsc
); /* blx register. */
6491 return arm_copy_undef (gdbarch
, insn
, dsc
);
6494 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6498 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6500 /* Not really supported. */
6501 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6505 return arm_copy_undef (gdbarch
, insn
, dsc
);
6510 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6511 struct regcache
*regs
,
6512 arm_displaced_step_closure
*dsc
)
6515 switch (bits (insn
, 20, 24))
6518 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6521 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6523 case 0x12: case 0x16:
6524 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6527 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6531 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6533 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6534 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6535 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6536 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6537 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6538 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6539 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6540 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6541 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6542 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6543 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6544 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6545 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6546 /* 2nd arg means "unprivileged". */
6547 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6551 /* Should be unreachable. */
6556 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6557 struct regcache
*regs
,
6558 arm_displaced_step_closure
*dsc
)
6560 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6561 uint32_t op1
= bits (insn
, 20, 24);
6563 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6564 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6565 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6566 else if ((!a
&& (op1
& 0x17) == 0x02)
6567 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6568 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6569 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6570 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6571 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6572 else if ((!a
&& (op1
& 0x17) == 0x03)
6573 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6574 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6575 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6576 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6577 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6578 else if ((!a
&& (op1
& 0x17) == 0x06)
6579 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6580 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6581 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6582 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6583 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6584 else if ((!a
&& (op1
& 0x17) == 0x07)
6585 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6586 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6588 /* Should be unreachable. */
6593 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6594 arm_displaced_step_closure
*dsc
)
6596 switch (bits (insn
, 20, 24))
6598 case 0x00: case 0x01: case 0x02: case 0x03:
6599 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6601 case 0x04: case 0x05: case 0x06: case 0x07:
6602 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6604 case 0x08: case 0x09: case 0x0a: case 0x0b:
6605 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6606 return arm_copy_unmodified (gdbarch
, insn
,
6607 "decode/pack/unpack/saturate/reverse", dsc
);
6610 if (bits (insn
, 5, 7) == 0) /* op2. */
6612 if (bits (insn
, 12, 15) == 0xf)
6613 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6615 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6618 return arm_copy_undef (gdbarch
, insn
, dsc
);
6620 case 0x1a: case 0x1b:
6621 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6622 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6624 return arm_copy_undef (gdbarch
, insn
, dsc
);
6626 case 0x1c: case 0x1d:
6627 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6629 if (bits (insn
, 0, 3) == 0xf)
6630 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6632 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6635 return arm_copy_undef (gdbarch
, insn
, dsc
);
6637 case 0x1e: case 0x1f:
6638 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6639 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6641 return arm_copy_undef (gdbarch
, insn
, dsc
);
6644 /* Should be unreachable. */
6649 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6650 struct regcache
*regs
,
6651 arm_displaced_step_closure
*dsc
)
6654 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6656 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6660 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6661 struct regcache
*regs
,
6662 arm_displaced_step_closure
*dsc
)
6664 unsigned int opcode
= bits (insn
, 20, 24);
6668 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6669 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6671 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6672 case 0x12: case 0x16:
6673 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6675 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6676 case 0x13: case 0x17:
6677 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6679 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6680 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6681 /* Note: no writeback for these instructions. Bit 25 will always be
6682 zero though (via caller), so the following works OK. */
6683 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6686 /* Should be unreachable. */
6690 /* Decode shifted register instructions. */
6693 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6694 uint16_t insn2
, struct regcache
*regs
,
6695 arm_displaced_step_closure
*dsc
)
6697 /* PC is only allowed to be used in instruction MOV. */
6699 unsigned int op
= bits (insn1
, 5, 8);
6700 unsigned int rn
= bits (insn1
, 0, 3);
6702 if (op
== 0x2 && rn
== 0xf) /* MOV */
6703 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6705 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6706 "dp (shift reg)", dsc
);
6710 /* Decode extension register load/store. Exactly the same as
6711 arm_decode_ext_reg_ld_st. */
6714 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6715 uint16_t insn2
, struct regcache
*regs
,
6716 arm_displaced_step_closure
*dsc
)
6718 unsigned int opcode
= bits (insn1
, 4, 8);
6722 case 0x04: case 0x05:
6723 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6724 "vfp/neon vmov", dsc
);
6726 case 0x08: case 0x0c: /* 01x00 */
6727 case 0x0a: case 0x0e: /* 01x10 */
6728 case 0x12: case 0x16: /* 10x10 */
6729 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6730 "vfp/neon vstm/vpush", dsc
);
6732 case 0x09: case 0x0d: /* 01x01 */
6733 case 0x0b: case 0x0f: /* 01x11 */
6734 case 0x13: case 0x17: /* 10x11 */
6735 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6736 "vfp/neon vldm/vpop", dsc
);
6738 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6739 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6741 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6742 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6745 /* Should be unreachable. */
6750 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6751 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6753 unsigned int op1
= bits (insn
, 20, 25);
6754 int op
= bit (insn
, 4);
6755 unsigned int coproc
= bits (insn
, 8, 11);
6757 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6758 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6759 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6760 && (coproc
& 0xe) != 0xa)
6762 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6763 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6764 && (coproc
& 0xe) != 0xa)
6765 /* ldc/ldc2 imm/lit. */
6766 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6767 else if ((op1
& 0x3e) == 0x00)
6768 return arm_copy_undef (gdbarch
, insn
, dsc
);
6769 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6770 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6771 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6772 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6773 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6774 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6775 else if ((op1
& 0x30) == 0x20 && !op
)
6777 if ((coproc
& 0xe) == 0xa)
6778 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6780 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6782 else if ((op1
& 0x30) == 0x20 && op
)
6783 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6784 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6785 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6786 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6787 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6788 else if ((op1
& 0x30) == 0x30)
6789 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6791 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6795 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6796 uint16_t insn2
, struct regcache
*regs
,
6797 arm_displaced_step_closure
*dsc
)
6799 unsigned int coproc
= bits (insn2
, 8, 11);
6800 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6801 unsigned int bit_9
= bit (insn1
, 9);
6802 unsigned int bit_4
= bit (insn1
, 4);
6807 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6808 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6810 else if (bit_5_8
== 0) /* UNDEFINED. */
6811 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6814 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6815 if ((coproc
& 0xe) == 0xa)
6816 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6818 else /* coproc is not 101x. */
6820 if (bit_4
== 0) /* STC/STC2. */
6821 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6823 else /* LDC/LDC2 {literal, immeidate}. */
6824 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6830 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6836 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6837 arm_displaced_step_closure
*dsc
, int rd
)
6843 Preparation: Rd <- PC
6849 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6850 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6854 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6855 arm_displaced_step_closure
*dsc
,
6856 int rd
, unsigned int imm
)
6859 /* Encoding T2: ADDS Rd, #imm */
6860 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6862 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6868 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6869 struct regcache
*regs
,
6870 arm_displaced_step_closure
*dsc
)
6872 unsigned int rd
= bits (insn
, 8, 10);
6873 unsigned int imm8
= bits (insn
, 0, 7);
6875 if (debug_displaced
)
6876 fprintf_unfiltered (gdb_stdlog
,
6877 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6880 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
6884 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
6885 uint16_t insn2
, struct regcache
*regs
,
6886 arm_displaced_step_closure
*dsc
)
6888 unsigned int rd
= bits (insn2
, 8, 11);
6889 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6890 extract raw immediate encoding rather than computing immediate. When
6891 generating ADD or SUB instruction, we can simply perform OR operation to
6892 set immediate into ADD. */
6893 unsigned int imm_3_8
= insn2
& 0x70ff;
6894 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
6896 if (debug_displaced
)
6897 fprintf_unfiltered (gdb_stdlog
,
6898 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
6899 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
6901 if (bit (insn1
, 7)) /* Encoding T2 */
6903 /* Encoding T3: SUB Rd, Rd, #imm */
6904 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
6905 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
6907 else /* Encoding T3 */
6909 /* Encoding T3: ADD Rd, Rd, #imm */
6910 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
6911 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
6915 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6921 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6922 struct regcache
*regs
,
6923 arm_displaced_step_closure
*dsc
)
6925 unsigned int rt
= bits (insn1
, 8, 10);
6927 int imm8
= (bits (insn1
, 0, 7) << 2);
6933 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
6935 Insn: LDR R0, [R2, R3];
6936 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
6938 if (debug_displaced
)
6939 fprintf_unfiltered (gdb_stdlog
,
6940 "displaced: copying thumb ldr r%d [pc #%d]\n"
6943 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6944 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6945 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6946 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6947 /* The assembler calculates the required value of the offset from the
6948 Align(PC,4) value of this instruction to the label. */
6949 pc
= pc
& 0xfffffffc;
6951 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
6952 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
6955 dsc
->u
.ldst
.xfersize
= 4;
6957 dsc
->u
.ldst
.immed
= 0;
6958 dsc
->u
.ldst
.writeback
= 0;
6959 dsc
->u
.ldst
.restore_r4
= 0;
6961 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
6963 dsc
->cleanup
= &cleanup_load
;
6968 /* Copy Thumb cbnz/cbz insruction. */
6971 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
6972 struct regcache
*regs
,
6973 arm_displaced_step_closure
*dsc
)
6975 int non_zero
= bit (insn1
, 11);
6976 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
6977 CORE_ADDR from
= dsc
->insn_addr
;
6978 int rn
= bits (insn1
, 0, 2);
6979 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6981 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
6982 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
6983 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
6984 condition is false, let it be, cleanup_branch will do nothing. */
6985 if (dsc
->u
.branch
.cond
)
6987 dsc
->u
.branch
.cond
= INST_AL
;
6988 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
6991 dsc
->u
.branch
.dest
= from
+ 2;
6993 dsc
->u
.branch
.link
= 0;
6994 dsc
->u
.branch
.exchange
= 0;
6996 if (debug_displaced
)
6997 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
6998 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
6999 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7001 dsc
->modinsn
[0] = THUMB_NOP
;
7003 dsc
->cleanup
= &cleanup_branch
;
7007 /* Copy Table Branch Byte/Halfword */
7009 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7010 uint16_t insn2
, struct regcache
*regs
,
7011 arm_displaced_step_closure
*dsc
)
7013 ULONGEST rn_val
, rm_val
;
7014 int is_tbh
= bit (insn2
, 4);
7015 CORE_ADDR halfwords
= 0;
7016 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7018 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7019 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7025 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7026 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7032 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7033 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7036 if (debug_displaced
)
7037 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7038 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7039 (unsigned int) rn_val
, (unsigned int) rm_val
,
7040 (unsigned int) halfwords
);
7042 dsc
->u
.branch
.cond
= INST_AL
;
7043 dsc
->u
.branch
.link
= 0;
7044 dsc
->u
.branch
.exchange
= 0;
7045 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7047 dsc
->cleanup
= &cleanup_branch
;
7053 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7054 arm_displaced_step_closure
*dsc
)
7057 int val
= displaced_read_reg (regs
, dsc
, 7);
7058 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7061 val
= displaced_read_reg (regs
, dsc
, 8);
7062 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7065 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7070 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7071 struct regcache
*regs
,
7072 arm_displaced_step_closure
*dsc
)
7074 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7076 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7079 (1) register list is full, that is, r0-r7 are used.
7080 Prepare: tmp[0] <- r8
7082 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7083 MOV r8, r7; Move value of r7 to r8;
7084 POP {r7}; Store PC value into r7.
7086 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7088 (2) register list is not full, supposing there are N registers in
7089 register list (except PC, 0 <= N <= 7).
7090 Prepare: for each i, 0 - N, tmp[i] <- ri.
7092 POP {r0, r1, ...., rN};
7094 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7095 from tmp[] properly.
7097 if (debug_displaced
)
7098 fprintf_unfiltered (gdb_stdlog
,
7099 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7100 dsc
->u
.block
.regmask
, insn1
);
7102 if (dsc
->u
.block
.regmask
== 0xff)
7104 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7106 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7107 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7108 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7111 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7115 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7117 unsigned int new_regmask
;
7119 for (i
= 0; i
< num_in_list
+ 1; i
++)
7120 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7122 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7124 if (debug_displaced
)
7125 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7126 "{..., pc}: original reg list %.4x,"
7127 " modified list %.4x\n"),
7128 (int) dsc
->u
.block
.regmask
, new_regmask
);
7130 dsc
->u
.block
.regmask
|= 0x8000;
7131 dsc
->u
.block
.writeback
= 0;
7132 dsc
->u
.block
.cond
= INST_AL
;
7134 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7136 dsc
->cleanup
= &cleanup_block_load_pc
;
7143 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7144 struct regcache
*regs
,
7145 arm_displaced_step_closure
*dsc
)
7147 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7148 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7151 /* 16-bit thumb instructions. */
7152 switch (op_bit_12_15
)
7154 /* Shift (imme), add, subtract, move and compare. */
7155 case 0: case 1: case 2: case 3:
7156 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7157 "shift/add/sub/mov/cmp",
7161 switch (op_bit_10_11
)
7163 case 0: /* Data-processing */
7164 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7168 case 1: /* Special data instructions and branch and exchange. */
7170 unsigned short op
= bits (insn1
, 7, 9);
7171 if (op
== 6 || op
== 7) /* BX or BLX */
7172 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7173 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7174 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7176 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7180 default: /* LDR (literal) */
7181 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7184 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7185 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7188 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7189 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7190 else /* Generate SP-relative address */
7191 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7193 case 11: /* Misc 16-bit instructions */
7195 switch (bits (insn1
, 8, 11))
7197 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7198 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7200 case 12: case 13: /* POP */
7201 if (bit (insn1
, 8)) /* PC is in register list. */
7202 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7204 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7206 case 15: /* If-Then, and hints */
7207 if (bits (insn1
, 0, 3))
7208 /* If-Then makes up to four following instructions conditional.
7209 IT instruction itself is not conditional, so handle it as a
7210 common unmodified instruction. */
7211 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7214 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7217 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7222 if (op_bit_10_11
< 2) /* Store multiple registers */
7223 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7224 else /* Load multiple registers */
7225 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7227 case 13: /* Conditional branch and supervisor call */
7228 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7229 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7231 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7233 case 14: /* Unconditional branch */
7234 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7241 internal_error (__FILE__
, __LINE__
,
7242 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7246 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7247 uint16_t insn1
, uint16_t insn2
,
7248 struct regcache
*regs
,
7249 arm_displaced_step_closure
*dsc
)
7251 int rt
= bits (insn2
, 12, 15);
7252 int rn
= bits (insn1
, 0, 3);
7253 int op1
= bits (insn1
, 7, 8);
7255 switch (bits (insn1
, 5, 6))
7257 case 0: /* Load byte and memory hints */
7258 if (rt
== 0xf) /* PLD/PLI */
7261 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7262 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7264 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7269 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7270 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7273 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7274 "ldrb{reg, immediate}/ldrbt",
7279 case 1: /* Load halfword and memory hints. */
7280 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7281 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7282 "pld/unalloc memhint", dsc
);
7286 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7289 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7293 case 2: /* Load word */
7295 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7298 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7299 else if (op1
== 0x1) /* Encoding T3 */
7300 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7302 else /* op1 == 0x0 */
7304 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7305 /* LDR (immediate) */
7306 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7307 dsc
, bit (insn2
, 8), 1);
7308 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7309 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7312 /* LDR (register) */
7313 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7319 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7326 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7327 uint16_t insn2
, struct regcache
*regs
,
7328 arm_displaced_step_closure
*dsc
)
7331 unsigned short op
= bit (insn2
, 15);
7332 unsigned int op1
= bits (insn1
, 11, 12);
7338 switch (bits (insn1
, 9, 10))
7343 /* Load/store {dual, execlusive}, table branch. */
7344 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7345 && bits (insn2
, 5, 7) == 0)
7346 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7349 /* PC is not allowed to use in load/store {dual, exclusive}
7351 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7352 "load/store dual/ex", dsc
);
7354 else /* load/store multiple */
7356 switch (bits (insn1
, 7, 8))
7358 case 0: case 3: /* SRS, RFE */
7359 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7362 case 1: case 2: /* LDM/STM/PUSH/POP */
7363 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7370 /* Data-processing (shift register). */
7371 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7374 default: /* Coprocessor instructions. */
7375 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7380 case 2: /* op1 = 2 */
7381 if (op
) /* Branch and misc control. */
7383 if (bit (insn2
, 14) /* BLX/BL */
7384 || bit (insn2
, 12) /* Unconditional branch */
7385 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7386 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7388 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7393 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7395 int dp_op
= bits (insn1
, 4, 8);
7396 int rn
= bits (insn1
, 0, 3);
7397 if ((dp_op
== 0 || dp_op
== 0xa) && rn
== 0xf)
7398 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7401 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7404 else /* Data processing (modified immeidate) */
7405 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7409 case 3: /* op1 = 3 */
7410 switch (bits (insn1
, 9, 10))
7414 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7416 else /* NEON Load/Store and Store single data item */
7417 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7418 "neon elt/struct load/store",
7421 case 1: /* op1 = 3, bits (9, 10) == 1 */
7422 switch (bits (insn1
, 7, 8))
7424 case 0: case 1: /* Data processing (register) */
7425 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7428 case 2: /* Multiply and absolute difference */
7429 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7430 "mul/mua/diff", dsc
);
7432 case 3: /* Long multiply and divide */
7433 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7438 default: /* Coprocessor instructions */
7439 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7448 internal_error (__FILE__
, __LINE__
,
7449 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7454 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7455 struct regcache
*regs
,
7456 arm_displaced_step_closure
*dsc
)
7458 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7460 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7462 if (debug_displaced
)
7463 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7464 "at %.8lx\n", insn1
, (unsigned long) from
);
7467 dsc
->insn_size
= thumb_insn_size (insn1
);
7468 if (thumb_insn_size (insn1
) == 4)
7471 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7472 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7475 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7479 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7480 CORE_ADDR to
, struct regcache
*regs
,
7481 arm_displaced_step_closure
*dsc
)
7484 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7487 /* Most displaced instructions use a 1-instruction scratch space, so set this
7488 here and override below if/when necessary. */
7490 dsc
->insn_addr
= from
;
7491 dsc
->scratch_base
= to
;
7492 dsc
->cleanup
= NULL
;
7493 dsc
->wrote_to_pc
= 0;
7495 if (!displaced_in_arm_mode (regs
))
7496 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7500 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7501 if (debug_displaced
)
7502 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7503 "at %.8lx\n", (unsigned long) insn
,
7504 (unsigned long) from
);
7506 if ((insn
& 0xf0000000) == 0xf0000000)
7507 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7508 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7510 case 0x0: case 0x1: case 0x2: case 0x3:
7511 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7514 case 0x4: case 0x5: case 0x6:
7515 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7519 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7522 case 0x8: case 0x9: case 0xa: case 0xb:
7523 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7526 case 0xc: case 0xd: case 0xe: case 0xf:
7527 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7532 internal_error (__FILE__
, __LINE__
,
7533 _("arm_process_displaced_insn: Instruction decode error"));
7536 /* Actually set up the scratch space for a displaced instruction. */
7539 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7540 CORE_ADDR to
, arm_displaced_step_closure
*dsc
)
7542 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7543 unsigned int i
, len
, offset
;
7544 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7545 int size
= dsc
->is_thumb
? 2 : 4;
7546 const gdb_byte
*bkp_insn
;
7549 /* Poke modified instruction(s). */
7550 for (i
= 0; i
< dsc
->numinsns
; i
++)
7552 if (debug_displaced
)
7554 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7556 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7559 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7560 (unsigned short)dsc
->modinsn
[i
]);
7562 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7563 (unsigned long) to
+ offset
);
7566 write_memory_unsigned_integer (to
+ offset
, size
,
7567 byte_order_for_code
,
7572 /* Choose the correct breakpoint instruction. */
7575 bkp_insn
= tdep
->thumb_breakpoint
;
7576 len
= tdep
->thumb_breakpoint_size
;
7580 bkp_insn
= tdep
->arm_breakpoint
;
7581 len
= tdep
->arm_breakpoint_size
;
7584 /* Put breakpoint afterwards. */
7585 write_memory (to
+ offset
, bkp_insn
, len
);
7587 if (debug_displaced
)
7588 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7589 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7592 /* Entry point for cleaning things up after a displaced instruction has been
7596 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7597 struct displaced_step_closure
*dsc_
,
7598 CORE_ADDR from
, CORE_ADDR to
,
7599 struct regcache
*regs
)
7601 arm_displaced_step_closure
*dsc
= (arm_displaced_step_closure
*) dsc_
;
7604 dsc
->cleanup (gdbarch
, regs
, dsc
);
7606 if (!dsc
->wrote_to_pc
)
7607 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7608 dsc
->insn_addr
+ dsc
->insn_size
);
7612 #include "bfd-in2.h"
7613 #include "libcoff.h"
7616 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7618 gdb_disassembler
*di
7619 = static_cast<gdb_disassembler
*>(info
->application_data
);
7620 struct gdbarch
*gdbarch
= di
->arch ();
7622 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7624 static asymbol
*asym
;
7625 static combined_entry_type ce
;
7626 static struct coff_symbol_struct csym
;
7627 static struct bfd fake_bfd
;
7628 static bfd_target fake_target
;
7630 if (csym
.native
== NULL
)
7632 /* Create a fake symbol vector containing a Thumb symbol.
7633 This is solely so that the code in print_insn_little_arm()
7634 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7635 the presence of a Thumb symbol and switch to decoding
7636 Thumb instructions. */
7638 fake_target
.flavour
= bfd_target_coff_flavour
;
7639 fake_bfd
.xvec
= &fake_target
;
7640 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7642 csym
.symbol
.the_bfd
= &fake_bfd
;
7643 csym
.symbol
.name
= "fake";
7644 asym
= (asymbol
*) & csym
;
7647 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7648 info
->symbols
= &asym
;
7651 info
->symbols
= NULL
;
7653 /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
7654 accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
7655 opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
7656 the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
7657 in default_print_insn. */
7658 if (exec_bfd
!= NULL
)
7659 info
->flags
|= USER_SPECIFIED_MACHINE_TYPE
;
7661 return default_print_insn (memaddr
, info
);
7664 /* The following define instruction sequences that will cause ARM
7665 cpu's to take an undefined instruction trap. These are used to
7666 signal a breakpoint to GDB.
7668 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7669 modes. A different instruction is required for each mode. The ARM
7670 cpu's can also be big or little endian. Thus four different
7671 instructions are needed to support all cases.
7673 Note: ARMv4 defines several new instructions that will take the
7674 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7675 not in fact add the new instructions. The new undefined
7676 instructions in ARMv4 are all instructions that had no defined
7677 behaviour in earlier chips. There is no guarantee that they will
7678 raise an exception, but may be treated as NOP's. In practice, it
7679 may only safe to rely on instructions matching:
7681 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7682 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7683 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7685 Even this may only true if the condition predicate is true. The
7686 following use a condition predicate of ALWAYS so it is always TRUE.
7688 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7689 and NetBSD all use a software interrupt rather than an undefined
7690 instruction to force a trap. This can be handled by by the
7691 abi-specific code during establishment of the gdbarch vector. */
7693 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7694 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7695 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7696 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7698 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7699 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7700 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7701 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7703 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7706 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7708 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7709 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7711 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7713 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7715 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7716 check whether we are replacing a 32-bit instruction. */
7717 if (tdep
->thumb2_breakpoint
!= NULL
)
7721 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7723 unsigned short inst1
;
7725 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7726 if (thumb_insn_size (inst1
) == 4)
7727 return ARM_BP_KIND_THUMB2
;
7731 return ARM_BP_KIND_THUMB
;
7734 return ARM_BP_KIND_ARM
;
7738 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7740 static const gdb_byte
*
7741 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7747 case ARM_BP_KIND_ARM
:
7748 *size
= tdep
->arm_breakpoint_size
;
7749 return tdep
->arm_breakpoint
;
7750 case ARM_BP_KIND_THUMB
:
7751 *size
= tdep
->thumb_breakpoint_size
;
7752 return tdep
->thumb_breakpoint
;
7753 case ARM_BP_KIND_THUMB2
:
7754 *size
= tdep
->thumb2_breakpoint_size
;
7755 return tdep
->thumb2_breakpoint
;
7757 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7761 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7764 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7765 struct regcache
*regcache
,
7770 /* Check the memory pointed by PC is readable. */
7771 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7773 struct arm_get_next_pcs next_pcs_ctx
;
7775 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7776 &arm_get_next_pcs_ops
,
7777 gdbarch_byte_order (gdbarch
),
7778 gdbarch_byte_order_for_code (gdbarch
),
7782 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7784 /* If MEMADDR is the next instruction of current pc, do the
7785 software single step computation, and get the thumb mode by
7786 the destination address. */
7787 for (CORE_ADDR pc
: next_pcs
)
7789 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7791 if (IS_THUMB_ADDR (pc
))
7793 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7794 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7797 return ARM_BP_KIND_ARM
;
7802 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7805 /* Extract from an array REGBUF containing the (raw) register state a
7806 function return value of type TYPE, and copy that, in virtual
7807 format, into VALBUF. */
7810 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7813 struct gdbarch
*gdbarch
= regs
->arch ();
7814 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7816 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7818 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7822 /* The value is in register F0 in internal format. We need to
7823 extract the raw value and then convert it to the desired
7825 bfd_byte tmpbuf
[ARM_FP_REGISTER_SIZE
];
7827 regs
->cooked_read (ARM_F0_REGNUM
, tmpbuf
);
7828 target_float_convert (tmpbuf
, arm_ext_type (gdbarch
),
7833 case ARM_FLOAT_SOFT_FPA
:
7834 case ARM_FLOAT_SOFT_VFP
:
7835 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7836 not using the VFP ABI code. */
7838 regs
->cooked_read (ARM_A1_REGNUM
, valbuf
);
7839 if (TYPE_LENGTH (type
) > 4)
7840 regs
->cooked_read (ARM_A1_REGNUM
+ 1,
7841 valbuf
+ ARM_INT_REGISTER_SIZE
);
7845 internal_error (__FILE__
, __LINE__
,
7846 _("arm_extract_return_value: "
7847 "Floating point model not supported"));
7851 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7852 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7853 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7854 || TYPE_CODE (type
) == TYPE_CODE_PTR
7855 || TYPE_IS_REFERENCE (type
)
7856 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7858 /* If the type is a plain integer, then the access is
7859 straight-forward. Otherwise we have to play around a bit
7861 int len
= TYPE_LENGTH (type
);
7862 int regno
= ARM_A1_REGNUM
;
7867 /* By using store_unsigned_integer we avoid having to do
7868 anything special for small big-endian values. */
7869 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7870 store_unsigned_integer (valbuf
,
7871 (len
> ARM_INT_REGISTER_SIZE
7872 ? ARM_INT_REGISTER_SIZE
: len
),
7874 len
-= ARM_INT_REGISTER_SIZE
;
7875 valbuf
+= ARM_INT_REGISTER_SIZE
;
7880 /* For a structure or union the behaviour is as if the value had
7881 been stored to word-aligned memory and then loaded into
7882 registers with 32-bit load instruction(s). */
7883 int len
= TYPE_LENGTH (type
);
7884 int regno
= ARM_A1_REGNUM
;
7885 bfd_byte tmpbuf
[ARM_INT_REGISTER_SIZE
];
7889 regs
->cooked_read (regno
++, tmpbuf
);
7890 memcpy (valbuf
, tmpbuf
,
7891 len
> ARM_INT_REGISTER_SIZE
? ARM_INT_REGISTER_SIZE
: len
);
7892 len
-= ARM_INT_REGISTER_SIZE
;
7893 valbuf
+= ARM_INT_REGISTER_SIZE
;
7899 /* Will a function return an aggregate type in memory or in a
7900 register? Return 0 if an aggregate type can be returned in a
7901 register, 1 if it must be returned in memory. */
7904 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7906 enum type_code code
;
7908 type
= check_typedef (type
);
7910 /* Simple, non-aggregate types (ie not including vectors and
7911 complex) are always returned in a register (or registers). */
7912 code
= TYPE_CODE (type
);
7913 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
7914 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
7917 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
7919 /* Vector values should be returned using ARM registers if they
7920 are not over 16 bytes. */
7921 return (TYPE_LENGTH (type
) > 16);
7924 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7926 /* The AAPCS says all aggregates not larger than a word are returned
7928 if (TYPE_LENGTH (type
) <= ARM_INT_REGISTER_SIZE
)
7937 /* All aggregate types that won't fit in a register must be returned
7939 if (TYPE_LENGTH (type
) > ARM_INT_REGISTER_SIZE
)
7942 /* In the ARM ABI, "integer" like aggregate types are returned in
7943 registers. For an aggregate type to be integer like, its size
7944 must be less than or equal to ARM_INT_REGISTER_SIZE and the
7945 offset of each addressable subfield must be zero. Note that bit
7946 fields are not addressable, and all addressable subfields of
7947 unions always start at offset zero.
7949 This function is based on the behaviour of GCC 2.95.1.
7950 See: gcc/arm.c: arm_return_in_memory() for details.
7952 Note: All versions of GCC before GCC 2.95.2 do not set up the
7953 parameters correctly for a function returning the following
7954 structure: struct { float f;}; This should be returned in memory,
7955 not a register. Richard Earnshaw sent me a patch, but I do not
7956 know of any way to detect if a function like the above has been
7957 compiled with the correct calling convention. */
7959 /* Assume all other aggregate types can be returned in a register.
7960 Run a check for structures, unions and arrays. */
7963 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
7966 /* Need to check if this struct/union is "integer" like. For
7967 this to be true, its size must be less than or equal to
7968 ARM_INT_REGISTER_SIZE and the offset of each addressable
7969 subfield must be zero. Note that bit fields are not
7970 addressable, and unions always start at offset zero. If any
7971 of the subfields is a floating point type, the struct/union
7972 cannot be an integer type. */
7974 /* For each field in the object, check:
7975 1) Is it FP? --> yes, nRc = 1;
7976 2) Is it addressable (bitpos != 0) and
7977 not packed (bitsize == 0)?
7981 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
7983 enum type_code field_type_code
;
7986 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
7989 /* Is it a floating point type field? */
7990 if (field_type_code
== TYPE_CODE_FLT
)
7996 /* If bitpos != 0, then we have to care about it. */
7997 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
7999 /* Bitfields are not addressable. If the field bitsize is
8000 zero, then the field is not packed. Hence it cannot be
8001 a bitfield or any other packed type. */
8002 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8015 /* Write into appropriate registers a function return value of type
8016 TYPE, given in virtual format. */
8019 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8020 const gdb_byte
*valbuf
)
8022 struct gdbarch
*gdbarch
= regs
->arch ();
8023 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8025 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8027 gdb_byte buf
[ARM_FP_REGISTER_SIZE
];
8029 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8033 target_float_convert (valbuf
, type
, buf
, arm_ext_type (gdbarch
));
8034 regs
->cooked_write (ARM_F0_REGNUM
, buf
);
8037 case ARM_FLOAT_SOFT_FPA
:
8038 case ARM_FLOAT_SOFT_VFP
:
8039 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8040 not using the VFP ABI code. */
8042 regs
->cooked_write (ARM_A1_REGNUM
, valbuf
);
8043 if (TYPE_LENGTH (type
) > 4)
8044 regs
->cooked_write (ARM_A1_REGNUM
+ 1,
8045 valbuf
+ ARM_INT_REGISTER_SIZE
);
8049 internal_error (__FILE__
, __LINE__
,
8050 _("arm_store_return_value: Floating "
8051 "point model not supported"));
8055 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8056 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8057 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8058 || TYPE_CODE (type
) == TYPE_CODE_PTR
8059 || TYPE_IS_REFERENCE (type
)
8060 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8062 if (TYPE_LENGTH (type
) <= 4)
8064 /* Values of one word or less are zero/sign-extended and
8066 bfd_byte tmpbuf
[ARM_INT_REGISTER_SIZE
];
8067 LONGEST val
= unpack_long (type
, valbuf
);
8069 store_signed_integer (tmpbuf
, ARM_INT_REGISTER_SIZE
, byte_order
, val
);
8070 regs
->cooked_write (ARM_A1_REGNUM
, tmpbuf
);
8074 /* Integral values greater than one word are stored in consecutive
8075 registers starting with r0. This will always be a multiple of
8076 the regiser size. */
8077 int len
= TYPE_LENGTH (type
);
8078 int regno
= ARM_A1_REGNUM
;
8082 regs
->cooked_write (regno
++, valbuf
);
8083 len
-= ARM_INT_REGISTER_SIZE
;
8084 valbuf
+= ARM_INT_REGISTER_SIZE
;
8090 /* For a structure or union the behaviour is as if the value had
8091 been stored to word-aligned memory and then loaded into
8092 registers with 32-bit load instruction(s). */
8093 int len
= TYPE_LENGTH (type
);
8094 int regno
= ARM_A1_REGNUM
;
8095 bfd_byte tmpbuf
[ARM_INT_REGISTER_SIZE
];
8099 memcpy (tmpbuf
, valbuf
,
8100 len
> ARM_INT_REGISTER_SIZE
? ARM_INT_REGISTER_SIZE
: len
);
8101 regs
->cooked_write (regno
++, tmpbuf
);
8102 len
-= ARM_INT_REGISTER_SIZE
;
8103 valbuf
+= ARM_INT_REGISTER_SIZE
;
8109 /* Handle function return values. */
8111 static enum return_value_convention
8112 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8113 struct type
*valtype
, struct regcache
*regcache
,
8114 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8116 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8117 struct type
*func_type
= function
? value_type (function
) : NULL
;
8118 enum arm_vfp_cprc_base_type vfp_base_type
;
8121 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8122 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8124 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8125 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8127 for (i
= 0; i
< vfp_base_count
; i
++)
8129 if (reg_char
== 'q')
8132 arm_neon_quad_write (gdbarch
, regcache
, i
,
8133 writebuf
+ i
* unit_length
);
8136 arm_neon_quad_read (gdbarch
, regcache
, i
,
8137 readbuf
+ i
* unit_length
);
8144 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8145 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8148 regcache
->cooked_write (regnum
, writebuf
+ i
* unit_length
);
8150 regcache
->cooked_read (regnum
, readbuf
+ i
* unit_length
);
8153 return RETURN_VALUE_REGISTER_CONVENTION
;
8156 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8157 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8158 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8160 if (tdep
->struct_return
== pcc_struct_return
8161 || arm_return_in_memory (gdbarch
, valtype
))
8162 return RETURN_VALUE_STRUCT_CONVENTION
;
8164 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8166 if (arm_return_in_memory (gdbarch
, valtype
))
8167 return RETURN_VALUE_STRUCT_CONVENTION
;
8171 arm_store_return_value (valtype
, regcache
, writebuf
);
8174 arm_extract_return_value (valtype
, regcache
, readbuf
);
8176 return RETURN_VALUE_REGISTER_CONVENTION
;
8181 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8183 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8185 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8187 gdb_byte buf
[ARM_INT_REGISTER_SIZE
];
8189 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8191 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8192 ARM_INT_REGISTER_SIZE
))
8195 *pc
= extract_unsigned_integer (buf
, ARM_INT_REGISTER_SIZE
, byte_order
);
8199 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8200 return the target PC. Otherwise return 0. */
8203 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8207 CORE_ADDR start_addr
;
8209 /* Find the starting address and name of the function containing the PC. */
8210 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8212 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8214 start_addr
= arm_skip_bx_reg (frame
, pc
);
8215 if (start_addr
!= 0)
8221 /* If PC is in a Thumb call or return stub, return the address of the
8222 target PC, which is in a register. The thunk functions are called
8223 _call_via_xx, where x is the register name. The possible names
8224 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8225 functions, named __ARM_call_via_r[0-7]. */
8226 if (startswith (name
, "_call_via_")
8227 || startswith (name
, "__ARM_call_via_"))
8229 /* Use the name suffix to determine which register contains the
8231 static const char *table
[15] =
8232 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8233 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8236 int offset
= strlen (name
) - 2;
8238 for (regno
= 0; regno
<= 14; regno
++)
8239 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8240 return get_frame_register_unsigned (frame
, regno
);
8243 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8244 non-interworking calls to foo. We could decode the stubs
8245 to find the target but it's easier to use the symbol table. */
8246 namelen
= strlen (name
);
8247 if (name
[0] == '_' && name
[1] == '_'
8248 && ((namelen
> 2 + strlen ("_from_thumb")
8249 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8250 || (namelen
> 2 + strlen ("_from_arm")
8251 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8254 int target_len
= namelen
- 2;
8255 struct bound_minimal_symbol minsym
;
8256 struct objfile
*objfile
;
8257 struct obj_section
*sec
;
8259 if (name
[namelen
- 1] == 'b')
8260 target_len
-= strlen ("_from_thumb");
8262 target_len
-= strlen ("_from_arm");
8264 target_name
= (char *) alloca (target_len
+ 1);
8265 memcpy (target_name
, name
+ 2, target_len
);
8266 target_name
[target_len
] = '\0';
8268 sec
= find_pc_section (pc
);
8269 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8270 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8271 if (minsym
.minsym
!= NULL
)
8272 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8277 return 0; /* not a stub */
8281 set_arm_command (const char *args
, int from_tty
)
8283 printf_unfiltered (_("\
8284 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8285 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8289 show_arm_command (const char *args
, int from_tty
)
8291 cmd_show_list (showarmcmdlist
, from_tty
, "");
8295 arm_update_current_architecture (void)
8297 struct gdbarch_info info
;
8299 /* If the current architecture is not ARM, we have nothing to do. */
8300 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8303 /* Update the architecture. */
8304 gdbarch_info_init (&info
);
8306 if (!gdbarch_update_p (info
))
8307 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8311 set_fp_model_sfunc (const char *args
, int from_tty
,
8312 struct cmd_list_element
*c
)
8316 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8317 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8319 arm_fp_model
= (enum arm_float_model
) fp_model
;
8323 if (fp_model
== ARM_FLOAT_LAST
)
8324 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8327 arm_update_current_architecture ();
8331 show_fp_model (struct ui_file
*file
, int from_tty
,
8332 struct cmd_list_element
*c
, const char *value
)
8334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8336 if (arm_fp_model
== ARM_FLOAT_AUTO
8337 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8338 fprintf_filtered (file
, _("\
8339 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8340 fp_model_strings
[tdep
->fp_model
]);
8342 fprintf_filtered (file
, _("\
8343 The current ARM floating point model is \"%s\".\n"),
8344 fp_model_strings
[arm_fp_model
]);
8348 arm_set_abi (const char *args
, int from_tty
,
8349 struct cmd_list_element
*c
)
8353 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8354 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8356 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8360 if (arm_abi
== ARM_ABI_LAST
)
8361 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8364 arm_update_current_architecture ();
8368 arm_show_abi (struct ui_file
*file
, int from_tty
,
8369 struct cmd_list_element
*c
, const char *value
)
8371 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8373 if (arm_abi_global
== ARM_ABI_AUTO
8374 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8375 fprintf_filtered (file
, _("\
8376 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8377 arm_abi_strings
[tdep
->arm_abi
]);
8379 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8384 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8385 struct cmd_list_element
*c
, const char *value
)
8387 fprintf_filtered (file
,
8388 _("The current execution mode assumed "
8389 "(when symbols are unavailable) is \"%s\".\n"),
8390 arm_fallback_mode_string
);
8394 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8395 struct cmd_list_element
*c
, const char *value
)
8397 fprintf_filtered (file
,
8398 _("The current execution mode assumed "
8399 "(even when symbols are available) is \"%s\".\n"),
8400 arm_force_mode_string
);
8403 /* If the user changes the register disassembly style used for info
8404 register and other commands, we have to also switch the style used
8405 in opcodes for disassembly output. This function is run in the "set
8406 arm disassembly" command, and does that. */
8409 set_disassembly_style_sfunc (const char *args
, int from_tty
,
8410 struct cmd_list_element
*c
)
8412 /* Convert the short style name into the long style name (eg, reg-names-*)
8413 before calling the generic set_disassembler_options() function. */
8414 std::string long_name
= std::string ("reg-names-") + disassembly_style
;
8415 set_disassembler_options (&long_name
[0]);
8419 show_disassembly_style_sfunc (struct ui_file
*file
, int from_tty
,
8420 struct cmd_list_element
*c
, const char *value
)
8422 struct gdbarch
*gdbarch
= get_current_arch ();
8423 char *options
= get_disassembler_options (gdbarch
);
8424 const char *style
= "";
8428 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
8429 if (CONST_STRNEQ (opt
, "reg-names-"))
8431 style
= &opt
[strlen ("reg-names-")];
8432 len
= strcspn (style
, ",");
8435 fprintf_unfiltered (file
, "The disassembly style is \"%.*s\".\n", len
, style
);
8438 /* Return the ARM register name corresponding to register I. */
8440 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8442 const int num_regs
= gdbarch_num_regs (gdbarch
);
8444 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8445 && i
>= num_regs
&& i
< num_regs
+ 32)
8447 static const char *const vfp_pseudo_names
[] = {
8448 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8449 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8450 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8451 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8454 return vfp_pseudo_names
[i
- num_regs
];
8457 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8458 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8460 static const char *const neon_pseudo_names
[] = {
8461 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8462 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8465 return neon_pseudo_names
[i
- num_regs
- 32];
8468 if (i
>= ARRAY_SIZE (arm_register_names
))
8469 /* These registers are only supported on targets which supply
8470 an XML description. */
8473 return arm_register_names
[i
];
8476 /* Test whether the coff symbol specific value corresponds to a Thumb
8480 coff_sym_is_thumb (int val
)
8482 return (val
== C_THUMBEXT
8483 || val
== C_THUMBSTAT
8484 || val
== C_THUMBEXTFUNC
8485 || val
== C_THUMBSTATFUNC
8486 || val
== C_THUMBLABEL
);
8489 /* arm_coff_make_msymbol_special()
8490 arm_elf_make_msymbol_special()
8492 These functions test whether the COFF or ELF symbol corresponds to
8493 an address in thumb code, and set a "special" bit in a minimal
8494 symbol to indicate that it does. */
8497 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8499 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8501 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8502 == ST_BRANCH_TO_THUMB
)
8503 MSYMBOL_SET_SPECIAL (msym
);
8507 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8509 if (coff_sym_is_thumb (val
))
8510 MSYMBOL_SET_SPECIAL (msym
);
8514 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8517 const char *name
= bfd_asymbol_name (sym
);
8518 struct arm_per_objfile
*data
;
8519 struct arm_mapping_symbol new_map_sym
;
8521 gdb_assert (name
[0] == '$');
8522 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8525 data
= arm_objfile_data_key
.get (objfile
);
8527 data
= arm_objfile_data_key
.emplace (objfile
,
8528 objfile
->obfd
->section_count
);
8529 arm_mapping_symbol_vec
&map
8530 = data
->section_maps
[bfd_get_section (sym
)->index
];
8532 new_map_sym
.value
= sym
->value
;
8533 new_map_sym
.type
= name
[1];
8535 /* Insert at the end, the vector will be sorted on first use. */
8536 map
.push_back (new_map_sym
);
8540 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8542 struct gdbarch
*gdbarch
= regcache
->arch ();
8543 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8545 /* If necessary, set the T bit. */
8548 ULONGEST val
, t_bit
;
8549 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8550 t_bit
= arm_psr_thumb_bit (gdbarch
);
8551 if (arm_pc_is_thumb (gdbarch
, pc
))
8552 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8555 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8560 /* Read the contents of a NEON quad register, by reading from two
8561 double registers. This is used to implement the quad pseudo
8562 registers, and for argument passing in case the quad registers are
8563 missing; vectors are passed in quad registers when using the VFP
8564 ABI, even if a NEON unit is not present. REGNUM is the index of
8565 the quad register, in [0, 15]. */
8567 static enum register_status
8568 arm_neon_quad_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
8569 int regnum
, gdb_byte
*buf
)
8572 gdb_byte reg_buf
[8];
8573 int offset
, double_regnum
;
8574 enum register_status status
;
8576 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8577 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8580 /* d0 is always the least significant half of q0. */
8581 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8586 status
= regcache
->raw_read (double_regnum
, reg_buf
);
8587 if (status
!= REG_VALID
)
8589 memcpy (buf
+ offset
, reg_buf
, 8);
8591 offset
= 8 - offset
;
8592 status
= regcache
->raw_read (double_regnum
+ 1, reg_buf
);
8593 if (status
!= REG_VALID
)
8595 memcpy (buf
+ offset
, reg_buf
, 8);
8600 static enum register_status
8601 arm_pseudo_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
8602 int regnum
, gdb_byte
*buf
)
8604 const int num_regs
= gdbarch_num_regs (gdbarch
);
8606 gdb_byte reg_buf
[8];
8607 int offset
, double_regnum
;
8609 gdb_assert (regnum
>= num_regs
);
8612 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8613 /* Quad-precision register. */
8614 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8617 enum register_status status
;
8619 /* Single-precision register. */
8620 gdb_assert (regnum
< 32);
8622 /* s0 is always the least significant half of d0. */
8623 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8624 offset
= (regnum
& 1) ? 0 : 4;
8626 offset
= (regnum
& 1) ? 4 : 0;
8628 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8629 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8632 status
= regcache
->raw_read (double_regnum
, reg_buf
);
8633 if (status
== REG_VALID
)
8634 memcpy (buf
, reg_buf
+ offset
, 4);
8639 /* Store the contents of BUF to a NEON quad register, by writing to
8640 two double registers. This is used to implement the quad pseudo
8641 registers, and for argument passing in case the quad registers are
8642 missing; vectors are passed in quad registers when using the VFP
8643 ABI, even if a NEON unit is not present. REGNUM is the index
8644 of the quad register, in [0, 15]. */
8647 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8648 int regnum
, const gdb_byte
*buf
)
8651 int offset
, double_regnum
;
8653 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8654 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8657 /* d0 is always the least significant half of q0. */
8658 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8663 regcache
->raw_write (double_regnum
, buf
+ offset
);
8664 offset
= 8 - offset
;
8665 regcache
->raw_write (double_regnum
+ 1, buf
+ offset
);
8669 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8670 int regnum
, const gdb_byte
*buf
)
8672 const int num_regs
= gdbarch_num_regs (gdbarch
);
8674 gdb_byte reg_buf
[8];
8675 int offset
, double_regnum
;
8677 gdb_assert (regnum
>= num_regs
);
8680 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8681 /* Quad-precision register. */
8682 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8685 /* Single-precision register. */
8686 gdb_assert (regnum
< 32);
8688 /* s0 is always the least significant half of d0. */
8689 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8690 offset
= (regnum
& 1) ? 0 : 4;
8692 offset
= (regnum
& 1) ? 4 : 0;
8694 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8695 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8698 regcache
->raw_read (double_regnum
, reg_buf
);
8699 memcpy (reg_buf
+ offset
, buf
, 4);
8700 regcache
->raw_write (double_regnum
, reg_buf
);
8704 static struct value
*
8705 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8707 const int *reg_p
= (const int *) baton
;
8708 return value_of_register (*reg_p
, frame
);
8711 static enum gdb_osabi
8712 arm_elf_osabi_sniffer (bfd
*abfd
)
8714 unsigned int elfosabi
;
8715 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8717 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8719 if (elfosabi
== ELFOSABI_ARM
)
8720 /* GNU tools use this value. Check note sections in this case,
8722 bfd_map_over_sections (abfd
,
8723 generic_elf_osabi_sniff_abi_tag_sections
,
8726 /* Anything else will be handled by the generic ELF sniffer. */
8731 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8732 struct reggroup
*group
)
8734 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8735 this, FPS register belongs to save_regroup, restore_reggroup, and
8736 all_reggroup, of course. */
8737 if (regnum
== ARM_FPS_REGNUM
)
8738 return (group
== float_reggroup
8739 || group
== save_reggroup
8740 || group
== restore_reggroup
8741 || group
== all_reggroup
);
8743 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8746 /* For backward-compatibility we allow two 'g' packet lengths with
8747 the remote protocol depending on whether FPA registers are
8748 supplied. M-profile targets do not have FPA registers, but some
8749 stubs already exist in the wild which use a 'g' packet which
8750 supplies them albeit with dummy values. The packet format which
8751 includes FPA registers should be considered deprecated for
8752 M-profile targets. */
8755 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8757 if (gdbarch_tdep (gdbarch
)->is_m
)
8759 const target_desc
*tdesc
;
8761 /* If we know from the executable this is an M-profile target,
8762 cater for remote targets whose register set layout is the
8763 same as the FPA layout. */
8764 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA
);
8765 register_remote_g_packet_guess (gdbarch
,
8766 ARM_CORE_REGS_SIZE
+ ARM_FP_REGS_SIZE
,
8769 /* The regular M-profile layout. */
8770 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE
);
8771 register_remote_g_packet_guess (gdbarch
, ARM_CORE_REGS_SIZE
,
8774 /* M-profile plus M4F VFP. */
8775 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_VFP_D16
);
8776 register_remote_g_packet_guess (gdbarch
,
8777 ARM_CORE_REGS_SIZE
+ ARM_VFP2_REGS_SIZE
,
8781 /* Otherwise we don't have a useful guess. */
8784 /* Implement the code_of_frame_writable gdbarch method. */
8787 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8789 if (gdbarch_tdep (gdbarch
)->is_m
8790 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8792 /* M-profile exception frames return to some magic PCs, where
8793 isn't writable at all. */
8800 /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it
8801 to be postfixed by a version (eg armv7hl). */
8804 arm_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
8806 if (strcmp (gdbarch_bfd_arch_info (gdbarch
)->arch_name
, "arm") == 0)
8807 return "arm(v[^- ]*)?";
8808 return gdbarch_bfd_arch_info (gdbarch
)->arch_name
;
8811 /* Initialize the current architecture based on INFO. If possible,
8812 re-use an architecture from ARCHES, which is a list of
8813 architectures already created during this debugging session.
8815 Called e.g. at program startup, when reading a core file, and when
8816 reading a binary file. */
8818 static struct gdbarch
*
8819 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8821 struct gdbarch_tdep
*tdep
;
8822 struct gdbarch
*gdbarch
;
8823 struct gdbarch_list
*best_arch
;
8824 enum arm_abi_kind arm_abi
= arm_abi_global
;
8825 enum arm_float_model fp_model
= arm_fp_model
;
8826 struct tdesc_arch_data
*tdesc_data
= NULL
;
8828 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8829 int have_wmmx_registers
= 0;
8831 int have_fpa_registers
= 1;
8832 const struct target_desc
*tdesc
= info
.target_desc
;
8834 /* If we have an object to base this architecture on, try to determine
8837 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8839 int ei_osabi
, e_flags
;
8841 switch (bfd_get_flavour (info
.abfd
))
8843 case bfd_target_coff_flavour
:
8844 /* Assume it's an old APCS-style ABI. */
8846 arm_abi
= ARM_ABI_APCS
;
8849 case bfd_target_elf_flavour
:
8850 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8851 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8853 if (ei_osabi
== ELFOSABI_ARM
)
8855 /* GNU tools used to use this value, but do not for EABI
8856 objects. There's nowhere to tag an EABI version
8857 anyway, so assume APCS. */
8858 arm_abi
= ARM_ABI_APCS
;
8860 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
8862 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8866 case EF_ARM_EABI_UNKNOWN
:
8867 /* Assume GNU tools. */
8868 arm_abi
= ARM_ABI_APCS
;
8871 case EF_ARM_EABI_VER4
:
8872 case EF_ARM_EABI_VER5
:
8873 arm_abi
= ARM_ABI_AAPCS
;
8874 /* EABI binaries default to VFP float ordering.
8875 They may also contain build attributes that can
8876 be used to identify if the VFP argument-passing
8878 if (fp_model
== ARM_FLOAT_AUTO
)
8881 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8885 case AEABI_VFP_args_base
:
8886 /* "The user intended FP parameter/result
8887 passing to conform to AAPCS, base
8889 fp_model
= ARM_FLOAT_SOFT_VFP
;
8891 case AEABI_VFP_args_vfp
:
8892 /* "The user intended FP parameter/result
8893 passing to conform to AAPCS, VFP
8895 fp_model
= ARM_FLOAT_VFP
;
8897 case AEABI_VFP_args_toolchain
:
8898 /* "The user intended FP parameter/result
8899 passing to conform to tool chain-specific
8900 conventions" - we don't know any such
8901 conventions, so leave it as "auto". */
8903 case AEABI_VFP_args_compatible
:
8904 /* "Code is compatible with both the base
8905 and VFP variants; the user did not permit
8906 non-variadic functions to pass FP
8907 parameters/results" - leave it as
8911 /* Attribute value not mentioned in the
8912 November 2012 ABI, so leave it as
8917 fp_model
= ARM_FLOAT_SOFT_VFP
;
8923 /* Leave it as "auto". */
8924 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
8929 /* Detect M-profile programs. This only works if the
8930 executable file includes build attributes; GCC does
8931 copy them to the executable, but e.g. RealView does
8934 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
8937 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
8938 Tag_CPU_arch_profile
);
8940 /* GCC specifies the profile for v6-M; RealView only
8941 specifies the profile for architectures starting with
8942 V7 (as opposed to architectures with a tag
8943 numerically greater than TAG_CPU_ARCH_V7). */
8944 if (!tdesc_has_registers (tdesc
)
8945 && (attr_arch
== TAG_CPU_ARCH_V6_M
8946 || attr_arch
== TAG_CPU_ARCH_V6S_M
8947 || attr_profile
== 'M'))
8952 if (fp_model
== ARM_FLOAT_AUTO
)
8954 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
8957 /* Leave it as "auto". Strictly speaking this case
8958 means FPA, but almost nobody uses that now, and
8959 many toolchains fail to set the appropriate bits
8960 for the floating-point model they use. */
8962 case EF_ARM_SOFT_FLOAT
:
8963 fp_model
= ARM_FLOAT_SOFT_FPA
;
8965 case EF_ARM_VFP_FLOAT
:
8966 fp_model
= ARM_FLOAT_VFP
;
8968 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
8969 fp_model
= ARM_FLOAT_SOFT_VFP
;
8974 if (e_flags
& EF_ARM_BE8
)
8975 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
8980 /* Leave it as "auto". */
8985 /* Check any target description for validity. */
8986 if (tdesc_has_registers (tdesc
))
8988 /* For most registers we require GDB's default names; but also allow
8989 the numeric names for sp / lr / pc, as a convenience. */
8990 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
8991 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
8992 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
8994 const struct tdesc_feature
*feature
;
8997 feature
= tdesc_find_feature (tdesc
,
8998 "org.gnu.gdb.arm.core");
8999 if (feature
== NULL
)
9001 feature
= tdesc_find_feature (tdesc
,
9002 "org.gnu.gdb.arm.m-profile");
9003 if (feature
== NULL
)
9009 tdesc_data
= tdesc_data_alloc ();
9012 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9013 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9014 arm_register_names
[i
]);
9015 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9018 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9021 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9025 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9026 ARM_PS_REGNUM
, "xpsr");
9028 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9029 ARM_PS_REGNUM
, "cpsr");
9033 tdesc_data_cleanup (tdesc_data
);
9037 feature
= tdesc_find_feature (tdesc
,
9038 "org.gnu.gdb.arm.fpa");
9039 if (feature
!= NULL
)
9042 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9043 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9044 arm_register_names
[i
]);
9047 tdesc_data_cleanup (tdesc_data
);
9052 have_fpa_registers
= 0;
9054 feature
= tdesc_find_feature (tdesc
,
9055 "org.gnu.gdb.xscale.iwmmxt");
9056 if (feature
!= NULL
)
9058 static const char *const iwmmxt_names
[] = {
9059 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9060 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9061 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9062 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9066 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9068 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9069 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9071 /* Check for the control registers, but do not fail if they
9073 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9074 tdesc_numbered_register (feature
, tdesc_data
, i
,
9075 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9077 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9079 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9080 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9084 tdesc_data_cleanup (tdesc_data
);
9088 have_wmmx_registers
= 1;
9091 /* If we have a VFP unit, check whether the single precision registers
9092 are present. If not, then we will synthesize them as pseudo
9094 feature
= tdesc_find_feature (tdesc
,
9095 "org.gnu.gdb.arm.vfp");
9096 if (feature
!= NULL
)
9098 static const char *const vfp_double_names
[] = {
9099 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9100 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9101 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9102 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9105 /* Require the double precision registers. There must be either
9108 for (i
= 0; i
< 32; i
++)
9110 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9112 vfp_double_names
[i
]);
9116 if (!valid_p
&& i
== 16)
9119 /* Also require FPSCR. */
9120 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9121 ARM_FPSCR_REGNUM
, "fpscr");
9124 tdesc_data_cleanup (tdesc_data
);
9128 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9129 have_vfp_pseudos
= 1;
9131 vfp_register_count
= i
;
9133 /* If we have VFP, also check for NEON. The architecture allows
9134 NEON without VFP (integer vector operations only), but GDB
9135 does not support that. */
9136 feature
= tdesc_find_feature (tdesc
,
9137 "org.gnu.gdb.arm.neon");
9138 if (feature
!= NULL
)
9140 /* NEON requires 32 double-precision registers. */
9143 tdesc_data_cleanup (tdesc_data
);
9147 /* If there are quad registers defined by the stub, use
9148 their type; otherwise (normally) provide them with
9149 the default type. */
9150 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9151 have_neon_pseudos
= 1;
9158 /* If there is already a candidate, use it. */
9159 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9161 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9163 if (arm_abi
!= ARM_ABI_AUTO
9164 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9167 if (fp_model
!= ARM_FLOAT_AUTO
9168 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9171 /* There are various other properties in tdep that we do not
9172 need to check here: those derived from a target description,
9173 since gdbarches with a different target description are
9174 automatically disqualified. */
9176 /* Do check is_m, though, since it might come from the binary. */
9177 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9180 /* Found a match. */
9184 if (best_arch
!= NULL
)
9186 if (tdesc_data
!= NULL
)
9187 tdesc_data_cleanup (tdesc_data
);
9188 return best_arch
->gdbarch
;
9191 tdep
= XCNEW (struct gdbarch_tdep
);
9192 gdbarch
= gdbarch_alloc (&info
, tdep
);
9194 /* Record additional information about the architecture we are defining.
9195 These are gdbarch discriminators, like the OSABI. */
9196 tdep
->arm_abi
= arm_abi
;
9197 tdep
->fp_model
= fp_model
;
9199 tdep
->have_fpa_registers
= have_fpa_registers
;
9200 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9201 gdb_assert (vfp_register_count
== 0
9202 || vfp_register_count
== 16
9203 || vfp_register_count
== 32);
9204 tdep
->vfp_register_count
= vfp_register_count
;
9205 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9206 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9207 tdep
->have_neon
= have_neon
;
9209 arm_register_g_packet_guesses (gdbarch
);
9212 switch (info
.byte_order_for_code
)
9214 case BFD_ENDIAN_BIG
:
9215 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9216 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9217 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9218 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9222 case BFD_ENDIAN_LITTLE
:
9223 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9224 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9225 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9226 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9231 internal_error (__FILE__
, __LINE__
,
9232 _("arm_gdbarch_init: bad byte order for float format"));
9235 /* On ARM targets char defaults to unsigned. */
9236 set_gdbarch_char_signed (gdbarch
, 0);
9238 /* wchar_t is unsigned under the AAPCS. */
9239 if (tdep
->arm_abi
== ARM_ABI_AAPCS
)
9240 set_gdbarch_wchar_signed (gdbarch
, 0);
9242 set_gdbarch_wchar_signed (gdbarch
, 1);
9244 /* Compute type alignment. */
9245 set_gdbarch_type_align (gdbarch
, arm_type_align
);
9247 /* Note: for displaced stepping, this includes the breakpoint, and one word
9248 of additional scratch space. This setting isn't used for anything beside
9249 displaced stepping at present. */
9250 set_gdbarch_max_insn_length (gdbarch
, 4 * ARM_DISPLACED_MODIFIED_INSNS
);
9252 /* This should be low enough for everything. */
9253 tdep
->lowest_pc
= 0x20;
9254 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9256 /* The default, for both APCS and AAPCS, is to return small
9257 structures in registers. */
9258 tdep
->struct_return
= reg_struct_return
;
9260 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9261 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9264 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9266 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9268 frame_base_set_default (gdbarch
, &arm_normal_base
);
9270 /* Address manipulation. */
9271 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9273 /* Advance PC across function entry code. */
9274 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9276 /* Detect whether PC is at a point where the stack has been destroyed. */
9277 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9279 /* Skip trampolines. */
9280 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9282 /* The stack grows downward. */
9283 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9285 /* Breakpoint manipulation. */
9286 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
9287 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
9288 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9289 arm_breakpoint_kind_from_current_state
);
9291 /* Information about registers, etc. */
9292 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9293 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9294 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9295 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9296 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9298 /* This "info float" is FPA-specific. Use the generic version if we
9300 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9301 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9303 /* Internal <-> external register number maps. */
9304 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9305 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9307 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9309 /* Returning results. */
9310 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9313 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9315 /* Minsymbol frobbing. */
9316 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9317 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9318 arm_coff_make_msymbol_special
);
9319 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9321 /* Thumb-2 IT block support. */
9322 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9323 arm_adjust_breakpoint_address
);
9325 /* Virtual tables. */
9326 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9328 /* Hook in the ABI-specific overrides, if they have been registered. */
9329 gdbarch_init_osabi (info
, gdbarch
);
9331 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9333 /* Add some default predicates. */
9335 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9336 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9337 dwarf2_append_unwinders (gdbarch
);
9338 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9339 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9340 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9342 /* Now we have tuned the configuration, set a few final things,
9343 based on what the OS ABI has told us. */
9345 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9346 binaries are always marked. */
9347 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9348 tdep
->arm_abi
= ARM_ABI_APCS
;
9350 /* Watchpoints are not steppable. */
9351 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9353 /* We used to default to FPA for generic ARM, but almost nobody
9354 uses that now, and we now provide a way for the user to force
9355 the model. So default to the most useful variant. */
9356 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9357 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9359 if (tdep
->jb_pc
>= 0)
9360 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9362 /* Floating point sizes and format. */
9363 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9364 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9366 set_gdbarch_double_format
9367 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9368 set_gdbarch_long_double_format
9369 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9373 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9374 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9377 if (have_vfp_pseudos
)
9379 /* NOTE: These are the only pseudo registers used by
9380 the ARM target at the moment. If more are added, a
9381 little more care in numbering will be needed. */
9383 int num_pseudos
= 32;
9384 if (have_neon_pseudos
)
9386 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9387 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9388 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9393 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9395 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9397 /* Override tdesc_register_type to adjust the types of VFP
9398 registers for NEON. */
9399 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9402 /* Add standard register aliases. We add aliases even for those
9403 nanes which are used by the current architecture - it's simpler,
9404 and does no harm, since nothing ever lists user registers. */
9405 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9406 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9407 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9409 set_gdbarch_disassembler_options (gdbarch
, &arm_disassembler_options
);
9410 set_gdbarch_valid_disassembler_options (gdbarch
, disassembler_options_arm ());
9412 set_gdbarch_gnu_triplet_regexp (gdbarch
, arm_gnu_triplet_regexp
);
9418 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9420 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9425 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9426 (unsigned long) tdep
->lowest_pc
);
9432 static void arm_record_test (void);
9437 _initialize_arm_tdep (void)
9441 char regdesc
[1024], *rdptr
= regdesc
;
9442 size_t rest
= sizeof (regdesc
);
9444 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9446 /* Add ourselves to objfile event chain. */
9447 gdb::observers::new_objfile
.attach (arm_exidx_new_objfile
);
9449 /* Register an ELF OS ABI sniffer for ARM binaries. */
9450 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9451 bfd_target_elf_flavour
,
9452 arm_elf_osabi_sniffer
);
9454 /* Initialize the standard target descriptions. */
9455 initialize_tdesc_arm_with_m ();
9456 initialize_tdesc_arm_with_m_fpa_layout ();
9457 initialize_tdesc_arm_with_m_vfp_d16 ();
9458 initialize_tdesc_arm_with_iwmmxt ();
9459 initialize_tdesc_arm_with_vfpv2 ();
9460 initialize_tdesc_arm_with_vfpv3 ();
9461 initialize_tdesc_arm_with_neon ();
9463 /* Add root prefix command for all "set arm"/"show arm" commands. */
9464 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9465 _("Various ARM-specific commands."),
9466 &setarmcmdlist
, "set arm ", 0, &setlist
);
9468 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9469 _("Various ARM-specific commands."),
9470 &showarmcmdlist
, "show arm ", 0, &showlist
);
9473 arm_disassembler_options
= xstrdup ("reg-names-std");
9474 const disasm_options_t
*disasm_options
9475 = &disassembler_options_arm ()->options
;
9476 int num_disassembly_styles
= 0;
9477 for (i
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9478 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9479 num_disassembly_styles
++;
9481 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
9482 valid_disassembly_styles
= XNEWVEC (const char *,
9483 num_disassembly_styles
+ 1);
9484 for (i
= j
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9485 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9487 size_t offset
= strlen ("reg-names-");
9488 const char *style
= disasm_options
->name
[i
];
9489 valid_disassembly_styles
[j
++] = &style
[offset
];
9490 length
= snprintf (rdptr
, rest
, "%s - %s\n", &style
[offset
],
9491 disasm_options
->description
[i
]);
9495 /* Mark the end of valid options. */
9496 valid_disassembly_styles
[num_disassembly_styles
] = NULL
;
9498 /* Create the help text. */
9499 std::string helptext
= string_printf ("%s%s%s",
9500 _("The valid values are:\n"),
9502 _("The default is \"std\"."));
9504 add_setshow_enum_cmd("disassembler", no_class
,
9505 valid_disassembly_styles
, &disassembly_style
,
9506 _("Set the disassembly style."),
9507 _("Show the disassembly style."),
9509 set_disassembly_style_sfunc
,
9510 show_disassembly_style_sfunc
,
9511 &setarmcmdlist
, &showarmcmdlist
);
9513 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9514 _("Set usage of ARM 32-bit mode."),
9515 _("Show usage of ARM 32-bit mode."),
9516 _("When off, a 26-bit PC will be used."),
9518 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9520 &setarmcmdlist
, &showarmcmdlist
);
9522 /* Add a command to allow the user to force the FPU model. */
9523 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9524 _("Set the floating point type."),
9525 _("Show the floating point type."),
9526 _("auto - Determine the FP typefrom the OS-ABI.\n\
9527 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9528 fpa - FPA co-processor (GCC compiled).\n\
9529 softvfp - Software FP with pure-endian doubles.\n\
9530 vfp - VFP co-processor."),
9531 set_fp_model_sfunc
, show_fp_model
,
9532 &setarmcmdlist
, &showarmcmdlist
);
9534 /* Add a command to allow the user to force the ABI. */
9535 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9538 NULL
, arm_set_abi
, arm_show_abi
,
9539 &setarmcmdlist
, &showarmcmdlist
);
9541 /* Add two commands to allow the user to force the assumed
9543 add_setshow_enum_cmd ("fallback-mode", class_support
,
9544 arm_mode_strings
, &arm_fallback_mode_string
,
9545 _("Set the mode assumed when symbols are unavailable."),
9546 _("Show the mode assumed when symbols are unavailable."),
9547 NULL
, NULL
, arm_show_fallback_mode
,
9548 &setarmcmdlist
, &showarmcmdlist
);
9549 add_setshow_enum_cmd ("force-mode", class_support
,
9550 arm_mode_strings
, &arm_force_mode_string
,
9551 _("Set the mode assumed even when symbols are available."),
9552 _("Show the mode assumed even when symbols are available."),
9553 NULL
, NULL
, arm_show_force_mode
,
9554 &setarmcmdlist
, &showarmcmdlist
);
9556 /* Debugging flag. */
9557 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9558 _("Set ARM debugging."),
9559 _("Show ARM debugging."),
9560 _("When on, arm-specific debugging is enabled."),
9562 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9563 &setdebuglist
, &showdebuglist
);
9566 selftests::register_test ("arm-record", selftests::arm_record_test
);
9571 /* ARM-reversible process record data structures. */
9573 #define ARM_INSN_SIZE_BYTES 4
9574 #define THUMB_INSN_SIZE_BYTES 2
9575 #define THUMB2_INSN_SIZE_BYTES 4
9578 /* Position of the bit within a 32-bit ARM instruction
9579 that defines whether the instruction is a load or store. */
9580 #define INSN_S_L_BIT_NUM 20
9582 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9585 unsigned int reg_len = LENGTH; \
9588 REGS = XNEWVEC (uint32_t, reg_len); \
9589 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9594 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9597 unsigned int mem_len = LENGTH; \
9600 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9601 memcpy(&MEMS->len, &RECORD_BUF[0], \
9602 sizeof(struct arm_mem_r) * LENGTH); \
9607 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9608 #define INSN_RECORDED(ARM_RECORD) \
9609 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9611 /* ARM memory record structure. */
9614 uint32_t len
; /* Record length. */
9615 uint32_t addr
; /* Memory address. */
9618 /* ARM instruction record contains opcode of current insn
9619 and execution state (before entry to decode_insn()),
9620 contains list of to-be-modified registers and
9621 memory blocks (on return from decode_insn()). */
9623 typedef struct insn_decode_record_t
9625 struct gdbarch
*gdbarch
;
9626 struct regcache
*regcache
;
9627 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9628 uint32_t arm_insn
; /* Should accommodate thumb. */
9629 uint32_t cond
; /* Condition code. */
9630 uint32_t opcode
; /* Insn opcode. */
9631 uint32_t decode
; /* Insn decode bits. */
9632 uint32_t mem_rec_count
; /* No of mem records. */
9633 uint32_t reg_rec_count
; /* No of reg records. */
9634 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9635 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9636 } insn_decode_record
;
9639 /* Checks ARM SBZ and SBO mandatory fields. */
9642 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9644 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9663 enum arm_record_result
9665 ARM_RECORD_SUCCESS
= 0,
9666 ARM_RECORD_FAILURE
= 1
9673 } arm_record_strx_t
;
9684 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9685 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9688 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9689 ULONGEST u_regval
[2]= {0};
9691 uint32_t reg_src1
= 0, reg_src2
= 0;
9692 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9694 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9695 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9697 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9699 /* 1) Handle misc store, immediate offset. */
9700 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9701 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9702 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9703 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9705 if (ARM_PC_REGNUM
== reg_src1
)
9707 /* If R15 was used as Rn, hence current PC+8. */
9708 u_regval
[0] = u_regval
[0] + 8;
9710 offset_8
= (immed_high
<< 4) | immed_low
;
9711 /* Calculate target store address. */
9712 if (14 == arm_insn_r
->opcode
)
9714 tgt_mem_addr
= u_regval
[0] + offset_8
;
9718 tgt_mem_addr
= u_regval
[0] - offset_8
;
9720 if (ARM_RECORD_STRH
== str_type
)
9722 record_buf_mem
[0] = 2;
9723 record_buf_mem
[1] = tgt_mem_addr
;
9724 arm_insn_r
->mem_rec_count
= 1;
9726 else if (ARM_RECORD_STRD
== str_type
)
9728 record_buf_mem
[0] = 4;
9729 record_buf_mem
[1] = tgt_mem_addr
;
9730 record_buf_mem
[2] = 4;
9731 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9732 arm_insn_r
->mem_rec_count
= 2;
9735 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9737 /* 2) Store, register offset. */
9739 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9741 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9742 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9743 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9746 /* If R15 was used as Rn, hence current PC+8. */
9747 u_regval
[0] = u_regval
[0] + 8;
9749 /* Calculate target store address, Rn +/- Rm, register offset. */
9750 if (12 == arm_insn_r
->opcode
)
9752 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9756 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9758 if (ARM_RECORD_STRH
== str_type
)
9760 record_buf_mem
[0] = 2;
9761 record_buf_mem
[1] = tgt_mem_addr
;
9762 arm_insn_r
->mem_rec_count
= 1;
9764 else if (ARM_RECORD_STRD
== str_type
)
9766 record_buf_mem
[0] = 4;
9767 record_buf_mem
[1] = tgt_mem_addr
;
9768 record_buf_mem
[2] = 4;
9769 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9770 arm_insn_r
->mem_rec_count
= 2;
9773 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9774 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9776 /* 3) Store, immediate pre-indexed. */
9777 /* 5) Store, immediate post-indexed. */
9778 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9779 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9780 offset_8
= (immed_high
<< 4) | immed_low
;
9781 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9782 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9783 /* Calculate target store address, Rn +/- Rm, register offset. */
9784 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9786 tgt_mem_addr
= u_regval
[0] + offset_8
;
9790 tgt_mem_addr
= u_regval
[0] - offset_8
;
9792 if (ARM_RECORD_STRH
== str_type
)
9794 record_buf_mem
[0] = 2;
9795 record_buf_mem
[1] = tgt_mem_addr
;
9796 arm_insn_r
->mem_rec_count
= 1;
9798 else if (ARM_RECORD_STRD
== str_type
)
9800 record_buf_mem
[0] = 4;
9801 record_buf_mem
[1] = tgt_mem_addr
;
9802 record_buf_mem
[2] = 4;
9803 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9804 arm_insn_r
->mem_rec_count
= 2;
9806 /* Record Rn also as it changes. */
9807 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9808 arm_insn_r
->reg_rec_count
= 1;
9810 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9811 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9813 /* 4) Store, register pre-indexed. */
9814 /* 6) Store, register post -indexed. */
9815 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9816 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9817 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9818 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9819 /* Calculate target store address, Rn +/- Rm, register offset. */
9820 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9822 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9826 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9828 if (ARM_RECORD_STRH
== str_type
)
9830 record_buf_mem
[0] = 2;
9831 record_buf_mem
[1] = tgt_mem_addr
;
9832 arm_insn_r
->mem_rec_count
= 1;
9834 else if (ARM_RECORD_STRD
== str_type
)
9836 record_buf_mem
[0] = 4;
9837 record_buf_mem
[1] = tgt_mem_addr
;
9838 record_buf_mem
[2] = 4;
9839 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9840 arm_insn_r
->mem_rec_count
= 2;
9842 /* Record Rn also as it changes. */
9843 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9844 arm_insn_r
->reg_rec_count
= 1;
9849 /* Handling ARM extension space insns. */
9852 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9854 int ret
= 0; /* Return value: -1:record failure ; 0:success */
9855 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9856 uint32_t record_buf
[8], record_buf_mem
[8];
9857 uint32_t reg_src1
= 0;
9858 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9859 ULONGEST u_regval
= 0;
9861 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9862 /* Handle unconditional insn extension space. */
9864 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9865 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9866 if (arm_insn_r
->cond
)
9868 /* PLD has no affect on architectural state, it just affects
9870 if (5 == ((opcode1
& 0xE0) >> 5))
9873 record_buf
[0] = ARM_PS_REGNUM
;
9874 record_buf
[1] = ARM_LR_REGNUM
;
9875 arm_insn_r
->reg_rec_count
= 2;
9877 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9881 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
9882 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
9885 /* Undefined instruction on ARM V5; need to handle if later
9886 versions define it. */
9889 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
9890 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9891 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
9893 /* Handle arithmetic insn extension space. */
9894 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
9895 && !INSN_RECORDED(arm_insn_r
))
9897 /* Handle MLA(S) and MUL(S). */
9898 if (in_inclusive_range (insn_op1
, 0U, 3U))
9900 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9901 record_buf
[1] = ARM_PS_REGNUM
;
9902 arm_insn_r
->reg_rec_count
= 2;
9904 else if (in_inclusive_range (insn_op1
, 4U, 15U))
9906 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9907 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
9908 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9909 record_buf
[2] = ARM_PS_REGNUM
;
9910 arm_insn_r
->reg_rec_count
= 3;
9914 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
9915 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
9916 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
9918 /* Handle control insn extension space. */
9920 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
9921 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
9923 if (!bit (arm_insn_r
->arm_insn
,25))
9925 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
9927 if ((0 == insn_op1
) || (2 == insn_op1
))
9930 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9931 arm_insn_r
->reg_rec_count
= 1;
9933 else if (1 == insn_op1
)
9935 /* CSPR is going to be changed. */
9936 record_buf
[0] = ARM_PS_REGNUM
;
9937 arm_insn_r
->reg_rec_count
= 1;
9939 else if (3 == insn_op1
)
9941 /* SPSR is going to be changed. */
9942 /* We need to get SPSR value, which is yet to be done. */
9946 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
9951 record_buf
[0] = ARM_PS_REGNUM
;
9952 arm_insn_r
->reg_rec_count
= 1;
9954 else if (3 == insn_op1
)
9957 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9958 arm_insn_r
->reg_rec_count
= 1;
9961 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
9964 record_buf
[0] = ARM_PS_REGNUM
;
9965 record_buf
[1] = ARM_LR_REGNUM
;
9966 arm_insn_r
->reg_rec_count
= 2;
9968 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
9970 /* QADD, QSUB, QDADD, QDSUB */
9971 record_buf
[0] = ARM_PS_REGNUM
;
9972 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9973 arm_insn_r
->reg_rec_count
= 2;
9975 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
9978 record_buf
[0] = ARM_PS_REGNUM
;
9979 record_buf
[1] = ARM_LR_REGNUM
;
9980 arm_insn_r
->reg_rec_count
= 2;
9982 /* Save SPSR also;how? */
9985 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
9986 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
9987 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
9988 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
9991 if (0 == insn_op1
|| 1 == insn_op1
)
9993 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
9994 /* We dont do optimization for SMULW<y> where we
9996 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9997 record_buf
[1] = ARM_PS_REGNUM
;
9998 arm_insn_r
->reg_rec_count
= 2;
10000 else if (2 == insn_op1
)
10003 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10004 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10005 arm_insn_r
->reg_rec_count
= 2;
10007 else if (3 == insn_op1
)
10010 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10011 arm_insn_r
->reg_rec_count
= 1;
10017 /* MSR : immediate form. */
10020 /* CSPR is going to be changed. */
10021 record_buf
[0] = ARM_PS_REGNUM
;
10022 arm_insn_r
->reg_rec_count
= 1;
10024 else if (3 == insn_op1
)
10026 /* SPSR is going to be changed. */
10027 /* we need to get SPSR value, which is yet to be done */
10033 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10034 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10035 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10037 /* Handle load/store insn extension space. */
10039 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10040 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10041 && !INSN_RECORDED(arm_insn_r
))
10046 /* These insn, changes register and memory as well. */
10047 /* SWP or SWPB insn. */
10048 /* Get memory address given by Rn. */
10049 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10050 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10051 /* SWP insn ?, swaps word. */
10052 if (8 == arm_insn_r
->opcode
)
10054 record_buf_mem
[0] = 4;
10058 /* SWPB insn, swaps only byte. */
10059 record_buf_mem
[0] = 1;
10061 record_buf_mem
[1] = u_regval
;
10062 arm_insn_r
->mem_rec_count
= 1;
10063 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10064 arm_insn_r
->reg_rec_count
= 1;
10066 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10069 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10072 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10075 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10076 record_buf
[1] = record_buf
[0] + 1;
10077 arm_insn_r
->reg_rec_count
= 2;
10079 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10082 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10085 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10087 /* LDRH, LDRSB, LDRSH. */
10088 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10089 arm_insn_r
->reg_rec_count
= 1;
10094 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10095 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10096 && !INSN_RECORDED(arm_insn_r
))
10099 /* Handle coprocessor insn extension space. */
10102 /* To be done for ARMv5 and later; as of now we return -1. */
10106 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10107 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10112 /* Handling opcode 000 insns. */
10115 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10117 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10118 uint32_t record_buf
[8], record_buf_mem
[8];
10119 ULONGEST u_regval
[2] = {0};
10121 uint32_t reg_src1
= 0;
10122 uint32_t opcode1
= 0;
10124 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10125 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10126 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10128 if (!((opcode1
& 0x19) == 0x10))
10130 /* Data-processing (register) and Data-processing (register-shifted
10132 /* Out of 11 shifter operands mode, all the insn modifies destination
10133 register, which is specified by 13-16 decode. */
10134 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10135 record_buf
[1] = ARM_PS_REGNUM
;
10136 arm_insn_r
->reg_rec_count
= 2;
10138 else if ((arm_insn_r
->decode
< 8) && ((opcode1
& 0x19) == 0x10))
10140 /* Miscellaneous instructions */
10142 if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10143 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10145 /* Handle BLX, branch and link/exchange. */
10146 if (9 == arm_insn_r
->opcode
)
10148 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10149 and R14 stores the return address. */
10150 record_buf
[0] = ARM_PS_REGNUM
;
10151 record_buf
[1] = ARM_LR_REGNUM
;
10152 arm_insn_r
->reg_rec_count
= 2;
10155 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10157 /* Handle enhanced software breakpoint insn, BKPT. */
10158 /* CPSR is changed to be executed in ARM state, disabling normal
10159 interrupts, entering abort mode. */
10160 /* According to high vector configuration PC is set. */
10161 /* user hit breakpoint and type reverse, in
10162 that case, we need to go back with previous CPSR and
10163 Program Counter. */
10164 record_buf
[0] = ARM_PS_REGNUM
;
10165 record_buf
[1] = ARM_LR_REGNUM
;
10166 arm_insn_r
->reg_rec_count
= 2;
10168 /* Save SPSR also; how? */
10171 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10172 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10174 /* Handle BX, branch and link/exchange. */
10175 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10176 record_buf
[0] = ARM_PS_REGNUM
;
10177 arm_insn_r
->reg_rec_count
= 1;
10179 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10180 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10181 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10183 /* Count leading zeros: CLZ. */
10184 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10185 arm_insn_r
->reg_rec_count
= 1;
10187 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10188 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10189 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10190 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0))
10192 /* Handle MRS insn. */
10193 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10194 arm_insn_r
->reg_rec_count
= 1;
10197 else if (9 == arm_insn_r
->decode
&& opcode1
< 0x10)
10199 /* Multiply and multiply-accumulate */
10201 /* Handle multiply instructions. */
10202 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10203 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10205 /* Handle MLA and MUL. */
10206 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10207 record_buf
[1] = ARM_PS_REGNUM
;
10208 arm_insn_r
->reg_rec_count
= 2;
10210 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10212 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10213 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10214 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10215 record_buf
[2] = ARM_PS_REGNUM
;
10216 arm_insn_r
->reg_rec_count
= 3;
10219 else if (9 == arm_insn_r
->decode
&& opcode1
> 0x10)
10221 /* Synchronization primitives */
10223 /* Handling SWP, SWPB. */
10224 /* These insn, changes register and memory as well. */
10225 /* SWP or SWPB insn. */
10227 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10228 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10229 /* SWP insn ?, swaps word. */
10230 if (8 == arm_insn_r
->opcode
)
10232 record_buf_mem
[0] = 4;
10236 /* SWPB insn, swaps only byte. */
10237 record_buf_mem
[0] = 1;
10239 record_buf_mem
[1] = u_regval
[0];
10240 arm_insn_r
->mem_rec_count
= 1;
10241 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10242 arm_insn_r
->reg_rec_count
= 1;
10244 else if (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
10245 || 15 == arm_insn_r
->decode
)
10247 if ((opcode1
& 0x12) == 2)
10249 /* Extra load/store (unprivileged) */
10254 /* Extra load/store */
10255 switch (bits (arm_insn_r
->arm_insn
, 5, 6))
10258 if ((opcode1
& 0x05) == 0x0 || (opcode1
& 0x05) == 0x4)
10260 /* STRH (register), STRH (immediate) */
10261 arm_record_strx (arm_insn_r
, &record_buf
[0],
10262 &record_buf_mem
[0], ARM_RECORD_STRH
);
10264 else if ((opcode1
& 0x05) == 0x1)
10266 /* LDRH (register) */
10267 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10268 arm_insn_r
->reg_rec_count
= 1;
10270 if (bit (arm_insn_r
->arm_insn
, 21))
10272 /* Write back to Rn. */
10273 record_buf
[arm_insn_r
->reg_rec_count
++]
10274 = bits (arm_insn_r
->arm_insn
, 16, 19);
10277 else if ((opcode1
& 0x05) == 0x5)
10279 /* LDRH (immediate), LDRH (literal) */
10280 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
10282 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10283 arm_insn_r
->reg_rec_count
= 1;
10287 /*LDRH (immediate) */
10288 if (bit (arm_insn_r
->arm_insn
, 21))
10290 /* Write back to Rn. */
10291 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
10299 if ((opcode1
& 0x05) == 0x0)
10301 /* LDRD (register) */
10302 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10303 record_buf
[1] = record_buf
[0] + 1;
10304 arm_insn_r
->reg_rec_count
= 2;
10306 if (bit (arm_insn_r
->arm_insn
, 21))
10308 /* Write back to Rn. */
10309 record_buf
[arm_insn_r
->reg_rec_count
++]
10310 = bits (arm_insn_r
->arm_insn
, 16, 19);
10313 else if ((opcode1
& 0x05) == 0x1)
10315 /* LDRSB (register) */
10316 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10317 arm_insn_r
->reg_rec_count
= 1;
10319 if (bit (arm_insn_r
->arm_insn
, 21))
10321 /* Write back to Rn. */
10322 record_buf
[arm_insn_r
->reg_rec_count
++]
10323 = bits (arm_insn_r
->arm_insn
, 16, 19);
10326 else if ((opcode1
& 0x05) == 0x4 || (opcode1
& 0x05) == 0x5)
10328 /* LDRD (immediate), LDRD (literal), LDRSB (immediate),
10330 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
10332 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10333 arm_insn_r
->reg_rec_count
= 1;
10337 /*LDRD (immediate), LDRSB (immediate) */
10338 if (bit (arm_insn_r
->arm_insn
, 21))
10340 /* Write back to Rn. */
10341 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
10349 if ((opcode1
& 0x05) == 0x0)
10351 /* STRD (register) */
10352 arm_record_strx (arm_insn_r
, &record_buf
[0],
10353 &record_buf_mem
[0], ARM_RECORD_STRD
);
10355 else if ((opcode1
& 0x05) == 0x1)
10357 /* LDRSH (register) */
10358 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10359 arm_insn_r
->reg_rec_count
= 1;
10361 if (bit (arm_insn_r
->arm_insn
, 21))
10363 /* Write back to Rn. */
10364 record_buf
[arm_insn_r
->reg_rec_count
++]
10365 = bits (arm_insn_r
->arm_insn
, 16, 19);
10368 else if ((opcode1
& 0x05) == 0x4)
10370 /* STRD (immediate) */
10371 arm_record_strx (arm_insn_r
, &record_buf
[0],
10372 &record_buf_mem
[0], ARM_RECORD_STRD
);
10374 else if ((opcode1
& 0x05) == 0x5)
10376 /* LDRSH (immediate), LDRSH (literal) */
10377 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10378 arm_insn_r
->reg_rec_count
= 1;
10380 if (bit (arm_insn_r
->arm_insn
, 21))
10382 /* Write back to Rn. */
10383 record_buf
[arm_insn_r
->reg_rec_count
++]
10384 = bits (arm_insn_r
->arm_insn
, 16, 19);
10400 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10401 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10405 /* Handling opcode 001 insns. */
10408 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10410 uint32_t record_buf
[8], record_buf_mem
[8];
10412 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10413 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10415 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10416 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10417 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10420 /* Handle MSR insn. */
10421 if (9 == arm_insn_r
->opcode
)
10423 /* CSPR is going to be changed. */
10424 record_buf
[0] = ARM_PS_REGNUM
;
10425 arm_insn_r
->reg_rec_count
= 1;
10429 /* SPSR is going to be changed. */
10432 else if (arm_insn_r
->opcode
<= 15)
10434 /* Normal data processing insns. */
10435 /* Out of 11 shifter operands mode, all the insn modifies destination
10436 register, which is specified by 13-16 decode. */
10437 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10438 record_buf
[1] = ARM_PS_REGNUM
;
10439 arm_insn_r
->reg_rec_count
= 2;
10446 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10447 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10452 arm_record_media (insn_decode_record
*arm_insn_r
)
10454 uint32_t record_buf
[8];
10456 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10459 /* Parallel addition and subtraction, signed */
10461 /* Parallel addition and subtraction, unsigned */
10464 /* Packing, unpacking, saturation and reversal */
10466 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10468 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10474 /* Signed multiplies */
10476 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10477 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10479 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10481 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10482 else if (op1
== 0x4)
10483 record_buf
[arm_insn_r
->reg_rec_count
++]
10484 = bits (arm_insn_r
->arm_insn
, 12, 15);
10490 if (bit (arm_insn_r
->arm_insn
, 21)
10491 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10494 record_buf
[arm_insn_r
->reg_rec_count
++]
10495 = bits (arm_insn_r
->arm_insn
, 12, 15);
10497 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10498 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10500 /* USAD8 and USADA8 */
10501 record_buf
[arm_insn_r
->reg_rec_count
++]
10502 = bits (arm_insn_r
->arm_insn
, 16, 19);
10509 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10510 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10512 /* Permanently UNDEFINED */
10517 /* BFC, BFI and UBFX */
10518 record_buf
[arm_insn_r
->reg_rec_count
++]
10519 = bits (arm_insn_r
->arm_insn
, 12, 15);
10528 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10533 /* Handle ARM mode instructions with opcode 010. */
10536 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10538 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10540 uint32_t reg_base
, reg_dest
;
10541 uint32_t offset_12
, tgt_mem_addr
;
10542 uint32_t record_buf
[8], record_buf_mem
[8];
10543 unsigned char wback
;
10546 /* Calculate wback. */
10547 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10548 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10550 arm_insn_r
->reg_rec_count
= 0;
10551 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10553 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10555 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10558 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10559 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10561 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10562 preceeds a LDR instruction having R15 as reg_base, it
10563 emulates a branch and link instruction, and hence we need to save
10564 CPSR and PC as well. */
10565 if (ARM_PC_REGNUM
== reg_dest
)
10566 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10568 /* If wback is true, also save the base register, which is going to be
10571 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10575 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10577 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10578 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10580 /* Handle bit U. */
10581 if (bit (arm_insn_r
->arm_insn
, 23))
10583 /* U == 1: Add the offset. */
10584 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10588 /* U == 0: subtract the offset. */
10589 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10592 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10594 if (bit (arm_insn_r
->arm_insn
, 22))
10596 /* STRB and STRBT: 1 byte. */
10597 record_buf_mem
[0] = 1;
10601 /* STR and STRT: 4 bytes. */
10602 record_buf_mem
[0] = 4;
10605 /* Handle bit P. */
10606 if (bit (arm_insn_r
->arm_insn
, 24))
10607 record_buf_mem
[1] = tgt_mem_addr
;
10609 record_buf_mem
[1] = (uint32_t) u_regval
;
10611 arm_insn_r
->mem_rec_count
= 1;
10613 /* If wback is true, also save the base register, which is going to be
10616 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10619 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10620 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10624 /* Handling opcode 011 insns. */
10627 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10629 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10631 uint32_t shift_imm
= 0;
10632 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10633 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10634 uint32_t record_buf
[8], record_buf_mem
[8];
10637 ULONGEST u_regval
[2];
10639 if (bit (arm_insn_r
->arm_insn
, 4))
10640 return arm_record_media (arm_insn_r
);
10642 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10643 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10645 /* Handle enhanced store insns and LDRD DSP insn,
10646 order begins according to addressing modes for store insns
10650 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10652 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10653 /* LDR insn has a capability to do branching, if
10654 MOV LR, PC is precedded by LDR insn having Rn as R15
10655 in that case, it emulates branch and link insn, and hence we
10656 need to save CSPR and PC as well. */
10657 if (15 != reg_dest
)
10659 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10660 arm_insn_r
->reg_rec_count
= 1;
10664 record_buf
[0] = reg_dest
;
10665 record_buf
[1] = ARM_PS_REGNUM
;
10666 arm_insn_r
->reg_rec_count
= 2;
10671 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10673 /* Store insn, register offset and register pre-indexed,
10674 register post-indexed. */
10676 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10678 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10679 regcache_raw_read_unsigned (reg_cache
, reg_src1
10681 regcache_raw_read_unsigned (reg_cache
, reg_src2
10683 if (15 == reg_src2
)
10685 /* If R15 was used as Rn, hence current PC+8. */
10686 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10687 u_regval
[0] = u_regval
[0] + 8;
10689 /* Calculate target store address, Rn +/- Rm, register offset. */
10691 if (bit (arm_insn_r
->arm_insn
, 23))
10693 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10697 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10700 switch (arm_insn_r
->opcode
)
10714 record_buf_mem
[0] = 4;
10729 record_buf_mem
[0] = 1;
10733 gdb_assert_not_reached ("no decoding pattern found");
10736 record_buf_mem
[1] = tgt_mem_addr
;
10737 arm_insn_r
->mem_rec_count
= 1;
10739 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10740 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10741 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10742 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10743 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10744 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10747 /* Rn is going to be changed in pre-indexed mode and
10748 post-indexed mode as well. */
10749 record_buf
[0] = reg_src2
;
10750 arm_insn_r
->reg_rec_count
= 1;
10755 /* Store insn, scaled register offset; scaled pre-indexed. */
10756 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10758 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10760 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10761 /* Get shift_imm. */
10762 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10763 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10764 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10765 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10766 /* Offset_12 used as shift. */
10770 /* Offset_12 used as index. */
10771 offset_12
= u_regval
[0] << shift_imm
;
10775 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10781 if (bit (u_regval
[0], 31))
10783 offset_12
= 0xFFFFFFFF;
10792 /* This is arithmetic shift. */
10793 offset_12
= s_word
>> shift_imm
;
10800 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10802 /* Get C flag value and shift it by 31. */
10803 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10804 | (u_regval
[0]) >> 1);
10808 offset_12
= (u_regval
[0] >> shift_imm
) \
10810 (sizeof(uint32_t) - shift_imm
));
10815 gdb_assert_not_reached ("no decoding pattern found");
10819 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10821 if (bit (arm_insn_r
->arm_insn
, 23))
10823 tgt_mem_addr
= u_regval
[1] + offset_12
;
10827 tgt_mem_addr
= u_regval
[1] - offset_12
;
10830 switch (arm_insn_r
->opcode
)
10844 record_buf_mem
[0] = 4;
10859 record_buf_mem
[0] = 1;
10863 gdb_assert_not_reached ("no decoding pattern found");
10866 record_buf_mem
[1] = tgt_mem_addr
;
10867 arm_insn_r
->mem_rec_count
= 1;
10869 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10870 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10871 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10872 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10873 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10874 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10877 /* Rn is going to be changed in register scaled pre-indexed
10878 mode,and scaled post indexed mode. */
10879 record_buf
[0] = reg_src2
;
10880 arm_insn_r
->reg_rec_count
= 1;
10885 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10886 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10890 /* Handle ARM mode instructions with opcode 100. */
10893 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10895 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10896 uint32_t register_count
= 0, register_bits
;
10897 uint32_t reg_base
, addr_mode
;
10898 uint32_t record_buf
[24], record_buf_mem
[48];
10902 /* Fetch the list of registers. */
10903 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10904 arm_insn_r
->reg_rec_count
= 0;
10906 /* Fetch the base register that contains the address we are loading data
10908 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10910 /* Calculate wback. */
10911 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10913 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10915 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10917 /* Find out which registers are going to be loaded from memory. */
10918 while (register_bits
)
10920 if (register_bits
& 0x00000001)
10921 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10922 register_bits
= register_bits
>> 1;
10927 /* If wback is true, also save the base register, which is going to be
10930 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10932 /* Save the CPSR register. */
10933 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10937 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10939 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10941 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10943 /* Find out how many registers are going to be stored to memory. */
10944 while (register_bits
)
10946 if (register_bits
& 0x00000001)
10948 register_bits
= register_bits
>> 1;
10953 /* STMDA (STMED): Decrement after. */
10955 record_buf_mem
[1] = (uint32_t) u_regval
10956 - register_count
* ARM_INT_REGISTER_SIZE
+ 4;
10958 /* STM (STMIA, STMEA): Increment after. */
10960 record_buf_mem
[1] = (uint32_t) u_regval
;
10962 /* STMDB (STMFD): Decrement before. */
10964 record_buf_mem
[1] = (uint32_t) u_regval
10965 - register_count
* ARM_INT_REGISTER_SIZE
;
10967 /* STMIB (STMFA): Increment before. */
10969 record_buf_mem
[1] = (uint32_t) u_regval
+ ARM_INT_REGISTER_SIZE
;
10972 gdb_assert_not_reached ("no decoding pattern found");
10976 record_buf_mem
[0] = register_count
* ARM_INT_REGISTER_SIZE
;
10977 arm_insn_r
->mem_rec_count
= 1;
10979 /* If wback is true, also save the base register, which is going to be
10982 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10985 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10986 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10990 /* Handling opcode 101 insns. */
10993 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
10995 uint32_t record_buf
[8];
10997 /* Handle B, BL, BLX(1) insns. */
10998 /* B simply branches so we do nothing here. */
10999 /* Note: BLX(1) doesnt fall here but instead it falls into
11000 extension space. */
11001 if (bit (arm_insn_r
->arm_insn
, 24))
11003 record_buf
[0] = ARM_LR_REGNUM
;
11004 arm_insn_r
->reg_rec_count
= 1;
11007 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11013 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11015 printf_unfiltered (_("Process record does not support instruction "
11016 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11017 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11022 /* Record handler for vector data transfer instructions. */
11025 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11027 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11028 uint32_t record_buf
[4];
11030 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11031 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11032 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11033 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11034 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11036 /* Handle VMOV instruction. */
11037 if (bit_l
&& bit_c
)
11039 record_buf
[0] = reg_t
;
11040 arm_insn_r
->reg_rec_count
= 1;
11042 else if (bit_l
&& !bit_c
)
11044 /* Handle VMOV instruction. */
11045 if (bits_a
== 0x00)
11047 record_buf
[0] = reg_t
;
11048 arm_insn_r
->reg_rec_count
= 1;
11050 /* Handle VMRS instruction. */
11051 else if (bits_a
== 0x07)
11054 reg_t
= ARM_PS_REGNUM
;
11056 record_buf
[0] = reg_t
;
11057 arm_insn_r
->reg_rec_count
= 1;
11060 else if (!bit_l
&& !bit_c
)
11062 /* Handle VMOV instruction. */
11063 if (bits_a
== 0x00)
11065 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11067 arm_insn_r
->reg_rec_count
= 1;
11069 /* Handle VMSR instruction. */
11070 else if (bits_a
== 0x07)
11072 record_buf
[0] = ARM_FPSCR_REGNUM
;
11073 arm_insn_r
->reg_rec_count
= 1;
11076 else if (!bit_l
&& bit_c
)
11078 /* Handle VMOV instruction. */
11079 if (!(bits_a
& 0x04))
11081 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11083 arm_insn_r
->reg_rec_count
= 1;
11085 /* Handle VDUP instruction. */
11088 if (bit (arm_insn_r
->arm_insn
, 21))
11090 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11091 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11092 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11093 arm_insn_r
->reg_rec_count
= 2;
11097 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11098 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11099 arm_insn_r
->reg_rec_count
= 1;
11104 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11108 /* Record handler for extension register load/store instructions. */
11111 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11113 uint32_t opcode
, single_reg
;
11114 uint8_t op_vldm_vstm
;
11115 uint32_t record_buf
[8], record_buf_mem
[128];
11116 ULONGEST u_regval
= 0;
11118 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11120 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11121 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11122 op_vldm_vstm
= opcode
& 0x1b;
11124 /* Handle VMOV instructions. */
11125 if ((opcode
& 0x1e) == 0x04)
11127 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11129 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11130 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11131 arm_insn_r
->reg_rec_count
= 2;
11135 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11136 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11140 /* The first S register number m is REG_M:M (M is bit 5),
11141 the corresponding D register number is REG_M:M / 2, which
11143 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11144 /* The second S register number is REG_M:M + 1, the
11145 corresponding D register number is (REG_M:M + 1) / 2.
11146 IOW, if bit M is 1, the first and second S registers
11147 are mapped to different D registers, otherwise, they are
11148 in the same D register. */
11151 record_buf
[arm_insn_r
->reg_rec_count
++]
11152 = ARM_D0_REGNUM
+ reg_m
+ 1;
11157 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11158 arm_insn_r
->reg_rec_count
= 1;
11162 /* Handle VSTM and VPUSH instructions. */
11163 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11164 || op_vldm_vstm
== 0x12)
11166 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11167 uint32_t memory_index
= 0;
11169 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11170 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11171 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11172 imm_off32
= imm_off8
<< 2;
11173 memory_count
= imm_off8
;
11175 if (bit (arm_insn_r
->arm_insn
, 23))
11176 start_address
= u_regval
;
11178 start_address
= u_regval
- imm_off32
;
11180 if (bit (arm_insn_r
->arm_insn
, 21))
11182 record_buf
[0] = reg_rn
;
11183 arm_insn_r
->reg_rec_count
= 1;
11186 while (memory_count
> 0)
11190 record_buf_mem
[memory_index
] = 4;
11191 record_buf_mem
[memory_index
+ 1] = start_address
;
11192 start_address
= start_address
+ 4;
11193 memory_index
= memory_index
+ 2;
11197 record_buf_mem
[memory_index
] = 4;
11198 record_buf_mem
[memory_index
+ 1] = start_address
;
11199 record_buf_mem
[memory_index
+ 2] = 4;
11200 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11201 start_address
= start_address
+ 8;
11202 memory_index
= memory_index
+ 4;
11206 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11208 /* Handle VLDM instructions. */
11209 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11210 || op_vldm_vstm
== 0x13)
11212 uint32_t reg_count
, reg_vd
;
11213 uint32_t reg_index
= 0;
11214 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11216 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11217 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11219 /* REG_VD is the first D register number. If the instruction
11220 loads memory to S registers (SINGLE_REG is TRUE), the register
11221 number is (REG_VD << 1 | bit D), so the corresponding D
11222 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11224 reg_vd
= reg_vd
| (bit_d
<< 4);
11226 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11227 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11229 /* If the instruction loads memory to D register, REG_COUNT should
11230 be divided by 2, according to the ARM Architecture Reference
11231 Manual. If the instruction loads memory to S register, divide by
11232 2 as well because two S registers are mapped to D register. */
11233 reg_count
= reg_count
/ 2;
11234 if (single_reg
&& bit_d
)
11236 /* Increase the register count if S register list starts from
11237 an odd number (bit d is one). */
11241 while (reg_count
> 0)
11243 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11246 arm_insn_r
->reg_rec_count
= reg_index
;
11248 /* VSTR Vector store register. */
11249 else if ((opcode
& 0x13) == 0x10)
11251 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11252 uint32_t memory_index
= 0;
11254 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11255 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11256 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11257 imm_off32
= imm_off8
<< 2;
11259 if (bit (arm_insn_r
->arm_insn
, 23))
11260 start_address
= u_regval
+ imm_off32
;
11262 start_address
= u_regval
- imm_off32
;
11266 record_buf_mem
[memory_index
] = 4;
11267 record_buf_mem
[memory_index
+ 1] = start_address
;
11268 arm_insn_r
->mem_rec_count
= 1;
11272 record_buf_mem
[memory_index
] = 4;
11273 record_buf_mem
[memory_index
+ 1] = start_address
;
11274 record_buf_mem
[memory_index
+ 2] = 4;
11275 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11276 arm_insn_r
->mem_rec_count
= 2;
11279 /* VLDR Vector load register. */
11280 else if ((opcode
& 0x13) == 0x11)
11282 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11286 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11287 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11291 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11292 /* Record register D rather than pseudo register S. */
11293 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11295 arm_insn_r
->reg_rec_count
= 1;
11298 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11299 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11303 /* Record handler for arm/thumb mode VFP data processing instructions. */
11306 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11308 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11309 uint32_t record_buf
[4];
11310 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11311 enum insn_types curr_insn_type
= INSN_INV
;
11313 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11314 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11315 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11316 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11317 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11318 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11319 /* Mask off the "D" bit. */
11320 opc1
= opc1
& ~0x04;
11322 /* Handle VMLA, VMLS. */
11325 if (bit (arm_insn_r
->arm_insn
, 10))
11327 if (bit (arm_insn_r
->arm_insn
, 6))
11328 curr_insn_type
= INSN_T0
;
11330 curr_insn_type
= INSN_T1
;
11335 curr_insn_type
= INSN_T1
;
11337 curr_insn_type
= INSN_T2
;
11340 /* Handle VNMLA, VNMLS, VNMUL. */
11341 else if (opc1
== 0x01)
11344 curr_insn_type
= INSN_T1
;
11346 curr_insn_type
= INSN_T2
;
11349 else if (opc1
== 0x02 && !(opc3
& 0x01))
11351 if (bit (arm_insn_r
->arm_insn
, 10))
11353 if (bit (arm_insn_r
->arm_insn
, 6))
11354 curr_insn_type
= INSN_T0
;
11356 curr_insn_type
= INSN_T1
;
11361 curr_insn_type
= INSN_T1
;
11363 curr_insn_type
= INSN_T2
;
11366 /* Handle VADD, VSUB. */
11367 else if (opc1
== 0x03)
11369 if (!bit (arm_insn_r
->arm_insn
, 9))
11371 if (bit (arm_insn_r
->arm_insn
, 6))
11372 curr_insn_type
= INSN_T0
;
11374 curr_insn_type
= INSN_T1
;
11379 curr_insn_type
= INSN_T1
;
11381 curr_insn_type
= INSN_T2
;
11385 else if (opc1
== 0x08)
11388 curr_insn_type
= INSN_T1
;
11390 curr_insn_type
= INSN_T2
;
11392 /* Handle all other vfp data processing instructions. */
11393 else if (opc1
== 0x0b)
11396 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11398 if (bit (arm_insn_r
->arm_insn
, 4))
11400 if (bit (arm_insn_r
->arm_insn
, 6))
11401 curr_insn_type
= INSN_T0
;
11403 curr_insn_type
= INSN_T1
;
11408 curr_insn_type
= INSN_T1
;
11410 curr_insn_type
= INSN_T2
;
11413 /* Handle VNEG and VABS. */
11414 else if ((opc2
== 0x01 && opc3
== 0x01)
11415 || (opc2
== 0x00 && opc3
== 0x03))
11417 if (!bit (arm_insn_r
->arm_insn
, 11))
11419 if (bit (arm_insn_r
->arm_insn
, 6))
11420 curr_insn_type
= INSN_T0
;
11422 curr_insn_type
= INSN_T1
;
11427 curr_insn_type
= INSN_T1
;
11429 curr_insn_type
= INSN_T2
;
11432 /* Handle VSQRT. */
11433 else if (opc2
== 0x01 && opc3
== 0x03)
11436 curr_insn_type
= INSN_T1
;
11438 curr_insn_type
= INSN_T2
;
11441 else if (opc2
== 0x07 && opc3
== 0x03)
11444 curr_insn_type
= INSN_T1
;
11446 curr_insn_type
= INSN_T2
;
11448 else if (opc3
& 0x01)
11451 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11453 if (!bit (arm_insn_r
->arm_insn
, 18))
11454 curr_insn_type
= INSN_T2
;
11458 curr_insn_type
= INSN_T1
;
11460 curr_insn_type
= INSN_T2
;
11464 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11467 curr_insn_type
= INSN_T1
;
11469 curr_insn_type
= INSN_T2
;
11471 /* Handle VCVTB, VCVTT. */
11472 else if ((opc2
& 0x0e) == 0x02)
11473 curr_insn_type
= INSN_T2
;
11474 /* Handle VCMP, VCMPE. */
11475 else if ((opc2
& 0x0e) == 0x04)
11476 curr_insn_type
= INSN_T3
;
11480 switch (curr_insn_type
)
11483 reg_vd
= reg_vd
| (bit_d
<< 4);
11484 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11485 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11486 arm_insn_r
->reg_rec_count
= 2;
11490 reg_vd
= reg_vd
| (bit_d
<< 4);
11491 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11492 arm_insn_r
->reg_rec_count
= 1;
11496 reg_vd
= (reg_vd
<< 1) | bit_d
;
11497 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11498 arm_insn_r
->reg_rec_count
= 1;
11502 record_buf
[0] = ARM_FPSCR_REGNUM
;
11503 arm_insn_r
->reg_rec_count
= 1;
11507 gdb_assert_not_reached ("no decoding pattern found");
11511 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11515 /* Handling opcode 110 insns. */
11518 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11520 uint32_t op1
, op1_ebit
, coproc
;
11522 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11523 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11524 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11526 if ((coproc
& 0x0e) == 0x0a)
11528 /* Handle extension register ld/st instructions. */
11530 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11532 /* 64-bit transfers between arm core and extension registers. */
11533 if ((op1
& 0x3e) == 0x04)
11534 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11538 /* Handle coprocessor ld/st instructions. */
11543 return arm_record_unsupported_insn (arm_insn_r
);
11546 return arm_record_unsupported_insn (arm_insn_r
);
11549 /* Move to coprocessor from two arm core registers. */
11551 return arm_record_unsupported_insn (arm_insn_r
);
11553 /* Move to two arm core registers from coprocessor. */
11558 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11559 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11560 arm_insn_r
->reg_rec_count
= 2;
11562 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11566 return arm_record_unsupported_insn (arm_insn_r
);
11569 /* Handling opcode 111 insns. */
11572 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11574 uint32_t op
, op1_ebit
, coproc
, bits_24_25
;
11575 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11576 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11578 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11579 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11580 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11581 op
= bit (arm_insn_r
->arm_insn
, 4);
11582 bits_24_25
= bits (arm_insn_r
->arm_insn
, 24, 25);
11584 /* Handle arm SWI/SVC system call instructions. */
11585 if (bits_24_25
== 0x3)
11587 if (tdep
->arm_syscall_record
!= NULL
)
11589 ULONGEST svc_operand
, svc_number
;
11591 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11593 if (svc_operand
) /* OABI. */
11594 svc_number
= svc_operand
- 0x900000;
11596 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11598 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11602 printf_unfiltered (_("no syscall record support\n"));
11606 else if (bits_24_25
== 0x02)
11610 if ((coproc
& 0x0e) == 0x0a)
11612 /* 8, 16, and 32-bit transfer */
11613 return arm_record_vdata_transfer_insn (arm_insn_r
);
11620 uint32_t record_buf
[1];
11622 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11623 if (record_buf
[0] == 15)
11624 record_buf
[0] = ARM_PS_REGNUM
;
11626 arm_insn_r
->reg_rec_count
= 1;
11627 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11640 if ((coproc
& 0x0e) == 0x0a)
11642 /* VFP data-processing instructions. */
11643 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11654 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11658 if ((coproc
& 0x0e) != 0x0a)
11664 else if (op1
== 4 || op1
== 5)
11666 if ((coproc
& 0x0e) == 0x0a)
11668 /* 64-bit transfers between ARM core and extension */
11677 else if (op1
== 0 || op1
== 1)
11684 if ((coproc
& 0x0e) == 0x0a)
11686 /* Extension register load/store */
11690 /* STC, STC2, LDC, LDC2 */
11699 /* Handling opcode 000 insns. */
11702 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11704 uint32_t record_buf
[8];
11705 uint32_t reg_src1
= 0;
11707 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11709 record_buf
[0] = ARM_PS_REGNUM
;
11710 record_buf
[1] = reg_src1
;
11711 thumb_insn_r
->reg_rec_count
= 2;
11713 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11719 /* Handling opcode 001 insns. */
11722 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11724 uint32_t record_buf
[8];
11725 uint32_t reg_src1
= 0;
11727 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11729 record_buf
[0] = ARM_PS_REGNUM
;
11730 record_buf
[1] = reg_src1
;
11731 thumb_insn_r
->reg_rec_count
= 2;
11733 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11738 /* Handling opcode 010 insns. */
11741 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11743 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11744 uint32_t record_buf
[8], record_buf_mem
[8];
11746 uint32_t reg_src1
= 0, reg_src2
= 0;
11747 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11749 ULONGEST u_regval
[2] = {0};
11751 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11753 if (bit (thumb_insn_r
->arm_insn
, 12))
11755 /* Handle load/store register offset. */
11756 uint32_t opB
= bits (thumb_insn_r
->arm_insn
, 9, 11);
11758 if (in_inclusive_range (opB
, 4U, 7U))
11760 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11761 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11762 record_buf
[0] = reg_src1
;
11763 thumb_insn_r
->reg_rec_count
= 1;
11765 else if (in_inclusive_range (opB
, 0U, 2U))
11767 /* STR(2), STRB(2), STRH(2) . */
11768 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11769 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11770 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11771 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11773 record_buf_mem
[0] = 4; /* STR (2). */
11775 record_buf_mem
[0] = 1; /* STRB (2). */
11777 record_buf_mem
[0] = 2; /* STRH (2). */
11778 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11779 thumb_insn_r
->mem_rec_count
= 1;
11782 else if (bit (thumb_insn_r
->arm_insn
, 11))
11784 /* Handle load from literal pool. */
11786 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11787 record_buf
[0] = reg_src1
;
11788 thumb_insn_r
->reg_rec_count
= 1;
11792 /* Special data instructions and branch and exchange */
11793 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11794 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11795 if ((3 == opcode2
) && (!opcode3
))
11797 /* Branch with exchange. */
11798 record_buf
[0] = ARM_PS_REGNUM
;
11799 thumb_insn_r
->reg_rec_count
= 1;
11803 /* Format 8; special data processing insns. */
11804 record_buf
[0] = ARM_PS_REGNUM
;
11805 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11806 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11807 thumb_insn_r
->reg_rec_count
= 2;
11812 /* Format 5; data processing insns. */
11813 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11814 if (bit (thumb_insn_r
->arm_insn
, 7))
11816 reg_src1
= reg_src1
+ 8;
11818 record_buf
[0] = ARM_PS_REGNUM
;
11819 record_buf
[1] = reg_src1
;
11820 thumb_insn_r
->reg_rec_count
= 2;
11823 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11824 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11830 /* Handling opcode 001 insns. */
11833 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11835 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11836 uint32_t record_buf
[8], record_buf_mem
[8];
11838 uint32_t reg_src1
= 0;
11839 uint32_t opcode
= 0, immed_5
= 0;
11841 ULONGEST u_regval
= 0;
11843 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11848 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11849 record_buf
[0] = reg_src1
;
11850 thumb_insn_r
->reg_rec_count
= 1;
11855 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11856 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11857 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11858 record_buf_mem
[0] = 4;
11859 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11860 thumb_insn_r
->mem_rec_count
= 1;
11863 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11864 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11870 /* Handling opcode 100 insns. */
11873 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11875 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11876 uint32_t record_buf
[8], record_buf_mem
[8];
11878 uint32_t reg_src1
= 0;
11879 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11881 ULONGEST u_regval
= 0;
11883 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11888 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11889 record_buf
[0] = reg_src1
;
11890 thumb_insn_r
->reg_rec_count
= 1;
11892 else if (1 == opcode
)
11895 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11896 record_buf
[0] = reg_src1
;
11897 thumb_insn_r
->reg_rec_count
= 1;
11899 else if (2 == opcode
)
11902 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11903 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11904 record_buf_mem
[0] = 4;
11905 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11906 thumb_insn_r
->mem_rec_count
= 1;
11908 else if (0 == opcode
)
11911 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11912 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11913 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11914 record_buf_mem
[0] = 2;
11915 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11916 thumb_insn_r
->mem_rec_count
= 1;
11919 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11920 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11926 /* Handling opcode 101 insns. */
11929 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11931 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11933 uint32_t opcode
= 0;
11934 uint32_t register_bits
= 0, register_count
= 0;
11935 uint32_t index
= 0, start_address
= 0;
11936 uint32_t record_buf
[24], record_buf_mem
[48];
11939 ULONGEST u_regval
= 0;
11941 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11943 if (opcode
== 0 || opcode
== 1)
11945 /* ADR and ADD (SP plus immediate) */
11947 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11948 record_buf
[0] = reg_src1
;
11949 thumb_insn_r
->reg_rec_count
= 1;
11953 /* Miscellaneous 16-bit instructions */
11954 uint32_t opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 11);
11959 /* SETEND and CPS */
11962 /* ADD/SUB (SP plus immediate) */
11963 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11964 record_buf
[0] = ARM_SP_REGNUM
;
11965 thumb_insn_r
->reg_rec_count
= 1;
11967 case 1: /* fall through */
11968 case 3: /* fall through */
11969 case 9: /* fall through */
11974 /* SXTH, SXTB, UXTH, UXTB */
11975 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
11976 thumb_insn_r
->reg_rec_count
= 1;
11978 case 4: /* fall through */
11981 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11982 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11983 while (register_bits
)
11985 if (register_bits
& 0x00000001)
11987 register_bits
= register_bits
>> 1;
11989 start_address
= u_regval
- \
11990 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11991 thumb_insn_r
->mem_rec_count
= register_count
;
11992 while (register_count
)
11994 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11995 record_buf_mem
[(register_count
* 2) - 2] = 4;
11996 start_address
= start_address
+ 4;
11999 record_buf
[0] = ARM_SP_REGNUM
;
12000 thumb_insn_r
->reg_rec_count
= 1;
12003 /* REV, REV16, REVSH */
12004 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
12005 thumb_insn_r
->reg_rec_count
= 1;
12007 case 12: /* fall through */
12010 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12011 while (register_bits
)
12013 if (register_bits
& 0x00000001)
12014 record_buf
[index
++] = register_count
;
12015 register_bits
= register_bits
>> 1;
12018 record_buf
[index
++] = ARM_PS_REGNUM
;
12019 record_buf
[index
++] = ARM_SP_REGNUM
;
12020 thumb_insn_r
->reg_rec_count
= index
;
12024 /* Handle enhanced software breakpoint insn, BKPT. */
12025 /* CPSR is changed to be executed in ARM state, disabling normal
12026 interrupts, entering abort mode. */
12027 /* According to high vector configuration PC is set. */
12028 /* User hits breakpoint and type reverse, in that case, we need to go back with
12029 previous CPSR and Program Counter. */
12030 record_buf
[0] = ARM_PS_REGNUM
;
12031 record_buf
[1] = ARM_LR_REGNUM
;
12032 thumb_insn_r
->reg_rec_count
= 2;
12033 /* We need to save SPSR value, which is not yet done. */
12034 printf_unfiltered (_("Process record does not support instruction "
12035 "0x%0x at address %s.\n"),
12036 thumb_insn_r
->arm_insn
,
12037 paddress (thumb_insn_r
->gdbarch
,
12038 thumb_insn_r
->this_addr
));
12042 /* If-Then, and hints */
12049 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12050 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12056 /* Handling opcode 110 insns. */
12059 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12061 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12062 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12064 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12065 uint32_t reg_src1
= 0;
12066 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12067 uint32_t index
= 0, start_address
= 0;
12068 uint32_t record_buf
[24], record_buf_mem
[48];
12070 ULONGEST u_regval
= 0;
12072 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12073 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12079 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12081 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12082 while (register_bits
)
12084 if (register_bits
& 0x00000001)
12085 record_buf
[index
++] = register_count
;
12086 register_bits
= register_bits
>> 1;
12089 record_buf
[index
++] = reg_src1
;
12090 thumb_insn_r
->reg_rec_count
= index
;
12092 else if (0 == opcode2
)
12094 /* It handles both STMIA. */
12095 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12097 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12098 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12099 while (register_bits
)
12101 if (register_bits
& 0x00000001)
12103 register_bits
= register_bits
>> 1;
12105 start_address
= u_regval
;
12106 thumb_insn_r
->mem_rec_count
= register_count
;
12107 while (register_count
)
12109 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12110 record_buf_mem
[(register_count
* 2) - 2] = 4;
12111 start_address
= start_address
+ 4;
12115 else if (0x1F == opcode1
)
12117 /* Handle arm syscall insn. */
12118 if (tdep
->arm_syscall_record
!= NULL
)
12120 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12121 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12125 printf_unfiltered (_("no syscall record support\n"));
12130 /* B (1), conditional branch is automatically taken care in process_record,
12131 as PC is saved there. */
12133 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12134 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12140 /* Handling opcode 111 insns. */
12143 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12145 uint32_t record_buf
[8];
12146 uint32_t bits_h
= 0;
12148 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12150 if (2 == bits_h
|| 3 == bits_h
)
12153 record_buf
[0] = ARM_LR_REGNUM
;
12154 thumb_insn_r
->reg_rec_count
= 1;
12156 else if (1 == bits_h
)
12159 record_buf
[0] = ARM_PS_REGNUM
;
12160 record_buf
[1] = ARM_LR_REGNUM
;
12161 thumb_insn_r
->reg_rec_count
= 2;
12164 /* B(2) is automatically taken care in process_record, as PC is
12167 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12172 /* Handler for thumb2 load/store multiple instructions. */
12175 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12177 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12179 uint32_t reg_rn
, op
;
12180 uint32_t register_bits
= 0, register_count
= 0;
12181 uint32_t index
= 0, start_address
= 0;
12182 uint32_t record_buf
[24], record_buf_mem
[48];
12184 ULONGEST u_regval
= 0;
12186 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12187 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12189 if (0 == op
|| 3 == op
)
12191 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12193 /* Handle RFE instruction. */
12194 record_buf
[0] = ARM_PS_REGNUM
;
12195 thumb2_insn_r
->reg_rec_count
= 1;
12199 /* Handle SRS instruction after reading banked SP. */
12200 return arm_record_unsupported_insn (thumb2_insn_r
);
12203 else if (1 == op
|| 2 == op
)
12205 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12207 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12208 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12209 while (register_bits
)
12211 if (register_bits
& 0x00000001)
12212 record_buf
[index
++] = register_count
;
12215 register_bits
= register_bits
>> 1;
12217 record_buf
[index
++] = reg_rn
;
12218 record_buf
[index
++] = ARM_PS_REGNUM
;
12219 thumb2_insn_r
->reg_rec_count
= index
;
12223 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12224 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12225 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12226 while (register_bits
)
12228 if (register_bits
& 0x00000001)
12231 register_bits
= register_bits
>> 1;
12236 /* Start address calculation for LDMDB/LDMEA. */
12237 start_address
= u_regval
;
12241 /* Start address calculation for LDMDB/LDMEA. */
12242 start_address
= u_regval
- register_count
* 4;
12245 thumb2_insn_r
->mem_rec_count
= register_count
;
12246 while (register_count
)
12248 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12249 record_buf_mem
[register_count
* 2 - 2] = 4;
12250 start_address
= start_address
+ 4;
12253 record_buf
[0] = reg_rn
;
12254 record_buf
[1] = ARM_PS_REGNUM
;
12255 thumb2_insn_r
->reg_rec_count
= 2;
12259 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12261 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12263 return ARM_RECORD_SUCCESS
;
12266 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12270 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12272 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12274 uint32_t reg_rd
, reg_rn
, offset_imm
;
12275 uint32_t reg_dest1
, reg_dest2
;
12276 uint32_t address
, offset_addr
;
12277 uint32_t record_buf
[8], record_buf_mem
[8];
12278 uint32_t op1
, op2
, op3
;
12280 ULONGEST u_regval
[2];
12282 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12283 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12284 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12286 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12288 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12290 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12291 record_buf
[0] = reg_dest1
;
12292 record_buf
[1] = ARM_PS_REGNUM
;
12293 thumb2_insn_r
->reg_rec_count
= 2;
12296 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12298 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12299 record_buf
[2] = reg_dest2
;
12300 thumb2_insn_r
->reg_rec_count
= 3;
12305 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12306 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12308 if (0 == op1
&& 0 == op2
)
12310 /* Handle STREX. */
12311 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12312 address
= u_regval
[0] + (offset_imm
* 4);
12313 record_buf_mem
[0] = 4;
12314 record_buf_mem
[1] = address
;
12315 thumb2_insn_r
->mem_rec_count
= 1;
12316 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12317 record_buf
[0] = reg_rd
;
12318 thumb2_insn_r
->reg_rec_count
= 1;
12320 else if (1 == op1
&& 0 == op2
)
12322 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12323 record_buf
[0] = reg_rd
;
12324 thumb2_insn_r
->reg_rec_count
= 1;
12325 address
= u_regval
[0];
12326 record_buf_mem
[1] = address
;
12330 /* Handle STREXB. */
12331 record_buf_mem
[0] = 1;
12332 thumb2_insn_r
->mem_rec_count
= 1;
12336 /* Handle STREXH. */
12337 record_buf_mem
[0] = 2 ;
12338 thumb2_insn_r
->mem_rec_count
= 1;
12342 /* Handle STREXD. */
12343 address
= u_regval
[0];
12344 record_buf_mem
[0] = 4;
12345 record_buf_mem
[2] = 4;
12346 record_buf_mem
[3] = address
+ 4;
12347 thumb2_insn_r
->mem_rec_count
= 2;
12352 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12354 if (bit (thumb2_insn_r
->arm_insn
, 24))
12356 if (bit (thumb2_insn_r
->arm_insn
, 23))
12357 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12359 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12361 address
= offset_addr
;
12364 address
= u_regval
[0];
12366 record_buf_mem
[0] = 4;
12367 record_buf_mem
[1] = address
;
12368 record_buf_mem
[2] = 4;
12369 record_buf_mem
[3] = address
+ 4;
12370 thumb2_insn_r
->mem_rec_count
= 2;
12371 record_buf
[0] = reg_rn
;
12372 thumb2_insn_r
->reg_rec_count
= 1;
12376 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12378 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12380 return ARM_RECORD_SUCCESS
;
12383 /* Handler for thumb2 data processing (shift register and modified immediate)
12387 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12389 uint32_t reg_rd
, op
;
12390 uint32_t record_buf
[8];
12392 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12393 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12395 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12397 record_buf
[0] = ARM_PS_REGNUM
;
12398 thumb2_insn_r
->reg_rec_count
= 1;
12402 record_buf
[0] = reg_rd
;
12403 record_buf
[1] = ARM_PS_REGNUM
;
12404 thumb2_insn_r
->reg_rec_count
= 2;
12407 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12409 return ARM_RECORD_SUCCESS
;
12412 /* Generic handler for thumb2 instructions which effect destination and PS
12416 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12419 uint32_t record_buf
[8];
12421 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12423 record_buf
[0] = reg_rd
;
12424 record_buf
[1] = ARM_PS_REGNUM
;
12425 thumb2_insn_r
->reg_rec_count
= 2;
12427 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12429 return ARM_RECORD_SUCCESS
;
12432 /* Handler for thumb2 branch and miscellaneous control instructions. */
12435 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12437 uint32_t op
, op1
, op2
;
12438 uint32_t record_buf
[8];
12440 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12441 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12442 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12444 /* Handle MSR insn. */
12445 if (!(op1
& 0x2) && 0x38 == op
)
12449 /* CPSR is going to be changed. */
12450 record_buf
[0] = ARM_PS_REGNUM
;
12451 thumb2_insn_r
->reg_rec_count
= 1;
12455 arm_record_unsupported_insn(thumb2_insn_r
);
12459 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12462 record_buf
[0] = ARM_PS_REGNUM
;
12463 record_buf
[1] = ARM_LR_REGNUM
;
12464 thumb2_insn_r
->reg_rec_count
= 2;
12467 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12469 return ARM_RECORD_SUCCESS
;
12472 /* Handler for thumb2 store single data item instructions. */
12475 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12477 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12479 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12480 uint32_t address
, offset_addr
;
12481 uint32_t record_buf
[8], record_buf_mem
[8];
12484 ULONGEST u_regval
[2];
12486 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12487 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12488 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12489 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12491 if (bit (thumb2_insn_r
->arm_insn
, 23))
12494 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12495 offset_addr
= u_regval
[0] + offset_imm
;
12496 address
= offset_addr
;
12501 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12503 /* Handle STRB (register). */
12504 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12505 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12506 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12507 offset_addr
= u_regval
[1] << shift_imm
;
12508 address
= u_regval
[0] + offset_addr
;
12512 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12513 if (bit (thumb2_insn_r
->arm_insn
, 10))
12515 if (bit (thumb2_insn_r
->arm_insn
, 9))
12516 offset_addr
= u_regval
[0] + offset_imm
;
12518 offset_addr
= u_regval
[0] - offset_imm
;
12520 address
= offset_addr
;
12523 address
= u_regval
[0];
12529 /* Store byte instructions. */
12532 record_buf_mem
[0] = 1;
12534 /* Store half word instructions. */
12537 record_buf_mem
[0] = 2;
12539 /* Store word instructions. */
12542 record_buf_mem
[0] = 4;
12546 gdb_assert_not_reached ("no decoding pattern found");
12550 record_buf_mem
[1] = address
;
12551 thumb2_insn_r
->mem_rec_count
= 1;
12552 record_buf
[0] = reg_rn
;
12553 thumb2_insn_r
->reg_rec_count
= 1;
12555 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12557 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12559 return ARM_RECORD_SUCCESS
;
12562 /* Handler for thumb2 load memory hints instructions. */
12565 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12567 uint32_t record_buf
[8];
12568 uint32_t reg_rt
, reg_rn
;
12570 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12571 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12573 if (ARM_PC_REGNUM
!= reg_rt
)
12575 record_buf
[0] = reg_rt
;
12576 record_buf
[1] = reg_rn
;
12577 record_buf
[2] = ARM_PS_REGNUM
;
12578 thumb2_insn_r
->reg_rec_count
= 3;
12580 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12582 return ARM_RECORD_SUCCESS
;
12585 return ARM_RECORD_FAILURE
;
12588 /* Handler for thumb2 load word instructions. */
12591 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12593 uint32_t record_buf
[8];
12595 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12596 record_buf
[1] = ARM_PS_REGNUM
;
12597 thumb2_insn_r
->reg_rec_count
= 2;
12599 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12601 return ARM_RECORD_SUCCESS
;
12604 /* Handler for thumb2 long multiply, long multiply accumulate, and
12605 divide instructions. */
12608 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12610 uint32_t opcode1
= 0, opcode2
= 0;
12611 uint32_t record_buf
[8];
12613 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12614 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12616 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12618 /* Handle SMULL, UMULL, SMULAL. */
12619 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12620 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12621 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12622 record_buf
[2] = ARM_PS_REGNUM
;
12623 thumb2_insn_r
->reg_rec_count
= 3;
12625 else if (1 == opcode1
|| 3 == opcode2
)
12627 /* Handle SDIV and UDIV. */
12628 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12629 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12630 record_buf
[2] = ARM_PS_REGNUM
;
12631 thumb2_insn_r
->reg_rec_count
= 3;
12634 return ARM_RECORD_FAILURE
;
12636 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12638 return ARM_RECORD_SUCCESS
;
12641 /* Record handler for thumb32 coprocessor instructions. */
12644 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12646 if (bit (thumb2_insn_r
->arm_insn
, 25))
12647 return arm_record_coproc_data_proc (thumb2_insn_r
);
12649 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12652 /* Record handler for advance SIMD structure load/store instructions. */
12655 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12657 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12658 uint32_t l_bit
, a_bit
, b_bits
;
12659 uint32_t record_buf
[128], record_buf_mem
[128];
12660 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12661 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12664 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12665 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12666 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12667 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12668 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12669 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12670 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12671 f_elem
= 8 / f_ebytes
;
12675 ULONGEST u_regval
= 0;
12676 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12677 address
= u_regval
;
12682 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12684 if (b_bits
== 0x07)
12686 else if (b_bits
== 0x0a)
12688 else if (b_bits
== 0x06)
12690 else if (b_bits
== 0x02)
12695 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12697 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12699 record_buf_mem
[index_m
++] = f_ebytes
;
12700 record_buf_mem
[index_m
++] = address
;
12701 address
= address
+ f_ebytes
;
12702 thumb2_insn_r
->mem_rec_count
+= 1;
12707 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12709 if (b_bits
== 0x09 || b_bits
== 0x08)
12711 else if (b_bits
== 0x03)
12716 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12717 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12719 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12721 record_buf_mem
[index_m
++] = f_ebytes
;
12722 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12723 thumb2_insn_r
->mem_rec_count
+= 1;
12725 address
= address
+ (2 * f_ebytes
);
12729 else if ((b_bits
& 0x0e) == 0x04)
12731 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12733 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12735 record_buf_mem
[index_m
++] = f_ebytes
;
12736 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12737 thumb2_insn_r
->mem_rec_count
+= 1;
12739 address
= address
+ (3 * f_ebytes
);
12743 else if (!(b_bits
& 0x0e))
12745 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12747 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12749 record_buf_mem
[index_m
++] = f_ebytes
;
12750 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12751 thumb2_insn_r
->mem_rec_count
+= 1;
12753 address
= address
+ (4 * f_ebytes
);
12759 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12761 if (bft_size
== 0x00)
12763 else if (bft_size
== 0x01)
12765 else if (bft_size
== 0x02)
12771 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12772 thumb2_insn_r
->mem_rec_count
= 1;
12774 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12775 thumb2_insn_r
->mem_rec_count
= 2;
12777 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12778 thumb2_insn_r
->mem_rec_count
= 3;
12780 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12781 thumb2_insn_r
->mem_rec_count
= 4;
12783 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12785 record_buf_mem
[index_m
] = f_ebytes
;
12786 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12795 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12796 thumb2_insn_r
->reg_rec_count
= 1;
12798 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12799 thumb2_insn_r
->reg_rec_count
= 2;
12801 else if ((b_bits
& 0x0e) == 0x04)
12802 thumb2_insn_r
->reg_rec_count
= 3;
12804 else if (!(b_bits
& 0x0e))
12805 thumb2_insn_r
->reg_rec_count
= 4;
12810 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12811 thumb2_insn_r
->reg_rec_count
= 1;
12813 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12814 thumb2_insn_r
->reg_rec_count
= 2;
12816 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12817 thumb2_insn_r
->reg_rec_count
= 3;
12819 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12820 thumb2_insn_r
->reg_rec_count
= 4;
12822 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12823 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12827 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12829 record_buf
[index_r
] = reg_rn
;
12830 thumb2_insn_r
->reg_rec_count
+= 1;
12833 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12835 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12840 /* Decodes thumb2 instruction type and invokes its record handler. */
12842 static unsigned int
12843 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12845 uint32_t op
, op1
, op2
;
12847 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12848 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12849 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12853 if (!(op2
& 0x64 ))
12855 /* Load/store multiple instruction. */
12856 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12858 else if ((op2
& 0x64) == 0x4)
12860 /* Load/store (dual/exclusive) and table branch instruction. */
12861 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12863 else if ((op2
& 0x60) == 0x20)
12865 /* Data-processing (shifted register). */
12866 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12868 else if (op2
& 0x40)
12870 /* Co-processor instructions. */
12871 return thumb2_record_coproc_insn (thumb2_insn_r
);
12874 else if (op1
== 0x02)
12878 /* Branches and miscellaneous control instructions. */
12879 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12881 else if (op2
& 0x20)
12883 /* Data-processing (plain binary immediate) instruction. */
12884 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12888 /* Data-processing (modified immediate). */
12889 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12892 else if (op1
== 0x03)
12894 if (!(op2
& 0x71 ))
12896 /* Store single data item. */
12897 return thumb2_record_str_single_data (thumb2_insn_r
);
12899 else if (!((op2
& 0x71) ^ 0x10))
12901 /* Advanced SIMD or structure load/store instructions. */
12902 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12904 else if (!((op2
& 0x67) ^ 0x01))
12906 /* Load byte, memory hints instruction. */
12907 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12909 else if (!((op2
& 0x67) ^ 0x03))
12911 /* Load halfword, memory hints instruction. */
12912 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12914 else if (!((op2
& 0x67) ^ 0x05))
12916 /* Load word instruction. */
12917 return thumb2_record_ld_word (thumb2_insn_r
);
12919 else if (!((op2
& 0x70) ^ 0x20))
12921 /* Data-processing (register) instruction. */
12922 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12924 else if (!((op2
& 0x78) ^ 0x30))
12926 /* Multiply, multiply accumulate, abs diff instruction. */
12927 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12929 else if (!((op2
& 0x78) ^ 0x38))
12931 /* Long multiply, long multiply accumulate, and divide. */
12932 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12934 else if (op2
& 0x40)
12936 /* Co-processor instructions. */
12937 return thumb2_record_coproc_insn (thumb2_insn_r
);
12945 /* Abstract memory reader. */
12947 class abstract_memory_reader
12950 /* Read LEN bytes of target memory at address MEMADDR, placing the
12951 results in GDB's memory at BUF. Return true on success. */
12953 virtual bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) = 0;
12956 /* Instruction reader from real target. */
12958 class instruction_reader
: public abstract_memory_reader
12961 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
12963 if (target_read_memory (memaddr
, buf
, len
))
12972 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12973 and positive val on fauilure. */
12976 extract_arm_insn (abstract_memory_reader
& reader
,
12977 insn_decode_record
*insn_record
, uint32_t insn_size
)
12979 gdb_byte buf
[insn_size
];
12981 memset (&buf
[0], 0, insn_size
);
12983 if (!reader
.read (insn_record
->this_addr
, buf
, insn_size
))
12985 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12987 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12991 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12993 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12997 decode_insn (abstract_memory_reader
&reader
, insn_decode_record
*arm_record
,
12998 record_type_t record_type
, uint32_t insn_size
)
13001 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
13003 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13005 arm_record_data_proc_misc_ld_str
, /* 000. */
13006 arm_record_data_proc_imm
, /* 001. */
13007 arm_record_ld_st_imm_offset
, /* 010. */
13008 arm_record_ld_st_reg_offset
, /* 011. */
13009 arm_record_ld_st_multiple
, /* 100. */
13010 arm_record_b_bl
, /* 101. */
13011 arm_record_asimd_vfp_coproc
, /* 110. */
13012 arm_record_coproc_data_proc
/* 111. */
13015 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
13017 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13019 thumb_record_shift_add_sub
, /* 000. */
13020 thumb_record_add_sub_cmp_mov
, /* 001. */
13021 thumb_record_ld_st_reg_offset
, /* 010. */
13022 thumb_record_ld_st_imm_offset
, /* 011. */
13023 thumb_record_ld_st_stack
, /* 100. */
13024 thumb_record_misc
, /* 101. */
13025 thumb_record_ldm_stm_swi
, /* 110. */
13026 thumb_record_branch
/* 111. */
13029 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13030 uint32_t insn_id
= 0;
13032 if (extract_arm_insn (reader
, arm_record
, insn_size
))
13036 printf_unfiltered (_("Process record: error reading memory at "
13037 "addr %s len = %d.\n"),
13038 paddress (arm_record
->gdbarch
,
13039 arm_record
->this_addr
), insn_size
);
13043 else if (ARM_RECORD
== record_type
)
13045 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13046 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13048 if (arm_record
->cond
== 0xf)
13049 ret
= arm_record_extension_space (arm_record
);
13052 /* If this insn has fallen into extension space
13053 then we need not decode it anymore. */
13054 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13056 if (ret
!= ARM_RECORD_SUCCESS
)
13058 arm_record_unsupported_insn (arm_record
);
13062 else if (THUMB_RECORD
== record_type
)
13064 /* As thumb does not have condition codes, we set negative. */
13065 arm_record
->cond
= -1;
13066 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13067 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13068 if (ret
!= ARM_RECORD_SUCCESS
)
13070 arm_record_unsupported_insn (arm_record
);
13074 else if (THUMB2_RECORD
== record_type
)
13076 /* As thumb does not have condition codes, we set negative. */
13077 arm_record
->cond
= -1;
13079 /* Swap first half of 32bit thumb instruction with second half. */
13080 arm_record
->arm_insn
13081 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13083 ret
= thumb2_record_decode_insn_handler (arm_record
);
13085 if (ret
!= ARM_RECORD_SUCCESS
)
13087 arm_record_unsupported_insn (arm_record
);
13093 /* Throw assertion. */
13094 gdb_assert_not_reached ("not a valid instruction, could not decode");
13101 namespace selftests
{
13103 /* Provide both 16-bit and 32-bit thumb instructions. */
13105 class instruction_reader_thumb
: public abstract_memory_reader
13108 template<size_t SIZE
>
13109 instruction_reader_thumb (enum bfd_endian endian
,
13110 const uint16_t (&insns
)[SIZE
])
13111 : m_endian (endian
), m_insns (insns
), m_insns_size (SIZE
)
13114 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
13116 SELF_CHECK (len
== 4 || len
== 2);
13117 SELF_CHECK (memaddr
% 2 == 0);
13118 SELF_CHECK ((memaddr
/ 2) < m_insns_size
);
13120 store_unsigned_integer (buf
, 2, m_endian
, m_insns
[memaddr
/ 2]);
13123 store_unsigned_integer (&buf
[2], 2, m_endian
,
13124 m_insns
[memaddr
/ 2 + 1]);
13130 enum bfd_endian m_endian
;
13131 const uint16_t *m_insns
;
13132 size_t m_insns_size
;
13136 arm_record_test (void)
13138 struct gdbarch_info info
;
13139 gdbarch_info_init (&info
);
13140 info
.bfd_arch_info
= bfd_scan_arch ("arm");
13142 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
13144 SELF_CHECK (gdbarch
!= NULL
);
13146 /* 16-bit Thumb instructions. */
13148 insn_decode_record arm_record
;
13150 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13151 arm_record
.gdbarch
= gdbarch
;
13153 static const uint16_t insns
[] = {
13154 /* db b2 uxtb r3, r3 */
13156 /* cd 58 ldr r5, [r1, r3] */
13160 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13161 instruction_reader_thumb
reader (endian
, insns
);
13162 int ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13163 THUMB_INSN_SIZE_BYTES
);
13165 SELF_CHECK (ret
== 0);
13166 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13167 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13168 SELF_CHECK (arm_record
.arm_regs
[0] == 3);
13170 arm_record
.this_addr
+= 2;
13171 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13172 THUMB_INSN_SIZE_BYTES
);
13174 SELF_CHECK (ret
== 0);
13175 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13176 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13177 SELF_CHECK (arm_record
.arm_regs
[0] == 5);
13180 /* 32-bit Thumb-2 instructions. */
13182 insn_decode_record arm_record
;
13184 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13185 arm_record
.gdbarch
= gdbarch
;
13187 static const uint16_t insns
[] = {
13188 /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
13192 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13193 instruction_reader_thumb
reader (endian
, insns
);
13194 int ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13195 THUMB2_INSN_SIZE_BYTES
);
13197 SELF_CHECK (ret
== 0);
13198 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13199 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13200 SELF_CHECK (arm_record
.arm_regs
[0] == 7);
13203 } // namespace selftests
13204 #endif /* GDB_SELF_TEST */
13206 /* Cleans up local record registers and memory allocations. */
13209 deallocate_reg_mem (insn_decode_record
*record
)
13211 xfree (record
->arm_regs
);
13212 xfree (record
->arm_mems
);
13216 /* Parse the current instruction and record the values of the registers and
13217 memory that will be changed in current instruction to record_arch_list".
13218 Return -1 if something is wrong. */
13221 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13222 CORE_ADDR insn_addr
)
13225 uint32_t no_of_rec
= 0;
13226 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13227 ULONGEST t_bit
= 0, insn_id
= 0;
13229 ULONGEST u_regval
= 0;
13231 insn_decode_record arm_record
;
13233 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13234 arm_record
.regcache
= regcache
;
13235 arm_record
.this_addr
= insn_addr
;
13236 arm_record
.gdbarch
= gdbarch
;
13239 if (record_debug
> 1)
13241 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13243 paddress (gdbarch
, arm_record
.this_addr
));
13246 instruction_reader reader
;
13247 if (extract_arm_insn (reader
, &arm_record
, 2))
13251 printf_unfiltered (_("Process record: error reading memory at "
13252 "addr %s len = %d.\n"),
13253 paddress (arm_record
.gdbarch
,
13254 arm_record
.this_addr
), 2);
13259 /* Check the insn, whether it is thumb or arm one. */
13261 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13262 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13265 if (!(u_regval
& t_bit
))
13267 /* We are decoding arm insn. */
13268 ret
= decode_insn (reader
, &arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13272 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13273 /* is it thumb2 insn? */
13274 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13276 ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13277 THUMB2_INSN_SIZE_BYTES
);
13281 /* We are decoding thumb insn. */
13282 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13283 THUMB_INSN_SIZE_BYTES
);
13289 /* Record registers. */
13290 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13291 if (arm_record
.arm_regs
)
13293 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13295 if (record_full_arch_list_add_reg
13296 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13300 /* Record memories. */
13301 if (arm_record
.arm_mems
)
13303 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13305 if (record_full_arch_list_add_mem
13306 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13307 arm_record
.arm_mems
[no_of_rec
].len
))
13312 if (record_full_arch_list_add_end ())
13317 deallocate_reg_mem (&arm_record
);
13322 /* See arm-tdep.h. */
13324 const target_desc
*
13325 arm_read_description (arm_fp_type fp_type
)
13327 struct target_desc
*tdesc
= tdesc_arm_list
[fp_type
];
13329 if (tdesc
== nullptr)
13331 tdesc
= arm_create_target_description (fp_type
);
13332 tdesc_arm_list
[fp_type
] = tdesc
;
13338 /* See arm-tdep.h. */
13340 const target_desc
*
13341 arm_read_mprofile_description (arm_m_profile_type m_type
)
13343 struct target_desc
*tdesc
= tdesc_arm_mprofile_list
[m_type
];
13345 if (tdesc
== nullptr)
13347 tdesc
= arm_create_mprofile_target_description (m_type
);
13348 tdesc_arm_mprofile_list
[m_type
] = tdesc
;