gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright 2002, 2003 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330,
  19    Boston, MA 02111-1307, USA.  */
  20
  21 /* Register numbers of various important registers.  Note that some of
  22    these values are "real" register numbers, and correspond to the
  23    general registers of the machine, and some are "phony" register
  24    numbers which are too large to be actual register numbers as far as
  25    the user is concerned but do serve to get the desired values when
  26    passed to read_register.  */
  27
  28 enum gdb_regnum {
  29   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  30   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  31   ARM_AP_REGNUM = 11,
  32   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  33   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  34   ARM_PC_REGNUM = 15,           /* Contains program counter */
  35   ARM_F0_REGNUM = 16,           /* first floating point register */
  36   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  37   ARM_F7_REGNUM = 23,           /* last floating point register */
  38   ARM_FPS_REGNUM = 24,          /* floating point status register */
  39   ARM_PS_REGNUM = 25,           /* Contains processor status */
  40   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  41   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  42   ARM_NUM_ARG_REGS = 4,
  43   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  44   ARM_NUM_FP_ARG_REGS = 4,
  45   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  46 };
  47
  48 /* Size of integer registers.  */
  49 #define INT_REGISTER_SIZE               4
  50
  51 /* Say how long FP registers are.  Used for documentation purposes and
  52    code readability in this header.  IEEE extended doubles are 80
  53    bits.  DWORD aligned they use 96 bits.  */
  54 #define FP_REGISTER_SIZE        12
  55
  56 /* Status registers are the same size as general purpose registers.
  57    Used for documentation purposes and code readability in this
  58    header.  */
  59 #define STATUS_REGISTER_SIZE    4
  60
  61 /* Number of machine registers.  The only define actually required
  62    is NUM_REGS.  The other definitions are used for documentation
  63    purposes and code readability.  */
  64 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  65    (and called PS for processor status) so the status bits can be cleared
  66    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  67    in PS.  */
  68 #define NUM_FREGS       8       /* Number of floating point registers.  */
  69 #define NUM_SREGS       2       /* Number of status registers.  */
  70 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  71
  72
  73 /* Instruction condition field values.  */
  74 #define INST_EQ         0x0
  75 #define INST_NE         0x1
  76 #define INST_CS         0x2
  77 #define INST_CC         0x3
  78 #define INST_MI         0x4
  79 #define INST_PL         0x5
  80 #define INST_VS         0x6
  81 #define INST_VC         0x7
  82 #define INST_HI         0x8
  83 #define INST_LS         0x9
  84 #define INST_GE         0xa
  85 #define INST_LT         0xb
  86 #define INST_GT         0xc
  87 #define INST_LE         0xd
  88 #define INST_AL         0xe
  89 #define INST_NV         0xf
  90
  91 #define FLAG_N          0x80000000
  92 #define FLAG_Z          0x40000000
  93 #define FLAG_C          0x20000000
  94 #define FLAG_V          0x10000000
  95
  96 /* Type of floating-point code in use by inferior.  There are really 3 models
  97    that are traditionally supported (plus the endianness issue), but gcc can
  98    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
  99    functions are passed in floating-point registers.
 100
 101    In addition to the traditional models, VFP adds two more.
 102
 103    If you update this enum, don't forget to update fp_model_strings in
 104    arm-tdep.c.  */
 105
 106 enum arm_float_model
 107 {
 108   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 109   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 110   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 111   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 112   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 113   ARM_FLOAT_LAST        /* Keep at end.  */
 114 };
 115
 116 /* ABI used by the inferior.  */
 117 enum arm_abi_kind
 118 {
 119   ARM_ABI_AUTO,
 120   ARM_ABI_APCS,
 121   ARM_ABI_AAPCS,
 122   ARM_ABI_LAST
 123 };
 124
 125 /* Target-dependent structure in gdbarch.  */
 126 struct gdbarch_tdep
 127 {
 128   /* The ABI for this architecture.  It should never be set to
 129      ARM_ABI_AUTO.  */
 130   enum arm_abi_kind arm_abi;
 131
 132   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 133
 134   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 135                                    will appear.  */
 136
 137   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 138   int arm_breakpoint_size;      /* And its size.  */
 139   const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn.  */
 140   int thumb_breakpoint_size;    /* And its size.  */
 141
 142   int jb_pc;                    /* Offset to PC value in jump buffer.
 143                                    If this is negative, longjmp support
 144                                    will be disabled.  */
 145   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 146 };
 147
 148 #ifndef LOWEST_PC
 149 #define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
 150 #endif
 151
 152 /* Prototypes for internal interfaces needed by more than one MD file.  */
 153 int arm_pc_is_thumb_dummy (CORE_ADDR);
 154
 155 int arm_pc_is_thumb (CORE_ADDR);
 156
 157 CORE_ADDR thumb_get_next_pc (CORE_ADDR);
 158
 159 CORE_ADDR arm_get_next_pc (CORE_ADDR);