gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002, 2003, 2007, 2008, 2009 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARM_TDEP_H
  20 #define ARM_TDEP_H
  21
  22 /* Forward declarations.  */
  23 struct gdbarch;
  24 struct regset;
  25
  26 /* Register numbers of various important registers.  */
  27
  28 enum gdb_regnum {
  29   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  30   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  31   ARM_AP_REGNUM = 11,
  32   ARM_IP_REGNUM = 12,
  33   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  34   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  35   ARM_PC_REGNUM = 15,           /* Contains program counter */
  36   ARM_F0_REGNUM = 16,           /* first floating point register */
  37   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  38   ARM_F7_REGNUM = 23,           /* last floating point register */
  39   ARM_FPS_REGNUM = 24,          /* floating point status register */
  40   ARM_PS_REGNUM = 25,           /* Contains processor status */
  41   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  42   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  43   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  44   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  45   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  46   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  47   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  48   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  49   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  50
  51   ARM_NUM_REGS,
  52
  53   /* Other useful registers.  */
  54   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  55   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  56   ARM_NUM_ARG_REGS = 4,
  57   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  58   ARM_NUM_FP_ARG_REGS = 4,
  59   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  60 };
  61
  62 /* Size of integer registers.  */
  63 #define INT_REGISTER_SIZE               4
  64
  65 /* Say how long FP registers are.  Used for documentation purposes and
  66    code readability in this header.  IEEE extended doubles are 80
  67    bits.  DWORD aligned they use 96 bits.  */
  68 #define FP_REGISTER_SIZE        12
  69
  70 /* Number of machine registers.  The only define actually required
  71    is gdbarch_num_regs.  The other definitions are used for documentation
  72    purposes and code readability.  */
  73 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  74    (and called PS for processor status) so the status bits can be cleared
  75    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  76    in PS.  */
  77 #define NUM_FREGS       8       /* Number of floating point registers.  */
  78 #define NUM_SREGS       2       /* Number of status registers.  */
  79 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  80
  81
  82 /* Instruction condition field values.  */
  83 #define INST_EQ         0x0
  84 #define INST_NE         0x1
  85 #define INST_CS         0x2
  86 #define INST_CC         0x3
  87 #define INST_MI         0x4
  88 #define INST_PL         0x5
  89 #define INST_VS         0x6
  90 #define INST_VC         0x7
  91 #define INST_HI         0x8
  92 #define INST_LS         0x9
  93 #define INST_GE         0xa
  94 #define INST_LT         0xb
  95 #define INST_GT         0xc
  96 #define INST_LE         0xd
  97 #define INST_AL         0xe
  98 #define INST_NV         0xf
  99
 100 #define FLAG_N          0x80000000
 101 #define FLAG_Z          0x40000000
 102 #define FLAG_C          0x20000000
 103 #define FLAG_V          0x10000000
 104
 105 #define CPSR_T          0x20
 106
 107 /* Type of floating-point code in use by inferior.  There are really 3 models
 108    that are traditionally supported (plus the endianness issue), but gcc can
 109    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 110    functions are passed in floating-point registers.
 111
 112    In addition to the traditional models, VFP adds two more.
 113
 114    If you update this enum, don't forget to update fp_model_strings in
 115    arm-tdep.c.  */
 116
 117 enum arm_float_model
 118 {
 119   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 120   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 121   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 122   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 123   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 124   ARM_FLOAT_LAST        /* Keep at end.  */
 125 };
 126
 127 /* ABI used by the inferior.  */
 128 enum arm_abi_kind
 129 {
 130   ARM_ABI_AUTO,
 131   ARM_ABI_APCS,
 132   ARM_ABI_AAPCS,
 133   ARM_ABI_LAST
 134 };
 135
 136 /* Convention for returning structures.  */
 137
 138 enum struct_return
 139 {
 140   pcc_struct_return,            /* Return "short" structures in memory.  */
 141   reg_struct_return             /* Return "short" structures in registers.  */
 142 };
 143
 144 /* Target-dependent structure in gdbarch.  */
 145 struct gdbarch_tdep
 146 {
 147   /* The ABI for this architecture.  It should never be set to
 148      ARM_ABI_AUTO.  */
 149   enum arm_abi_kind arm_abi;
 150
 151   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 152
 153   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 154
 155   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 156                                    will appear.  */
 157
 158   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 159   int arm_breakpoint_size;      /* And its size.  */
 160   const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn.  */
 161   int thumb_breakpoint_size;    /* And its size.  */
 162
 163   int jb_pc;                    /* Offset to PC value in jump buffer.
 164                                    If this is negative, longjmp support
 165                                    will be disabled.  */
 166   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 167
 168   /* Convention for returning structures.  */
 169   enum struct_return struct_return;
 170
 171   /* Cached core file helpers.  */
 172   struct regset *gregset, *fpregset;
 173 };
 174
 175
 176 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 177 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
 178 int arm_software_single_step (struct frame_info *);
 179
 180 /* Functions exported from armbsd-tdep.h.  */
 181
 182 /* Return the appropriate register set for the core section identified
 183    by SECT_NAME and SECT_SIZE.  */
 184
 185 extern const struct regset *
 186   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 187                                    const char *sect_name, size_t sect_size);
 188
 189 #endif /* arm-tdep.h */