*** empty log message ***
[deliverable/binutils-gdb.git] / gdb / arm-tdep.h
1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 Boston, MA 02110-1301, USA. */
20
21 #ifndef ARM_TDEP_H
22 #define ARM_TDEP_H
23
24 /* Forward declarations. */
25 struct gdbarch;
26 struct regset;
27
28 /* Register numbers of various important registers. Note that some of
29 these values are "real" register numbers, and correspond to the
30 general registers of the machine, and some are "phony" register
31 numbers which are too large to be actual register numbers as far as
32 the user is concerned but do serve to get the desired values when
33 passed to read_register. */
34
35 enum gdb_regnum {
36 ARM_A1_REGNUM = 0, /* first integer-like argument */
37 ARM_A4_REGNUM = 3, /* last integer-like argument */
38 ARM_AP_REGNUM = 11,
39 ARM_SP_REGNUM = 13, /* Contains address of top of stack */
40 ARM_LR_REGNUM = 14, /* address to return to from a function call */
41 ARM_PC_REGNUM = 15, /* Contains program counter */
42 ARM_F0_REGNUM = 16, /* first floating point register */
43 ARM_F3_REGNUM = 19, /* last floating point argument register */
44 ARM_F7_REGNUM = 23, /* last floating point register */
45 ARM_FPS_REGNUM = 24, /* floating point status register */
46 ARM_PS_REGNUM = 25, /* Contains processor status */
47 ARM_WR0_REGNUM, /* WMMX data registers. */
48 ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
49 ARM_WC0_REGNUM, /* WMMX control registers. */
50 ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
51 ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
52 ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
53 ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
54 ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
55 ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
56
57 ARM_NUM_REGS,
58
59 /* Other useful registers. */
60 ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
61 THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
62 ARM_NUM_ARG_REGS = 4,
63 ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
64 ARM_NUM_FP_ARG_REGS = 4,
65 ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
66 };
67
68 /* Size of integer registers. */
69 #define INT_REGISTER_SIZE 4
70
71 /* Say how long FP registers are. Used for documentation purposes and
72 code readability in this header. IEEE extended doubles are 80
73 bits. DWORD aligned they use 96 bits. */
74 #define FP_REGISTER_SIZE 12
75
76 /* Status registers are the same size as general purpose registers.
77 Used for documentation purposes and code readability in this
78 header. */
79 #define STATUS_REGISTER_SIZE 4
80
81 /* Number of machine registers. The only define actually required
82 is NUM_REGS. The other definitions are used for documentation
83 purposes and code readability. */
84 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
85 (and called PS for processor status) so the status bits can be cleared
86 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
87 in PS. */
88 #define NUM_FREGS 8 /* Number of floating point registers. */
89 #define NUM_SREGS 2 /* Number of status registers. */
90 #define NUM_GREGS 16 /* Number of general purpose registers. */
91
92
93 /* Instruction condition field values. */
94 #define INST_EQ 0x0
95 #define INST_NE 0x1
96 #define INST_CS 0x2
97 #define INST_CC 0x3
98 #define INST_MI 0x4
99 #define INST_PL 0x5
100 #define INST_VS 0x6
101 #define INST_VC 0x7
102 #define INST_HI 0x8
103 #define INST_LS 0x9
104 #define INST_GE 0xa
105 #define INST_LT 0xb
106 #define INST_GT 0xc
107 #define INST_LE 0xd
108 #define INST_AL 0xe
109 #define INST_NV 0xf
110
111 #define FLAG_N 0x80000000
112 #define FLAG_Z 0x40000000
113 #define FLAG_C 0x20000000
114 #define FLAG_V 0x10000000
115
116 /* Type of floating-point code in use by inferior. There are really 3 models
117 that are traditionally supported (plus the endianness issue), but gcc can
118 only generate 2 of those. The third is APCS_FLOAT, where arguments to
119 functions are passed in floating-point registers.
120
121 In addition to the traditional models, VFP adds two more.
122
123 If you update this enum, don't forget to update fp_model_strings in
124 arm-tdep.c. */
125
126 enum arm_float_model
127 {
128 ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
129 ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
130 ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
131 ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
132 ARM_FLOAT_VFP, /* Full VFP calling convention. */
133 ARM_FLOAT_LAST /* Keep at end. */
134 };
135
136 /* ABI used by the inferior. */
137 enum arm_abi_kind
138 {
139 ARM_ABI_AUTO,
140 ARM_ABI_APCS,
141 ARM_ABI_AAPCS,
142 ARM_ABI_LAST
143 };
144
145 /* Convention for returning structures. */
146
147 enum struct_return
148 {
149 pcc_struct_return, /* Return "short" structures in memory. */
150 reg_struct_return /* Return "short" structures in registers. */
151 };
152
153 /* Target-dependent structure in gdbarch. */
154 struct gdbarch_tdep
155 {
156 /* The ABI for this architecture. It should never be set to
157 ARM_ABI_AUTO. */
158 enum arm_abi_kind arm_abi;
159
160 enum arm_float_model fp_model; /* Floating point calling conventions. */
161
162 int have_fpa_registers; /* Does the target report the FPA registers? */
163
164 CORE_ADDR lowest_pc; /* Lowest address at which instructions
165 will appear. */
166
167 const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
168 int arm_breakpoint_size; /* And its size. */
169 const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */
170 int thumb_breakpoint_size; /* And its size. */
171
172 int jb_pc; /* Offset to PC value in jump buffer.
173 If this is negative, longjmp support
174 will be disabled. */
175 size_t jb_elt_size; /* And the size of each entry in the buf. */
176
177 /* Convention for returning structures. */
178 enum struct_return struct_return;
179
180 /* Cached core file helpers. */
181 struct regset *gregset, *fpregset;
182 };
183
184
185
186 #ifndef LOWEST_PC
187 #define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
188 #endif
189
190 /* Functions exported from armbsd-tdep.h. */
191
192 /* Return the appropriate register set for the core section identified
193 by SECT_NAME and SECT_SIZE. */
194
195 extern const struct regset *
196 armbsd_regset_from_core_section (struct gdbarch *gdbarch,
197 const char *sect_name, size_t sect_size);
198
199 #endif /* arm-tdep.h */
This page took 0.035129 seconds and 4 git commands to generate.