gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  19    Boston, MA 02110-1301, USA.  */
  20
  21 #ifndef ARM_TDEP_H
  22 #define ARM_TDEP_H
  23
  24 /* Forward declarations.  */
  25 struct gdbarch;
  26 struct regset;
  27
  28 /* Register numbers of various important registers.  */
  29
  30 enum gdb_regnum {
  31   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  32   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  33   ARM_AP_REGNUM = 11,
  34   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  35   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  36   ARM_PC_REGNUM = 15,           /* Contains program counter */
  37   ARM_F0_REGNUM = 16,           /* first floating point register */
  38   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  39   ARM_F7_REGNUM = 23,           /* last floating point register */
  40   ARM_FPS_REGNUM = 24,          /* floating point status register */
  41   ARM_PS_REGNUM = 25,           /* Contains processor status */
  42   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  43   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  44   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  45   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  46   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  47   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  48   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  49   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  50   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  51
  52   ARM_NUM_REGS,
  53
  54   /* Other useful registers.  */
  55   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  56   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  57   ARM_NUM_ARG_REGS = 4,
  58   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  59   ARM_NUM_FP_ARG_REGS = 4,
  60   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  61 };
  62
  63 /* Size of integer registers.  */
  64 #define INT_REGISTER_SIZE               4
  65
  66 /* Say how long FP registers are.  Used for documentation purposes and
  67    code readability in this header.  IEEE extended doubles are 80
  68    bits.  DWORD aligned they use 96 bits.  */
  69 #define FP_REGISTER_SIZE        12
  70
  71 /* Status registers are the same size as general purpose registers.
  72    Used for documentation purposes and code readability in this
  73    header.  */
  74 #define STATUS_REGISTER_SIZE    4
  75
  76 /* Number of machine registers.  The only define actually required
  77    is NUM_REGS.  The other definitions are used for documentation
  78    purposes and code readability.  */
  79 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  80    (and called PS for processor status) so the status bits can be cleared
  81    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  82    in PS.  */
  83 #define NUM_FREGS       8       /* Number of floating point registers.  */
  84 #define NUM_SREGS       2       /* Number of status registers.  */
  85 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  86
  87
  88 /* Instruction condition field values.  */
  89 #define INST_EQ         0x0
  90 #define INST_NE         0x1
  91 #define INST_CS         0x2
  92 #define INST_CC         0x3
  93 #define INST_MI         0x4
  94 #define INST_PL         0x5
  95 #define INST_VS         0x6
  96 #define INST_VC         0x7
  97 #define INST_HI         0x8
  98 #define INST_LS         0x9
  99 #define INST_GE         0xa
 100 #define INST_LT         0xb
 101 #define INST_GT         0xc
 102 #define INST_LE         0xd
 103 #define INST_AL         0xe
 104 #define INST_NV         0xf
 105
 106 #define FLAG_N          0x80000000
 107 #define FLAG_Z          0x40000000
 108 #define FLAG_C          0x20000000
 109 #define FLAG_V          0x10000000
 110
 111 /* Type of floating-point code in use by inferior.  There are really 3 models
 112    that are traditionally supported (plus the endianness issue), but gcc can
 113    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 114    functions are passed in floating-point registers.
 115
 116    In addition to the traditional models, VFP adds two more.
 117
 118    If you update this enum, don't forget to update fp_model_strings in
 119    arm-tdep.c.  */
 120
 121 enum arm_float_model
 122 {
 123   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 124   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 125   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 126   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 127   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 128   ARM_FLOAT_LAST        /* Keep at end.  */
 129 };
 130
 131 /* ABI used by the inferior.  */
 132 enum arm_abi_kind
 133 {
 134   ARM_ABI_AUTO,
 135   ARM_ABI_APCS,
 136   ARM_ABI_AAPCS,
 137   ARM_ABI_LAST
 138 };
 139
 140 /* Convention for returning structures.  */
 141
 142 enum struct_return
 143 {
 144   pcc_struct_return,            /* Return "short" structures in memory.  */
 145   reg_struct_return             /* Return "short" structures in registers.  */
 146 };
 147
 148 /* Target-dependent structure in gdbarch.  */
 149 struct gdbarch_tdep
 150 {
 151   /* The ABI for this architecture.  It should never be set to
 152      ARM_ABI_AUTO.  */
 153   enum arm_abi_kind arm_abi;
 154
 155   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 156
 157   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 158
 159   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 160                                    will appear.  */
 161
 162   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 163   int arm_breakpoint_size;      /* And its size.  */
 164   const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn.  */
 165   int thumb_breakpoint_size;    /* And its size.  */
 166
 167   int jb_pc;                    /* Offset to PC value in jump buffer.
 168                                    If this is negative, longjmp support
 169                                    will be disabled.  */
 170   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 171
 172   /* Convention for returning structures.  */
 173   enum struct_return struct_return;
 174
 175   /* Cached core file helpers.  */
 176   struct regset *gregset, *fpregset;
 177 };
 178
 179
 180
 181 #ifndef LOWEST_PC
 182 #define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
 183 #endif
 184
 185 /* Functions exported from armbsd-tdep.h.  */
 186
 187 /* Return the appropriate register set for the core section identified
 188    by SECT_NAME and SECT_SIZE.  */
 189
 190 extern const struct regset *
 191   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 192                                    const char *sect_name, size_t sect_size);
 193
 194 #endif /* arm-tdep.h */