gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002-2015 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARM_TDEP_H
  20 #define ARM_TDEP_H
  21
  22 /* Forward declarations.  */
  23 struct gdbarch;
  24 struct regset;
  25 struct address_space;
  26
  27 #include "arch/arm.h"
  28
  29 /* Say how long FP registers are.  Used for documentation purposes and
  30    code readability in this header.  IEEE extended doubles are 80
  31    bits.  DWORD aligned they use 96 bits.  */
  32 #define FP_REGISTER_SIZE        12
  33
  34 /* Say how long VFP double precision registers are.  Used for documentation
  35    purposes and code readability.  These are fixed at 64 bits.  */
  36 #define VFP_REGISTER_SIZE       8
  37
  38 /* Number of machine registers.  The only define actually required
  39    is gdbarch_num_regs.  The other definitions are used for documentation
  40    purposes and code readability.  */
  41 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  42    (and called PS for processor status) so the status bits can be cleared
  43    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  44    in PS.  */
  45 #define NUM_FREGS       8       /* Number of floating point registers.  */
  46 #define NUM_SREGS       2       /* Number of status registers.  */
  47 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  48
  49
  50
  51 /* Type of floating-point code in use by inferior.  There are really 3 models
  52    that are traditionally supported (plus the endianness issue), but gcc can
  53    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
  54    functions are passed in floating-point registers.
  55
  56    In addition to the traditional models, VFP adds two more.
  57
  58    If you update this enum, don't forget to update fp_model_strings in
  59    arm-tdep.c.  */
  60
  61 enum arm_float_model
  62 {
  63   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
  64   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
  65   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
  66   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
  67   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
  68   ARM_FLOAT_LAST        /* Keep at end.  */
  69 };
  70
  71 /* ABI used by the inferior.  */
  72 enum arm_abi_kind
  73 {
  74   ARM_ABI_AUTO,
  75   ARM_ABI_APCS,
  76   ARM_ABI_AAPCS,
  77   ARM_ABI_LAST
  78 };
  79
  80 /* Convention for returning structures.  */
  81
  82 enum struct_return
  83 {
  84   pcc_struct_return,            /* Return "short" structures in memory.  */
  85   reg_struct_return             /* Return "short" structures in registers.  */
  86 };
  87
  88 /* Target-dependent structure in gdbarch.  */
  89 struct gdbarch_tdep
  90 {
  91   /* The ABI for this architecture.  It should never be set to
  92      ARM_ABI_AUTO.  */
  93   enum arm_abi_kind arm_abi;
  94
  95   enum arm_float_model fp_model; /* Floating point calling conventions.  */
  96
  97   int have_fpa_registers;       /* Does the target report the FPA registers?  */
  98   int have_wmmx_registers;      /* Does the target report the WMMX registers?  */
  99   /* The number of VFP registers reported by the target.  It is zero
 100      if VFP registers are not supported.  */
 101   int vfp_register_count;
 102   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 103                                    VFP registers?  */
 104   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 105                                    NEON registers?  Requires
 106                                    have_vfp_pseudos.  */
 107   int have_neon;                /* Do we have a NEON unit?  */
 108
 109   int is_m;                     /* Does the target follow the "M" profile.  */
 110   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 111                                    will appear.  */
 112
 113   const gdb_byte *arm_breakpoint;       /* Breakpoint pattern for an ARM insn.  */
 114   int arm_breakpoint_size;      /* And its size.  */
 115   const gdb_byte *thumb_breakpoint;     /* Breakpoint pattern for a Thumb insn.  */
 116   int thumb_breakpoint_size;    /* And its size.  */
 117
 118   /* If the Thumb breakpoint is an undefined instruction (which is
 119      affected by IT blocks) rather than a BKPT instruction (which is
 120      not), then we need a 32-bit Thumb breakpoint to preserve the
 121      instruction count in IT blocks.  */
 122   const gdb_byte *thumb2_breakpoint;
 123   int thumb2_breakpoint_size;
 124
 125   int jb_pc;                    /* Offset to PC value in jump buffer.
 126                                    If this is negative, longjmp support
 127                                    will be disabled.  */
 128   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 129
 130   /* Convention for returning structures.  */
 131   enum struct_return struct_return;
 132
 133   /* ISA-specific data types.  */
 134   struct type *arm_ext_type;
 135   struct type *neon_double_type;
 136   struct type *neon_quad_type;
 137
 138   /* Return the expected next PC if the program is stopped at a syscall
 139      instruction.  */
 140   CORE_ADDR (*syscall_next_pc) (struct regcache *regcache);
 141
 142    /* syscall record.  */
 143   int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
 144 };
 145
 146 /* Structures used for displaced stepping.  */
 147
 148 /* The maximum number of temporaries available for displaced instructions.  */
 149 #define DISPLACED_TEMPS                 16
 150 /* The maximum number of modified instructions generated for one single-stepped
 151    instruction, including the breakpoint (usually at the end of the instruction
 152    sequence) and any scratch words, etc.  */
 153 #define DISPLACED_MODIFIED_INSNS        8
 154
 155 struct displaced_step_closure
 156 {
 157   ULONGEST tmp[DISPLACED_TEMPS];
 158   int rd;
 159   int wrote_to_pc;
 160   union
 161   {
 162     struct
 163     {
 164       int xfersize;
 165       int rn;                      /* Writeback register.  */
 166       unsigned int immed : 1;      /* Offset is immediate.  */
 167       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 168       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 169     } ldst;
 170
 171     struct
 172     {
 173       unsigned long dest;
 174       unsigned int link : 1;
 175       unsigned int exchange : 1;
 176       unsigned int cond : 4;
 177     } branch;
 178
 179     struct
 180     {
 181       unsigned int regmask;
 182       int rn;
 183       CORE_ADDR xfer_addr;
 184       unsigned int load : 1;
 185       unsigned int user : 1;
 186       unsigned int increment : 1;
 187       unsigned int before : 1;
 188       unsigned int writeback : 1;
 189       unsigned int cond : 4;
 190     } block;
 191
 192     struct
 193     {
 194       unsigned int immed : 1;
 195     } preload;
 196
 197     struct
 198     {
 199       /* If non-NULL, override generic SVC handling (e.g. for a particular
 200          OS).  */
 201       int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
 202                           struct displaced_step_closure *dsc);
 203     } svc;
 204   } u;
 205
 206   /* The size of original instruction, 2 or 4.  */
 207   unsigned int insn_size;
 208   /* True if the original insn (and thus all replacement insns) are Thumb
 209      instead of ARM.   */
 210   unsigned int is_thumb;
 211
 212   /* The slots in the array is used in this way below,
 213      - ARM instruction occupies one slot,
 214      - Thumb 16 bit instruction occupies one slot,
 215      - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
 216   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 217   int numinsns;
 218   CORE_ADDR insn_addr;
 219   CORE_ADDR scratch_base;
 220   void (*cleanup) (struct gdbarch *, struct regcache *,
 221                    struct displaced_step_closure *);
 222 };
 223
 224 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 225    write may write to the PC, specifies the way the CPSR T bit, etc. is
 226    modified by the instruction.  */
 227
 228 enum pc_write_style
 229 {
 230   BRANCH_WRITE_PC,
 231   BX_WRITE_PC,
 232   LOAD_WRITE_PC,
 233   ALU_WRITE_PC,
 234   CANNOT_WRITE_PC
 235 };
 236
 237 extern void
 238   arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 239                               CORE_ADDR to, struct regcache *regs,
 240                               struct displaced_step_closure *dsc);
 241 extern void
 242   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 243                               CORE_ADDR to, struct displaced_step_closure *dsc);
 244 extern ULONGEST
 245   displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
 246                       int regno);
 247 extern void
 248   displaced_write_reg (struct regcache *regs,
 249                        struct displaced_step_closure *dsc, int regno,
 250                        ULONGEST val, enum pc_write_style write_pc);
 251
 252 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 253 CORE_ADDR arm_get_next_pc (struct regcache *regcache, CORE_ADDR pc);
 254 void arm_insert_single_step_breakpoint (struct gdbarch *,
 255                                         struct address_space *, CORE_ADDR);
 256 int arm_deal_with_atomic_sequence (struct regcache *);
 257 int arm_software_single_step (struct frame_info *);
 258 int arm_is_thumb (struct regcache *regcache);
 259 int arm_frame_is_thumb (struct frame_info *frame);
 260
 261 extern struct displaced_step_closure *
 262   arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
 263                                 struct regcache *);
 264 extern void arm_displaced_step_fixup (struct gdbarch *,
 265                                       struct displaced_step_closure *,
 266                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 267
 268 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 269 extern int arm_psr_thumb_bit (struct gdbarch *);
 270
 271 /* Is the instruction at the given memory address a Thumb or ARM
 272    instruction?  */
 273 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 274
 275 extern int arm_process_record (struct gdbarch *gdbarch,
 276                                struct regcache *regcache, CORE_ADDR addr);
 277 /* Functions exported from armbsd-tdep.h.  */
 278
 279 /* Return the appropriate register set for the core section identified
 280    by SECT_NAME and SECT_SIZE.  */
 281
 282 extern void
 283   armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
 284                                        iterate_over_regset_sections_cb *cb,
 285                                        void *cb_data,
 286                                        const struct regcache *regcache);
 287
 288 /* Target descriptions.  */
 289 extern struct target_desc *tdesc_arm_with_m;
 290 extern struct target_desc *tdesc_arm_with_iwmmxt;
 291 extern struct target_desc *tdesc_arm_with_vfpv2;
 292 extern struct target_desc *tdesc_arm_with_vfpv3;
 293 extern struct target_desc *tdesc_arm_with_neon;
 294
 295 #endif /* arm-tdep.h */