gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002-2015 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef ARM_TDEP_H
  20 #define ARM_TDEP_H
  21
  22 /* Forward declarations.  */
  23 struct gdbarch;
  24 struct regset;
  25 struct address_space;
  26 struct get_next_pcs;
  27 struct arm_get_next_pcs;
  28 struct gdb_get_next_pcs;
  29
  30 #include "arch/arm.h"
  31
  32 /* Say how long FP registers are.  Used for documentation purposes and
  33    code readability in this header.  IEEE extended doubles are 80
  34    bits.  DWORD aligned they use 96 bits.  */
  35 #define FP_REGISTER_SIZE        12
  36
  37 /* Say how long VFP double precision registers are.  Used for documentation
  38    purposes and code readability.  These are fixed at 64 bits.  */
  39 #define VFP_REGISTER_SIZE       8
  40
  41 /* Number of machine registers.  The only define actually required
  42    is gdbarch_num_regs.  The other definitions are used for documentation
  43    purposes and code readability.  */
  44 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  45    (and called PS for processor status) so the status bits can be cleared
  46    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  47    in PS.  */
  48 #define NUM_FREGS       8       /* Number of floating point registers.  */
  49 #define NUM_SREGS       2       /* Number of status registers.  */
  50 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  51
  52
  53
  54 /* Type of floating-point code in use by inferior.  There are really 3 models
  55    that are traditionally supported (plus the endianness issue), but gcc can
  56    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
  57    functions are passed in floating-point registers.
  58
  59    In addition to the traditional models, VFP adds two more.
  60
  61    If you update this enum, don't forget to update fp_model_strings in
  62    arm-tdep.c.  */
  63
  64 enum arm_float_model
  65 {
  66   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
  67   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
  68   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
  69   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
  70   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
  71   ARM_FLOAT_LAST        /* Keep at end.  */
  72 };
  73
  74 /* ABI used by the inferior.  */
  75 enum arm_abi_kind
  76 {
  77   ARM_ABI_AUTO,
  78   ARM_ABI_APCS,
  79   ARM_ABI_AAPCS,
  80   ARM_ABI_LAST
  81 };
  82
  83 /* Convention for returning structures.  */
  84
  85 enum struct_return
  86 {
  87   pcc_struct_return,            /* Return "short" structures in memory.  */
  88   reg_struct_return             /* Return "short" structures in registers.  */
  89 };
  90
  91 /* Target-dependent structure in gdbarch.  */
  92 struct gdbarch_tdep
  93 {
  94   /* The ABI for this architecture.  It should never be set to
  95      ARM_ABI_AUTO.  */
  96   enum arm_abi_kind arm_abi;
  97
  98   enum arm_float_model fp_model; /* Floating point calling conventions.  */
  99
 100   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 101   int have_wmmx_registers;      /* Does the target report the WMMX registers?  */
 102   /* The number of VFP registers reported by the target.  It is zero
 103      if VFP registers are not supported.  */
 104   int vfp_register_count;
 105   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 106                                    VFP registers?  */
 107   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 108                                    NEON registers?  Requires
 109                                    have_vfp_pseudos.  */
 110   int have_neon;                /* Do we have a NEON unit?  */
 111
 112   int is_m;                     /* Does the target follow the "M" profile.  */
 113   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 114                                    will appear.  */
 115
 116   const gdb_byte *arm_breakpoint;       /* Breakpoint pattern for an ARM insn.  */
 117   int arm_breakpoint_size;      /* And its size.  */
 118   const gdb_byte *thumb_breakpoint;     /* Breakpoint pattern for a Thumb insn.  */
 119   int thumb_breakpoint_size;    /* And its size.  */
 120
 121   /* If the Thumb breakpoint is an undefined instruction (which is
 122      affected by IT blocks) rather than a BKPT instruction (which is
 123      not), then we need a 32-bit Thumb breakpoint to preserve the
 124      instruction count in IT blocks.  */
 125   const gdb_byte *thumb2_breakpoint;
 126   int thumb2_breakpoint_size;
 127
 128   int jb_pc;                    /* Offset to PC value in jump buffer.
 129                                    If this is negative, longjmp support
 130                                    will be disabled.  */
 131   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 132
 133   /* Convention for returning structures.  */
 134   enum struct_return struct_return;
 135
 136   /* ISA-specific data types.  */
 137   struct type *arm_ext_type;
 138   struct type *neon_double_type;
 139   struct type *neon_quad_type;
 140
 141   /* Return the expected next PC if the program is stopped at a syscall
 142      instruction.  */
 143   CORE_ADDR (*syscall_next_pc) (struct regcache *regcache);
 144
 145    /* syscall record.  */
 146   int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
 147 };
 148
 149 /* Structures used for displaced stepping.  */
 150
 151 /* The maximum number of temporaries available for displaced instructions.  */
 152 #define DISPLACED_TEMPS                 16
 153 /* The maximum number of modified instructions generated for one single-stepped
 154    instruction, including the breakpoint (usually at the end of the instruction
 155    sequence) and any scratch words, etc.  */
 156 #define DISPLACED_MODIFIED_INSNS        8
 157
 158 struct displaced_step_closure
 159 {
 160   ULONGEST tmp[DISPLACED_TEMPS];
 161   int rd;
 162   int wrote_to_pc;
 163   union
 164   {
 165     struct
 166     {
 167       int xfersize;
 168       int rn;                      /* Writeback register.  */
 169       unsigned int immed : 1;      /* Offset is immediate.  */
 170       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 171       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 172     } ldst;
 173
 174     struct
 175     {
 176       unsigned long dest;
 177       unsigned int link : 1;
 178       unsigned int exchange : 1;
 179       unsigned int cond : 4;
 180     } branch;
 181
 182     struct
 183     {
 184       unsigned int regmask;
 185       int rn;
 186       CORE_ADDR xfer_addr;
 187       unsigned int load : 1;
 188       unsigned int user : 1;
 189       unsigned int increment : 1;
 190       unsigned int before : 1;
 191       unsigned int writeback : 1;
 192       unsigned int cond : 4;
 193     } block;
 194
 195     struct
 196     {
 197       unsigned int immed : 1;
 198     } preload;
 199
 200     struct
 201     {
 202       /* If non-NULL, override generic SVC handling (e.g. for a particular
 203          OS).  */
 204       int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
 205                           struct displaced_step_closure *dsc);
 206     } svc;
 207   } u;
 208
 209   /* The size of original instruction, 2 or 4.  */
 210   unsigned int insn_size;
 211   /* True if the original insn (and thus all replacement insns) are Thumb
 212      instead of ARM.   */
 213   unsigned int is_thumb;
 214
 215   /* The slots in the array is used in this way below,
 216      - ARM instruction occupies one slot,
 217      - Thumb 16 bit instruction occupies one slot,
 218      - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
 219   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 220   int numinsns;
 221   CORE_ADDR insn_addr;
 222   CORE_ADDR scratch_base;
 223   void (*cleanup) (struct gdbarch *, struct regcache *,
 224                    struct displaced_step_closure *);
 225 };
 226
 227 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 228    write may write to the PC, specifies the way the CPSR T bit, etc. is
 229    modified by the instruction.  */
 230
 231 enum pc_write_style
 232 {
 233   BRANCH_WRITE_PC,
 234   BX_WRITE_PC,
 235   LOAD_WRITE_PC,
 236   ALU_WRITE_PC,
 237   CANNOT_WRITE_PC
 238 };
 239
 240 extern void
 241   arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
 242                               CORE_ADDR to, struct regcache *regs,
 243                               struct displaced_step_closure *dsc);
 244 extern void
 245   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 246                               CORE_ADDR to, struct displaced_step_closure *dsc);
 247 extern ULONGEST
 248   displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
 249                       int regno);
 250 extern void
 251   displaced_write_reg (struct regcache *regs,
 252                        struct displaced_step_closure *dsc, int regno,
 253                        ULONGEST val, enum pc_write_style write_pc);
 254
 255 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 256
 257 ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
 258                                                         int len,
 259                                                         int byte_order);
 260
 261 CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
 262                                              CORE_ADDR val);
 263
 264 CORE_ADDR arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self,
 265                                             CORE_ADDR pc);
 266
 267 int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
 268
 269 void arm_insert_single_step_breakpoint (struct gdbarch *,
 270                                         struct address_space *, CORE_ADDR);
 271 int arm_software_single_step (struct frame_info *);
 272 int arm_is_thumb (struct regcache *regcache);
 273 int arm_frame_is_thumb (struct frame_info *frame);
 274
 275 extern struct displaced_step_closure *
 276   arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
 277                                 struct regcache *);
 278 extern void arm_displaced_step_fixup (struct gdbarch *,
 279                                       struct displaced_step_closure *,
 280                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 281
 282 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 283 extern int arm_psr_thumb_bit (struct gdbarch *);
 284
 285 /* Is the instruction at the given memory address a Thumb or ARM
 286    instruction?  */
 287 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 288
 289 extern int arm_process_record (struct gdbarch *gdbarch,
 290                                struct regcache *regcache, CORE_ADDR addr);
 291 /* Functions exported from armbsd-tdep.h.  */
 292
 293 /* Return the appropriate register set for the core section identified
 294    by SECT_NAME and SECT_SIZE.  */
 295
 296 extern void
 297   armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
 298                                        iterate_over_regset_sections_cb *cb,
 299                                        void *cb_data,
 300                                        const struct regcache *regcache);
 301
 302 /* Target descriptions.  */
 303 extern struct target_desc *tdesc_arm_with_m;
 304 extern struct target_desc *tdesc_arm_with_iwmmxt;
 305 extern struct target_desc *tdesc_arm_with_vfpv2;
 306 extern struct target_desc *tdesc_arm_with_vfpv3;
 307 extern struct target_desc *tdesc_arm_with_neon;
 308
 309 #endif /* arm-tdep.h */