gdb/config/arm/tm-arm.h

   1 /* Definitions to target GDB to ARM targets.
   2    Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef TM_ARM_H
  23 #define TM_ARM_H
  24
  25 #ifndef GDB_MULTI_ARCH
  26 #define GDB_MULTI_ARCH 1
  27 #endif
  28
  29 #include "regcache.h"
  30 #include "floatformat.h"
  31
  32 /* Forward declarations for prototypes.  */
  33 struct type;
  34 struct value;
  35
  36 /* IEEE format floating point.  */
  37 #define TARGET_DOUBLE_FORMAT  (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG \
  38                                ? &floatformat_ieee_double_big    \
  39                                : &floatformat_ieee_double_littlebyte_bigword)
  40
  41 CORE_ADDR arm_smash_text_address(CORE_ADDR);
  42 #define SMASH_TEXT_ADDRESS(ADDR) arm_smash_text_address (ADDR)
  43
  44 CORE_ADDR arm_addr_bits_remove (CORE_ADDR);
  45 #define ADDR_BITS_REMOVE(VAL)   arm_addr_bits_remove (VAL)
  46
  47 /* Offset from address of function to start of its code.  Zero on most
  48    machines.  */
  49
  50 #define FUNCTION_START_OFFSET   0
  51
  52 /* Advance PC across any function entry prologue instructions to reach
  53    some "real" code.  */
  54
  55 extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc);
  56
  57 #define SKIP_PROLOGUE(pc)  (arm_skip_prologue (pc))
  58
  59 /* Immediately after a function call, return the saved pc.  Can't
  60    always go through the frames for this because on some machines the
  61    new frame is not set up until the new function executes some
  62    instructions.  */
  63
  64 #define SAVED_PC_AFTER_CALL(frame)  arm_saved_pc_after_call (frame)
  65 struct frame_info;
  66 extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
  67
  68 /* The following define instruction sequences that will cause ARM
  69    cpu's to take an undefined instruction trap.  These are used to
  70    signal a breakpoint to GDB.
  71
  72    The newer ARMv4T cpu's are capable of operating in ARM or Thumb
  73    modes.  A different instruction is required for each mode.  The ARM
  74    cpu's can also be big or little endian.  Thus four different
  75    instructions are needed to support all cases.
  76
  77    Note: ARMv4 defines several new instructions that will take the
  78    undefined instruction trap.  ARM7TDMI is nominally ARMv4T, but does
  79    not in fact add the new instructions.  The new undefined
  80    instructions in ARMv4 are all instructions that had no defined
  81    behaviour in earlier chips.  There is no guarantee that they will
  82    raise an exception, but may be treated as NOP's.  In practice, it
  83    may only safe to rely on instructions matching:
  84
  85    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  86    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  87    C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
  88
  89    Even this may only true if the condition predicate is true. The
  90    following use a condition predicate of ALWAYS so it is always TRUE.
  91
  92    There are other ways of forcing a breakpoint.  ARM Linux, RISC iX,
  93    and NetBSD will all use a software interrupt rather than an
  94    undefined instruction to force a trap.  This can be handled by
  95    redefining some or all of the following in a target dependent
  96    fashion.  */
  97
  98 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
  99 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
 100 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
 101 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
 102
 103 /* Stack grows downward.  */
 104
 105 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 106
 107 /* !!!! if we're using RDP, then we're inserting breakpoints and
 108    storing their handles instread of what was in memory.  It is nice
 109    that this is the same size as a handle - otherwise remote-rdp will
 110    have to change. */
 111
 112 /* BREAKPOINT_FROM_PC uses the program counter value to determine
 113    whether a 16- or 32-bit breakpoint should be used.  It returns a
 114    pointer to a string of bytes that encode a breakpoint instruction,
 115    stores the length of the string to *lenptr, and adjusts the pc (if
 116    necessary) to point to the actual memory location where the
 117    breakpoint should be inserted.  */
 118
 119 extern breakpoint_from_pc_fn arm_breakpoint_from_pc;
 120 #define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr)
 121
 122 /* Amount PC must be decremented by after a breakpoint.  This is often
 123    the number of bytes in BREAKPOINT but not always.  */
 124
 125 #define DECR_PC_AFTER_BREAK 0
 126
 127 void arm_print_float_info (void);
 128 #define PRINT_FLOAT_INFO()      arm_print_float_info ()
 129
 130 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 131    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 132    real way to know how big a register is.  */
 133
 134 #define REGISTER_SIZE   4
 135
 136 /* Say how long FP registers are.  Used for documentation purposes and
 137    code readability in this header.  IEEE extended doubles are 80
 138    bits.  DWORD aligned they use 96 bits.  */
 139 #define FP_REGISTER_RAW_SIZE    12
 140
 141 /* GCC doesn't support long doubles (extended IEEE values).  The FP
 142    register virtual size is therefore 64 bits.  Used for documentation
 143    purposes and code readability in this header.  */
 144 #define FP_REGISTER_VIRTUAL_SIZE        8
 145
 146 /* Status registers are the same size as general purpose registers.
 147    Used for documentation purposes and code readability in this
 148    header.  */
 149 #define STATUS_REGISTER_SIZE    REGISTER_SIZE
 150
 151 /* Number of machine registers.  The only define actually required
 152    is NUM_REGS.  The other definitions are used for documentation
 153    purposes and code readability.  */
 154 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
 155    (and called PS for processor status) so the status bits can be cleared
 156    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
 157    in PS.  */
 158 #define NUM_FREGS       8       /* Number of floating point registers.  */
 159 #define NUM_SREGS       2       /* Number of status registers.  */
 160 #define NUM_GREGS       16      /* Number of general purpose registers.  */
 161 #define NUM_REGS        (NUM_GREGS + NUM_FREGS + NUM_SREGS)
 162
 163 /* An array of names of registers. */
 164 extern char **arm_register_names;
 165
 166 #define REGISTER_NAME(i) arm_register_name(i)
 167 char *arm_register_name (int);
 168
 169 /* Register numbers of various important registers.  Note that some of
 170    these values are "real" register numbers, and correspond to the
 171    general registers of the machine, and some are "phony" register
 172    numbers which are too large to be actual register numbers as far as
 173    the user is concerned but do serve to get the desired values when
 174    passed to read_register.  */
 175
 176 #define A1_REGNUM 0             /* first integer-like argument */
 177 #define A4_REGNUM 3             /* last integer-like argument */
 178 #define AP_REGNUM 11
 179 #define FP_REGNUM 11            /* Contains address of executing stack frame */
 180 #define SP_REGNUM 13            /* Contains address of top of stack */
 181 #define LR_REGNUM 14            /* address to return to from a function call */
 182 #define PC_REGNUM 15            /* Contains program counter */
 183 #define F0_REGNUM 16            /* first floating point register */
 184 #define F3_REGNUM 19            /* last floating point argument register */
 185 #define F7_REGNUM 23            /* last floating point register */
 186 #define FPS_REGNUM 24           /* floating point status register */
 187 #define PS_REGNUM 25            /* Contains processor status */
 188
 189 #define THUMB_FP_REGNUM 7       /* R7 is frame register on Thumb */
 190
 191 #define ARM_NUM_ARG_REGS        4
 192 #define ARM_LAST_ARG_REGNUM     A4_REGNUM
 193 #define ARM_NUM_FP_ARG_REGS     4
 194 #define ARM_LAST_FP_ARG_REGNUM  F3_REGNUM
 195
 196 /* Instruction condition field values.  */
 197 #define INST_EQ         0x0
 198 #define INST_NE         0x1
 199 #define INST_CS         0x2
 200 #define INST_CC         0x3
 201 #define INST_MI         0x4
 202 #define INST_PL         0x5
 203 #define INST_VS         0x6
 204 #define INST_VC         0x7
 205 #define INST_HI         0x8
 206 #define INST_LS         0x9
 207 #define INST_GE         0xa
 208 #define INST_LT         0xb
 209 #define INST_GT         0xc
 210 #define INST_LE         0xd
 211 #define INST_AL         0xe
 212 #define INST_NV         0xf
 213
 214 #define FLAG_N          0x80000000
 215 #define FLAG_Z          0x40000000
 216 #define FLAG_C          0x20000000
 217 #define FLAG_V          0x10000000
 218
 219
 220
 221 /* Total amount of space needed to store our copies of the machine's
 222    register state, the array `registers'.  */
 223
 224 #define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \
 225                         (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \
 226                         (NUM_SREGS * STATUS_REGISTER_SIZE))
 227
 228 /* Index within `registers' of the first byte of the space for
 229    register N.  */
 230
 231 #define REGISTER_BYTE(N) \
 232      ((N) < F0_REGNUM \
 233       ? (N) * REGISTER_SIZE \
 234       : ((N) < PS_REGNUM \
 235          ? (NUM_GREGS * REGISTER_SIZE + \
 236             ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \
 237          : (NUM_GREGS * REGISTER_SIZE + \
 238             NUM_FREGS * FP_REGISTER_RAW_SIZE + \
 239             ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE)))
 240
 241 /* Number of bytes of storage in the actual machine representation for
 242    register N.  All registers are 4 bytes, except fp0 - fp7, which are
 243    12 bytes in length.  */
 244 #define REGISTER_RAW_SIZE(N) \
 245      ((N) < F0_REGNUM ? REGISTER_SIZE : \
 246       (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE)
 247
 248 /* Number of bytes of storage in a program's representation
 249    for register N.  */
 250 #define REGISTER_VIRTUAL_SIZE(N) \
 251         ((N) < F0_REGNUM ? REGISTER_SIZE : \
 252          (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE)
 253
 254 /* Largest value REGISTER_RAW_SIZE can have.  */
 255
 256 #define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE
 257
 258 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 259 #define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE
 260
 261 /* Return the GDB type object for the "standard" data type of data in
 262    register N.  */
 263
 264 extern struct type *arm_register_type (int regnum);
 265 #define REGISTER_VIRTUAL_TYPE(N) arm_register_type (N)
 266
 267 /* The system C compiler uses a similar structure return convention to gcc */
 268 extern use_struct_convention_fn arm_use_struct_convention;
 269 #define USE_STRUCT_CONVENTION(gcc_p, type) \
 270      arm_use_struct_convention (gcc_p, type)
 271
 272 /* Store the address of the place in which to copy the structure the
 273    subroutine will return.  This is called from call_function. */
 274
 275 #define STORE_STRUCT_RETURN(ADDR, SP) \
 276      write_register (A1_REGNUM, (ADDR))
 277
 278 /* Extract from an array REGBUF containing the (raw) register state a
 279    function return value of type TYPE, and copy that, in virtual
 280    format, into VALBUF.  */
 281
 282 extern void arm_extract_return_value (struct type *, char[], char *);
 283 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 284      arm_extract_return_value ((TYPE), (REGBUF), (VALBUF))
 285
 286 /* Write into appropriate registers a function return value of type
 287    TYPE, given in virtual format.  */
 288
 289 extern void convert_to_extended (void *dbl, void *ptr);
 290 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 291   if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) {                              \
 292     char _buf[MAX_REGISTER_RAW_SIZE];                                   \
 293     convert_to_extended (VALBUF, _buf);                                         \
 294     write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \
 295   } else                                                                \
 296     write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE))
 297
 298 /* Extract from an array REGBUF containing the (raw) register state
 299    the address in which a function should return its structure value,
 300    as a CORE_ADDR (or an expression that can be used as one).  */
 301
 302 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 303   (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0)))
 304
 305 /* Specify that for the native compiler variables for a particular
 306    lexical context are listed after the beginning LBRAC instead of
 307    before in the executables list of symbols.  */
 308 #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
 309 \f
 310 #define CALL_DUMMY_WORDS arm_call_dummy_words
 311 extern LONGEST arm_call_dummy_words[];
 312
 313 #define SIZEOF_CALL_DUMMY_WORDS (3 * sizeof (LONGEST))
 314
 315 #define CALL_DUMMY_START_OFFSET  0      /* Start execution at beginning of dummy */
 316
 317 #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
 318 extern int arm_call_dummy_breakpoint_offset (void);
 319
 320 /* Insert the specified number of args and function address into a
 321    call sequence of the above form stored at DUMMYNAME.  */
 322
 323 #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
 324    arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p))
 325
 326 void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun,
 327                          int nargs, struct value ** args,
 328                          struct type * type, int gcc_p);
 329
 330 /* Most ARMs don't have single stepping capability, so provide a
 331    single-stepping mechanism by default */
 332 #undef SOFTWARE_SINGLE_STEP_P
 333 #define SOFTWARE_SINGLE_STEP_P() 1
 334
 335 #define SOFTWARE_SINGLE_STEP(sig,bpt) arm_software_single_step((sig), (bpt))
 336 void arm_software_single_step (int, int);
 337
 338 struct minimal_symbol;
 339
 340 void arm_elf_make_msymbol_special(asymbol *, struct minimal_symbol *);
 341 #define ELF_MAKE_MSYMBOL_SPECIAL(SYM,MSYM) \
 342         arm_elf_make_msymbol_special (SYM, MSYM)
 343
 344 void arm_coff_make_msymbol_special(int, struct minimal_symbol *);
 345 #define COFF_MAKE_MSYMBOL_SPECIAL(VAL,MSYM) \
 346         arm_coff_make_msymbol_special (VAL, MSYM)
 347
 348 /* The first 0x20 bytes are the trap vectors.  */
 349 #define LOWEST_PC       0x20
 350
 351 #endif /* TM_ARM_H */