gdb/config/arm/tm-arm.h

   1 /* Definitions to target GDB to ARM targets.
   2    Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef TM_ARM_H
  23 #define TM_ARM_H
  24
  25 #include "regcache.h"
  26 #include "floatformat.h"
  27
  28 /* Forward declarations for prototypes.  */
  29 struct type;
  30 struct value;
  31
  32 /* IEEE format floating point.  */
  33 #define TARGET_DOUBLE_FORMAT  (target_byte_order == BFD_ENDIAN_BIG \
  34                                ? &floatformat_ieee_double_big    \
  35                                : &floatformat_ieee_double_littlebyte_bigword)
  36
  37 CORE_ADDR arm_smash_text_address(CORE_ADDR);
  38 #define SMASH_TEXT_ADDRESS(ADDR) arm_smash_text_address (ADDR)
  39
  40 CORE_ADDR arm_addr_bits_remove (CORE_ADDR);
  41 #define ADDR_BITS_REMOVE(VAL)   arm_addr_bits_remove (VAL)
  42
  43 /* Offset from address of function to start of its code.  Zero on most
  44    machines.  */
  45
  46 #define FUNCTION_START_OFFSET   0
  47
  48 /* Advance PC across any function entry prologue instructions to reach
  49    some "real" code.  */
  50
  51 extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc);
  52
  53 #define SKIP_PROLOGUE(pc)  (arm_skip_prologue (pc))
  54
  55 /* Immediately after a function call, return the saved pc.  Can't
  56    always go through the frames for this because on some machines the
  57    new frame is not set up until the new function executes some
  58    instructions.  */
  59
  60 #define SAVED_PC_AFTER_CALL(frame)  arm_saved_pc_after_call (frame)
  61 struct frame_info;
  62 extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
  63
  64 /* The following define instruction sequences that will cause ARM
  65    cpu's to take an undefined instruction trap.  These are used to
  66    signal a breakpoint to GDB.
  67
  68    The newer ARMv4T cpu's are capable of operating in ARM or Thumb
  69    modes.  A different instruction is required for each mode.  The ARM
  70    cpu's can also be big or little endian.  Thus four different
  71    instructions are needed to support all cases.
  72
  73    Note: ARMv4 defines several new instructions that will take the
  74    undefined instruction trap.  ARM7TDMI is nominally ARMv4T, but does
  75    not in fact add the new instructions.  The new undefined
  76    instructions in ARMv4 are all instructions that had no defined
  77    behaviour in earlier chips.  There is no guarantee that they will
  78    raise an exception, but may be treated as NOP's.  In practice, it
  79    may only safe to rely on instructions matching:
  80
  81    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  82    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  83    C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
  84
  85    Even this may only true if the condition predicate is true. The
  86    following use a condition predicate of ALWAYS so it is always TRUE.
  87
  88    There are other ways of forcing a breakpoint.  ARM Linux, RISC iX,
  89    and NetBSD will all use a software interrupt rather than an
  90    undefined instruction to force a trap.  This can be handled by
  91    redefining some or all of the following in a target dependent
  92    fashion.  */
  93
  94 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
  95 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
  96 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
  97 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
  98
  99 /* Stack grows downward.  */
 100
 101 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 102
 103 /* !!!! if we're using RDP, then we're inserting breakpoints and
 104    storing their handles instread of what was in memory.  It is nice
 105    that this is the same size as a handle - otherwise remote-rdp will
 106    have to change. */
 107
 108 /* BREAKPOINT_FROM_PC uses the program counter value to determine
 109    whether a 16- or 32-bit breakpoint should be used.  It returns a
 110    pointer to a string of bytes that encode a breakpoint instruction,
 111    stores the length of the string to *lenptr, and adjusts the pc (if
 112    necessary) to point to the actual memory location where the
 113    breakpoint should be inserted.  */
 114
 115 extern breakpoint_from_pc_fn arm_breakpoint_from_pc;
 116 #define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr)
 117
 118 /* Amount PC must be decremented by after a breakpoint.  This is often
 119    the number of bytes in BREAKPOINT but not always.  */
 120
 121 #define DECR_PC_AFTER_BREAK 0
 122
 123 void arm_print_float_info (void);
 124 #define PRINT_FLOAT_INFO()      arm_print_float_info ()
 125
 126 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 127    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 128    real way to know how big a register is.  */
 129
 130 #define REGISTER_SIZE   4
 131
 132 /* Say how long FP registers are.  Used for documentation purposes and
 133    code readability in this header.  IEEE extended doubles are 80
 134    bits.  DWORD aligned they use 96 bits.  */
 135 #define FP_REGISTER_RAW_SIZE    12
 136
 137 /* GCC doesn't support long doubles (extended IEEE values).  The FP
 138    register virtual size is therefore 64 bits.  Used for documentation
 139    purposes and code readability in this header.  */
 140 #define FP_REGISTER_VIRTUAL_SIZE        8
 141
 142 /* Status registers are the same size as general purpose registers.
 143    Used for documentation purposes and code readability in this
 144    header.  */
 145 #define STATUS_REGISTER_SIZE    REGISTER_SIZE
 146
 147 /* Number of machine registers.  The only define actually required
 148    is NUM_REGS.  The other definitions are used for documentation
 149    purposes and code readability.  */
 150 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
 151    (and called PS for processor status) so the status bits can be cleared
 152    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
 153    in PS.  */
 154 #define NUM_FREGS       8       /* Number of floating point registers.  */
 155 #define NUM_SREGS       2       /* Number of status registers.  */
 156 #define NUM_GREGS       16      /* Number of general purpose registers.  */
 157 #define NUM_REGS        (NUM_GREGS + NUM_FREGS + NUM_SREGS)
 158
 159 /* An array of names of registers. */
 160 extern char **arm_register_names;
 161
 162 #define REGISTER_NAME(i) arm_register_name(i)
 163 char *arm_register_name (int);
 164
 165 /* Register numbers of various important registers.  Note that some of
 166    these values are "real" register numbers, and correspond to the
 167    general registers of the machine, and some are "phony" register
 168    numbers which are too large to be actual register numbers as far as
 169    the user is concerned but do serve to get the desired values when
 170    passed to read_register.  */
 171
 172 #define A1_REGNUM 0             /* first integer-like argument */
 173 #define A4_REGNUM 3             /* last integer-like argument */
 174 #define AP_REGNUM 11
 175 #define FP_REGNUM 11            /* Contains address of executing stack frame */
 176 #define SP_REGNUM 13            /* Contains address of top of stack */
 177 #define LR_REGNUM 14            /* address to return to from a function call */
 178 #define PC_REGNUM 15            /* Contains program counter */
 179 #define F0_REGNUM 16            /* first floating point register */
 180 #define F3_REGNUM 19            /* last floating point argument register */
 181 #define F7_REGNUM 23            /* last floating point register */
 182 #define FPS_REGNUM 24           /* floating point status register */
 183 #define PS_REGNUM 25            /* Contains processor status */
 184
 185 #define THUMB_FP_REGNUM 7       /* R7 is frame register on Thumb */
 186
 187 #define ARM_NUM_ARG_REGS        4
 188 #define ARM_LAST_ARG_REGNUM     A4_REGNUM
 189 #define ARM_NUM_FP_ARG_REGS     4
 190 #define ARM_LAST_FP_ARG_REGNUM  F3_REGNUM
 191
 192 /* Instruction condition field values.  */
 193 #define INST_EQ         0x0
 194 #define INST_NE         0x1
 195 #define INST_CS         0x2
 196 #define INST_CC         0x3
 197 #define INST_MI         0x4
 198 #define INST_PL         0x5
 199 #define INST_VS         0x6
 200 #define INST_VC         0x7
 201 #define INST_HI         0x8
 202 #define INST_LS         0x9
 203 #define INST_GE         0xa
 204 #define INST_LT         0xb
 205 #define INST_GT         0xc
 206 #define INST_LE         0xd
 207 #define INST_AL         0xe
 208 #define INST_NV         0xf
 209
 210 #define FLAG_N          0x80000000
 211 #define FLAG_Z          0x40000000
 212 #define FLAG_C          0x20000000
 213 #define FLAG_V          0x10000000
 214
 215
 216
 217 /* Total amount of space needed to store our copies of the machine's
 218    register state, the array `registers'.  */
 219
 220 #define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \
 221                         (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \
 222                         (NUM_SREGS * STATUS_REGISTER_SIZE))
 223
 224 /* Index within `registers' of the first byte of the space for
 225    register N.  */
 226
 227 #define REGISTER_BYTE(N) \
 228      ((N) < F0_REGNUM \
 229       ? (N) * REGISTER_SIZE \
 230       : ((N) < PS_REGNUM \
 231          ? (NUM_GREGS * REGISTER_SIZE + \
 232             ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \
 233          : (NUM_GREGS * REGISTER_SIZE + \
 234             NUM_FREGS * FP_REGISTER_RAW_SIZE + \
 235             ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE)))
 236
 237 /* Number of bytes of storage in the actual machine representation for
 238    register N.  All registers are 4 bytes, except fp0 - fp7, which are
 239    12 bytes in length.  */
 240 #define REGISTER_RAW_SIZE(N) \
 241      ((N) < F0_REGNUM ? REGISTER_SIZE : \
 242       (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE)
 243
 244 /* Number of bytes of storage in a program's representation
 245    for register N.  */
 246 #define REGISTER_VIRTUAL_SIZE(N) \
 247         ((N) < F0_REGNUM ? REGISTER_SIZE : \
 248          (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE)
 249
 250 /* Largest value REGISTER_RAW_SIZE can have.  */
 251
 252 #define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE
 253
 254 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 255 #define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE
 256
 257 /* Return the GDB type object for the "standard" data type of data in
 258    register N.  */
 259
 260 extern struct type *arm_register_type (int regnum);
 261 #define REGISTER_VIRTUAL_TYPE(N) arm_register_type (N)
 262
 263 /* The system C compiler uses a similar structure return convention to gcc */
 264 extern use_struct_convention_fn arm_use_struct_convention;
 265 #define USE_STRUCT_CONVENTION(gcc_p, type) \
 266      arm_use_struct_convention (gcc_p, type)
 267
 268 /* Store the address of the place in which to copy the structure the
 269    subroutine will return.  This is called from call_function. */
 270
 271 #define STORE_STRUCT_RETURN(ADDR, SP) \
 272      write_register (A1_REGNUM, (ADDR))
 273
 274 /* Extract from an array REGBUF containing the (raw) register state a
 275    function return value of type TYPE, and copy that, in virtual
 276    format, into VALBUF.  */
 277
 278 extern void arm_extract_return_value (struct type *, char[], char *);
 279 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 280      arm_extract_return_value ((TYPE), (REGBUF), (VALBUF))
 281
 282 /* Write into appropriate registers a function return value of type
 283    TYPE, given in virtual format.  */
 284
 285 extern void convert_to_extended (void *dbl, void *ptr);
 286 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 287   if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) {                              \
 288     char _buf[MAX_REGISTER_RAW_SIZE];                                   \
 289     convert_to_extended (VALBUF, _buf);                                         \
 290     write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \
 291   } else                                                                \
 292     write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE))
 293
 294 /* Extract from an array REGBUF containing the (raw) register state
 295    the address in which a function should return its structure value,
 296    as a CORE_ADDR (or an expression that can be used as one).  */
 297
 298 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 299   (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0)))
 300
 301 /* Specify that for the native compiler variables for a particular
 302    lexical context are listed after the beginning LBRAC instead of
 303    before in the executables list of symbols.  */
 304 #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
 305 \f
 306
 307 extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi);
 308 #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
 309         arm_init_extra_frame_info ((fromleaf), (fi))
 310
 311 /* Return the frame address.  On ARM, it is R11; on Thumb it is R7.  */
 312 CORE_ADDR arm_target_read_fp (void);
 313 #define TARGET_READ_FP() arm_target_read_fp ()
 314
 315 /* Describe the pointer in each stack frame to the previous stack
 316    frame (its caller).  */
 317
 318 /* FRAME_CHAIN takes a frame's nominal address and produces the
 319    frame's chain-pointer.
 320
 321    However, if FRAME_CHAIN_VALID returns zero,
 322    it means the given frame is the outermost one and has no caller.  */
 323
 324 CORE_ADDR arm_frame_chain (struct frame_info *);
 325 #define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe)
 326
 327 int arm_frame_chain_valid (CORE_ADDR, struct frame_info *);
 328 #define FRAME_CHAIN_VALID(chain, thisframe) \
 329      arm_frame_chain_valid (chain, thisframe)
 330
 331 /* Define other aspects of the stack frame.  */
 332
 333 int arm_frameless_function_invocation (struct frame_info *fi);
 334 #define FRAMELESS_FUNCTION_INVOCATION(FI) arm_frameless_function_invocation(FI)
 335
 336 CORE_ADDR arm_frame_saved_pc (struct frame_info *);
 337 #define FRAME_SAVED_PC(FI)      arm_frame_saved_pc (FI)
 338
 339 CORE_ADDR arm_frame_args_address(struct frame_info *);
 340 #define FRAME_ARGS_ADDRESS(FI) arm_frame_args_address(FI)
 341
 342 CORE_ADDR arm_frame_locals_address(struct frame_info *);
 343 #define FRAME_LOCALS_ADDRESS(FI) arm_frame_locals_address(FI)
 344
 345 int arm_frame_num_args(struct frame_info *);
 346 #define FRAME_NUM_ARGS(FI) arm_frame_num_args(FI)
 347
 348 /* Return number of bytes at start of arglist that are not really args. */
 349
 350 #define FRAME_ARGS_SKIP 0
 351
 352 /* Put here the code to store, into a struct frame_saved_regs, the
 353    addresses of the saved registers of frame described by FRAME_INFO.
 354    This includes special registers such as pc and fp saved in special
 355    ways in the stack frame.  sp is even more special: the address we
 356    return for it IS the sp for the next frame.  */
 357
 358 void arm_frame_init_saved_regs (struct frame_info *);
 359 #define FRAME_INIT_SAVED_REGS(frame_info) \
 360         arm_frame_init_saved_regs (frame_info);
 361
 362 /* Things needed for making the inferior call functions.  */
 363
 364 CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int, CORE_ADDR);
 365 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 366      arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr))
 367
 368 /* Push an empty stack frame, to record the current PC, etc.  */
 369
 370 void arm_push_dummy_frame (void);
 371
 372 #define PUSH_DUMMY_FRAME arm_push_dummy_frame ()
 373
 374 /* Discard from the stack the innermost frame, restoring all registers.  */
 375
 376 void arm_pop_frame (void);
 377
 378 #define POP_FRAME arm_pop_frame ()
 379
 380 #define CALL_DUMMY_P (1)
 381
 382 #define CALL_DUMMY_WORDS arm_call_dummy_words
 383 extern LONGEST arm_call_dummy_words[];
 384
 385 #define SIZEOF_CALL_DUMMY_WORDS (3 * sizeof (LONGEST))
 386
 387 #define CALL_DUMMY_START_OFFSET  0      /* Start execution at beginning of dummy */
 388
 389 #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
 390 extern int arm_call_dummy_breakpoint_offset (void);
 391
 392 /* Insert the specified number of args and function address into a
 393    call sequence of the above form stored at DUMMYNAME.  */
 394
 395 #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
 396    arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p))
 397
 398 void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun,
 399                          int nargs, struct value ** args,
 400                          struct type * type, int gcc_p);
 401
 402 /* Most ARMs don't have single stepping capability, so provide a
 403    single-stepping mechanism by default */
 404 #undef SOFTWARE_SINGLE_STEP_P
 405 #define SOFTWARE_SINGLE_STEP_P() 1
 406
 407 #define SOFTWARE_SINGLE_STEP(sig,bpt) arm_software_single_step((sig), (bpt))
 408 void arm_software_single_step (int, int);
 409
 410 CORE_ADDR arm_get_next_pc (CORE_ADDR pc);
 411
 412
 413 struct minimal_symbol;
 414
 415 void arm_elf_make_msymbol_special(asymbol *, struct minimal_symbol *);
 416 #define ELF_MAKE_MSYMBOL_SPECIAL(SYM,MSYM) \
 417         arm_elf_make_msymbol_special (SYM, MSYM)
 418
 419 void arm_coff_make_msymbol_special(int, struct minimal_symbol *);
 420 #define COFF_MAKE_MSYMBOL_SPECIAL(VAL,MSYM) \
 421         arm_coff_make_msymbol_special (VAL, MSYM)
 422
 423 /* The first 0x20 bytes are the trap vectors.  */
 424 #define LOWEST_PC       0x20
 425
 426 /* Function to determine whether MEMADDR is in a Thumb function.  */
 427 extern int arm_pc_is_thumb (bfd_vma memaddr);
 428
 429 /* Function to determine whether MEMADDR is in a call dummy called from
 430    a Thumb function.  */
 431 extern int arm_pc_is_thumb_dummy (bfd_vma memaddr);
 432
 433 #endif /* TM_ARM_H */