gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000
   4    Free Software Foundation, Inc.
   5    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   6    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   7
   8    This file is part of GDB.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330,
  23    Boston, MA 02111-1307, USA.  */
  24
  25 #ifndef TM_MIPS_H
  26 #define TM_MIPS_H 1
  27
  28 #define GDB_MULTI_ARCH 1
  29
  30 #include "regcache.h"
  31
  32 struct frame_info;
  33 struct symbol;
  34 struct type;
  35 struct value;
  36
  37 #include <bfd.h>
  38 #include "coff/sym.h"           /* Needed for PDR below.  */
  39 #include "coff/symconst.h"
  40
  41 #if !defined (MIPS_EABI)
  42 #define MIPS_EABI 0
  43 #endif
  44
  45 /* PC should be masked to remove possible MIPS16 flag */
  46 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  47 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  48 #endif
  49 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  50 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  51 #endif
  52
  53 /* The name of the usual type of MIPS processor that is in the target
  54    system.  */
  55
  56 #define DEFAULT_MIPS_TYPE "generic"
  57
  58 /* Remove useless bits from an instruction address.  */
  59
  60 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  61 CORE_ADDR mips_addr_bits_remove (CORE_ADDR addr);
  62
  63 /* Remove useless bits from the stack pointer.  */
  64
  65 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  66
  67 /* Offset from address of function to start of its code.
  68    Zero on most machines.  */
  69
  70 #define FUNCTION_START_OFFSET 0
  71
  72 /* Return non-zero if PC points to an instruction which will cause a step
  73    to execute both the instruction at PC and an instruction at PC+4.  */
  74 extern int mips_step_skips_delay (CORE_ADDR);
  75 #define STEP_SKIPS_DELAY_P (1)
  76 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  77
  78 /* Are we currently handling a signal */
  79
  80 extern int in_sigtramp (CORE_ADDR, char *);
  81 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
  82
  83 /* Say how long (ordinary) registers are.  This is a piece of bogosity
  84    used in push_word and a few other places; REGISTER_RAW_SIZE is the
  85    real way to know how big a register is.  */
  86
  87 #define REGISTER_SIZE 4
  88
  89 /* The size of a register.  This is predefined in tm-mips64.h.  We
  90    can't use REGISTER_SIZE because that is used for various other
  91    things.  */
  92
  93 #ifndef MIPS_REGSIZE
  94 #define MIPS_REGSIZE 4
  95 #endif
  96
  97 /* Number of machine registers */
  98
  99 #ifndef NUM_REGS
 100 #define NUM_REGS 90
 101 #endif
 102
 103 /* Given the register index, return the name of the corresponding
 104    register. */
 105 extern char *mips_register_name (int regnr);
 106 #define REGISTER_NAME(i) mips_register_name (i)
 107
 108 /* Initializer for an array of names of registers.
 109    There should be NUM_REGS strings in this initializer.  */
 110
 111 #ifndef MIPS_REGISTER_NAMES
 112 #define MIPS_REGISTER_NAMES     \
 113     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 114         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 115         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 116         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 117         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 118         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 119         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 120         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 121         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 122         "fsr",  "fir",  "fp",   "", \
 123         "",     "",     "",     "",     "",     "",     "",     "", \
 124         "",     "",     "",     "",     "",     "",     "",     "", \
 125     }
 126 #endif
 127
 128 /* Register numbers of various important registers.
 129    Note that some of these values are "real" register numbers,
 130    and correspond to the general registers of the machine,
 131    and some are "phony" register numbers which are too large
 132    to be actual register numbers as far as the user is concerned
 133    but do serve to get the desired values when passed to read_register.  */
 134
 135 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 136 #define V0_REGNUM 2             /* Function integer return value */
 137 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 138 #if MIPS_EABI
 139 #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 140 #else
 141 #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 142 #endif
 143 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 144 #define SP_REGNUM 29            /* Contains address of top of stack */
 145 #define RA_REGNUM 31            /* Contains return address value */
 146 #define PS_REGNUM 32            /* Contains processor status */
 147 #define HI_REGNUM 34            /* Multiple/divide temp */
 148 #define LO_REGNUM 33            /* ... */
 149 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 150 #define CAUSE_REGNUM 36         /* describes last exception */
 151 #define PC_REGNUM 37            /* Contains program counter */
 152 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 153 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 154 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 155 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 156 #else /* old ABI uses F12 through F15 for args */
 157 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 158 #endif
 159 #define FCRCS_REGNUM 70         /* FP control/status */
 160 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 161 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 162 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 163 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 164 #define PRID_REGNUM 89          /* Processor ID */
 165 #define LAST_EMBED_REGNUM 89    /* Last one */
 166
 167 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 168    of register dumps. */
 169
 170 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 171 extern void mips_do_registers_info (int, int);
 172
 173 /* Total amount of space needed to store our copies of the machine's
 174    register state, the array `registers'.  */
 175
 176 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 177
 178 /* Index within `registers' of the first byte of the space for
 179    register N.  */
 180
 181 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 182
 183 /* Number of bytes of storage in the actual machine representation for
 184    register N.  NOTE: This indirectly defines the register size
 185    transfered by the GDB protocol. */
 186
 187 extern int mips_register_raw_size (int reg_nr);
 188 #define REGISTER_RAW_SIZE(N) (mips_register_raw_size ((N)))
 189
 190
 191 /* Covert between the RAW and VIRTUAL registers.
 192
 193    Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
 194    really 32 bit registers.  This is a legacy of the 64 bit MIPS GDB
 195    protocol which transfers 64 bits for 32 bit registers. */
 196
 197 extern int mips_register_convertible (int reg_nr);
 198 #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
 199
 200
 201 void mips_register_convert_to_virtual (int reg_nr, struct type *virtual_type,
 202                                        char *raw_buf, char *virt_buf);
 203 #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
 204   mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
 205
 206 void mips_register_convert_to_raw (struct type *virtual_type, int reg_nr,
 207                                    char *virt_buf, char *raw_buf);
 208 #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
 209   mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
 210
 211 /* Number of bytes of storage in the program's representation
 212    for register N. */
 213
 214 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 215
 216 /* Largest value REGISTER_RAW_SIZE can have.  */
 217
 218 #define MAX_REGISTER_RAW_SIZE 8
 219
 220 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 221
 222 #define MAX_REGISTER_VIRTUAL_SIZE 8
 223
 224 /* Return the GDB type object for the "standard" data type of data in
 225    register N.  */
 226
 227 #ifndef REGISTER_VIRTUAL_TYPE
 228 #define REGISTER_VIRTUAL_TYPE(N) \
 229         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 230          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 231          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 232          : builtin_type_int)
 233 #endif
 234
 235 /* All mips targets store doubles in a register pair with the least
 236    significant register in the lower numbered register.
 237    If the target is big endian, double register values need conversion
 238    between memory and register formats.  */
 239
 240 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 241   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 242           && REGISTER_RAW_SIZE (n) == 4                                 \
 243           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 244           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 245           && TYPE_LENGTH(type) == 8) {                                  \
 246         char __temp[4];                                                 \
 247         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 248         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 249         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 250
 251 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 252   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 253           && REGISTER_RAW_SIZE (n) == 4                                 \
 254           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 255           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 256           && TYPE_LENGTH(type) == 8) {                                  \
 257         char __temp[4];                                                 \
 258         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 259         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 260         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 261
 262 /* Store the address of the place in which to copy the structure the
 263    subroutine will return.  Handled by mips_push_arguments.  */
 264
 265 #define STORE_STRUCT_RETURN(addr, sp)
 266 /**/
 267
 268 /* Extract from an array REGBUF containing the (raw) register state
 269    a function return value of type TYPE, and copy that, in virtual format,
 270    into VALBUF.  XXX floats */
 271
 272 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 273   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 274 extern void mips_extract_return_value (struct type *, char[], char *);
 275
 276 /* Write into appropriate registers a function return value
 277    of type TYPE, given in virtual format.  */
 278
 279 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 280   mips_store_return_value(TYPE, VALBUF)
 281 extern void mips_store_return_value (struct type *, char *);
 282
 283 /* Extract from an array REGBUF containing the (raw) register state
 284    the address in which a function should return its structure value,
 285    as a CORE_ADDR (or an expression that can be used as one).  */
 286 /* The address is passed in a0 upon entry to the function, but when
 287    the function exits, the compiler has copied the value to v0.  This
 288    convention is specified by the System V ABI, so I think we can rely
 289    on it.  */
 290
 291 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 292   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 293                     REGISTER_RAW_SIZE (V0_REGNUM)))
 294
 295 extern use_struct_convention_fn mips_use_struct_convention;
 296 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 297 \f
 298 /* Describe the pointer in each stack frame to the previous stack frame
 299    (its caller).  */
 300
 301 /* FRAME_CHAIN takes a frame's nominal address
 302    and produces the frame's chain-pointer. */
 303
 304 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 305 extern CORE_ADDR mips_frame_chain (struct frame_info *);
 306
 307 /* Define other aspects of the stack frame.  */
 308
 309
 310 /* A macro that tells us whether the function invocation represented
 311    by FI does not have a frame on the stack associated with it.  If it
 312    does not, FRAMELESS is set to 1, else 0.  */
 313 /* We handle this differently for mips, and maybe we should not */
 314
 315 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 316
 317 /* Saved Pc.  */
 318
 319 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 320 extern CORE_ADDR mips_frame_saved_pc (struct frame_info *);
 321
 322 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 323
 324 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 325
 326 /* Return number of args passed to a frame.
 327    Can return -1, meaning no way to tell.  */
 328
 329 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 330 extern int mips_frame_num_args (struct frame_info *);
 331
 332 /* Return number of bytes at start of arglist that are not really args.  */
 333
 334 #define FRAME_ARGS_SKIP 0
 335
 336 /* Put here the code to store, into a struct frame_saved_regs,
 337    the addresses of the saved registers of frame described by FRAME_INFO.
 338    This includes special registers such as pc and fp saved in special
 339    ways in the stack frame.  sp is even more special:
 340    the address we return for it IS the sp for the next frame.  */
 341
 342 #define FRAME_INIT_SAVED_REGS(frame_info) \
 343   do { \
 344     if ((frame_info)->saved_regs == NULL) \
 345       mips_find_saved_regs (frame_info); \
 346     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 347   } while (0)
 348 extern void mips_find_saved_regs (struct frame_info *);
 349 \f
 350
 351 /* Things needed for making the inferior call functions.  */
 352
 353 /* Stack must be aligned on 32-bit boundaries when synthesizing
 354    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 355    handle it. */
 356
 357 extern CORE_ADDR mips_push_arguments (int, struct value **, CORE_ADDR, int,
 358                                       CORE_ADDR);
 359 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 360   (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
 361
 362 extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
 363 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 364
 365 /* Push an empty stack frame, to record the current PC, etc.  */
 366
 367 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 368 extern void mips_push_dummy_frame (void);
 369
 370 /* Discard from the stack the innermost frame, restoring all registers.  */
 371
 372 #define POP_FRAME               mips_pop_frame()
 373 extern void mips_pop_frame (void);
 374
 375 #define CALL_DUMMY_START_OFFSET (0)
 376
 377 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 378
 379 /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
 380    platform), $t9 ($25) (Dest_Reg) contains the address of the callee
 381    (used for PIC).  It doesn't hurt to do this on other systems; $t9
 382    will be ignored.  */
 383 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 384     write_register(T9_REGNUM, fun)
 385
 386 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 387
 388 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 389 extern CORE_ADDR mips_call_dummy_address (void);
 390
 391 /* There's a mess in stack frame creation.  See comments in blockframe.c
 392    near reference to INIT_FRAME_PC_FIRST.  */
 393
 394 #define INIT_FRAME_PC(fromleaf, prev)   /* nada */
 395
 396 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 397    mips_init_frame_pc_first(fromleaf, prev)
 398 extern void mips_init_frame_pc_first (int, struct frame_info *);
 399
 400 /* Special symbol found in blocks associated with routines.  We can hang
 401    mips_extra_func_info_t's off of this.  */
 402
 403 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 404 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 405
 406 /* Specific information about a procedure.
 407    This overlays the MIPS's PDR records,
 408    mipsread.c (ab)uses this to save memory */
 409
 410 typedef struct mips_extra_func_info
 411   {
 412     long numargs;               /* number of args to procedure (was iopt) */
 413     bfd_vma high_addr;          /* upper address bound */
 414     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 415     PDR pdr;                    /* Procedure descriptor record */
 416   }
 417  *mips_extra_func_info_t;
 418
 419 extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *);
 420 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 421   mips_init_extra_frame_info(fromleaf, fci)
 422
 423 extern void mips_print_extra_frame_info (struct frame_info *frame);
 424 #define PRINT_EXTRA_FRAME_INFO(fi) \
 425   mips_print_extra_frame_info (fi)
 426
 427 /* It takes two values to specify a frame on the MIPS.
 428
 429    In fact, the *PC* is the primary value that sets up a frame.  The
 430    PC is looked up to see what function it's in; symbol information
 431    from that function tells us which register is the frame pointer
 432    base, and what offset from there is the "virtual frame pointer".
 433    (This is usually an offset from SP.)  On most non-MIPS machines,
 434    the primary value is the SP, and the PC, if needed, disambiguates
 435    multiple functions with the same SP.  But on the MIPS we can't do
 436    that since the PC is not stored in the same part of the frame every
 437    time.  This does not seem to be a very clever way to set up frames,
 438    but there is nothing we can do about that.  */
 439
 440 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 441 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 442
 443 /* Select the default mips disassembler */
 444
 445 #define TM_PRINT_INSN_MACH 0
 446
 447
 448 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 449 extern CORE_ADDR sigtramp_address, sigtramp_end;
 450 extern void fixup_sigtramp (void);
 451
 452 /* Defined in mips-tdep.c and used in remote-mips.c */
 453 extern char *mips_read_processor_type (void);
 454
 455 /* Functions for dealing with MIPS16 call and return stubs.  */
 456 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 457 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 458 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 459 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 460 extern int mips_in_call_stub (CORE_ADDR pc, char *name);
 461 extern int mips_in_return_stub (CORE_ADDR pc, char *name);
 462 extern CORE_ADDR mips_skip_stub (CORE_ADDR pc);
 463 extern int mips_ignore_helper (CORE_ADDR pc);
 464
 465 #ifndef TARGET_MIPS
 466 #define TARGET_MIPS
 467 #endif
 468
 469 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 470 #define MIPS_INSTLEN 4          /* Length of an instruction */
 471 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 472 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 473 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 474
 475 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 476    macros to test, set, or clear bit 0 of addresses.  */
 477 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 478 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 479 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 480
 481 #endif /* TM_MIPS_H */
 482
 483 /* Macros for setting and testing a bit in a minimal symbol that
 484    marks it as 16-bit function.  The MSB of the minimal symbol's
 485    "info" field is used for this purpose. This field is already
 486    being used to store the symbol size, so the assumption is
 487    that the symbol size cannot exceed 2^31.
 488
 489    ELF_MAKE_MSYMBOL_SPECIAL
 490    tests whether an ELF symbol is "special", i.e. refers
 491    to a 16-bit function, and sets a "special" bit in a
 492    minimal symbol to mark it as a 16-bit function
 493    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 494    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 495    the "info" field with the "special" bit masked out
 496  */
 497
 498 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 499  { \
 500   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 501     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 502     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 503   } \
 504  }
 505
 506 #define MSYMBOL_IS_SPECIAL(msym) \
 507   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 508 #define MSYMBOL_SIZE(msym) \
 509   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 510
 511
 512 /* Command to set the processor type. */
 513 extern void mips_set_processor_type_command (char *, int);
 514
 515
 516 /* MIPS sign extends addresses */
 517 #define POINTER_TO_ADDRESS(TYPE,BUF) (signed_pointer_to_address (TYPE, BUF))
 518 #define ADDRESS_TO_POINTER(TYPE,BUF,ADDR) (address_to_signed_pointer (TYPE, BUF, ADDR))