gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2
   3    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
   4    1997, 1998, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
   5
   6    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   7    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   8
   9    This file is part of GDB.
  10
  11    This program is free software; you can redistribute it and/or modify
  12    it under the terms of the GNU General Public License as published by
  13    the Free Software Foundation; either version 2 of the License, or
  14    (at your option) any later version.
  15
  16    This program is distributed in the hope that it will be useful,
  17    but WITHOUT ANY WARRANTY; without even the implied warranty of
  18    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19    GNU General Public License for more details.
  20
  21    You should have received a copy of the GNU General Public License
  22    along with this program; if not, write to the Free Software
  23    Foundation, Inc., 59 Temple Place - Suite 330,
  24    Boston, MA 02111-1307, USA.  */
  25
  26 #ifndef TM_MIPS_H
  27 #define TM_MIPS_H 1
  28
  29 #define GDB_MULTI_ARCH 1
  30
  31 #include "regcache.h"
  32
  33 struct frame_info;
  34 struct symbol;
  35 struct type;
  36 struct value;
  37
  38 #include <bfd.h>
  39 #include "coff/sym.h"           /* Needed for PDR below.  */
  40 #include "coff/symconst.h"
  41
  42 /* Return non-zero if PC points to an instruction which will cause a step
  43    to execute both the instruction at PC and an instruction at PC+4.  */
  44 extern int mips_step_skips_delay (CORE_ADDR);
  45 #define STEP_SKIPS_DELAY_P (1)
  46 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  47
  48 /* The size of a register.  This is predefined in tm-mips64.h.  */
  49
  50 #ifndef MIPS_REGSIZE
  51 #define MIPS_REGSIZE 4
  52 #endif
  53
  54 /* Initializer for an array of names for registers 32 and above.
  55    There should be NUM_REGS-32 strings in this initializer.  */
  56
  57 #ifndef MIPS_REGISTER_NAMES
  58 #define MIPS_REGISTER_NAMES     \
  59     {   "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
  60         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
  61         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
  62         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
  63         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
  64         "fsr",  "fir",  ""/*"fp"*/,     "", \
  65         "",     "",     "",     "",     "",     "",     "",     "", \
  66         "",     "",     "",     "",     "",     "",     "",     "", \
  67     }
  68 #endif
  69
  70 /* Register numbers of various important registers.
  71    Note that some of these values are "real" register numbers,
  72    and correspond to the general registers of the machine,
  73    and some are "phony" register numbers which are too large
  74    to be actual register numbers as far as the user is concerned
  75    but do serve to get the desired values when passed to read_register.  */
  76
  77 #define ZERO_REGNUM 0           /* read-only register, always 0 */
  78 #define V0_REGNUM 2             /* Function integer return value */
  79 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
  80 #define T9_REGNUM 25            /* Contains address of callee in PIC */
  81 #define SP_REGNUM 29            /* Contains address of top of stack */
  82 #define RA_REGNUM 31            /* Contains return address value */
  83 #define PS_REGNUM 32            /* Contains processor status */
  84 #define HI_REGNUM 34            /* Multiple/divide temp */
  85 #define LO_REGNUM 33            /* ... */
  86 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
  87 #define CAUSE_REGNUM 36         /* describes last exception */
  88 #define PC_REGNUM 37            /* Contains program counter */
  89 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
  90 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
  91 #define FCRCS_REGNUM 70         /* FP control/status */
  92 #define FCRIR_REGNUM 71         /* FP implementation/revision */
  93 #define UNUSED_REGNUM 73        /* Never used, FIXME */
  94 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
  95 #define PRID_REGNUM 89          /* Processor ID */
  96 #define LAST_EMBED_REGNUM 89    /* Last one */
  97
  98 /* Index within `registers' of the first byte of the space for
  99    register N.  */
 100
 101 #define MIPS_REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 102
 103 /* Return the GDB type object for the "standard" data type of data in
 104    register N.  */
 105
 106 #ifndef MIPS_REGISTER_TYPE
 107 #define MIPS_REGISTER_TYPE(N) \
 108         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 109          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 110          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 111          : builtin_type_int)
 112 #endif
 113
 114 /* Special symbol found in blocks associated with routines.  We can hang
 115    mips_extra_func_info_t's off of this.  */
 116
 117 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 118 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 119
 120 /* Specific information about a procedure.
 121    This overlays the MIPS's PDR records,
 122    mipsread.c (ab)uses this to save memory */
 123
 124 typedef struct mips_extra_func_info
 125   {
 126     long numargs;               /* number of args to procedure (was iopt) */
 127     bfd_vma high_addr;          /* upper address bound */
 128     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 129     PDR pdr;                    /* Procedure descriptor record */
 130   }
 131  *mips_extra_func_info_t;
 132
 133 extern void mips_print_extra_frame_info (struct frame_info *frame);
 134 #define PRINT_EXTRA_FRAME_INFO(fi) \
 135   mips_print_extra_frame_info (fi)
 136
 137 /* It takes two values to specify a frame on the MIPS.
 138
 139    In fact, the *PC* is the primary value that sets up a frame.  The
 140    PC is looked up to see what function it's in; symbol information
 141    from that function tells us which register is the frame pointer
 142    base, and what offset from there is the "virtual frame pointer".
 143    (This is usually an offset from SP.)  On most non-MIPS machines,
 144    the primary value is the SP, and the PC, if needed, disambiguates
 145    multiple functions with the same SP.  But on the MIPS we can't do
 146    that since the PC is not stored in the same part of the frame every
 147    time.  This does not seem to be a very clever way to set up frames,
 148    but there is nothing we can do about that.  */
 149
 150 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 151 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 152
 153 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 154 extern CORE_ADDR sigtramp_address, sigtramp_end;
 155 extern void fixup_sigtramp (void);
 156
 157 /* Defined in mips-tdep.c and used in remote-mips.c */
 158 extern char *mips_read_processor_type (void);
 159
 160 /* Functions for dealing with MIPS16 call and return stubs.  */
 161 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 162 extern int mips_ignore_helper (CORE_ADDR pc);
 163
 164 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 165 #define MIPS_INSTLEN 4          /* Length of an instruction */
 166 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 167 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 168 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 169
 170 #endif /* TM_MIPS_H */
 171
 172 /* Command to set the processor type. */
 173 extern void mips_set_processor_type_command (char *, int);
 174
 175 /* Single step based on where the current instruction will take us.  */
 176 extern void mips_software_single_step (enum target_signal, int);