gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7 This file is part of GDB.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef TM_MIPS_H
  24 #define TM_MIPS_H 1
  25
  26 #ifdef __STDC__
  27 struct frame_info;
  28 struct symbol;
  29 struct type;
  30 struct value;
  31 #endif
  32
  33 #include <bfd.h>
  34 #include "coff/sym.h"           /* Needed for PDR below.  */
  35 #include "coff/symconst.h"
  36
  37 #if !defined (TARGET_BYTE_ORDER)
  38 #define TARGET_BYTE_ORDER LITTLE_ENDIAN
  39 #endif
  40
  41 #if !defined (GDB_TARGET_IS_MIPS64)
  42 #define GDB_TARGET_IS_MIPS64 0
  43 #endif
  44
  45 #if !defined (MIPS_EABI)
  46 #define MIPS_EABI 0
  47 #endif
  48
  49 #if !defined (TARGET_MONITOR_PROMPT)
  50 #define TARGET_MONITOR_PROMPT "<IDT>"
  51 #endif
  52
  53 /* PC should be masked to remove possible MIPS16 flag */
  54 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  55 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  56 #endif
  57 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  58 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  59 #endif
  60
  61 /* Floating point is IEEE compliant */
  62 #define IEEE_FLOAT
  63
  64 /* Some MIPS boards are provided both with and without a floating
  65    point coprocessor.  The MIPS R4650 chip has only single precision
  66    floating point.  We provide a user settable variable to tell gdb
  67    what type of floating point to use.  */
  68
  69 enum mips_fpu_type
  70 {
  71   MIPS_FPU_DOUBLE,      /* Full double precision floating point.  */
  72   MIPS_FPU_SINGLE,      /* Single precision floating point (R4650).  */
  73   MIPS_FPU_NONE         /* No floating point.  */
  74 };
  75
  76 extern enum mips_fpu_type mips_fpu;
  77
  78 /* The name of the usual type of MIPS processor that is in the target
  79    system.  */
  80
  81 #define DEFAULT_MIPS_TYPE "generic"
  82
  83 /* Remove useless bits from an instruction address.  */
  84
  85 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  86 CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
  87
  88 /* Remove useless bits from the stack pointer.  */
  89
  90 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  91
  92 /* Offset from address of function to start of its code.
  93    Zero on most machines.  */
  94
  95 #define FUNCTION_START_OFFSET 0
  96
  97 /* Advance PC across any function entry prologue instructions
  98    to reach some "real" code.  */
  99
 100 #define SKIP_PROLOGUE(pc)       pc = mips_skip_prologue (pc, 0)
 101 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
 102
 103 /* Return non-zero if PC points to an instruction which will cause a step
 104    to execute both the instruction at PC and an instruction at PC+4.  */
 105 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
 106 extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
 107
 108 /* Immediately after a function call, return the saved pc.
 109    Can't always go through the frames for this because on some machines
 110    the new frame is not set up until the new function executes
 111    some instructions.  */
 112
 113 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
 114
 115 /* Are we currently handling a signal */
 116
 117 extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
 118 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
 119
 120 /* Stack grows downward.  */
 121
 122 #define INNER_THAN <
 123
 124 #define BIG_ENDIAN 4321
 125
 126 /* Old-style breakpoint macros.
 127    The IDT board uses an unusual breakpoint value, and sometimes gets
 128    confused when it sees the usual MIPS breakpoint instruction.  */
 129
 130 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
 131 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
 132 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
 133 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
 134 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
 135 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
 136 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
 137 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
 138
 139 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 140    16- or 32-bit breakpoint should be used.  It returns a pointer
 141    to a string of bytes that encode a breakpoint instruction, stores
 142    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 143    point to the actual memory location where the breakpoint should be
 144    inserted.  */
 145
 146 unsigned char *mips_breakpoint_from_pc PARAMS ((CORE_ADDR *pcptr, int *lenptr));
 147 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 148
 149 /* Amount PC must be decremented by after a breakpoint.
 150    This is often the number of bytes in BREAKPOINT
 151    but not always.  */
 152
 153 #define DECR_PC_AFTER_BREAK 0
 154
 155 /* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
 156
 157 int mips_about_to_return PARAMS ((CORE_ADDR pc));
 158 #define ABOUT_TO_RETURN(pc) mips_about_to_return (pc)
 159
 160 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 161    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 162    real way to know how big a register is.  */
 163
 164 #define REGISTER_SIZE 4
 165
 166 /* The size of a register.  This is predefined in tm-mips64.h.  We
 167    can't use REGISTER_SIZE because that is used for various other
 168    things.  */
 169
 170 #ifndef MIPS_REGSIZE
 171 #define MIPS_REGSIZE 4
 172 #endif
 173
 174 /* The sizes of floating point registers.  */
 175
 176 #define MIPS_FPU_SINGLE_REGSIZE 4
 177 #define MIPS_FPU_DOUBLE_REGSIZE 8
 178
 179 /* Number of machine registers */
 180
 181 #ifndef NUM_REGS
 182 #define NUM_REGS 90
 183 #endif
 184
 185 /* Initializer for an array of names of registers.
 186    There should be NUM_REGS strings in this initializer.  */
 187
 188 #ifndef REGISTER_NAMES
 189 #define REGISTER_NAMES  \
 190     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 191         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 192         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 193         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 194         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 195         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 196         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 197         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 198         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 199         "fsr",  "fir",  "fp",   "", \
 200         "",     "",     "",     "",     "",     "",     "",     "", \
 201         "",     "",     "",     "",     "",     "",     "",     "", \
 202     }
 203 #endif
 204
 205 /* Register numbers of various important registers.
 206    Note that some of these values are "real" register numbers,
 207    and correspond to the general registers of the machine,
 208    and some are "phony" register numbers which are too large
 209    to be actual register numbers as far as the user is concerned
 210    but do serve to get the desired values when passed to read_register.  */
 211
 212 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 213 #define V0_REGNUM 2             /* Function integer return value */
 214 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 215 #if MIPS_EABI
 216 #  define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 217 #  define MIPS_NUM_ARG_REGS 8
 218 #else
 219 #  define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 220 #  define MIPS_NUM_ARG_REGS 4
 221 #endif
 222 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 223 #define SP_REGNUM 29            /* Contains address of top of stack */
 224 #define RA_REGNUM 31            /* Contains return address value */
 225 #define PS_REGNUM 32            /* Contains processor status */
 226 #define HI_REGNUM 34            /* Multiple/divide temp */
 227 #define LO_REGNUM 33            /* ... */
 228 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 229 #define CAUSE_REGNUM 36         /* describes last exception */
 230 #define PC_REGNUM 37            /* Contains program counter */
 231 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 232 #define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */
 233 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 234 #  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 235 #  define MIPS_NUM_FP_ARG_REGS 8
 236 #else                           /* old ABI uses F12 through F15 for args */
 237 #  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 238 #  define MIPS_NUM_FP_ARG_REGS 4
 239 #endif
 240 #define FCRCS_REGNUM 70         /* FP control/status */
 241 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 242 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 243 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 244 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 245 #define PRID_REGNUM 89          /* Processor ID */
 246 #define LAST_EMBED_REGNUM 89    /* Last one */
 247
 248 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 249    of register dumps. */
 250
 251 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 252 extern void mips_do_registers_info PARAMS ((int, int));
 253
 254 /* Total amount of space needed to store our copies of the machine's
 255    register state, the array `registers'.  */
 256
 257 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 258
 259 /* Index within `registers' of the first byte of the space for
 260    register N.  */
 261
 262 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 263
 264 /* Number of bytes of storage in the actual machine representation
 265    for register N.  On mips, all regs are the same size.  */
 266
 267 #define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
 268
 269 /* Number of bytes of storage in the program's representation
 270    for register N.  On mips, all regs are the same size.  */
 271
 272 #define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
 273
 274 /* Largest value REGISTER_RAW_SIZE can have.  */
 275
 276 #define MAX_REGISTER_RAW_SIZE 8
 277
 278 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 279
 280 #define MAX_REGISTER_VIRTUAL_SIZE 8
 281
 282 /* Return the GDB type object for the "standard" data type
 283    of data in register N.  */
 284
 285 #ifndef REGISTER_VIRTUAL_TYPE
 286 #define REGISTER_VIRTUAL_TYPE(N) \
 287         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32)  \
 288          ? builtin_type_float : builtin_type_int)
 289 #endif
 290
 291 /* All mips targets store doubles in a register pair with the least
 292    significant register in the lower numbered register.
 293    If the target is big endian, double register values need conversion
 294    between memory and register formats.  */
 295
 296 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 297   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 298           && REGISTER_RAW_SIZE (n) == 4                                 \
 299           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 300           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 301           && TYPE_LENGTH(type) == 8) {                                  \
 302         char __temp[4];                                                 \
 303         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 304         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 305         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 306
 307 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 308   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 309           && REGISTER_RAW_SIZE (n) == 4                                 \
 310           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 311           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 312           && TYPE_LENGTH(type) == 8) {                                  \
 313         char __temp[4];                                                 \
 314         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 315         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 316         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 317
 318 /* Store the address of the place in which to copy the structure the
 319    subroutine will return.  Handled by mips_push_arguments.  */
 320
 321 #define STORE_STRUCT_RETURN(addr, sp)   /**/
 322
 323 /* Extract from an array REGBUF containing the (raw) register state
 324    a function return value of type TYPE, and copy that, in virtual format,
 325    into VALBUF.  XXX floats */
 326
 327 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 328   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 329 extern void
 330 mips_extract_return_value PARAMS ((struct type *, char [], char *));
 331
 332 /* Write into appropriate registers a function return value
 333    of type TYPE, given in virtual format.  */
 334
 335 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 336   mips_store_return_value(TYPE, VALBUF)
 337 extern void mips_store_return_value PARAMS ((struct type *, char *));
 338
 339 /* Extract from an array REGBUF containing the (raw) register state
 340    the address in which a function should return its structure value,
 341    as a CORE_ADDR (or an expression that can be used as one).  */
 342 /* The address is passed in a0 upon entry to the function, but when
 343    the function exits, the compiler has copied the value to v0.  This
 344    convention is specified by the System V ABI, so I think we can rely
 345    on it.  */
 346
 347 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 348   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 349                     REGISTER_RAW_SIZE (V0_REGNUM)))
 350
 351 #if MIPS_EABI
 352 #undef  USE_STRUCT_CONVENTION
 353 #define USE_STRUCT_CONVENTION(gcc_p, type) \
 354   (TYPE_LENGTH (type) > 2 * MIPS_REGSIZE)
 355 #else
 356 /* Structures are returned by ref in extra arg0 */
 357 #define USE_STRUCT_CONVENTION(gcc_p, type)      1
 358 #endif
 359 \f
 360 /* Describe the pointer in each stack frame to the previous stack frame
 361    (its caller).  */
 362
 363 /* FRAME_CHAIN takes a frame's nominal address
 364    and produces the frame's chain-pointer. */
 365
 366 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 367 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
 368
 369 /* Define other aspects of the stack frame.  */
 370
 371
 372 /* A macro that tells us whether the function invocation represented
 373    by FI does not have a frame on the stack associated with it.  If it
 374    does not, FRAMELESS is set to 1, else 0.  */
 375 /* We handle this differently for mips, and maybe we should not */
 376
 377 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}
 378
 379 /* Saved Pc.  */
 380
 381 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 382 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
 383
 384 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 385
 386 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 387
 388 /* Return number of args passed to a frame.
 389    Can return -1, meaning no way to tell.  */
 390
 391 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
 392 extern int mips_frame_num_args PARAMS ((struct frame_info *));
 393
 394 /* Return number of bytes at start of arglist that are not really args.  */
 395
 396 #define FRAME_ARGS_SKIP 0
 397
 398 /* Put here the code to store, into a struct frame_saved_regs,
 399    the addresses of the saved registers of frame described by FRAME_INFO.
 400    This includes special registers such as pc and fp saved in special
 401    ways in the stack frame.  sp is even more special:
 402    the address we return for it IS the sp for the next frame.  */
 403
 404 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
 405   do { \
 406     if ((frame_info)->saved_regs == NULL) \
 407       mips_find_saved_regs (frame_info); \
 408     (frame_saved_regs) = *(frame_info)->saved_regs; \
 409     (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
 410   } while (0)
 411 extern void mips_find_saved_regs PARAMS ((struct frame_info *));
 412
 413 \f
 414 /* Things needed for making the inferior call functions.  */
 415
 416 /* Stack must be aligned on 32-bit boundaries when synthesizing
 417    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 418    handle it. */
 419
 420 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 421     sp = mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))
 422 extern CORE_ADDR
 423 mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
 424
 425 /* Push an empty stack frame, to record the current PC, etc.  */
 426
 427 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 428 extern void mips_push_dummy_frame PARAMS ((void));
 429
 430 /* Discard from the stack the innermost frame, restoring all registers.  */
 431
 432 #define POP_FRAME               mips_pop_frame()
 433 extern void mips_pop_frame PARAMS ((void));
 434
 435 #define CALL_DUMMY { 0 }
 436
 437 #define CALL_DUMMY_START_OFFSET (0)
 438
 439 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 440
 441 /* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
 442    It doesn't hurt to do this on other systems; $t9 will be ignored.  */
 443 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 444     write_register(T9_REGNUM, fun)
 445
 446 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 447
 448 #define CALL_DUMMY_ADDRESS() (entry_point_address ())
 449
 450 /* There's a mess in stack frame creation.  See comments in blockframe.c
 451    near reference to INIT_FRAME_PC_FIRST.  */
 452
 453 #define INIT_FRAME_PC(fromleaf, prev) /* nada */
 454
 455 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 456    mips_init_frame_pc_first(fromleaf, prev)
 457 extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
 458
 459 /* Special symbol found in blocks associated with routines.  We can hang
 460    mips_extra_func_info_t's off of this.  */
 461
 462 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 463 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
 464
 465 /* Specific information about a procedure.
 466    This overlays the MIPS's PDR records,
 467    mipsread.c (ab)uses this to save memory */
 468
 469 typedef struct mips_extra_func_info {
 470         long    numargs;        /* number of args to procedure (was iopt) */
 471         bfd_vma high_addr;      /* upper address bound */
 472         long    frame_adjust;   /* offset of FP from SP (used on MIPS16) */
 473         PDR     pdr;            /* Procedure descriptor record */
 474 } *mips_extra_func_info_t;
 475
 476 #define EXTRA_FRAME_INFO \
 477   mips_extra_func_info_t proc_desc; \
 478   int num_args;\
 479   struct frame_saved_regs *saved_regs;
 480
 481 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
 482 extern void init_extra_frame_info PARAMS ((struct frame_info *));
 483
 484 #define PRINT_EXTRA_FRAME_INFO(fi) \
 485   { \
 486     if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
 487       printf_filtered (" frame pointer is at %s+%d\n", \
 488                        reg_names[fi->proc_desc->pdr.framereg], \
 489                                  fi->proc_desc->pdr.frameoffset); \
 490   }
 491
 492 /* It takes two values to specify a frame on the MIPS.
 493
 494    In fact, the *PC* is the primary value that sets up a frame.  The
 495    PC is looked up to see what function it's in; symbol information
 496    from that function tells us which register is the frame pointer
 497    base, and what offset from there is the "virtual frame pointer".
 498    (This is usually an offset from SP.)  On most non-MIPS machines,
 499    the primary value is the SP, and the PC, if needed, disambiguates
 500    multiple functions with the same SP.  But on the MIPS we can't do
 501    that since the PC is not stored in the same part of the frame every
 502    time.  This does not seem to be a very clever way to set up frames,
 503    but there is nothing we can do about that).  */
 504
 505 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 506 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
 507
 508 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 509
 510 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 511
 512 /* Convert a ecoff register number to a gdb REGNUM */
 513
 514 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 515
 516 /* If the current gcc for for this target does not produce correct debugging
 517    information for float parameters, both prototyped and unprototyped, then
 518    define this macro.  This forces gdb to  always assume that floats are
 519    passed as doubles and then converted in the callee.
 520
 521    For the mips chip, it appears that the debug info marks the parameters as
 522    floats regardless of whether the function is prototyped, but the actual
 523    values are passed as doubles for the non-prototyped case and floats for
 524    the prototyped case.  Thus we choose to make the non-prototyped case work
 525    for C and break the prototyped case, since the non-prototyped case is
 526    probably much more common.  (FIXME). */
 527
 528 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
 529
 530 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 531 extern CORE_ADDR sigtramp_address, sigtramp_end;
 532 extern void fixup_sigtramp PARAMS ((void));
 533
 534 /* Defined in mips-tdep.c and used in remote-mips.c */
 535 extern char *mips_read_processor_type PARAMS ((void));
 536
 537 /* Functions for dealing with MIPS16 call and return stubs.  */
 538 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 539 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 540 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 541 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 542 extern int mips_in_call_stub PARAMS ((CORE_ADDR pc,  char *name));
 543 extern int mips_in_return_stub PARAMS ((CORE_ADDR pc,  char *name));
 544 extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
 545 extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
 546
 547 #ifndef TARGET_MIPS
 548 #define TARGET_MIPS
 549 #endif
 550
 551 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 552 #define MIPS_INSTLEN 4          /* Length of an instruction */
 553 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16*/
 554 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 555 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 556
 557 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 558    macros to test, set, or clear bit 0 of addresses.  */
 559 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 560 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 561 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 562
 563 #endif  /* TM_MIPS_H */
 564
 565 /* Macros for setting and testing a bit in a minimal symbol that
 566    marks it as 16-bit function.  The MSB of the minimal symbol's
 567    "info" field is used for this purpose. This field is already
 568    being used to store the symbol size, so the assumption is
 569    that the symbol size cannot exceed 2^31.
 570
 571    MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", i.e. refers
 572                         to a 16-bit function, and sets a "special" bit in a
 573                         minimal symbol to mark it as a 16-bit function
 574    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 575    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 576                         the "info" field with the "special" bit masked out
 577 */
 578
 579 #define MAKE_MSYMBOL_SPECIAL(sym,msym) \
 580  { \
 581   if (((elf_symbol_type *) sym) -> internal_elf_sym.st_other == STO_MIPS16) { \
 582     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 583     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 584   } \
 585  }
 586
 587 #define MSYMBOL_IS_SPECIAL(msym) \
 588   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 589 #define MSYMBOL_SIZE(msym) \
 590   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)