gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000
   4    Free Software Foundation, Inc.
   5    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   6    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   7
   8    This file is part of GDB.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330,
  23    Boston, MA 02111-1307, USA.  */
  24
  25 #ifndef TM_MIPS_H
  26 #define TM_MIPS_H 1
  27
  28 #define GDB_MULTI_ARCH 1
  29
  30 #include "regcache.h"
  31
  32 struct frame_info;
  33 struct symbol;
  34 struct type;
  35 struct value;
  36
  37 #include <bfd.h>
  38 #include "coff/sym.h"           /* Needed for PDR below.  */
  39 #include "coff/symconst.h"
  40
  41 #if !defined (MIPS_EABI)
  42 #define MIPS_EABI 0
  43 #endif
  44
  45 /* PC should be masked to remove possible MIPS16 flag */
  46 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  47 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  48 #endif
  49 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  50 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  51 #endif
  52
  53 /* The name of the usual type of MIPS processor that is in the target
  54    system.  */
  55
  56 #define DEFAULT_MIPS_TYPE "generic"
  57
  58 /* Remove useless bits from the stack pointer.  */
  59
  60 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  61
  62 /* Offset from address of function to start of its code.
  63    Zero on most machines.  */
  64
  65 #define FUNCTION_START_OFFSET 0
  66
  67 /* Return non-zero if PC points to an instruction which will cause a step
  68    to execute both the instruction at PC and an instruction at PC+4.  */
  69 extern int mips_step_skips_delay (CORE_ADDR);
  70 #define STEP_SKIPS_DELAY_P (1)
  71 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  72
  73 /* Are we currently handling a signal */
  74
  75 extern int in_sigtramp (CORE_ADDR, char *);
  76 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
  77
  78 /* Say how long (ordinary) registers are.  This is a piece of bogosity
  79    used in push_word and a few other places; REGISTER_RAW_SIZE is the
  80    real way to know how big a register is.  */
  81
  82 #define REGISTER_SIZE 4
  83
  84 /* The size of a register.  This is predefined in tm-mips64.h.  We
  85    can't use REGISTER_SIZE because that is used for various other
  86    things.  */
  87
  88 #ifndef MIPS_REGSIZE
  89 #define MIPS_REGSIZE 4
  90 #endif
  91
  92 /* Number of machine registers */
  93
  94 #ifndef NUM_REGS
  95 #define NUM_REGS 90
  96 #endif
  97
  98 /* Given the register index, return the name of the corresponding
  99    register. */
 100 extern char *mips_register_name (int regnr);
 101 #define REGISTER_NAME(i) mips_register_name (i)
 102
 103 /* Initializer for an array of names of registers.
 104    There should be NUM_REGS strings in this initializer.  */
 105
 106 #ifndef MIPS_REGISTER_NAMES
 107 #define MIPS_REGISTER_NAMES     \
 108     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 109         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 110         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 111         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 112         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 113         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 114         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 115         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 116         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 117         "fsr",  "fir",  "fp",   "", \
 118         "",     "",     "",     "",     "",     "",     "",     "", \
 119         "",     "",     "",     "",     "",     "",     "",     "", \
 120     }
 121 #endif
 122
 123 /* Register numbers of various important registers.
 124    Note that some of these values are "real" register numbers,
 125    and correspond to the general registers of the machine,
 126    and some are "phony" register numbers which are too large
 127    to be actual register numbers as far as the user is concerned
 128    but do serve to get the desired values when passed to read_register.  */
 129
 130 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 131 #define V0_REGNUM 2             /* Function integer return value */
 132 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 133 #if MIPS_EABI
 134 #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 135 #else
 136 #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 137 #endif
 138 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 139 #define SP_REGNUM 29            /* Contains address of top of stack */
 140 #define RA_REGNUM 31            /* Contains return address value */
 141 #define PS_REGNUM 32            /* Contains processor status */
 142 #define HI_REGNUM 34            /* Multiple/divide temp */
 143 #define LO_REGNUM 33            /* ... */
 144 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 145 #define CAUSE_REGNUM 36         /* describes last exception */
 146 #define PC_REGNUM 37            /* Contains program counter */
 147 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 148 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 149 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 150 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 151 #else /* old ABI uses F12 through F15 for args */
 152 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 153 #endif
 154 #define FCRCS_REGNUM 70         /* FP control/status */
 155 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 156 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 157 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 158 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 159 #define PRID_REGNUM 89          /* Processor ID */
 160 #define LAST_EMBED_REGNUM 89    /* Last one */
 161
 162 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 163    of register dumps. */
 164
 165 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 166 extern void mips_do_registers_info (int, int);
 167
 168 /* Total amount of space needed to store our copies of the machine's
 169    register state, the array `registers'.  */
 170
 171 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 172
 173 /* Index within `registers' of the first byte of the space for
 174    register N.  */
 175
 176 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 177
 178 /* Covert between the RAW and VIRTUAL registers.
 179
 180    Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
 181    really 32 bit registers.  This is a legacy of the 64 bit MIPS GDB
 182    protocol which transfers 64 bits for 32 bit registers. */
 183
 184 extern int mips_register_convertible (int reg_nr);
 185 #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
 186
 187
 188 void mips_register_convert_to_virtual (int reg_nr, struct type *virtual_type,
 189                                        char *raw_buf, char *virt_buf);
 190 #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
 191   mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
 192
 193 void mips_register_convert_to_raw (struct type *virtual_type, int reg_nr,
 194                                    char *virt_buf, char *raw_buf);
 195 #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
 196   mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
 197
 198 /* Number of bytes of storage in the program's representation
 199    for register N. */
 200
 201 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 202
 203 /* Largest value REGISTER_RAW_SIZE can have.  */
 204
 205 #define MAX_REGISTER_RAW_SIZE 8
 206
 207 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 208
 209 #define MAX_REGISTER_VIRTUAL_SIZE 8
 210
 211 /* Return the GDB type object for the "standard" data type of data in
 212    register N.  */
 213
 214 #ifndef REGISTER_VIRTUAL_TYPE
 215 #define REGISTER_VIRTUAL_TYPE(N) \
 216         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 217          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 218          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 219          : builtin_type_int)
 220 #endif
 221
 222 /* All mips targets store doubles in a register pair with the least
 223    significant register in the lower numbered register.
 224    If the target is big endian, double register values need conversion
 225    between memory and register formats.  */
 226
 227 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 228   do {if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG                           \
 229           && REGISTER_RAW_SIZE (n) == 4                                 \
 230           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 231           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 232           && TYPE_LENGTH(type) == 8) {                                  \
 233         char __temp[4];                                                 \
 234         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 235         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 236         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 237
 238 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 239   do {if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG                           \
 240           && REGISTER_RAW_SIZE (n) == 4                                 \
 241           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 242           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 243           && TYPE_LENGTH(type) == 8) {                                  \
 244         char __temp[4];                                                 \
 245         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 246         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 247         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 248
 249 /* Store the address of the place in which to copy the structure the
 250    subroutine will return.  Handled by mips_push_arguments.  */
 251
 252 #define STORE_STRUCT_RETURN(addr, sp)
 253 /**/
 254
 255 /* Extract from an array REGBUF containing the (raw) register state
 256    a function return value of type TYPE, and copy that, in virtual format,
 257    into VALBUF.  XXX floats */
 258
 259 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 260   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 261 extern void mips_extract_return_value (struct type *, char[], char *);
 262
 263 /* Write into appropriate registers a function return value
 264    of type TYPE, given in virtual format.  */
 265
 266 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 267   mips_store_return_value(TYPE, VALBUF)
 268 extern void mips_store_return_value (struct type *, char *);
 269
 270 /* Extract from an array REGBUF containing the (raw) register state
 271    the address in which a function should return its structure value,
 272    as a CORE_ADDR (or an expression that can be used as one).  */
 273 /* The address is passed in a0 upon entry to the function, but when
 274    the function exits, the compiler has copied the value to v0.  This
 275    convention is specified by the System V ABI, so I think we can rely
 276    on it.  */
 277
 278 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 279   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 280                     REGISTER_RAW_SIZE (V0_REGNUM)))
 281
 282 extern use_struct_convention_fn mips_use_struct_convention;
 283 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 284 \f
 285 /* Describe the pointer in each stack frame to the previous stack frame
 286    (its caller).  */
 287
 288 /* FRAME_CHAIN takes a frame's nominal address
 289    and produces the frame's chain-pointer. */
 290
 291 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 292 extern CORE_ADDR mips_frame_chain (struct frame_info *);
 293
 294 /* Define other aspects of the stack frame.  */
 295
 296
 297 /* A macro that tells us whether the function invocation represented
 298    by FI does not have a frame on the stack associated with it.  If it
 299    does not, FRAMELESS is set to 1, else 0.  */
 300 /* We handle this differently for mips, and maybe we should not */
 301
 302 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 303
 304 /* Saved Pc.  */
 305
 306 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 307 extern CORE_ADDR mips_frame_saved_pc (struct frame_info *);
 308
 309 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 310
 311 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 312
 313 /* Return number of args passed to a frame.
 314    Can return -1, meaning no way to tell.  */
 315
 316 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 317 extern int mips_frame_num_args (struct frame_info *);
 318
 319 /* Return number of bytes at start of arglist that are not really args.  */
 320
 321 #define FRAME_ARGS_SKIP 0
 322
 323 /* Put here the code to store, into a struct frame_saved_regs,
 324    the addresses of the saved registers of frame described by FRAME_INFO.
 325    This includes special registers such as pc and fp saved in special
 326    ways in the stack frame.  sp is even more special:
 327    the address we return for it IS the sp for the next frame.  */
 328
 329 #define FRAME_INIT_SAVED_REGS(frame_info) \
 330   do { \
 331     if ((frame_info)->saved_regs == NULL) \
 332       mips_find_saved_regs (frame_info); \
 333     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 334   } while (0)
 335 extern void mips_find_saved_regs (struct frame_info *);
 336 \f
 337
 338 /* Things needed for making the inferior call functions.  */
 339
 340 /* Stack must be aligned on 32-bit boundaries when synthesizing
 341    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 342    handle it. */
 343
 344 extern CORE_ADDR mips_push_arguments (int, struct value **, CORE_ADDR, int,
 345                                       CORE_ADDR);
 346 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 347   (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
 348
 349 extern CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
 350 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 351
 352 /* Push an empty stack frame, to record the current PC, etc.  */
 353
 354 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 355 extern void mips_push_dummy_frame (void);
 356
 357 /* Discard from the stack the innermost frame, restoring all registers.  */
 358
 359 #define POP_FRAME               mips_pop_frame()
 360 extern void mips_pop_frame (void);
 361
 362 #define CALL_DUMMY_START_OFFSET (0)
 363
 364 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 365
 366 /* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
 367    platform), $t9 ($25) (Dest_Reg) contains the address of the callee
 368    (used for PIC).  It doesn't hurt to do this on other systems; $t9
 369    will be ignored.  */
 370 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 371     write_register(T9_REGNUM, fun)
 372
 373 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 374 extern CORE_ADDR mips_call_dummy_address (void);
 375
 376 /* Special symbol found in blocks associated with routines.  We can hang
 377    mips_extra_func_info_t's off of this.  */
 378
 379 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 380 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 381
 382 /* Specific information about a procedure.
 383    This overlays the MIPS's PDR records,
 384    mipsread.c (ab)uses this to save memory */
 385
 386 typedef struct mips_extra_func_info
 387   {
 388     long numargs;               /* number of args to procedure (was iopt) */
 389     bfd_vma high_addr;          /* upper address bound */
 390     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 391     PDR pdr;                    /* Procedure descriptor record */
 392   }
 393  *mips_extra_func_info_t;
 394
 395 extern void mips_init_extra_frame_info (int fromleaf, struct frame_info *);
 396 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 397   mips_init_extra_frame_info(fromleaf, fci)
 398
 399 extern void mips_print_extra_frame_info (struct frame_info *frame);
 400 #define PRINT_EXTRA_FRAME_INFO(fi) \
 401   mips_print_extra_frame_info (fi)
 402
 403 /* It takes two values to specify a frame on the MIPS.
 404
 405    In fact, the *PC* is the primary value that sets up a frame.  The
 406    PC is looked up to see what function it's in; symbol information
 407    from that function tells us which register is the frame pointer
 408    base, and what offset from there is the "virtual frame pointer".
 409    (This is usually an offset from SP.)  On most non-MIPS machines,
 410    the primary value is the SP, and the PC, if needed, disambiguates
 411    multiple functions with the same SP.  But on the MIPS we can't do
 412    that since the PC is not stored in the same part of the frame every
 413    time.  This does not seem to be a very clever way to set up frames,
 414    but there is nothing we can do about that.  */
 415
 416 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 417 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 418
 419 /* Select the default mips disassembler */
 420
 421 #define TM_PRINT_INSN_MACH 0
 422
 423
 424 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 425 extern CORE_ADDR sigtramp_address, sigtramp_end;
 426 extern void fixup_sigtramp (void);
 427
 428 /* Defined in mips-tdep.c and used in remote-mips.c */
 429 extern char *mips_read_processor_type (void);
 430
 431 /* Functions for dealing with MIPS16 call and return stubs.  */
 432 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 433 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 434 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 435 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 436 extern int mips_in_call_stub (CORE_ADDR pc, char *name);
 437 extern int mips_in_return_stub (CORE_ADDR pc, char *name);
 438 extern CORE_ADDR mips_skip_stub (CORE_ADDR pc);
 439 extern int mips_ignore_helper (CORE_ADDR pc);
 440
 441 #ifndef TARGET_MIPS
 442 #define TARGET_MIPS
 443 #endif
 444
 445 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 446 #define MIPS_INSTLEN 4          /* Length of an instruction */
 447 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 448 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 449 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 450
 451 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 452    macros to test, set, or clear bit 0 of addresses.  */
 453 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 454 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 455 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 456
 457 #endif /* TM_MIPS_H */
 458
 459 /* Macros for setting and testing a bit in a minimal symbol that
 460    marks it as 16-bit function.  The MSB of the minimal symbol's
 461    "info" field is used for this purpose. This field is already
 462    being used to store the symbol size, so the assumption is
 463    that the symbol size cannot exceed 2^31.
 464
 465    ELF_MAKE_MSYMBOL_SPECIAL
 466    tests whether an ELF symbol is "special", i.e. refers
 467    to a 16-bit function, and sets a "special" bit in a
 468    minimal symbol to mark it as a 16-bit function
 469    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 470    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 471    the "info" field with the "special" bit masked out
 472  */
 473
 474 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 475  { \
 476   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 477     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 478     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 479   } \
 480  }
 481
 482 #define MSYMBOL_IS_SPECIAL(msym) \
 483   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 484 #define MSYMBOL_SIZE(msym) \
 485   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 486
 487
 488 /* Command to set the processor type. */
 489 extern void mips_set_processor_type_command (char *, int);
 490
 491
 492 /* Single step based on where the current instruction will take us.  */
 493 extern void mips_software_single_step (enum target_signal, int);