1 /* Definitions to make GDB run on a mips box under 4.3bsd.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
3 Free Software Foundation, Inc.
4 Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
5 and by Alessandro Forin (af@cs.cmu.edu) at CMU..
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "coff/sym.h" /* Needed for PDR below. */
25 #include "coff/symconst.h"
27 #if !defined (TARGET_BYTE_ORDER)
28 #define TARGET_BYTE_ORDER LITTLE_ENDIAN
31 #if !defined (GDB_TARGET_IS_MIPS64)
32 #define GDB_TARGET_IS_MIPS64 0
35 #if !defined (TARGET_MONITOR_PROMPT)
36 #define TARGET_MONITOR_PROMPT { '<', 'I', 'D', 'T', '>' }
39 /* Floating point is IEEE compliant */
42 /* Some MIPS boards are provided both with and without a floating
43 point coprocessor. The MIPS R4650 chip has only single precision
44 floating point. We provide a user settable variable to tell gdb
45 what type of floating point to use. */
49 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
50 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
51 MIPS_FPU_NONE
/* No floating point. */
54 extern enum mips_fpu_type mips_fpu
;
56 /* The name of the usual type of MIPS processor that is in the target
59 #define DEFAULT_MIPS_TYPE "generic"
61 /* Offset from address of function to start of its code.
62 Zero on most machines. */
64 #define FUNCTION_START_OFFSET 0
66 /* Advance PC across any function entry prologue instructions
67 to reach some "real" code. */
69 #define SKIP_PROLOGUE(pc) pc = mips_skip_prologue (pc, 0)
70 extern CORE_ADDR mips_skip_prologue
PARAMS ((CORE_ADDR addr
, int lenient
));
72 /* Return non-zero if PC points to an instruction which will cause a step
73 to execute both the instruction at PC and an instruction at PC+4. */
74 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
76 /* Immediately after a function call, return the saved pc.
77 Can't always go through the frames for this because on some machines
78 the new frame is not set up until the new function executes
81 #define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
83 /* Are we currently handling a signal */
85 extern int in_sigtramp
PARAMS ((CORE_ADDR
, char *));
86 #define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
88 /* Stack grows downward. */
92 #define BIG_ENDIAN 4321
93 #if TARGET_BYTE_ORDER == BIG_ENDIAN
94 #define BREAKPOINT {0, 0x5, 0, 0xd}
96 #define BREAKPOINT {0xd, 0, 0x5, 0}
99 /* Amount PC must be decremented by after a breakpoint.
100 This is often the number of bytes in BREAKPOINT
103 #define DECR_PC_AFTER_BREAK 0
105 /* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
107 #define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)
109 /* Say how long (ordinary) registers are. This is a piece of bogosity
110 used in push_word and a few other places; REGISTER_RAW_SIZE is the
111 real way to know how big a register is. */
113 #define REGISTER_SIZE 4
115 /* The size of a register. This is predefined in tm-mips64.h. We
116 can't use REGISTER_SIZE because that is used for various other
120 #define MIPS_REGSIZE 4
123 /* Number of machine registers */
127 /* Initializer for an array of names of registers.
128 There should be NUM_REGS strings in this initializer. */
130 #define REGISTER_NAMES \
131 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
132 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
133 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
134 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
135 "sr", "lo", "hi", "bad", "cause","pc", \
136 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
137 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
138 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
139 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
140 "fsr", "fir", "fp", "", \
141 "", "", "", "", "", "", "", "", \
142 "", "", "", "", "", "", "", "", \
145 /* Register numbers of various important registers.
146 Note that some of these values are "real" register numbers,
147 and correspond to the general registers of the machine,
148 and some are "phony" register numbers which are too large
149 to be actual register numbers as far as the user is concerned
150 but do serve to get the desired values when passed to read_register. */
152 #define ZERO_REGNUM 0 /* read-only register, always 0 */
153 #define V0_REGNUM 2 /* Function integer return value */
154 #define A0_REGNUM 4 /* Loc of first arg during a subr call */
155 #define SP_REGNUM 29 /* Contains address of top of stack */
156 #define RA_REGNUM 31 /* Contains return address value */
157 #define PS_REGNUM 32 /* Contains processor status */
158 #define HI_REGNUM 34 /* Multiple/divide temp */
159 #define LO_REGNUM 33 /* ... */
160 #define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
161 #define CAUSE_REGNUM 36 /* describes last exception */
162 #define PC_REGNUM 37 /* Contains program counter */
163 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
164 #define FCRCS_REGNUM 70 /* FP control/status */
165 #define FCRIR_REGNUM 71 /* FP implementation/revision */
166 #define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
167 #define UNUSED_REGNUM 73 /* Never used, FIXME */
168 #define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */
169 #define PRID_REGNUM 89 /* Processor ID */
170 #define LAST_EMBED_REGNUM 89 /* Last one */
172 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
173 of register dumps. */
175 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
177 /* Total amount of space needed to store our copies of the machine's
178 register state, the array `registers'. */
180 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
182 /* Index within `registers' of the first byte of the space for
185 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
187 /* Number of bytes of storage in the actual machine representation
188 for register N. On mips, all regs are the same size. */
190 #define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
192 /* Number of bytes of storage in the program's representation
193 for register N. On mips, all regs are the same size. */
195 #define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
197 /* Largest value REGISTER_RAW_SIZE can have. */
199 #define MAX_REGISTER_RAW_SIZE 8
201 /* Largest value REGISTER_VIRTUAL_SIZE can have. */
203 #define MAX_REGISTER_VIRTUAL_SIZE 8
205 /* Return the GDB type object for the "standard" data type
206 of data in register N. */
208 #ifndef REGISTER_VIRTUAL_TYPE
209 #define REGISTER_VIRTUAL_TYPE(N) \
210 (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) \
211 ? builtin_type_float : builtin_type_int)
214 #if HOST_BYTE_ORDER == BIG_ENDIAN
215 /* All mips targets store doubles in a register pair with the least
216 significant register in the lower numbered register.
217 If the host is big endian, double register values need conversion between
218 memory and register formats. */
220 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
221 do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
222 TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
224 memcpy (__temp, ((char *)(buffer))+4, 4); \
225 memcpy (((char *)(buffer))+4, (buffer), 4); \
226 memcpy (((char *)(buffer)), __temp, 4); }} while (0)
228 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
229 do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
230 TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
232 memcpy (__temp, ((char *)(buffer))+4, 4); \
233 memcpy (((char *)(buffer))+4, (buffer), 4); \
234 memcpy (((char *)(buffer)), __temp, 4); }} while (0)
237 /* Store the address of the place in which to copy the structure the
238 subroutine will return. Handled by mips_push_arguments. */
240 #define STORE_STRUCT_RETURN(addr, sp) /**/
242 /* Extract from an array REGBUF containing the (raw) register state
243 a function return value of type TYPE, and copy that, in virtual format,
244 into VALBUF. XXX floats */
246 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
247 mips_extract_return_value(TYPE, REGBUF, VALBUF)
249 /* Write into appropriate registers a function return value
250 of type TYPE, given in virtual format. */
252 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
253 mips_store_return_value(TYPE, VALBUF)
255 /* Extract from an array REGBUF containing the (raw) register state
256 the address in which a function should return its structure value,
257 as a CORE_ADDR (or an expression that can be used as one). */
258 /* The address is passed in a0 upon entry to the function, but when
259 the function exits, the compiler has copied the value to v0. This
260 convention is specified by the System V ABI, so I think we can rely
263 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
264 (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
265 REGISTER_RAW_SIZE (V0_REGNUM)))
267 /* Structures are returned by ref in extra arg0 */
268 #define USE_STRUCT_CONVENTION(gcc_p, type) 1
271 /* Describe the pointer in each stack frame to the previous stack frame
274 /* FRAME_CHAIN takes a frame's nominal address
275 and produces the frame's chain-pointer. */
277 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
279 /* Define other aspects of the stack frame. */
282 /* A macro that tells us whether the function invocation represented
283 by FI does not have a frame on the stack associated with it. If it
284 does not, FRAMELESS is set to 1, else 0. */
285 /* We handle this differently for mips, and maybe we should not */
287 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS) {(FRAMELESS) = 0;}
291 #define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME))
293 #define FRAME_ARGS_ADDRESS(fi) (fi)->frame
295 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
297 /* Return number of args passed to a frame.
298 Can return -1, meaning no way to tell. */
300 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
302 /* Return number of bytes at start of arglist that are not really args. */
304 #define FRAME_ARGS_SKIP 0
306 /* Put here the code to store, into a struct frame_saved_regs,
307 the addresses of the saved registers of frame described by FRAME_INFO.
308 This includes special registers such as pc and fp saved in special
309 ways in the stack frame. sp is even more special:
310 the address we return for it IS the sp for the next frame. */
312 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
314 if ((frame_info)->saved_regs == NULL) \
315 mips_find_saved_regs (frame_info); \
316 (frame_saved_regs) = *(frame_info)->saved_regs; \
317 (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
321 /* Things needed for making the inferior call functions. */
323 /* Stack has strict alignment. However, use PUSH_ARGUMENTS
324 to take care of it. */
325 /*#define STACK_ALIGN(addr) (((addr)+3)&~3)*/
327 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
328 sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
330 /* Push an empty stack frame, to record the current PC, etc. */
332 #define PUSH_DUMMY_FRAME mips_push_dummy_frame()
334 /* Discard from the stack the innermost frame, restoring all registers. */
336 #define POP_FRAME mips_pop_frame()
338 #define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
340 #define OP_LDFPR 061 /* lwc1 */
343 #define OP_LDGPR 043 /* lw */
345 #define CALL_DUMMY_SIZE (16*4)
347 #define CALL_DUMMY {\
348 MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
349 0, /* nop # ... to stop raw backtrace*/\
350 0x27bd0000, /* addu sp,?0 # Pseudo prologue */\
351 /* Start here; reload FP regs, then GP regs: */\
352 MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\
353 MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
354 MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
355 MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
356 MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\
357 MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
358 MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
359 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
360 (017<<26)| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\
361 MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
362 (Dest_Reg<<21) | (31<<11) | 9, /* jalr $r31 */\
363 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
367 #define CALL_DUMMY_START_OFFSET 12
369 #define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))
371 /* Insert the specified number of args and function address
372 into a call sequence of the above form stored at DUMMYNAME. */
374 /* For big endian mips machines we need to switch the order of the
375 words with a floating-point value (it was already coerced to a double
376 by mips_push_arguments). */
377 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
380 store_unsigned_integer \
381 (dummyname + 11 * 4, 4, \
382 (extract_unsigned_integer (dummyname + 11 * 4, 4) \
383 | (((fun) >> 16) & 0xffff))); \
384 store_unsigned_integer \
385 (dummyname + 12 * 4, 4, \
386 (extract_unsigned_integer (dummyname + 12 * 4, 4) \
387 | ((fun) & 0xffff))); \
388 if (mips_fpu == MIPS_FPU_NONE) \
390 store_unsigned_integer (dummyname + 3 * 4, 4, \
391 (unsigned LONGEST) 0); \
392 store_unsigned_integer (dummyname + 4 * 4, 4, \
393 (unsigned LONGEST) 0); \
394 store_unsigned_integer (dummyname + 5 * 4, 4, \
395 (unsigned LONGEST) 0); \
396 store_unsigned_integer (dummyname + 6 * 4, 4, \
397 (unsigned LONGEST) 0); \
399 else if (mips_fpu == MIPS_FPU_SINGLE) \
401 /* This isn't right. mips_push_arguments will call \
402 value_arg_coerce, which will convert all float arguments \
403 to doubles. If the function prototype is float, though, \
404 it will be expecting a float argument in a float \
406 store_unsigned_integer (dummyname + 4 * 4, 4, \
407 (unsigned LONGEST) 0); \
408 store_unsigned_integer (dummyname + 6 * 4, 4, \
409 (unsigned LONGEST) 0); \
411 else if (TARGET_BYTE_ORDER == BIG_ENDIAN \
412 && ! GDB_TARGET_IS_MIPS64) \
415 && TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT) \
417 if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8) \
418 error ("floating point value too large to pass to function");\
419 store_unsigned_integer \
420 (dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\
421 store_unsigned_integer \
422 (dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\
425 && TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT) \
427 if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8) \
428 error ("floating point value too large to pass to function");\
429 store_unsigned_integer \
430 (dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\
431 store_unsigned_integer \
432 (dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\
438 /* There's a mess in stack frame creation. See comments in blockframe.c
439 near reference to INIT_FRAME_PC_FIRST. */
441 #define INIT_FRAME_PC(fromleaf, prev) /* nada */
443 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
444 (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
445 (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
447 /* Special symbol found in blocks associated with routines. We can hang
448 mips_extra_func_info_t's off of this. */
450 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
452 /* Specific information about a procedure.
453 This overlays the MIPS's PDR records,
454 mipsread.c (ab)uses this to save memory */
456 typedef struct mips_extra_func_info
{
457 long numargs
; /* number of args to procedure (was iopt) */
458 PDR pdr
; /* Procedure descriptor record */
459 } *mips_extra_func_info_t
;
461 #define EXTRA_FRAME_INFO \
462 mips_extra_func_info_t proc_desc; \
464 struct frame_saved_regs *saved_regs;
466 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
468 #define PRINT_EXTRA_FRAME_INFO(fi) \
470 if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
471 printf_filtered (" frame pointer is at %s+%d\n", \
472 reg_names[fi->proc_desc->pdr.framereg], \
473 fi->proc_desc->pdr.frameoffset); \
476 /* It takes two values to specify a frame on the MIPS.
478 In fact, the *PC* is the primary value that sets up a frame. The
479 PC is looked up to see what function it's in; symbol information
480 from that function tells us which register is the frame pointer
481 base, and what offset from there is the "virtual frame pointer".
482 (This is usually an offset from SP.) On most non-MIPS machines,
483 the primary value is the SP, and the PC, if needed, disambiguates
484 multiple functions with the same SP. But on the MIPS we can't do
485 that since the PC is not stored in the same part of the frame every
486 time. This does not seem to be a very clever way to set up frames,
487 but there is nothing we can do about that). */
489 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
490 extern struct frame_info
*setup_arbitrary_frame
PARAMS ((int, CORE_ADDR
*));
492 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
494 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
496 /* Convert a ecoff register number to a gdb REGNUM */
498 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)