gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330,
  22    Boston, MA 02111-1307, USA.  */
  23
  24 #ifndef TM_MIPS_H
  25 #define TM_MIPS_H 1
  26
  27 struct frame_info;
  28 struct symbol;
  29 struct type;
  30 struct value;
  31
  32 #include <bfd.h>
  33 #include "coff/sym.h"           /* Needed for PDR below.  */
  34 #include "coff/symconst.h"
  35
  36 #if !defined (TARGET_BYTE_ORDER_DEFAULT)
  37 #define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN
  38 #endif
  39
  40 #if !defined (GDB_TARGET_IS_MIPS64)
  41 #define GDB_TARGET_IS_MIPS64 0
  42 #endif
  43
  44 #if !defined (MIPS_EABI)
  45 #define MIPS_EABI 0
  46 #endif
  47
  48 #if !defined (TARGET_MONITOR_PROMPT)
  49 #define TARGET_MONITOR_PROMPT "<IDT>"
  50 #endif
  51
  52 /* PC should be masked to remove possible MIPS16 flag */
  53 #if !defined (GDB_TARGET_MASK_DISAS_PC)
  54 #define GDB_TARGET_MASK_DISAS_PC(addr) UNMAKE_MIPS16_ADDR(addr)
  55 #endif
  56 #if !defined (GDB_TARGET_UNMASK_DISAS_PC)
  57 #define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
  58 #endif
  59
  60 /* Floating point is IEEE compliant */
  61 #define IEEE_FLOAT
  62
  63 /* The name of the usual type of MIPS processor that is in the target
  64    system.  */
  65
  66 #define DEFAULT_MIPS_TYPE "generic"
  67
  68 /* Remove useless bits from an instruction address.  */
  69
  70 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  71 CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
  72
  73 /* Remove useless bits from the stack pointer.  */
  74
  75 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  76
  77 /* Offset from address of function to start of its code.
  78    Zero on most machines.  */
  79
  80 #define FUNCTION_START_OFFSET 0
  81
  82 /* Advance PC across any function entry prologue instructions
  83    to reach some "real" code.  */
  84
  85 #define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
  86 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
  87
  88 /* Return non-zero if PC points to an instruction which will cause a step
  89    to execute both the instruction at PC and an instruction at PC+4.  */
  90 extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
  91 #define STEP_SKIPS_DELAY_P (1)
  92 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  93
  94 /* Immediately after a function call, return the saved pc.
  95    Can't always go through the frames for this because on some machines
  96    the new frame is not set up until the new function executes
  97    some instructions.  */
  98
  99 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
 100
 101 /* Are we currently handling a signal */
 102
 103 extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
 104 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
 105
 106 /* Stack grows downward.  */
 107
 108 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 109
 110 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 111    16- or 32-bit breakpoint should be used.  It returns a pointer
 112    to a string of bytes that encode a breakpoint instruction, stores
 113    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 114    point to the actual memory location where the breakpoint should be
 115    inserted.  */
 116
 117 extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
 118 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 119
 120 /* Amount PC must be decremented by after a breakpoint.
 121    This is often the number of bytes in BREAKPOINT
 122    but not always.  */
 123
 124 #define DECR_PC_AFTER_BREAK 0
 125
 126 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 127    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 128    real way to know how big a register is.  */
 129
 130 #define REGISTER_SIZE 4
 131
 132 /* The size of a register.  This is predefined in tm-mips64.h.  We
 133    can't use REGISTER_SIZE because that is used for various other
 134    things.  */
 135
 136 #ifndef MIPS_REGSIZE
 137 #define MIPS_REGSIZE 4
 138 #endif
 139
 140 /* The sizes of floating point registers.  */
 141
 142 #define MIPS_FPU_SINGLE_REGSIZE 4
 143 #define MIPS_FPU_DOUBLE_REGSIZE 8
 144
 145 /* Number of machine registers */
 146
 147 #ifndef NUM_REGS
 148 #define NUM_REGS 90
 149 #endif
 150
 151 /* Given the register index, return the name of the corresponding
 152    register. */
 153 extern char *mips_register_name PARAMS ((int regnr));
 154 #define REGISTER_NAME(i) mips_register_name (i)
 155
 156 /* Initializer for an array of names of registers.
 157    There should be NUM_REGS strings in this initializer.  */
 158
 159 #ifndef MIPS_REGISTER_NAMES
 160 #define MIPS_REGISTER_NAMES     \
 161     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 162         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 163         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 164         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 165         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 166         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 167         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 168         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 169         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 170         "fsr",  "fir",  "fp",   "", \
 171         "",     "",     "",     "",     "",     "",     "",     "", \
 172         "",     "",     "",     "",     "",     "",     "",     "", \
 173     }
 174 #endif
 175
 176 /* Register numbers of various important registers.
 177    Note that some of these values are "real" register numbers,
 178    and correspond to the general registers of the machine,
 179    and some are "phony" register numbers which are too large
 180    to be actual register numbers as far as the user is concerned
 181    but do serve to get the desired values when passed to read_register.  */
 182
 183 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 184 #define V0_REGNUM 2             /* Function integer return value */
 185 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 186 #if MIPS_EABI
 187 #define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 188 #define MIPS_NUM_ARG_REGS 8
 189 #else
 190 #define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 191 #define MIPS_NUM_ARG_REGS 4
 192 #endif
 193 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 194 #define SP_REGNUM 29            /* Contains address of top of stack */
 195 #define RA_REGNUM 31            /* Contains return address value */
 196 #define PS_REGNUM 32            /* Contains processor status */
 197 #define HI_REGNUM 34            /* Multiple/divide temp */
 198 #define LO_REGNUM 33            /* ... */
 199 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 200 #define CAUSE_REGNUM 36         /* describes last exception */
 201 #define PC_REGNUM 37            /* Contains program counter */
 202 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 203 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 204 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 205 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 206 #define MIPS_NUM_FP_ARG_REGS 8
 207 #else /* old ABI uses F12 through F15 for args */
 208 #define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 209 #define MIPS_NUM_FP_ARG_REGS 4
 210 #endif
 211 #define FCRCS_REGNUM 70         /* FP control/status */
 212 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 213 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 214 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 215 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 216 #define PRID_REGNUM 89          /* Processor ID */
 217 #define LAST_EMBED_REGNUM 89    /* Last one */
 218
 219 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 220    of register dumps. */
 221
 222 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 223 extern void mips_do_registers_info PARAMS ((int, int));
 224
 225 /* Total amount of space needed to store our copies of the machine's
 226    register state, the array `registers'.  */
 227
 228 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 229
 230 /* Index within `registers' of the first byte of the space for
 231    register N.  */
 232
 233 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 234
 235 /* Number of bytes of storage in the actual machine representation for
 236    register N.  NOTE: This indirectly defines the register size
 237    transfered by the GDB protocol. */
 238
 239 extern int mips_register_raw_size PARAMS ((int reg_nr));
 240 #define REGISTER_RAW_SIZE(N) (mips_register_raw_size ((N)))
 241
 242
 243 /* Covert between the RAW and VIRTUAL registers.
 244
 245    Some MIPS (SR, FSR, FIR) have a `raw' size of MIPS_REGSIZE but are
 246    really 32 bit registers.  This is a legacy of the 64 bit MIPS GDB
 247    protocol which transfers 64 bits for 32 bit registers. */
 248
 249 extern int mips_register_convertible PARAMS ((int reg_nr));
 250 #define REGISTER_CONVERTIBLE(N) (mips_register_convertible ((N)))
 251
 252
 253 void mips_register_convert_to_virtual PARAMS ((int reg_nr, struct type *virtual_type, char *raw_buf, char *virt_buf));
 254 #define REGISTER_CONVERT_TO_VIRTUAL(N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF) \
 255   mips_register_convert_to_virtual (N,VIRTUAL_TYPE,RAW_BUF,VIRT_BUF)
 256
 257 void mips_register_convert_to_raw PARAMS ((struct type *virtual_type, int reg_nr, char *virt_buf, char *raw_buf));
 258 #define REGISTER_CONVERT_TO_RAW(VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF) \
 259   mips_register_convert_to_raw (VIRTUAL_TYPE,N,VIRT_BUF,RAW_BUF)
 260
 261 /* Number of bytes of storage in the program's representation
 262    for register N. */
 263
 264 #define REGISTER_VIRTUAL_SIZE(N) TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (N))
 265
 266 /* Largest value REGISTER_RAW_SIZE can have.  */
 267
 268 #define MAX_REGISTER_RAW_SIZE 8
 269
 270 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 271
 272 #define MAX_REGISTER_VIRTUAL_SIZE 8
 273
 274 /* Return the GDB type object for the "standard" data type of data in
 275    register N.  */
 276
 277 #ifndef REGISTER_VIRTUAL_TYPE
 278 #define REGISTER_VIRTUAL_TYPE(N) \
 279         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 280          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 281          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 282          : builtin_type_int)
 283 #endif
 284
 285 /* All mips targets store doubles in a register pair with the least
 286    significant register in the lower numbered register.
 287    If the target is big endian, double register values need conversion
 288    between memory and register formats.  */
 289
 290 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 291   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 292           && REGISTER_RAW_SIZE (n) == 4                                 \
 293           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 294           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 295           && TYPE_LENGTH(type) == 8) {                                  \
 296         char __temp[4];                                                 \
 297         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 298         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 299         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 300
 301 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 302   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 303           && REGISTER_RAW_SIZE (n) == 4                                 \
 304           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 305           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 306           && TYPE_LENGTH(type) == 8) {                                  \
 307         char __temp[4];                                                 \
 308         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 309         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 310         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 311
 312 /* Store the address of the place in which to copy the structure the
 313    subroutine will return.  Handled by mips_push_arguments.  */
 314
 315 #define STORE_STRUCT_RETURN(addr, sp)
 316 /**/
 317
 318 /* Extract from an array REGBUF containing the (raw) register state
 319    a function return value of type TYPE, and copy that, in virtual format,
 320    into VALBUF.  XXX floats */
 321
 322 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 323   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 324 extern void
 325 mips_extract_return_value PARAMS ((struct type *, char[], char *));
 326
 327 /* Write into appropriate registers a function return value
 328    of type TYPE, given in virtual format.  */
 329
 330 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 331   mips_store_return_value(TYPE, VALBUF)
 332 extern void mips_store_return_value PARAMS ((struct type *, char *));
 333
 334 /* Extract from an array REGBUF containing the (raw) register state
 335    the address in which a function should return its structure value,
 336    as a CORE_ADDR (or an expression that can be used as one).  */
 337 /* The address is passed in a0 upon entry to the function, but when
 338    the function exits, the compiler has copied the value to v0.  This
 339    convention is specified by the System V ABI, so I think we can rely
 340    on it.  */
 341
 342 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 343   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 344                     REGISTER_RAW_SIZE (V0_REGNUM)))
 345
 346 extern use_struct_convention_fn mips_use_struct_convention;
 347 #define USE_STRUCT_CONVENTION(gcc_p, type) mips_use_struct_convention (gcc_p, type)
 348 \f
 349 /* Describe the pointer in each stack frame to the previous stack frame
 350    (its caller).  */
 351
 352 /* FRAME_CHAIN takes a frame's nominal address
 353    and produces the frame's chain-pointer. */
 354
 355 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 356 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
 357
 358 /* Define other aspects of the stack frame.  */
 359
 360
 361 /* A macro that tells us whether the function invocation represented
 362    by FI does not have a frame on the stack associated with it.  If it
 363    does not, FRAMELESS is set to 1, else 0.  */
 364 /* We handle this differently for mips, and maybe we should not */
 365
 366 #define FRAMELESS_FUNCTION_INVOCATION(FI)  (0)
 367
 368 /* Saved Pc.  */
 369
 370 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 371 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
 372
 373 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 374
 375 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 376
 377 /* Return number of args passed to a frame.
 378    Can return -1, meaning no way to tell.  */
 379
 380 #define FRAME_NUM_ARGS(fi)      (mips_frame_num_args(fi))
 381 extern int mips_frame_num_args PARAMS ((struct frame_info *));
 382
 383 /* Return number of bytes at start of arglist that are not really args.  */
 384
 385 #define FRAME_ARGS_SKIP 0
 386
 387 /* Put here the code to store, into a struct frame_saved_regs,
 388    the addresses of the saved registers of frame described by FRAME_INFO.
 389    This includes special registers such as pc and fp saved in special
 390    ways in the stack frame.  sp is even more special:
 391    the address we return for it IS the sp for the next frame.  */
 392
 393 #define FRAME_INIT_SAVED_REGS(frame_info) \
 394   do { \
 395     if ((frame_info)->saved_regs == NULL) \
 396       mips_find_saved_regs (frame_info); \
 397     (frame_info)->saved_regs[SP_REGNUM] = (frame_info)->frame; \
 398   } while (0)
 399 extern void mips_find_saved_regs PARAMS ((struct frame_info *));
 400 \f
 401
 402 /* Things needed for making the inferior call functions.  */
 403
 404 /* Stack must be aligned on 32-bit boundaries when synthesizing
 405    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 406    handle it. */
 407
 408 extern CORE_ADDR mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
 409 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 410   (mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
 411
 412 extern CORE_ADDR mips_push_return_address PARAMS ((CORE_ADDR pc, CORE_ADDR sp));
 413 #define PUSH_RETURN_ADDRESS(PC, SP) (mips_push_return_address ((PC), (SP)))
 414
 415 /* Push an empty stack frame, to record the current PC, etc.  */
 416
 417 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 418 extern void mips_push_dummy_frame PARAMS ((void));
 419
 420 /* Discard from the stack the innermost frame, restoring all registers.  */
 421
 422 #define POP_FRAME               mips_pop_frame()
 423 extern void mips_pop_frame PARAMS ((void));
 424
 425 #if !GDB_MULTI_ARCH
 426 #define CALL_DUMMY { 0 }
 427 #endif
 428
 429 #define CALL_DUMMY_START_OFFSET (0)
 430
 431 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 432
 433 /* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
 434    It doesn't hurt to do this on other systems; $t9 will be ignored.  */
 435 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 436     write_register(T9_REGNUM, fun)
 437
 438 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 439
 440 #define CALL_DUMMY_ADDRESS() (mips_call_dummy_address ())
 441 extern CORE_ADDR mips_call_dummy_address PARAMS ((void));
 442
 443 /* There's a mess in stack frame creation.  See comments in blockframe.c
 444    near reference to INIT_FRAME_PC_FIRST.  */
 445
 446 #define INIT_FRAME_PC(fromleaf, prev)   /* nada */
 447
 448 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 449    mips_init_frame_pc_first(fromleaf, prev)
 450 extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
 451
 452 /* Special symbol found in blocks associated with routines.  We can hang
 453    mips_extra_func_info_t's off of this.  */
 454
 455 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 456 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
 457
 458 /* Specific information about a procedure.
 459    This overlays the MIPS's PDR records,
 460    mipsread.c (ab)uses this to save memory */
 461
 462 typedef struct mips_extra_func_info
 463   {
 464     long numargs;               /* number of args to procedure (was iopt) */
 465     bfd_vma high_addr;          /* upper address bound */
 466     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 467     PDR pdr;                    /* Procedure descriptor record */
 468   }
 469  *mips_extra_func_info_t;
 470
 471 extern void mips_init_extra_frame_info PARAMS ((int fromleaf, struct frame_info *));
 472 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
 473   mips_init_extra_frame_info(fromleaf, fci)
 474
 475 extern void mips_print_extra_frame_info PARAMS ((struct frame_info * frame));
 476 #define PRINT_EXTRA_FRAME_INFO(fi) \
 477   mips_print_extra_frame_info (fi)
 478
 479 /* It takes two values to specify a frame on the MIPS.
 480
 481    In fact, the *PC* is the primary value that sets up a frame.  The
 482    PC is looked up to see what function it's in; symbol information
 483    from that function tells us which register is the frame pointer
 484    base, and what offset from there is the "virtual frame pointer".
 485    (This is usually an offset from SP.)  On most non-MIPS machines,
 486    the primary value is the SP, and the PC, if needed, disambiguates
 487    multiple functions with the same SP.  But on the MIPS we can't do
 488    that since the PC is not stored in the same part of the frame every
 489    time.  This does not seem to be a very clever way to set up frames,
 490    but there is nothing we can do about that).  */
 491
 492 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 493 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
 494
 495 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 496
 497 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 498
 499 /* Convert a ecoff register number to a gdb REGNUM */
 500
 501 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 502
 503 /* If the current gcc for for this target does not produce correct debugging
 504    information for float parameters, both prototyped and unprototyped, then
 505    define this macro.  This forces gdb to  always assume that floats are
 506    passed as doubles and then converted in the callee.
 507
 508    For the mips chip, it appears that the debug info marks the parameters as
 509    floats regardless of whether the function is prototyped, but the actual
 510    values are passed as doubles for the non-prototyped case and floats for
 511    the prototyped case.  Thus we choose to make the non-prototyped case work
 512    for C and break the prototyped case, since the non-prototyped case is
 513    probably much more common.  (FIXME). */
 514
 515 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
 516
 517 /* Select the default mips disassembler */
 518
 519 #define TM_PRINT_INSN_MACH 0
 520
 521
 522 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 523 extern CORE_ADDR sigtramp_address, sigtramp_end;
 524 extern void fixup_sigtramp PARAMS ((void));
 525
 526 /* Defined in mips-tdep.c and used in remote-mips.c */
 527 extern char *mips_read_processor_type PARAMS ((void));
 528
 529 /* Functions for dealing with MIPS16 call and return stubs.  */
 530 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 531 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 532 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 533 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 534 extern int mips_in_call_stub PARAMS ((CORE_ADDR pc, char *name));
 535 extern int mips_in_return_stub PARAMS ((CORE_ADDR pc, char *name));
 536 extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
 537 extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
 538
 539 #ifndef TARGET_MIPS
 540 #define TARGET_MIPS
 541 #endif
 542
 543 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 544 #define MIPS_INSTLEN 4          /* Length of an instruction */
 545 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 546 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 547 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 548
 549 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 550    macros to test, set, or clear bit 0 of addresses.  */
 551 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 552 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 553 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 554
 555 #endif /* TM_MIPS_H */
 556
 557 /* Macros for setting and testing a bit in a minimal symbol that
 558    marks it as 16-bit function.  The MSB of the minimal symbol's
 559    "info" field is used for this purpose. This field is already
 560    being used to store the symbol size, so the assumption is
 561    that the symbol size cannot exceed 2^31.
 562
 563    ELF_MAKE_MSYMBOL_SPECIAL
 564    tests whether an ELF symbol is "special", i.e. refers
 565    to a 16-bit function, and sets a "special" bit in a
 566    minimal symbol to mark it as a 16-bit function
 567    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 568    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 569    the "info" field with the "special" bit masked out
 570  */
 571
 572 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 573  { \
 574   if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) { \
 575     MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); \
 576     SYMBOL_VALUE_ADDRESS (msym) |= 1; \
 577   } \
 578  }
 579
 580 #define MSYMBOL_IS_SPECIAL(msym) \
 581   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 582 #define MSYMBOL_SIZE(msym) \
 583   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 584
 585
 586 /* Command to set the processor type. */
 587 extern void mips_set_processor_type_command (char *, int);