gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2
   3    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
   4    1997, 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
   5
   6    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   7    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   8
   9    This file is part of GDB.
  10
  11    This program is free software; you can redistribute it and/or modify
  12    it under the terms of the GNU General Public License as published by
  13    the Free Software Foundation; either version 2 of the License, or
  14    (at your option) any later version.
  15
  16    This program is distributed in the hope that it will be useful,
  17    but WITHOUT ANY WARRANTY; without even the implied warranty of
  18    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19    GNU General Public License for more details.
  20
  21    You should have received a copy of the GNU General Public License
  22    along with this program; if not, write to the Free Software
  23    Foundation, Inc., 59 Temple Place - Suite 330,
  24    Boston, MA 02111-1307, USA.  */
  25
  26 #ifndef TM_MIPS_H
  27 #define TM_MIPS_H 1
  28
  29 #define GDB_MULTI_ARCH 1
  30
  31 #include "regcache.h"
  32
  33 struct frame_info;
  34 struct symbol;
  35 struct type;
  36 struct value;
  37
  38 #include <bfd.h>
  39 #include "coff/sym.h"           /* Needed for PDR below.  */
  40 #include "coff/symconst.h"
  41
  42 /* Return non-zero if PC points to an instruction which will cause a step
  43    to execute both the instruction at PC and an instruction at PC+4.  */
  44 extern int mips_step_skips_delay (CORE_ADDR);
  45 #define STEP_SKIPS_DELAY_P (1)
  46 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  47
  48 /* Say how long (ordinary) registers are.  This is a piece of bogosity
  49    used in push_word and a few other places; REGISTER_RAW_SIZE is the
  50    real way to know how big a register is.  */
  51
  52 #define REGISTER_SIZE 4
  53
  54 /* The size of a register.  This is predefined in tm-mips64.h.  We
  55    can't use REGISTER_SIZE because that is used for various other
  56    things.  */
  57
  58 #ifndef MIPS_REGSIZE
  59 #define MIPS_REGSIZE 4
  60 #endif
  61
  62 /* Initializer for an array of names of registers.
  63    There should be NUM_REGS strings in this initializer.  */
  64
  65 #ifndef MIPS_REGISTER_NAMES
  66 #define MIPS_REGISTER_NAMES     \
  67     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
  68         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
  69         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
  70         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
  71         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
  72         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
  73         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
  74         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
  75         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
  76         "fsr",  "fir",  ""/*"fp"*/,     "", \
  77         "",     "",     "",     "",     "",     "",     "",     "", \
  78         "",     "",     "",     "",     "",     "",     "",     "", \
  79     }
  80 #endif
  81
  82 /* Register numbers of various important registers.
  83    Note that some of these values are "real" register numbers,
  84    and correspond to the general registers of the machine,
  85    and some are "phony" register numbers which are too large
  86    to be actual register numbers as far as the user is concerned
  87    but do serve to get the desired values when passed to read_register.  */
  88
  89 #define ZERO_REGNUM 0           /* read-only register, always 0 */
  90 #define V0_REGNUM 2             /* Function integer return value */
  91 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
  92 #define T9_REGNUM 25            /* Contains address of callee in PIC */
  93 #define SP_REGNUM 29            /* Contains address of top of stack */
  94 #define RA_REGNUM 31            /* Contains return address value */
  95 #define PS_REGNUM 32            /* Contains processor status */
  96 #define HI_REGNUM 34            /* Multiple/divide temp */
  97 #define LO_REGNUM 33            /* ... */
  98 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
  99 #define CAUSE_REGNUM 36         /* describes last exception */
 100 #define PC_REGNUM 37            /* Contains program counter */
 101 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 102 #define FPA0_REGNUM (FP0_REGNUM+12)     /* First float argument register */
 103 #define FCRCS_REGNUM 70         /* FP control/status */
 104 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 105 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 106 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 107 #define PRID_REGNUM 89          /* Processor ID */
 108 #define LAST_EMBED_REGNUM 89    /* Last one */
 109
 110 /* Total amount of space needed to store our copies of the machine's
 111    register state, the array `registers'.  */
 112
 113 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 114
 115 /* Index within `registers' of the first byte of the space for
 116    register N.  */
 117
 118 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 119
 120 /* Return the GDB type object for the "standard" data type of data in
 121    register N.  */
 122
 123 #ifndef REGISTER_VIRTUAL_TYPE
 124 #define REGISTER_VIRTUAL_TYPE(N) \
 125         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_float \
 126          : ((N) == 32 /*SR*/) ? builtin_type_uint32 \
 127          : ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
 128          : builtin_type_int)
 129 #endif
 130
 131 /* All mips targets store doubles in a register pair with the least
 132    significant register in the lower numbered register.
 133    If the target is big endian, double register values need conversion
 134    between memory and register formats.  */
 135
 136 extern void mips_register_convert_to_type (int regnum,
 137                                            struct type *type,
 138                                            char *buffer);
 139 extern void mips_register_convert_from_type (int regnum,
 140                                              struct type *type,
 141                                              char *buffer);
 142
 143 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)       \
 144   mips_register_convert_to_type ((n), (type), (buffer))
 145
 146 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)     \
 147   mips_register_convert_from_type ((n), (type), (buffer))
 148
 149 \f
 150 /* Special symbol found in blocks associated with routines.  We can hang
 151    mips_extra_func_info_t's off of this.  */
 152
 153 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 154 extern void ecoff_relocate_efi (struct symbol *, CORE_ADDR);
 155
 156 /* Specific information about a procedure.
 157    This overlays the MIPS's PDR records,
 158    mipsread.c (ab)uses this to save memory */
 159
 160 typedef struct mips_extra_func_info
 161   {
 162     long numargs;               /* number of args to procedure (was iopt) */
 163     bfd_vma high_addr;          /* upper address bound */
 164     long frame_adjust;          /* offset of FP from SP (used on MIPS16) */
 165     PDR pdr;                    /* Procedure descriptor record */
 166   }
 167  *mips_extra_func_info_t;
 168
 169 extern void mips_print_extra_frame_info (struct frame_info *frame);
 170 #define PRINT_EXTRA_FRAME_INFO(fi) \
 171   mips_print_extra_frame_info (fi)
 172
 173 /* It takes two values to specify a frame on the MIPS.
 174
 175    In fact, the *PC* is the primary value that sets up a frame.  The
 176    PC is looked up to see what function it's in; symbol information
 177    from that function tells us which register is the frame pointer
 178    base, and what offset from there is the "virtual frame pointer".
 179    (This is usually an offset from SP.)  On most non-MIPS machines,
 180    the primary value is the SP, and the PC, if needed, disambiguates
 181    multiple functions with the same SP.  But on the MIPS we can't do
 182    that since the PC is not stored in the same part of the frame every
 183    time.  This does not seem to be a very clever way to set up frames,
 184    but there is nothing we can do about that.  */
 185
 186 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 187 extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
 188
 189 /* Select the default mips disassembler */
 190
 191 #define TM_PRINT_INSN_MACH 0
 192
 193 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 194 extern CORE_ADDR sigtramp_address, sigtramp_end;
 195 extern void fixup_sigtramp (void);
 196
 197 /* Defined in mips-tdep.c and used in remote-mips.c */
 198 extern char *mips_read_processor_type (void);
 199
 200 /* Functions for dealing with MIPS16 call and return stubs.  */
 201 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 202 extern int mips_ignore_helper (CORE_ADDR pc);
 203
 204 #ifndef TARGET_MIPS
 205 #define TARGET_MIPS
 206 #endif
 207
 208 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 209 #define MIPS_INSTLEN 4          /* Length of an instruction */
 210 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16 */
 211 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 212 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 213
 214 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 215    macros to test, set, or clear bit 0 of addresses.  */
 216 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 217 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 218 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 219
 220 #endif /* TM_MIPS_H */
 221
 222 /* Command to set the processor type. */
 223 extern void mips_set_processor_type_command (char *, int);
 224
 225 /* Single step based on where the current instruction will take us.  */
 226 extern void mips_software_single_step (enum target_signal, int);