1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 Contributed by Axis Communications AB.
7 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
31 #include "dwarf2-frame.h"
39 #include "opcode/cris.h"
40 #include "arch-utils.h"
42 #include "gdb_assert.h"
44 /* To get entry_point_address. */
47 #include "solib.h" /* Support for shared libraries. */
48 #include "solib-svr4.h"
49 #include "gdb_string.h"
54 /* There are no floating point registers. Used in gdbserver low-linux.c. */
57 /* There are 16 general registers. */
60 /* There are 16 special registers. */
63 /* CRISv32 has a pseudo PC register, not noted here. */
65 /* CRISv32 has 16 support registers. */
69 /* Register numbers of various important registers.
70 CRIS_FP_REGNUM Contains address of executing stack frame.
71 STR_REGNUM Contains the address of structure return values.
72 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
73 ARG1_REGNUM Contains the first parameter to a function.
74 ARG2_REGNUM Contains the second parameter to a function.
75 ARG3_REGNUM Contains the third parameter to a function.
76 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
77 SP_REGNUM Contains address of top of stack.
78 PC_REGNUM Contains address of next instruction.
79 SRP_REGNUM Subroutine return pointer register.
80 BRP_REGNUM Breakpoint return pointer register. */
84 /* Enums with respect to the general registers, valid for all
85 CRIS versions. The frame pointer is always in R8. */
87 /* ABI related registers. */
95 /* Registers which happen to be common. */
100 /* CRISv10 et. al. specific registers. */
112 /* CRISv32 specific registers. */
125 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
127 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
147 extern const struct cris_spec_reg cris_spec_regs
[];
149 /* CRIS version, set via the user command 'set cris-version'. Affects
150 register names and sizes. */
151 static int usr_cmd_cris_version
;
153 /* Indicates whether to trust the above variable. */
154 static int usr_cmd_cris_version_valid
= 0;
156 static const char cris_mode_normal
[] = "normal";
157 static const char cris_mode_guru
[] = "guru";
158 static const char *cris_modes
[] = {
164 /* CRIS mode, set via the user command 'set cris-mode'. Affects
165 type of break instruction among other things. */
166 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
168 /* Whether to make use of Dwarf-2 CFI (default on). */
169 static int usr_cmd_cris_dwarf2_cfi
= 1;
171 /* CRIS architecture specific information. */
175 const char *cris_mode
;
179 /* Functions for accessing target dependent data. */
184 return (gdbarch_tdep (current_gdbarch
)->cris_version
);
190 return (gdbarch_tdep (current_gdbarch
)->cris_mode
);
193 /* Sigtramp identification code copied from i386-linux-tdep.c. */
195 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
196 #define SIGTRAMP_OFFSET0 0
197 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
198 #define SIGTRAMP_OFFSET1 4
200 static const unsigned short sigtramp_code
[] =
202 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
203 SIGTRAMP_INSN1
/* break 13 */
206 #define SIGTRAMP_LEN (sizeof sigtramp_code)
208 /* Note: same length as normal sigtramp code. */
210 static const unsigned short rt_sigtramp_code
[] =
212 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
213 SIGTRAMP_INSN1
/* break 13 */
216 /* If PC is in a sigtramp routine, return the address of the start of
217 the routine. Otherwise, return 0. */
220 cris_sigtramp_start (struct frame_info
*next_frame
)
222 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
223 gdb_byte buf
[SIGTRAMP_LEN
];
225 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
228 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
230 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
233 pc
-= SIGTRAMP_OFFSET1
;
234 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
238 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
244 /* If PC is in a RT sigtramp routine, return the address of the start of
245 the routine. Otherwise, return 0. */
248 cris_rt_sigtramp_start (struct frame_info
*next_frame
)
250 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
251 gdb_byte buf
[SIGTRAMP_LEN
];
253 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
256 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
258 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
261 pc
-= SIGTRAMP_OFFSET1
;
262 if (!safe_frame_unwind_memory (next_frame
, pc
, buf
, SIGTRAMP_LEN
))
266 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
272 /* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
273 routine, return the address of the associated sigcontext structure. */
276 cris_sigcontext_addr (struct frame_info
*next_frame
)
282 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
283 sp
= extract_unsigned_integer (buf
, 4);
285 /* Look for normal sigtramp frame first. */
286 pc
= cris_sigtramp_start (next_frame
);
289 /* struct signal_frame (arch/cris/kernel/signal.c) contains
290 struct sigcontext as its first member, meaning the SP points to
295 pc
= cris_rt_sigtramp_start (next_frame
);
298 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
299 a struct ucontext, which in turn contains a struct sigcontext.
301 4 + 4 + 128 to struct ucontext, then
302 4 + 4 + 12 to struct sigcontext. */
306 error (_("Couldn't recognize signal trampoline."));
310 struct cris_unwind_cache
312 /* The previous frame's inner most stack address. Used as this
313 frame ID's stack_addr. */
315 /* The frame's base, optionally used by the high-level debug info. */
318 /* How far the SP and r8 (FP) have been offset from the start of
319 the stack frame (as defined by the previous frame's stack
325 /* From old frame_extra_info struct. */
329 /* Table indicating the location of each and every register. */
330 struct trad_frame_saved_reg
*saved_regs
;
333 static struct cris_unwind_cache
*
334 cris_sigtramp_frame_unwind_cache (struct frame_info
*next_frame
,
337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
338 struct cris_unwind_cache
*info
;
346 return (*this_cache
);
348 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
349 (*this_cache
) = info
;
350 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
352 /* Zero all fields. */
358 info
->uses_frame
= 0;
360 info
->leaf_function
= 0;
362 frame_unwind_register (next_frame
, SP_REGNUM
, buf
);
363 info
->base
= extract_unsigned_integer (buf
, 4);
365 addr
= cris_sigcontext_addr (next_frame
);
367 /* Layout of the sigcontext struct:
370 unsigned long oldmask;
374 if (tdep
->cris_version
== 10)
376 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
378 for (i
= 0; i
<= 13; i
++)
379 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
381 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
382 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
383 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
384 /* Note: IRP is off by 2 at this point. There's no point in correcting
385 it though since that will mean that the backtrace will show a PC
386 different from what is shown when stopped. */
387 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
388 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[IRP_REGNUM
];
389 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (24 * 4);
394 /* R0 to R13 are stored in order at offset (1 * 4) in
396 for (i
= 0; i
<= 13; i
++)
397 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
399 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
400 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
401 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
402 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
403 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
404 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
405 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
406 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
407 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
409 /* FIXME: If ERP is in a delay slot at this point then the PC will
410 be wrong at this point. This problem manifests itself in the
411 sigaltstack.exp test case, which occasionally generates FAILs when
412 the signal is received while in a delay slot.
414 This could be solved by a couple of read_memory_unsigned_integer and a
415 trad_frame_set_value. */
416 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[ERP_REGNUM
];
418 info
->saved_regs
[SP_REGNUM
].addr
= addr
+ (25 * 4);
425 cris_sigtramp_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
426 struct frame_id
*this_id
)
428 struct cris_unwind_cache
*cache
=
429 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
430 (*this_id
) = frame_id_build (cache
->base
, frame_pc_unwind (next_frame
));
433 /* Forward declaration. */
435 static void cris_frame_prev_register (struct frame_info
*next_frame
,
436 void **this_prologue_cache
,
437 int regnum
, int *optimizedp
,
438 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
439 int *realnump
, gdb_byte
*bufferp
);
441 cris_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
443 int regnum
, int *optimizedp
,
444 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
445 int *realnump
, gdb_byte
*valuep
)
447 /* Make sure we've initialized the cache. */
448 cris_sigtramp_frame_unwind_cache (next_frame
, this_cache
);
449 cris_frame_prev_register (next_frame
, this_cache
, regnum
,
450 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
453 static const struct frame_unwind cris_sigtramp_frame_unwind
=
456 cris_sigtramp_frame_this_id
,
457 cris_sigtramp_frame_prev_register
460 static const struct frame_unwind
*
461 cris_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
463 if (cris_sigtramp_start (next_frame
)
464 || cris_rt_sigtramp_start (next_frame
))
465 return &cris_sigtramp_frame_unwind
;
471 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
472 struct frame_info
*this_frame
)
474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
479 if (cris_mode () == cris_mode_guru
)
481 frame_unwind_register (this_frame
, NRP_REGNUM
, buf
);
485 frame_unwind_register (this_frame
, ERP_REGNUM
, buf
);
488 erp
= extract_unsigned_integer (buf
, 4);
492 /* In delay slot - check if there's a breakpoint at the preceding
494 if (breakpoint_here_p (erp
& ~0x1))
500 /* Hardware watchpoint support. */
502 /* We support 6 hardware data watchpoints, but cannot trigger on execute
503 (any combination of read/write is fine). */
506 cris_can_use_hardware_watchpoint (int type
, int count
, int other
)
508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
510 /* No bookkeeping is done here; it is handled by the remote debug agent. */
512 if (tdep
->cris_version
!= 32)
515 /* CRISv32: Six data watchpoints, one for instructions. */
516 return (((type
== bp_read_watchpoint
|| type
== bp_access_watchpoint
517 || type
== bp_hardware_watchpoint
) && count
<= 6)
518 || (type
== bp_hardware_breakpoint
&& count
<= 1));
521 /* The CRISv32 hardware data watchpoints work by specifying ranges,
522 which have no alignment or length restrictions. */
525 cris_region_ok_for_watchpoint (CORE_ADDR addr
, int len
)
530 /* If the inferior has some watchpoint that triggered, return the
531 address associated with that watchpoint. Otherwise, return
535 cris_stopped_data_address (void)
538 eda
= get_frame_register_unsigned (get_current_frame (), EDA_REGNUM
);
542 /* The instruction environment needed to find single-step breakpoints. */
545 struct instruction_environment
547 unsigned long reg
[NUM_GENREGS
];
548 unsigned long preg
[NUM_SPECREGS
];
549 unsigned long branch_break_address
;
550 unsigned long delay_slot_pc
;
551 unsigned long prefix_value
;
556 int delay_slot_pc_active
;
558 int disable_interrupt
;
561 /* Machine-dependencies in CRIS for opcodes. */
563 /* Instruction sizes. */
564 enum cris_instruction_sizes
571 /* Addressing modes. */
572 enum cris_addressing_modes
579 /* Prefix addressing modes. */
580 enum cris_prefix_addressing_modes
582 PREFIX_INDEX_MODE
= 2,
583 PREFIX_ASSIGN_MODE
= 3,
585 /* Handle immediate byte offset addressing mode prefix format. */
586 PREFIX_OFFSET_MODE
= 2
589 /* Masks for opcodes. */
590 enum cris_opcode_masks
592 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
593 SIGNED_EXTEND_BIT_MASK
= 0x2,
594 SIGNED_BYTE_MASK
= 0x80,
595 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
596 SIGNED_WORD_MASK
= 0x8000,
597 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
598 SIGNED_DWORD_MASK
= 0x80000000,
599 SIGNED_QUICK_VALUE_MASK
= 0x20,
600 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
603 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
611 cris_get_operand2 (unsigned short insn
)
613 return ((insn
& 0xF000) >> 12);
617 cris_get_mode (unsigned short insn
)
619 return ((insn
& 0x0C00) >> 10);
623 cris_get_opcode (unsigned short insn
)
625 return ((insn
& 0x03C0) >> 6);
629 cris_get_size (unsigned short insn
)
631 return ((insn
& 0x0030) >> 4);
635 cris_get_operand1 (unsigned short insn
)
637 return (insn
& 0x000F);
640 /* Additional functions in order to handle opcodes. */
643 cris_get_quick_value (unsigned short insn
)
645 return (insn
& 0x003F);
649 cris_get_bdap_quick_offset (unsigned short insn
)
651 return (insn
& 0x00FF);
655 cris_get_branch_short_offset (unsigned short insn
)
657 return (insn
& 0x00FF);
661 cris_get_asr_shift_steps (unsigned long value
)
663 return (value
& 0x3F);
667 cris_get_clear_size (unsigned short insn
)
669 return ((insn
) & 0xC000);
673 cris_is_signed_extend_bit_on (unsigned short insn
)
675 return (((insn
) & 0x20) == 0x20);
679 cris_is_xflag_bit_on (unsigned short insn
)
681 return (((insn
) & 0x1000) == 0x1000);
685 cris_set_size_to_dword (unsigned short *insn
)
692 cris_get_signed_offset (unsigned short insn
)
694 return ((signed char) (insn
& 0x00FF));
697 /* Calls an op function given the op-type, working on the insn and the
699 static void cris_gdb_func (enum cris_op_type
, unsigned short, inst_env_type
*);
701 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
702 struct gdbarch_list
*);
704 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
706 static void set_cris_version (char *ignore_args
, int from_tty
,
707 struct cmd_list_element
*c
);
709 static void set_cris_mode (char *ignore_args
, int from_tty
,
710 struct cmd_list_element
*c
);
712 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
713 struct cmd_list_element
*c
);
715 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
716 struct frame_info
*next_frame
,
717 struct cris_unwind_cache
*info
);
719 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
720 struct frame_info
*next_frame
,
721 struct cris_unwind_cache
*info
);
723 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
724 struct frame_info
*next_frame
);
726 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
727 struct frame_info
*next_frame
);
729 /* When arguments must be pushed onto the stack, they go on in reverse
730 order. The below implements a FILO (stack) to do this.
731 Copied from d10v-tdep.c. */
736 struct stack_item
*prev
;
740 static struct stack_item
*
741 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
743 struct stack_item
*si
;
744 si
= xmalloc (sizeof (struct stack_item
));
745 si
->data
= xmalloc (len
);
748 memcpy (si
->data
, contents
, len
);
752 static struct stack_item
*
753 pop_stack_item (struct stack_item
*si
)
755 struct stack_item
*dead
= si
;
762 /* Put here the code to store, into fi->saved_regs, the addresses of
763 the saved registers of frame described by FRAME_INFO. This
764 includes special registers such as pc and fp saved in special ways
765 in the stack frame. sp is even more special: the address we return
766 for it IS the sp for the next frame. */
768 struct cris_unwind_cache
*
769 cris_frame_unwind_cache (struct frame_info
*next_frame
,
770 void **this_prologue_cache
)
773 struct cris_unwind_cache
*info
;
776 if ((*this_prologue_cache
))
777 return (*this_prologue_cache
);
779 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
780 (*this_prologue_cache
) = info
;
781 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
783 /* Zero all fields. */
789 info
->uses_frame
= 0;
791 info
->leaf_function
= 0;
793 /* Prologue analysis does the rest... */
794 if (cris_version () == 32)
795 crisv32_scan_prologue (frame_func_unwind (next_frame
, NORMAL_FRAME
),
798 cris_scan_prologue (frame_func_unwind (next_frame
, NORMAL_FRAME
),
804 /* Given a GDB frame, determine the address of the calling function's
805 frame. This will be used to create a new GDB frame struct. */
808 cris_frame_this_id (struct frame_info
*next_frame
,
809 void **this_prologue_cache
,
810 struct frame_id
*this_id
)
812 struct cris_unwind_cache
*info
813 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
818 /* The FUNC is easy. */
819 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
821 /* Hopefully the prologue analysis either correctly determined the
822 frame's base (which is the SP from the previous frame), or set
823 that base to "NULL". */
824 base
= info
->prev_sp
;
828 id
= frame_id_build (base
, func
);
834 cris_frame_prev_register (struct frame_info
*next_frame
,
835 void **this_prologue_cache
,
836 int regnum
, int *optimizedp
,
837 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
838 int *realnump
, gdb_byte
*bufferp
)
840 struct cris_unwind_cache
*info
841 = cris_frame_unwind_cache (next_frame
, this_prologue_cache
);
842 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
843 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
846 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
847 dummy frame. The frame ID's base needs to match the TOS value
848 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
851 static struct frame_id
852 cris_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
854 return frame_id_build (cris_unwind_sp (gdbarch
, next_frame
),
855 frame_pc_unwind (next_frame
));
859 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
861 /* Align to the size of an instruction (so that they can safely be
862 pushed onto the stack). */
867 cris_push_dummy_code (struct gdbarch
*gdbarch
,
868 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
869 struct value
**args
, int nargs
,
870 struct type
*value_type
,
871 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
873 /* Allocate space sufficient for a breakpoint. */
875 /* Store the address of that breakpoint */
877 /* CRIS always starts the call at the callee's entry point. */
883 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
884 struct regcache
*regcache
, CORE_ADDR bp_addr
,
885 int nargs
, struct value
**args
, CORE_ADDR sp
,
886 int struct_return
, CORE_ADDR struct_addr
)
895 /* The function's arguments and memory allocated by gdb for the arguments to
896 point at reside in separate areas on the stack.
897 Both frame pointers grow toward higher addresses. */
901 struct stack_item
*si
= NULL
;
903 /* Push the return address. */
904 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
906 /* Are we returning a value using a structure return or a normal value
907 return? struct_addr is the address of the reserved space for the return
908 structure to be written on the stack. */
911 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
914 /* Now load as many as possible of the first arguments into registers,
915 and push the rest onto the stack. */
916 argreg
= ARG1_REGNUM
;
919 for (argnum
= 0; argnum
< nargs
; argnum
++)
926 len
= TYPE_LENGTH (value_type (args
[argnum
]));
927 val
= (char *) value_contents (args
[argnum
]);
929 /* How may registers worth of storage do we need for this argument? */
930 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
932 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
934 /* Data passed by value. Fits in available register(s). */
935 for (i
= 0; i
< reg_demand
; i
++)
937 regcache_cooked_write_unsigned (regcache
, argreg
,
938 *(unsigned long *) val
);
943 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
945 /* Data passed by value. Does not fit in available register(s).
946 Use the register(s) first, then the stack. */
947 for (i
= 0; i
< reg_demand
; i
++)
949 if (argreg
<= ARG4_REGNUM
)
951 regcache_cooked_write_unsigned (regcache
, argreg
,
952 *(unsigned long *) val
);
958 /* Push item for later so that pushed arguments
959 come in the right order. */
960 si
= push_stack_item (si
, val
, 4);
965 else if (len
> (2 * 4))
968 internal_error (__FILE__
, __LINE__
, _("We don't do this"));
972 /* Data passed by value. No available registers. Put it on
974 si
= push_stack_item (si
, val
, len
);
980 /* fp_arg must be word-aligned (i.e., don't += len) to match
981 the function prologue. */
982 sp
= (sp
- si
->len
) & ~3;
983 write_memory (sp
, si
->data
, si
->len
);
984 si
= pop_stack_item (si
);
987 /* Finally, update the SP register. */
988 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
993 static const struct frame_unwind cris_frame_unwind
=
997 cris_frame_prev_register
1000 const struct frame_unwind
*
1001 cris_frame_sniffer (struct frame_info
*next_frame
)
1003 return &cris_frame_unwind
;
1007 cris_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1009 struct cris_unwind_cache
*info
1010 = cris_frame_unwind_cache (next_frame
, this_cache
);
1014 static const struct frame_base cris_frame_base
=
1017 cris_frame_base_address
,
1018 cris_frame_base_address
,
1019 cris_frame_base_address
1022 /* Frames information. The definition of the struct frame_info is
1026 enum frame_type type;
1030 If the compilation option -fno-omit-frame-pointer is present the
1031 variable frame will be set to the content of R8 which is the frame
1034 The variable pc contains the address where execution is performed
1035 in the present frame. The innermost frame contains the current content
1036 of the register PC. All other frames contain the content of the
1037 register PC in the next frame.
1039 The variable `type' indicates the frame's type: normal, SIGTRAMP
1040 (associated with a signal handler), dummy (associated with a dummy
1043 The variable return_pc contains the address where execution should be
1044 resumed when the present frame has finished, the return address.
1046 The variable leaf_function is 1 if the return address is in the register
1047 SRP, and 0 if it is on the stack.
1049 Prologue instructions C-code.
1050 The prologue may consist of (-fno-omit-frame-pointer)
1054 move.d sp,r8 move.d sp,r8
1056 movem rY,[sp] movem rY,[sp]
1057 move.S rZ,[r8-U] move.S rZ,[r8-U]
1059 where 1 is a non-terminal function, and 2 is a leaf-function.
1061 Note that this assumption is extremely brittle, and will break at the
1062 slightest change in GCC's prologue.
1064 If local variables are declared or register contents are saved on stack
1065 the subq-instruction will be present with X as the number of bytes
1066 needed for storage. The reshuffle with respect to r8 may be performed
1067 with any size S (b, w, d) and any of the general registers Z={0..13}.
1068 The offset U should be representable by a signed 8-bit value in all cases.
1069 Thus, the prefix word is assumed to be immediate byte offset mode followed
1070 by another word containing the instruction.
1079 Prologue instructions C++-code.
1080 Case 1) and 2) in the C-code may be followed by
1082 move.d r10,rS ; this
1086 move.S [r8+U],rZ ; P4
1088 if any of the call parameters are stored. The host expects these
1089 instructions to be executed in order to get the call parameters right. */
1091 /* Examine the prologue of a function. The variable ip is the address of
1092 the first instruction of the prologue. The variable limit is the address
1093 of the first instruction after the prologue. The variable fi contains the
1094 information in struct frame_info. The variable frameless_p controls whether
1095 the entire prologue is examined (0) or just enough instructions to
1096 determine that it is a prologue (1). */
1099 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1100 struct cris_unwind_cache
*info
)
1102 /* Present instruction. */
1103 unsigned short insn
;
1105 /* Next instruction, lookahead. */
1106 unsigned short insn_next
;
1109 /* Is there a push fp? */
1112 /* Number of byte on stack used for local variables and movem. */
1115 /* Highest register number in a movem. */
1118 /* move.d r<source_register>,rS */
1119 short source_register
;
1124 /* This frame is with respect to a leaf until a push srp is found. */
1127 info
->leaf_function
= 1;
1130 /* Assume nothing on stack. */
1134 /* If we were called without a next_frame, that means we were called
1135 from cris_skip_prologue which already tried to find the end of the
1136 prologue through the symbol information. 64 instructions past current
1137 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1138 limit
= next_frame
? frame_pc_unwind (next_frame
) : pc
+ 64;
1140 /* Find the prologue instructions. */
1141 while (pc
> 0 && pc
< limit
)
1143 insn
= read_memory_unsigned_integer (pc
, 2);
1147 /* push <reg> 32 bit instruction */
1148 insn_next
= read_memory_unsigned_integer (pc
, 2);
1150 regno
= cris_get_operand2 (insn_next
);
1153 info
->sp_offset
+= 4;
1155 /* This check, meant to recognize srp, used to be regno ==
1156 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1157 if (insn_next
== 0xBE7E)
1161 info
->leaf_function
= 0;
1164 else if (insn_next
== 0x8FEE)
1169 info
->r8_offset
= info
->sp_offset
;
1173 else if (insn
== 0x866E)
1178 info
->uses_frame
= 1;
1182 else if (cris_get_operand2 (insn
) == SP_REGNUM
1183 && cris_get_mode (insn
) == 0x0000
1184 && cris_get_opcode (insn
) == 0x000A)
1189 info
->sp_offset
+= cris_get_quick_value (insn
);
1192 else if (cris_get_mode (insn
) == 0x0002
1193 && cris_get_opcode (insn
) == 0x000F
1194 && cris_get_size (insn
) == 0x0003
1195 && cris_get_operand1 (insn
) == SP_REGNUM
)
1197 /* movem r<regsave>,[sp] */
1198 regsave
= cris_get_operand2 (insn
);
1200 else if (cris_get_operand2 (insn
) == SP_REGNUM
1201 && ((insn
& 0x0F00) >> 8) == 0x0001
1202 && (cris_get_signed_offset (insn
) < 0))
1204 /* Immediate byte offset addressing prefix word with sp as base
1205 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1206 is between 64 and 128.
1207 movem r<regsave>,[sp=sp-<val>] */
1210 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1212 insn_next
= read_memory_unsigned_integer (pc
, 2);
1214 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1215 && cris_get_opcode (insn_next
) == 0x000F
1216 && cris_get_size (insn_next
) == 0x0003
1217 && cris_get_operand1 (insn_next
) == SP_REGNUM
)
1219 regsave
= cris_get_operand2 (insn_next
);
1223 /* The prologue ended before the limit was reached. */
1228 else if (cris_get_mode (insn
) == 0x0001
1229 && cris_get_opcode (insn
) == 0x0009
1230 && cris_get_size (insn
) == 0x0002)
1232 /* move.d r<10..13>,r<0..15> */
1233 source_register
= cris_get_operand1 (insn
);
1235 /* FIXME? In the glibc solibs, the prologue might contain something
1236 like (this example taken from relocate_doit):
1238 sub.d 0xfffef426,$r0
1239 which isn't covered by the source_register check below. Question
1240 is whether to add a check for this combo, or make better use of
1241 the limit variable instead. */
1242 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1244 /* The prologue ended before the limit was reached. */
1249 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1250 /* The size is a fixed-size. */
1251 && ((insn
& 0x0F00) >> 8) == 0x0001
1252 /* A negative offset. */
1253 && (cris_get_signed_offset (insn
) < 0))
1255 /* move.S rZ,[r8-U] (?) */
1256 insn_next
= read_memory_unsigned_integer (pc
, 2);
1258 regno
= cris_get_operand2 (insn_next
);
1259 if ((regno
>= 0 && regno
< SP_REGNUM
)
1260 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1261 && cris_get_opcode (insn_next
) == 0x000F)
1263 /* move.S rZ,[r8-U] */
1268 /* The prologue ended before the limit was reached. */
1273 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1274 /* The size is a fixed-size. */
1275 && ((insn
& 0x0F00) >> 8) == 0x0001
1276 /* A positive offset. */
1277 && (cris_get_signed_offset (insn
) > 0))
1279 /* move.S [r8+U],rZ (?) */
1280 insn_next
= read_memory_unsigned_integer (pc
, 2);
1282 regno
= cris_get_operand2 (insn_next
);
1283 if ((regno
>= 0 && regno
< SP_REGNUM
)
1284 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1285 && cris_get_opcode (insn_next
) == 0x0009
1286 && cris_get_operand1 (insn_next
) == regno
)
1288 /* move.S [r8+U],rZ */
1293 /* The prologue ended before the limit was reached. */
1300 /* The prologue ended before the limit was reached. */
1306 /* We only want to know the end of the prologue when next_frame and info
1307 are NULL (called from cris_skip_prologue i.e.). */
1308 if (next_frame
== NULL
&& info
== NULL
)
1313 info
->size
= info
->sp_offset
;
1315 /* Compute the previous frame's stack pointer (which is also the
1316 frame's ID's stack address), and this frame's base pointer. */
1317 if (info
->uses_frame
)
1320 /* The SP was moved to the FP. This indicates that a new frame
1321 was created. Get THIS frame's FP value by unwinding it from
1323 frame_unwind_unsigned_register (next_frame
, CRIS_FP_REGNUM
,
1325 info
->base
= this_base
;
1326 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1328 /* The FP points at the last saved register. Adjust the FP back
1329 to before the first saved register giving the SP. */
1330 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1335 /* Assume that the FP is this frame's SP but with that pushed
1336 stack space added back. */
1337 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
1338 info
->base
= this_base
;
1339 info
->prev_sp
= info
->base
+ info
->size
;
1342 /* Calculate the addresses for the saved registers on the stack. */
1343 /* FIXME: The address calculation should really be done on the fly while
1344 we're analyzing the prologue (we only hold one regsave value as it is
1346 val
= info
->sp_offset
;
1348 for (regno
= regsave
; regno
>= 0; regno
--)
1350 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1354 /* The previous frame's SP needed to be computed. Save the computed
1356 trad_frame_set_value (info
->saved_regs
, SP_REGNUM
, info
->prev_sp
);
1358 if (!info
->leaf_function
)
1360 /* SRP saved on the stack. But where? */
1361 if (info
->r8_offset
== 0)
1363 /* R8 not pushed yet. */
1364 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1368 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1369 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1373 /* The PC is found in SRP (the actual register or located on the stack). */
1374 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1380 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
1381 struct cris_unwind_cache
*info
)
1385 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1386 meant to be a full-fledged prologue scanner. It is only needed for
1387 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1389 * PLT stubs (library calls)
1391 * signal trampolines
1393 For those cases, it is assumed that there is no actual prologue; that
1394 the stack pointer is not adjusted, and (as a consequence) the return
1395 address is not pushed onto the stack. */
1397 /* We only want to know the end of the prologue when next_frame and info
1398 are NULL (called from cris_skip_prologue i.e.). */
1399 if (next_frame
== NULL
&& info
== NULL
)
1404 /* The SP is assumed to be unaltered. */
1405 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
1406 info
->base
= this_base
;
1407 info
->prev_sp
= this_base
;
1409 /* The PC is assumed to be found in SRP. */
1410 info
->saved_regs
[PC_REGNUM
] = info
->saved_regs
[SRP_REGNUM
];
1415 /* Advance pc beyond any function entry prologue instructions at pc
1416 to reach some "real" code. */
1418 /* Given a PC value corresponding to the start of a function, return the PC
1419 of the first instruction after the function prologue. */
1422 cris_skip_prologue (CORE_ADDR pc
)
1424 CORE_ADDR func_addr
, func_end
;
1425 struct symtab_and_line sal
;
1426 CORE_ADDR pc_after_prologue
;
1428 /* If we have line debugging information, then the end of the prologue
1429 should the first assembly instruction of the first source line. */
1430 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1432 sal
= find_pc_line (func_addr
, 0);
1433 if (sal
.end
> 0 && sal
.end
< func_end
)
1437 if (cris_version () == 32)
1438 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1440 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1442 return pc_after_prologue
;
1446 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1449 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1454 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1457 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &sp
);
1461 /* Use the program counter to determine the contents and size of a breakpoint
1462 instruction. It returns a pointer to a string of bytes that encode a
1463 breakpoint instruction, stores the length of the string to *lenptr, and
1464 adjusts pcptr (if necessary) to point to the actual memory location where
1465 the breakpoint should be inserted. */
1467 static const unsigned char *
1468 cris_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1470 static unsigned char break8_insn
[] = {0x38, 0xe9};
1471 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1474 if (cris_mode () == cris_mode_guru
)
1475 return break15_insn
;
1480 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1484 cris_spec_reg_applicable (struct cris_spec_reg spec_reg
)
1486 int version
= cris_version ();
1488 switch (spec_reg
.applicable_version
)
1490 case cris_ver_version_all
:
1492 case cris_ver_warning
:
1493 /* Indeterminate/obsolete. */
1496 return (version
>= 0 && version
<= 3);
1498 return (version
>= 3);
1500 return (version
== 8 || version
== 9);
1502 return (version
>= 8);
1503 case cris_ver_v0_10
:
1504 return (version
>= 0 && version
<= 10);
1505 case cris_ver_v3_10
:
1506 return (version
>= 3 && version
<= 10);
1507 case cris_ver_v8_10
:
1508 return (version
>= 8 && version
<= 10);
1510 return (version
== 10);
1512 return (version
>= 10);
1514 return (version
>= 32);
1516 /* Invalid cris version. */
1521 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1522 register, -1 for an invalid register. */
1525 cris_register_size (int regno
)
1527 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1531 if (regno
>= 0 && regno
< NUM_GENREGS
)
1533 /* General registers (R0 - R15) are 32 bits. */
1536 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1538 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1539 Adjust regno accordingly. */
1540 spec_regno
= regno
- NUM_GENREGS
;
1542 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1544 if (cris_spec_regs
[i
].number
== spec_regno
1545 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1546 /* Go with the first applicable register. */
1547 return cris_spec_regs
[i
].reg_size
;
1549 /* Special register not applicable to this CRIS version. */
1552 else if (regno
>= PC_REGNUM
&& regno
< gdbarch_num_regs (current_gdbarch
))
1554 /* This will apply to CRISv32 only where there are additional registers
1555 after the special registers (pseudo PC and support registers). */
1563 /* Nonzero if regno should not be fetched from the target. This is the case
1564 for unimplemented (size 0) and non-existant registers. */
1567 cris_cannot_fetch_register (int regno
)
1569 return ((regno
< 0 || regno
>= gdbarch_num_regs (current_gdbarch
))
1570 || (cris_register_size (regno
) == 0));
1573 /* Nonzero if regno should not be written to the target, for various
1577 cris_cannot_store_register (int regno
)
1579 /* There are three kinds of registers we refuse to write to.
1580 1. Those that not implemented.
1581 2. Those that are read-only (depends on the processor mode).
1582 3. Those registers to which a write has no effect.
1586 || regno
>= gdbarch_num_regs (current_gdbarch
)
1587 || cris_register_size (regno
) == 0)
1588 /* Not implemented. */
1591 else if (regno
== VR_REGNUM
)
1595 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1596 /* Writing has no effect. */
1599 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1600 agent decide whether they are writable. */
1605 /* Nonzero if regno should not be fetched from the target. This is the case
1606 for unimplemented (size 0) and non-existant registers. */
1609 crisv32_cannot_fetch_register (int regno
)
1611 return ((regno
< 0 || regno
>= gdbarch_num_regs (current_gdbarch
))
1612 || (cris_register_size (regno
) == 0));
1615 /* Nonzero if regno should not be written to the target, for various
1619 crisv32_cannot_store_register (int regno
)
1621 /* There are three kinds of registers we refuse to write to.
1622 1. Those that not implemented.
1623 2. Those that are read-only (depends on the processor mode).
1624 3. Those registers to which a write has no effect.
1628 || regno
>= gdbarch_num_regs (current_gdbarch
)
1629 || cris_register_size (regno
) == 0)
1630 /* Not implemented. */
1633 else if (regno
== VR_REGNUM
)
1637 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1638 /* Writing has no effect. */
1641 /* Many special registers are read-only in user mode. Let the debug
1642 agent decide whether they are writable. */
1647 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1648 of data in register regno. */
1650 static struct type
*
1651 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1653 if (regno
== PC_REGNUM
)
1654 return builtin_type_void_func_ptr
;
1655 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1656 return builtin_type_void_data_ptr
;
1657 else if ((regno
>= 0 && regno
< SP_REGNUM
)
1658 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1659 /* Note: R8 taken care of previous clause. */
1660 return builtin_type_uint32
;
1661 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1662 return builtin_type_uint16
;
1663 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1664 return builtin_type_uint8
;
1666 /* Invalid (unimplemented) register. */
1667 return builtin_type_int0
;
1670 static struct type
*
1671 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1673 if (regno
== PC_REGNUM
)
1674 return builtin_type_void_func_ptr
;
1675 else if (regno
== SP_REGNUM
|| regno
== CRIS_FP_REGNUM
)
1676 return builtin_type_void_data_ptr
;
1677 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1678 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1679 || (regno
== PID_REGNUM
)
1680 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1681 /* Note: R8 and SP taken care of by previous clause. */
1682 return builtin_type_uint32
;
1683 else if (regno
== WZ_REGNUM
)
1684 return builtin_type_uint16
;
1685 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1686 return builtin_type_uint8
;
1689 /* Invalid (unimplemented) register. Should not happen as there are
1690 no unimplemented CRISv32 registers. */
1691 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1692 return builtin_type_int0
;
1696 /* Stores a function return value of type type, where valbuf is the address
1697 of the value to be stored. */
1699 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1702 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1706 int len
= TYPE_LENGTH (type
);
1710 /* Put the return value in R10. */
1711 val
= extract_unsigned_integer (valbuf
, len
);
1712 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1716 /* Put the return value in R10 and R11. */
1717 val
= extract_unsigned_integer (valbuf
, 4);
1718 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1719 val
= extract_unsigned_integer ((char *)valbuf
+ 4, len
- 4);
1720 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1723 error (_("cris_store_return_value: type length too large."));
1726 /* Return the name of register regno as a string. Return NULL for an invalid or
1727 unimplemented register. */
1730 cris_special_register_name (int regno
)
1735 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1736 Adjust regno accordingly. */
1737 spec_regno
= regno
- NUM_GENREGS
;
1739 /* Assume nothing about the layout of the cris_spec_regs struct
1741 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1743 if (cris_spec_regs
[i
].number
== spec_regno
1744 && cris_spec_reg_applicable (cris_spec_regs
[i
]))
1745 /* Go with the first applicable register. */
1746 return cris_spec_regs
[i
].name
;
1748 /* Special register not applicable to this CRIS version. */
1753 cris_register_name (int regno
)
1755 static char *cris_genreg_names
[] =
1756 { "r0", "r1", "r2", "r3", \
1757 "r4", "r5", "r6", "r7", \
1758 "r8", "r9", "r10", "r11", \
1759 "r12", "r13", "sp", "pc" };
1761 if (regno
>= 0 && regno
< NUM_GENREGS
)
1763 /* General register. */
1764 return cris_genreg_names
[regno
];
1766 else if (regno
>= NUM_GENREGS
&& regno
< gdbarch_num_regs (current_gdbarch
))
1768 return cris_special_register_name (regno
);
1772 /* Invalid register. */
1778 crisv32_register_name (int regno
)
1780 static char *crisv32_genreg_names
[] =
1781 { "r0", "r1", "r2", "r3", \
1782 "r4", "r5", "r6", "r7", \
1783 "r8", "r9", "r10", "r11", \
1784 "r12", "r13", "sp", "acr"
1787 static char *crisv32_sreg_names
[] =
1788 { "s0", "s1", "s2", "s3", \
1789 "s4", "s5", "s6", "s7", \
1790 "s8", "s9", "s10", "s11", \
1791 "s12", "s13", "s14", "s15"
1794 if (regno
>= 0 && regno
< NUM_GENREGS
)
1796 /* General register. */
1797 return crisv32_genreg_names
[regno
];
1799 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1801 return cris_special_register_name (regno
);
1803 else if (regno
== PC_REGNUM
)
1807 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1809 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1813 /* Invalid register. */
1818 /* Convert DWARF register number REG to the appropriate register
1819 number used by GDB. */
1822 cris_dwarf2_reg_to_regnum (int reg
)
1824 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1825 numbering, MOF is 18).
1826 Adapted from gcc/config/cris/cris.h. */
1827 static int cris_dwarf_regmap
[] = {
1839 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1840 regnum
= cris_dwarf_regmap
[reg
];
1843 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
1848 /* DWARF-2 frame support. */
1851 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1852 struct dwarf2_frame_state_reg
*reg
,
1853 struct frame_info
*next_frame
)
1855 /* The return address column. */
1856 if (regnum
== PC_REGNUM
)
1857 reg
->how
= DWARF2_FRAME_REG_RA
;
1859 /* The call frame address. */
1860 else if (regnum
== SP_REGNUM
)
1861 reg
->how
= DWARF2_FRAME_REG_CFA
;
1864 /* Extract from an array regbuf containing the raw register state a function
1865 return value of type type, and copy that, in virtual format, into
1868 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1871 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1875 int len
= TYPE_LENGTH (type
);
1879 /* Get the return value from R10. */
1880 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1881 store_unsigned_integer (valbuf
, len
, val
);
1885 /* Get the return value from R10 and R11. */
1886 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1887 store_unsigned_integer (valbuf
, 4, val
);
1888 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1889 store_unsigned_integer ((char *)valbuf
+ 4, len
- 4, val
);
1892 error (_("cris_extract_return_value: type length too large"));
1895 /* Handle the CRIS return value convention. */
1897 static enum return_value_convention
1898 cris_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1899 struct regcache
*regcache
, gdb_byte
*readbuf
,
1900 const gdb_byte
*writebuf
)
1902 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1903 || TYPE_CODE (type
) == TYPE_CODE_UNION
1904 || TYPE_LENGTH (type
) > 8)
1905 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1906 goes on the stack. */
1907 return RETURN_VALUE_STRUCT_CONVENTION
;
1910 cris_extract_return_value (type
, regcache
, readbuf
);
1912 cris_store_return_value (type
, regcache
, writebuf
);
1914 return RETURN_VALUE_REGISTER_CONVENTION
;
1917 /* Returns 1 if the given type will be passed by pointer rather than
1920 /* In the CRIS ABI, arguments shorter than or equal to 64 bits are passed
1924 cris_reg_struct_has_addr (int gcc_p
, struct type
*type
)
1926 return (TYPE_LENGTH (type
) > 8);
1929 /* Calculates a value that measures how good inst_args constraints an
1930 instruction. It stems from cris_constraint, found in cris-dis.c. */
1933 constraint (unsigned int insn
, const signed char *inst_args
,
1934 inst_env_type
*inst_env
)
1939 const char *s
= inst_args
;
1945 if ((insn
& 0x30) == 0x30)
1950 /* A prefix operand. */
1951 if (inst_env
->prefix_found
)
1957 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1958 valid "push" size. In case of special register, it may be != 4. */
1959 if (inst_env
->prefix_found
)
1965 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1973 tmp
= (insn
>> 0xC) & 0xF;
1975 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1977 /* Since we match four bits, we will give a value of
1978 4 - 1 = 3 in a match. If there is a corresponding
1979 exact match of a special register in another pattern, it
1980 will get a value of 4, which will be higher. This should
1981 be correct in that an exact pattern would match better that
1983 Note that there is a reason for not returning zero; the
1984 pattern for "clear" is partly matched in the bit-pattern
1985 (the two lower bits must be zero), while the bit-pattern
1986 for a move from a special register is matched in the
1987 register constraint.
1988 This also means we will will have a race condition if
1989 there is a partly match in three bits in the bit pattern. */
1990 if (tmp
== cris_spec_regs
[i
].number
)
1997 if (cris_spec_regs
[i
].name
== NULL
)
2004 /* Returns the number of bits set in the variable value. */
2007 number_of_bits (unsigned int value
)
2009 int number_of_bits
= 0;
2013 number_of_bits
+= 1;
2014 value
&= (value
- 1);
2016 return number_of_bits
;
2019 /* Finds the address that should contain the single step breakpoint(s).
2020 It stems from code in cris-dis.c. */
2023 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
2026 int max_level_of_match
= -1;
2027 int max_matched
= -1;
2030 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
2032 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
2033 && ((cris_opcodes
[i
].lose
& insn
) == 0)
2034 /* Only CRISv10 instructions, please. */
2035 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
2037 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
2038 if (level_of_match
>= 0)
2041 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
2042 if (level_of_match
> max_level_of_match
)
2045 max_level_of_match
= level_of_match
;
2046 if (level_of_match
== 16)
2048 /* All bits matched, cannot find better. */
2058 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
2059 actually an internal error. */
2062 find_step_target (struct frame_info
*frame
, inst_env_type
*inst_env
)
2066 unsigned short insn
;
2068 /* Create a local register image and set the initial state. */
2069 for (i
= 0; i
< NUM_GENREGS
; i
++)
2072 (unsigned long) get_frame_register_unsigned (frame
, i
);
2074 offset
= NUM_GENREGS
;
2075 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2078 (unsigned long) get_frame_register_unsigned (frame
, offset
+ i
);
2080 inst_env
->branch_found
= 0;
2081 inst_env
->slot_needed
= 0;
2082 inst_env
->delay_slot_pc_active
= 0;
2083 inst_env
->prefix_found
= 0;
2084 inst_env
->invalid
= 0;
2085 inst_env
->xflag_found
= 0;
2086 inst_env
->disable_interrupt
= 0;
2088 /* Look for a step target. */
2091 /* Read an instruction from the client. */
2092 insn
= read_memory_unsigned_integer (inst_env
->reg
[PC_REGNUM
], 2);
2094 /* If the instruction is not in a delay slot the new content of the
2095 PC is [PC] + 2. If the instruction is in a delay slot it is not
2096 that simple. Since a instruction in a delay slot cannot change
2097 the content of the PC, it does not matter what value PC will have.
2098 Just make sure it is a valid instruction. */
2099 if (!inst_env
->delay_slot_pc_active
)
2101 inst_env
->reg
[PC_REGNUM
] += 2;
2105 inst_env
->delay_slot_pc_active
= 0;
2106 inst_env
->reg
[PC_REGNUM
] = inst_env
->delay_slot_pc
;
2108 /* Analyse the present instruction. */
2109 i
= find_cris_op (insn
, inst_env
);
2112 inst_env
->invalid
= 1;
2116 cris_gdb_func (cris_opcodes
[i
].op
, insn
, inst_env
);
2118 } while (!inst_env
->invalid
2119 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2120 || inst_env
->slot_needed
));
2124 /* There is no hardware single-step support. The function find_step_target
2125 digs through the opcodes in order to find all possible targets.
2126 Either one ordinary target or two targets for branches may be found. */
2129 cris_software_single_step (struct frame_info
*frame
)
2131 inst_env_type inst_env
;
2133 /* Analyse the present instruction environment and insert
2135 int status
= find_step_target (frame
, &inst_env
);
2138 /* Could not find a target. Things are likely to go downhill
2140 warning (_("CRIS software single step could not find a step target."));
2144 /* Insert at most two breakpoints. One for the next PC content
2145 and possibly another one for a branch, jump, etc. */
2146 CORE_ADDR next_pc
= (CORE_ADDR
) inst_env
.reg
[PC_REGNUM
];
2147 insert_single_step_breakpoint (next_pc
);
2148 if (inst_env
.branch_found
2149 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2151 CORE_ADDR branch_target_address
2152 = (CORE_ADDR
) inst_env
.branch_break_address
;
2153 insert_single_step_breakpoint (branch_target_address
);
2160 /* Calculates the prefix value for quick offset addressing mode. */
2163 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2165 /* It's invalid to be in a delay slot. You can't have a prefix to this
2166 instruction (not 100% sure). */
2167 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2169 inst_env
->invalid
= 1;
2173 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2174 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2176 /* A prefix doesn't change the xflag_found. But the rest of the flags
2178 inst_env
->slot_needed
= 0;
2179 inst_env
->prefix_found
= 1;
2182 /* Updates the autoincrement register. The size of the increment is derived
2183 from the size of the operation. The PC is always kept aligned on even
2187 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2189 if (size
== INST_BYTE_SIZE
)
2191 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2193 /* The PC must be word aligned, so increase the PC with one
2194 word even if the size is byte. */
2195 if (cris_get_operand1 (inst
) == REG_PC
)
2197 inst_env
->reg
[REG_PC
] += 1;
2200 else if (size
== INST_WORD_SIZE
)
2202 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2204 else if (size
== INST_DWORD_SIZE
)
2206 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2211 inst_env
->invalid
= 1;
2215 /* Just a forward declaration. */
2217 static unsigned long get_data_from_address (unsigned short *inst
,
2220 /* Calculates the prefix value for the general case of offset addressing
2224 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2229 /* It's invalid to be in a delay slot. */
2230 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2232 inst_env
->invalid
= 1;
2236 /* The calculation of prefix_value used to be after process_autoincrement,
2237 but that fails for an instruction such as jsr [$r0+12] which is encoded
2238 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2239 mustn't be incremented until we have read it and what it points at. */
2240 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2242 /* The offset is an indirection of the contents of the operand1 register. */
2243 inst_env
->prefix_value
+=
2244 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)]);
2246 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2248 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2251 /* A prefix doesn't change the xflag_found. But the rest of the flags
2253 inst_env
->slot_needed
= 0;
2254 inst_env
->prefix_found
= 1;
2257 /* Calculates the prefix value for the index addressing mode. */
2260 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2262 /* It's invalid to be in a delay slot. I can't see that it's possible to
2263 have a prefix to this instruction. So I will treat this as invalid. */
2264 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2266 inst_env
->invalid
= 1;
2270 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2272 /* The offset is the operand2 value shifted the size of the instruction
2274 inst_env
->prefix_value
+=
2275 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2277 /* If the PC is operand1 (base) the address used is the address after
2278 the main instruction, i.e. address + 2 (the PC is already compensated
2279 for the prefix operation). */
2280 if (cris_get_operand1 (inst
) == REG_PC
)
2282 inst_env
->prefix_value
+= 2;
2285 /* A prefix doesn't change the xflag_found. But the rest of the flags
2287 inst_env
->slot_needed
= 0;
2288 inst_env
->xflag_found
= 0;
2289 inst_env
->prefix_found
= 1;
2292 /* Calculates the prefix value for the double indirect addressing mode. */
2295 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2300 /* It's invalid to be in a delay slot. */
2301 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2303 inst_env
->invalid
= 1;
2307 /* The prefix value is one dereference of the contents of the operand1
2309 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2310 inst_env
->prefix_value
= read_memory_unsigned_integer (address
, 4);
2312 /* Check if the mode is autoincrement. */
2313 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2315 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2318 /* A prefix doesn't change the xflag_found. But the rest of the flags
2320 inst_env
->slot_needed
= 0;
2321 inst_env
->xflag_found
= 0;
2322 inst_env
->prefix_found
= 1;
2325 /* Finds the destination for a branch with 8-bits offset. */
2328 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2333 /* If we have a prefix or are in a delay slot it's bad. */
2334 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2336 inst_env
->invalid
= 1;
2340 /* We have a branch, find out where the branch will land. */
2341 offset
= cris_get_branch_short_offset (inst
);
2343 /* Check if the offset is signed. */
2344 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2349 /* The offset ends with the sign bit, set it to zero. The address
2350 should always be word aligned. */
2351 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2353 inst_env
->branch_found
= 1;
2354 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2356 inst_env
->slot_needed
= 1;
2357 inst_env
->prefix_found
= 0;
2358 inst_env
->xflag_found
= 0;
2359 inst_env
->disable_interrupt
= 1;
2362 /* Finds the destination for a branch with 16-bits offset. */
2365 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2369 /* If we have a prefix or is in a delay slot it's bad. */
2370 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2372 inst_env
->invalid
= 1;
2376 /* We have a branch, find out the offset for the branch. */
2377 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2);
2379 /* The instruction is one word longer than normal, so add one word
2381 inst_env
->reg
[REG_PC
] += 2;
2383 inst_env
->branch_found
= 1;
2384 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2387 inst_env
->slot_needed
= 1;
2388 inst_env
->prefix_found
= 0;
2389 inst_env
->xflag_found
= 0;
2390 inst_env
->disable_interrupt
= 1;
2393 /* Handles the ABS instruction. */
2396 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2401 /* ABS can't have a prefix, so it's bad if it does. */
2402 if (inst_env
->prefix_found
)
2404 inst_env
->invalid
= 1;
2408 /* Check if the operation affects the PC. */
2409 if (cris_get_operand2 (inst
) == REG_PC
)
2412 /* It's invalid to change to the PC if we are in a delay slot. */
2413 if (inst_env
->slot_needed
)
2415 inst_env
->invalid
= 1;
2419 value
= (long) inst_env
->reg
[REG_PC
];
2421 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2422 if (value
!= SIGNED_DWORD_MASK
)
2425 inst_env
->reg
[REG_PC
] = (long) value
;
2429 inst_env
->slot_needed
= 0;
2430 inst_env
->prefix_found
= 0;
2431 inst_env
->xflag_found
= 0;
2432 inst_env
->disable_interrupt
= 0;
2435 /* Handles the ADDI instruction. */
2438 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2440 /* It's invalid to have the PC as base register. And ADDI can't have
2442 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2444 inst_env
->invalid
= 1;
2448 inst_env
->slot_needed
= 0;
2449 inst_env
->prefix_found
= 0;
2450 inst_env
->xflag_found
= 0;
2451 inst_env
->disable_interrupt
= 0;
2454 /* Handles the ASR instruction. */
2457 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2460 unsigned long value
;
2461 unsigned long signed_extend_mask
= 0;
2463 /* ASR can't have a prefix, so check that it doesn't. */
2464 if (inst_env
->prefix_found
)
2466 inst_env
->invalid
= 1;
2470 /* Check if the PC is the target register. */
2471 if (cris_get_operand2 (inst
) == REG_PC
)
2473 /* It's invalid to change the PC in a delay slot. */
2474 if (inst_env
->slot_needed
)
2476 inst_env
->invalid
= 1;
2479 /* Get the number of bits to shift. */
2480 shift_steps
= cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2481 value
= inst_env
->reg
[REG_PC
];
2483 /* Find out how many bits the operation should apply to. */
2484 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2486 if (value
& SIGNED_BYTE_MASK
)
2488 signed_extend_mask
= 0xFF;
2489 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2490 signed_extend_mask
= ~signed_extend_mask
;
2492 value
= value
>> shift_steps
;
2493 value
|= signed_extend_mask
;
2495 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2496 inst_env
->reg
[REG_PC
] |= value
;
2498 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2500 if (value
& SIGNED_WORD_MASK
)
2502 signed_extend_mask
= 0xFFFF;
2503 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2504 signed_extend_mask
= ~signed_extend_mask
;
2506 value
= value
>> shift_steps
;
2507 value
|= signed_extend_mask
;
2509 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2510 inst_env
->reg
[REG_PC
] |= value
;
2512 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2514 if (value
& SIGNED_DWORD_MASK
)
2516 signed_extend_mask
= 0xFFFFFFFF;
2517 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2518 signed_extend_mask
= ~signed_extend_mask
;
2520 value
= value
>> shift_steps
;
2521 value
|= signed_extend_mask
;
2522 inst_env
->reg
[REG_PC
] = value
;
2525 inst_env
->slot_needed
= 0;
2526 inst_env
->prefix_found
= 0;
2527 inst_env
->xflag_found
= 0;
2528 inst_env
->disable_interrupt
= 0;
2531 /* Handles the ASRQ instruction. */
2534 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2538 unsigned long value
;
2539 unsigned long signed_extend_mask
= 0;
2541 /* ASRQ can't have a prefix, so check that it doesn't. */
2542 if (inst_env
->prefix_found
)
2544 inst_env
->invalid
= 1;
2548 /* Check if the PC is the target register. */
2549 if (cris_get_operand2 (inst
) == REG_PC
)
2552 /* It's invalid to change the PC in a delay slot. */
2553 if (inst_env
->slot_needed
)
2555 inst_env
->invalid
= 1;
2558 /* The shift size is given as a 5 bit quick value, i.e. we don't
2559 want the the sign bit of the quick value. */
2560 shift_steps
= cris_get_asr_shift_steps (inst
);
2561 value
= inst_env
->reg
[REG_PC
];
2562 if (value
& SIGNED_DWORD_MASK
)
2564 signed_extend_mask
= 0xFFFFFFFF;
2565 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2566 signed_extend_mask
= ~signed_extend_mask
;
2568 value
= value
>> shift_steps
;
2569 value
|= signed_extend_mask
;
2570 inst_env
->reg
[REG_PC
] = value
;
2572 inst_env
->slot_needed
= 0;
2573 inst_env
->prefix_found
= 0;
2574 inst_env
->xflag_found
= 0;
2575 inst_env
->disable_interrupt
= 0;
2578 /* Handles the AX, EI and SETF instruction. */
2581 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2583 if (inst_env
->prefix_found
)
2585 inst_env
->invalid
= 1;
2588 /* Check if the instruction is setting the X flag. */
2589 if (cris_is_xflag_bit_on (inst
))
2591 inst_env
->xflag_found
= 1;
2595 inst_env
->xflag_found
= 0;
2597 inst_env
->slot_needed
= 0;
2598 inst_env
->prefix_found
= 0;
2599 inst_env
->disable_interrupt
= 1;
2602 /* Checks if the instruction is in assign mode. If so, it updates the assign
2603 register. Note that check_assign assumes that the caller has checked that
2604 there is a prefix to this instruction. The mode check depends on this. */
2607 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2609 /* Check if it's an assign addressing mode. */
2610 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2612 /* Assign the prefix value to operand 1. */
2613 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2617 /* Handles the 2-operand BOUND instruction. */
2620 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2622 /* It's invalid to have the PC as the index operand. */
2623 if (cris_get_operand2 (inst
) == REG_PC
)
2625 inst_env
->invalid
= 1;
2628 /* Check if we have a prefix. */
2629 if (inst_env
->prefix_found
)
2631 check_assign (inst
, inst_env
);
2633 /* Check if this is an autoincrement mode. */
2634 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2636 /* It's invalid to change the PC in a delay slot. */
2637 if (inst_env
->slot_needed
)
2639 inst_env
->invalid
= 1;
2642 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2644 inst_env
->slot_needed
= 0;
2645 inst_env
->prefix_found
= 0;
2646 inst_env
->xflag_found
= 0;
2647 inst_env
->disable_interrupt
= 0;
2650 /* Handles the 3-operand BOUND instruction. */
2653 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2655 /* It's an error if we haven't got a prefix. And it's also an error
2656 if the PC is the destination register. */
2657 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2659 inst_env
->invalid
= 1;
2662 inst_env
->slot_needed
= 0;
2663 inst_env
->prefix_found
= 0;
2664 inst_env
->xflag_found
= 0;
2665 inst_env
->disable_interrupt
= 0;
2668 /* Clears the status flags in inst_env. */
2671 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2673 /* It's an error if we have got a prefix. */
2674 if (inst_env
->prefix_found
)
2676 inst_env
->invalid
= 1;
2680 inst_env
->slot_needed
= 0;
2681 inst_env
->prefix_found
= 0;
2682 inst_env
->xflag_found
= 0;
2683 inst_env
->disable_interrupt
= 0;
2686 /* Clears the status flags in inst_env. */
2689 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2691 /* It's an error if we have got a prefix. */
2692 if (inst_env
->prefix_found
)
2694 inst_env
->invalid
= 1;
2698 inst_env
->slot_needed
= 0;
2699 inst_env
->prefix_found
= 0;
2700 inst_env
->xflag_found
= 0;
2701 inst_env
->disable_interrupt
= 1;
2704 /* Handles the CLEAR instruction if it's in register mode. */
2707 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2709 /* Check if the target is the PC. */
2710 if (cris_get_operand2 (inst
) == REG_PC
)
2712 /* The instruction will clear the instruction's size bits. */
2713 int clear_size
= cris_get_clear_size (inst
);
2714 if (clear_size
== INST_BYTE_SIZE
)
2716 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2718 if (clear_size
== INST_WORD_SIZE
)
2720 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2722 if (clear_size
== INST_DWORD_SIZE
)
2724 inst_env
->delay_slot_pc
= 0x0;
2726 /* The jump will be delayed with one delay slot. So we need a delay
2728 inst_env
->slot_needed
= 1;
2729 inst_env
->delay_slot_pc_active
= 1;
2733 /* The PC will not change => no delay slot. */
2734 inst_env
->slot_needed
= 0;
2736 inst_env
->prefix_found
= 0;
2737 inst_env
->xflag_found
= 0;
2738 inst_env
->disable_interrupt
= 0;
2741 /* Handles the TEST instruction if it's in register mode. */
2744 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2746 /* It's an error if we have got a prefix. */
2747 if (inst_env
->prefix_found
)
2749 inst_env
->invalid
= 1;
2752 inst_env
->slot_needed
= 0;
2753 inst_env
->prefix_found
= 0;
2754 inst_env
->xflag_found
= 0;
2755 inst_env
->disable_interrupt
= 0;
2759 /* Handles the CLEAR and TEST instruction if the instruction isn't
2760 in register mode. */
2763 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2765 /* Check if we are in a prefix mode. */
2766 if (inst_env
->prefix_found
)
2768 /* The only way the PC can change is if this instruction is in
2769 assign addressing mode. */
2770 check_assign (inst
, inst_env
);
2772 /* Indirect mode can't change the PC so just check if the mode is
2774 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2776 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2778 inst_env
->slot_needed
= 0;
2779 inst_env
->prefix_found
= 0;
2780 inst_env
->xflag_found
= 0;
2781 inst_env
->disable_interrupt
= 0;
2784 /* Checks that the PC isn't the destination register or the instructions has
2788 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2790 /* It's invalid to have the PC as the destination. The instruction can't
2792 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2794 inst_env
->invalid
= 1;
2798 inst_env
->slot_needed
= 0;
2799 inst_env
->prefix_found
= 0;
2800 inst_env
->xflag_found
= 0;
2801 inst_env
->disable_interrupt
= 0;
2804 /* Checks that the instruction doesn't have a prefix. */
2807 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2809 /* The instruction can't have a prefix. */
2810 if (inst_env
->prefix_found
)
2812 inst_env
->invalid
= 1;
2816 inst_env
->slot_needed
= 0;
2817 inst_env
->prefix_found
= 0;
2818 inst_env
->xflag_found
= 0;
2819 inst_env
->disable_interrupt
= 1;
2822 /* Checks that the PC isn't the destination register and that the instruction
2823 doesn't have a prefix. */
2826 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2828 /* It's invalid to have the PC as the destination. The instruction can't
2830 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2832 inst_env
->invalid
= 1;
2836 inst_env
->slot_needed
= 0;
2837 inst_env
->prefix_found
= 0;
2838 inst_env
->xflag_found
= 0;
2839 inst_env
->disable_interrupt
= 1;
2842 /* Handles the register mode JUMP instruction. */
2845 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2847 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2848 you can't have a prefix. */
2849 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2851 inst_env
->invalid
= 1;
2855 /* Just change the PC. */
2856 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2857 inst_env
->slot_needed
= 0;
2858 inst_env
->prefix_found
= 0;
2859 inst_env
->xflag_found
= 0;
2860 inst_env
->disable_interrupt
= 1;
2863 /* Handles the JUMP instruction for all modes except register. */
2866 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2868 unsigned long newpc
;
2871 /* It's invalid to do a JUMP in a delay slot. */
2872 if (inst_env
->slot_needed
)
2874 inst_env
->invalid
= 1;
2878 /* Check if we have a prefix. */
2879 if (inst_env
->prefix_found
)
2881 check_assign (inst
, inst_env
);
2883 /* Get the new value for the the PC. */
2885 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2890 /* Get the new value for the PC. */
2891 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2892 newpc
= read_memory_unsigned_integer (address
, 4);
2894 /* Check if we should increment a register. */
2895 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2897 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2900 inst_env
->reg
[REG_PC
] = newpc
;
2902 inst_env
->slot_needed
= 0;
2903 inst_env
->prefix_found
= 0;
2904 inst_env
->xflag_found
= 0;
2905 inst_env
->disable_interrupt
= 1;
2908 /* Handles moves to special registers (aka P-register) for all modes. */
2911 move_to_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2913 if (inst_env
->prefix_found
)
2915 /* The instruction has a prefix that means we are only interested if
2916 the instruction is in assign mode. */
2917 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2919 /* The prefix handles the problem if we are in a delay slot. */
2920 if (cris_get_operand1 (inst
) == REG_PC
)
2922 /* Just take care of the assign. */
2923 check_assign (inst
, inst_env
);
2927 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2929 /* The instruction doesn't have a prefix, the only case left that we
2930 are interested in is the autoincrement mode. */
2931 if (cris_get_operand1 (inst
) == REG_PC
)
2933 /* If the PC is to be incremented it's invalid to be in a
2935 if (inst_env
->slot_needed
)
2937 inst_env
->invalid
= 1;
2941 /* The increment depends on the size of the special register. */
2942 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2944 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2946 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
2948 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2952 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2956 inst_env
->slot_needed
= 0;
2957 inst_env
->prefix_found
= 0;
2958 inst_env
->xflag_found
= 0;
2959 inst_env
->disable_interrupt
= 1;
2962 /* Handles moves from special registers (aka P-register) for all modes
2966 none_reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2968 if (inst_env
->prefix_found
)
2970 /* The instruction has a prefix that means we are only interested if
2971 the instruction is in assign mode. */
2972 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2974 /* The prefix handles the problem if we are in a delay slot. */
2975 if (cris_get_operand1 (inst
) == REG_PC
)
2977 /* Just take care of the assign. */
2978 check_assign (inst
, inst_env
);
2982 /* The instruction doesn't have a prefix, the only case left that we
2983 are interested in is the autoincrement mode. */
2984 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2986 if (cris_get_operand1 (inst
) == REG_PC
)
2988 /* If the PC is to be incremented it's invalid to be in a
2990 if (inst_env
->slot_needed
)
2992 inst_env
->invalid
= 1;
2996 /* The increment depends on the size of the special register. */
2997 if (cris_register_size (cris_get_operand2 (inst
)) == 1)
2999 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
3001 else if (cris_register_size (cris_get_operand2 (inst
)) == 2)
3003 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
3007 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
3011 inst_env
->slot_needed
= 0;
3012 inst_env
->prefix_found
= 0;
3013 inst_env
->xflag_found
= 0;
3014 inst_env
->disable_interrupt
= 1;
3017 /* Handles moves from special registers (aka P-register) when the mode
3021 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
3023 /* Register mode move from special register can't have a prefix. */
3024 if (inst_env
->prefix_found
)
3026 inst_env
->invalid
= 1;
3030 if (cris_get_operand1 (inst
) == REG_PC
)
3032 /* It's invalid to change the PC in a delay slot. */
3033 if (inst_env
->slot_needed
)
3035 inst_env
->invalid
= 1;
3038 /* The destination is the PC, the jump will have a delay slot. */
3039 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
3040 inst_env
->slot_needed
= 1;
3041 inst_env
->delay_slot_pc_active
= 1;
3045 /* If the destination isn't PC, there will be no jump. */
3046 inst_env
->slot_needed
= 0;
3048 inst_env
->prefix_found
= 0;
3049 inst_env
->xflag_found
= 0;
3050 inst_env
->disable_interrupt
= 1;
3053 /* Handles the MOVEM from memory to general register instruction. */
3056 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3058 if (inst_env
->prefix_found
)
3060 /* The prefix handles the problem if we are in a delay slot. Is the
3061 MOVEM instruction going to change the PC? */
3062 if (cris_get_operand2 (inst
) >= REG_PC
)
3064 inst_env
->reg
[REG_PC
] =
3065 read_memory_unsigned_integer (inst_env
->prefix_value
, 4);
3067 /* The assign value is the value after the increment. Normally, the
3068 assign value is the value before the increment. */
3069 if ((cris_get_operand1 (inst
) == REG_PC
)
3070 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3072 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3073 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3078 /* Is the MOVEM instruction going to change the PC? */
3079 if (cris_get_operand2 (inst
) == REG_PC
)
3081 /* It's invalid to change the PC in a delay slot. */
3082 if (inst_env
->slot_needed
)
3084 inst_env
->invalid
= 1;
3087 inst_env
->reg
[REG_PC
] =
3088 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3091 /* The increment is not depending on the size, instead it's depending
3092 on the number of registers loaded from memory. */
3093 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3095 /* It's invalid to change the PC in a delay slot. */
3096 if (inst_env
->slot_needed
)
3098 inst_env
->invalid
= 1;
3101 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3104 inst_env
->slot_needed
= 0;
3105 inst_env
->prefix_found
= 0;
3106 inst_env
->xflag_found
= 0;
3107 inst_env
->disable_interrupt
= 0;
3110 /* Handles the MOVEM to memory from general register instruction. */
3113 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3115 if (inst_env
->prefix_found
)
3117 /* The assign value is the value after the increment. Normally, the
3118 assign value is the value before the increment. */
3119 if ((cris_get_operand1 (inst
) == REG_PC
) &&
3120 (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3122 /* The prefix handles the problem if we are in a delay slot. */
3123 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3124 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3129 /* The increment is not depending on the size, instead it's depending
3130 on the number of registers loaded to memory. */
3131 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3133 /* It's invalid to change the PC in a delay slot. */
3134 if (inst_env
->slot_needed
)
3136 inst_env
->invalid
= 1;
3139 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3142 inst_env
->slot_needed
= 0;
3143 inst_env
->prefix_found
= 0;
3144 inst_env
->xflag_found
= 0;
3145 inst_env
->disable_interrupt
= 0;
3148 /* Handles the intructions that's not yet implemented, by setting
3149 inst_env->invalid to true. */
3152 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3154 inst_env
->invalid
= 1;
3157 /* Handles the XOR instruction. */
3160 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3162 /* XOR can't have a prefix. */
3163 if (inst_env
->prefix_found
)
3165 inst_env
->invalid
= 1;
3169 /* Check if the PC is the target. */
3170 if (cris_get_operand2 (inst
) == REG_PC
)
3172 /* It's invalid to change the PC in a delay slot. */
3173 if (inst_env
->slot_needed
)
3175 inst_env
->invalid
= 1;
3178 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3180 inst_env
->slot_needed
= 0;
3181 inst_env
->prefix_found
= 0;
3182 inst_env
->xflag_found
= 0;
3183 inst_env
->disable_interrupt
= 0;
3186 /* Handles the MULS instruction. */
3189 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3191 /* MULS/U can't have a prefix. */
3192 if (inst_env
->prefix_found
)
3194 inst_env
->invalid
= 1;
3198 /* Consider it invalid if the PC is the target. */
3199 if (cris_get_operand2 (inst
) == REG_PC
)
3201 inst_env
->invalid
= 1;
3204 inst_env
->slot_needed
= 0;
3205 inst_env
->prefix_found
= 0;
3206 inst_env
->xflag_found
= 0;
3207 inst_env
->disable_interrupt
= 0;
3210 /* Handles the MULU instruction. */
3213 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3215 /* MULS/U can't have a prefix. */
3216 if (inst_env
->prefix_found
)
3218 inst_env
->invalid
= 1;
3222 /* Consider it invalid if the PC is the target. */
3223 if (cris_get_operand2 (inst
) == REG_PC
)
3225 inst_env
->invalid
= 1;
3228 inst_env
->slot_needed
= 0;
3229 inst_env
->prefix_found
= 0;
3230 inst_env
->xflag_found
= 0;
3231 inst_env
->disable_interrupt
= 0;
3234 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3235 The MOVE instruction is the move from source to register. */
3238 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3239 unsigned long source1
, unsigned long source2
)
3241 unsigned long pc_mask
;
3242 unsigned long operation_mask
;
3244 /* Find out how many bits the operation should apply to. */
3245 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3247 pc_mask
= 0xFFFFFF00;
3248 operation_mask
= 0xFF;
3250 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3252 pc_mask
= 0xFFFF0000;
3253 operation_mask
= 0xFFFF;
3255 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3258 operation_mask
= 0xFFFFFFFF;
3262 /* The size is out of range. */
3263 inst_env
->invalid
= 1;
3267 /* The instruction just works on uw_operation_mask bits. */
3268 source2
&= operation_mask
;
3269 source1
&= operation_mask
;
3271 /* Now calculate the result. The opcode's 3 first bits separates
3272 the different actions. */
3273 switch (cris_get_opcode (inst
) & 7)
3283 case 2: /* subtract */
3287 case 3: /* compare */
3299 inst_env
->invalid
= 1;
3305 /* Make sure that the result doesn't contain more than the instruction
3307 source2
&= operation_mask
;
3309 /* Calculate the new breakpoint address. */
3310 inst_env
->reg
[REG_PC
] &= pc_mask
;
3311 inst_env
->reg
[REG_PC
] |= source1
;
3315 /* Extends the value from either byte or word size to a dword. If the mode
3316 is zero extend then the value is extended with zero. If instead the mode
3317 is signed extend the sign bit of the value is taken into consideration. */
3319 static unsigned long
3320 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3322 /* The size can be either byte or word, check which one it is.
3323 Don't check the highest bit, it's indicating if it's a zero
3325 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3330 /* Check if the instruction is signed extend. If so, check if value has
3332 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3334 value
|= SIGNED_WORD_EXTEND_MASK
;
3342 /* Check if the instruction is signed extend. If so, check if value has
3344 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3346 value
|= SIGNED_BYTE_EXTEND_MASK
;
3349 /* The size should now be dword. */
3350 cris_set_size_to_dword (inst
);
3354 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3355 instruction. The MOVE instruction is the move from source to register. */
3358 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3359 inst_env_type
*inst_env
)
3361 unsigned long operand1
;
3362 unsigned long operand2
;
3364 /* It's invalid to have a prefix to the instruction. This is a register
3365 mode instruction and can't have a prefix. */
3366 if (inst_env
->prefix_found
)
3368 inst_env
->invalid
= 1;
3371 /* Check if the instruction has PC as its target. */
3372 if (cris_get_operand2 (inst
) == REG_PC
)
3374 if (inst_env
->slot_needed
)
3376 inst_env
->invalid
= 1;
3379 /* The instruction has the PC as its target register. */
3380 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3381 operand2
= inst_env
->reg
[REG_PC
];
3383 /* Check if it's a extend, signed or zero instruction. */
3384 if (cris_get_opcode (inst
) < 4)
3386 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3388 /* Calculate the PC value after the instruction, i.e. where the
3389 breakpoint should be. The order of the udw_operands is vital. */
3390 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3392 inst_env
->slot_needed
= 0;
3393 inst_env
->prefix_found
= 0;
3394 inst_env
->xflag_found
= 0;
3395 inst_env
->disable_interrupt
= 0;
3398 /* Returns the data contained at address. The size of the data is derived from
3399 the size of the operation. If the instruction is a zero or signed
3400 extend instruction, the size field is changed in instruction. */
3402 static unsigned long
3403 get_data_from_address (unsigned short *inst
, CORE_ADDR address
)
3405 int size
= cris_get_size (*inst
);
3406 unsigned long value
;
3408 /* If it's an extend instruction we don't want the signed extend bit,
3409 because it influences the size. */
3410 if (cris_get_opcode (*inst
) < 4)
3412 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3414 /* Is there a need for checking the size? Size should contain the number of
3417 value
= read_memory_unsigned_integer (address
, size
);
3419 /* Check if it's an extend, signed or zero instruction. */
3420 if (cris_get_opcode (*inst
) < 4)
3422 value
= do_sign_or_zero_extend (value
, inst
);
3427 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3428 instructions. The MOVE instruction is the move from source to register. */
3431 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3432 inst_env_type
*inst_env
)
3434 unsigned long operand2
;
3435 unsigned long operand3
;
3437 check_assign (inst
, inst_env
);
3438 if (cris_get_operand2 (inst
) == REG_PC
)
3440 operand2
= inst_env
->reg
[REG_PC
];
3442 /* Get the value of the third operand. */
3443 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3445 /* Calculate the PC value after the instruction, i.e. where the
3446 breakpoint should be. The order of the udw_operands is vital. */
3447 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3449 inst_env
->slot_needed
= 0;
3450 inst_env
->prefix_found
= 0;
3451 inst_env
->xflag_found
= 0;
3452 inst_env
->disable_interrupt
= 0;
3455 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3456 OR instructions. Note that for this to work as expected, the calling
3457 function must have made sure that there is a prefix to this instruction. */
3460 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3461 inst_env_type
*inst_env
)
3463 unsigned long operand2
;
3464 unsigned long operand3
;
3466 if (cris_get_operand1 (inst
) == REG_PC
)
3468 /* The PC will be changed by the instruction. */
3469 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3471 /* Get the value of the third operand. */
3472 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
);
3474 /* Calculate the PC value after the instruction, i.e. where the
3475 breakpoint should be. */
3476 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3478 inst_env
->slot_needed
= 0;
3479 inst_env
->prefix_found
= 0;
3480 inst_env
->xflag_found
= 0;
3481 inst_env
->disable_interrupt
= 0;
3484 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3485 instructions. The MOVE instruction is the move from source to register. */
3488 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3489 inst_env_type
*inst_env
)
3491 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3493 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3494 SUB, AND or OR something weird is going on (if everything works these
3495 instructions should end up in the three operand version). */
3496 inst_env
->invalid
= 1;
3501 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3503 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3505 inst_env
->slot_needed
= 0;
3506 inst_env
->prefix_found
= 0;
3507 inst_env
->xflag_found
= 0;
3508 inst_env
->disable_interrupt
= 0;
3511 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3512 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3513 source to register. */
3516 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3517 inst_env_type
*inst_env
)
3519 unsigned long operand1
;
3520 unsigned long operand2
;
3521 unsigned long operand3
;
3524 /* The instruction is either an indirect or autoincrement addressing mode.
3525 Check if the destination register is the PC. */
3526 if (cris_get_operand2 (inst
) == REG_PC
)
3528 /* Must be done here, get_data_from_address may change the size
3530 size
= cris_get_size (inst
);
3531 operand2
= inst_env
->reg
[REG_PC
];
3533 /* Get the value of the third operand, i.e. the indirect operand. */
3534 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3535 operand3
= get_data_from_address (&inst
, operand1
);
3537 /* Calculate the PC value after the instruction, i.e. where the
3538 breakpoint should be. The order of the udw_operands is vital. */
3539 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3541 /* If this is an autoincrement addressing mode, check if the increment
3543 if ((cris_get_operand1 (inst
) == REG_PC
) && (cris_get_mode (inst
) == AUTOINC_MODE
))
3545 /* Get the size field. */
3546 size
= cris_get_size (inst
);
3548 /* If it's an extend instruction we don't want the signed extend bit,
3549 because it influences the size. */
3550 if (cris_get_opcode (inst
) < 4)
3552 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3554 process_autoincrement (size
, inst
, inst_env
);
3556 inst_env
->slot_needed
= 0;
3557 inst_env
->prefix_found
= 0;
3558 inst_env
->xflag_found
= 0;
3559 inst_env
->disable_interrupt
= 0;
3562 /* Handles the two-operand addressing mode, all modes except register, for
3563 the ADD, SUB CMP, AND and OR instruction. */
3566 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3567 inst_env_type
*inst_env
)
3569 if (inst_env
->prefix_found
)
3571 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3573 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3575 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3577 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3581 /* The mode is invalid for a prefixed base instruction. */
3582 inst_env
->invalid
= 1;
3588 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3592 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3595 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3597 unsigned long operand1
;
3598 unsigned long operand2
;
3600 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3601 instruction and can't have a prefix. */
3602 if (inst_env
->prefix_found
)
3604 inst_env
->invalid
= 1;
3608 /* Check if the instruction has PC as its target. */
3609 if (cris_get_operand2 (inst
) == REG_PC
)
3611 if (inst_env
->slot_needed
)
3613 inst_env
->invalid
= 1;
3616 operand1
= cris_get_quick_value (inst
);
3617 operand2
= inst_env
->reg
[REG_PC
];
3619 /* The size should now be dword. */
3620 cris_set_size_to_dword (&inst
);
3622 /* Calculate the PC value after the instruction, i.e. where the
3623 breakpoint should be. */
3624 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3626 inst_env
->slot_needed
= 0;
3627 inst_env
->prefix_found
= 0;
3628 inst_env
->xflag_found
= 0;
3629 inst_env
->disable_interrupt
= 0;
3632 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3635 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3637 unsigned long operand1
;
3638 unsigned long operand2
;
3640 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3641 instruction and can't have a prefix. */
3642 if (inst_env
->prefix_found
)
3644 inst_env
->invalid
= 1;
3647 /* Check if the instruction has PC as its target. */
3648 if (cris_get_operand2 (inst
) == REG_PC
)
3650 if (inst_env
->slot_needed
)
3652 inst_env
->invalid
= 1;
3655 /* The instruction has the PC as its target register. */
3656 operand1
= cris_get_quick_value (inst
);
3657 operand2
= inst_env
->reg
[REG_PC
];
3659 /* The quick value is signed, so check if we must do a signed extend. */
3660 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3663 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3665 /* The size should now be dword. */
3666 cris_set_size_to_dword (&inst
);
3668 /* Calculate the PC value after the instruction, i.e. where the
3669 breakpoint should be. */
3670 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3672 inst_env
->slot_needed
= 0;
3673 inst_env
->prefix_found
= 0;
3674 inst_env
->xflag_found
= 0;
3675 inst_env
->disable_interrupt
= 0;
3678 /* Translate op_type to a function and call it. */
3681 cris_gdb_func (enum cris_op_type op_type
, unsigned short inst
,
3682 inst_env_type
*inst_env
)
3686 case cris_not_implemented_op
:
3687 not_implemented_op (inst
, inst_env
);
3691 abs_op (inst
, inst_env
);
3695 addi_op (inst
, inst_env
);
3699 asr_op (inst
, inst_env
);
3703 asrq_op (inst
, inst_env
);
3706 case cris_ax_ei_setf_op
:
3707 ax_ei_setf_op (inst
, inst_env
);
3710 case cris_bdap_prefix
:
3711 bdap_prefix (inst
, inst_env
);
3714 case cris_biap_prefix
:
3715 biap_prefix (inst
, inst_env
);
3719 break_op (inst
, inst_env
);
3722 case cris_btst_nop_op
:
3723 btst_nop_op (inst
, inst_env
);
3726 case cris_clearf_di_op
:
3727 clearf_di_op (inst
, inst_env
);
3730 case cris_dip_prefix
:
3731 dip_prefix (inst
, inst_env
);
3734 case cris_dstep_logshift_mstep_neg_not_op
:
3735 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3738 case cris_eight_bit_offset_branch_op
:
3739 eight_bit_offset_branch_op (inst
, inst_env
);
3742 case cris_move_mem_to_reg_movem_op
:
3743 move_mem_to_reg_movem_op (inst
, inst_env
);
3746 case cris_move_reg_to_mem_movem_op
:
3747 move_reg_to_mem_movem_op (inst
, inst_env
);
3750 case cris_move_to_preg_op
:
3751 move_to_preg_op (inst
, inst_env
);
3755 muls_op (inst
, inst_env
);
3759 mulu_op (inst
, inst_env
);
3762 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3763 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3766 case cris_none_reg_mode_clear_test_op
:
3767 none_reg_mode_clear_test_op (inst
, inst_env
);
3770 case cris_none_reg_mode_jump_op
:
3771 none_reg_mode_jump_op (inst
, inst_env
);
3774 case cris_none_reg_mode_move_from_preg_op
:
3775 none_reg_mode_move_from_preg_op (inst
, inst_env
);
3778 case cris_quick_mode_add_sub_op
:
3779 quick_mode_add_sub_op (inst
, inst_env
);
3782 case cris_quick_mode_and_cmp_move_or_op
:
3783 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3786 case cris_quick_mode_bdap_prefix
:
3787 quick_mode_bdap_prefix (inst
, inst_env
);
3790 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3791 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3794 case cris_reg_mode_clear_op
:
3795 reg_mode_clear_op (inst
, inst_env
);
3798 case cris_reg_mode_jump_op
:
3799 reg_mode_jump_op (inst
, inst_env
);
3802 case cris_reg_mode_move_from_preg_op
:
3803 reg_mode_move_from_preg_op (inst
, inst_env
);
3806 case cris_reg_mode_test_op
:
3807 reg_mode_test_op (inst
, inst_env
);
3811 scc_op (inst
, inst_env
);
3814 case cris_sixteen_bit_offset_branch_op
:
3815 sixteen_bit_offset_branch_op (inst
, inst_env
);
3818 case cris_three_operand_add_sub_cmp_and_or_op
:
3819 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3822 case cris_three_operand_bound_op
:
3823 three_operand_bound_op (inst
, inst_env
);
3826 case cris_two_operand_bound_op
:
3827 two_operand_bound_op (inst
, inst_env
);
3831 xor_op (inst
, inst_env
);
3836 /* This wrapper is to avoid cris_get_assembler being called before
3837 exec_bfd has been set. */
3840 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3842 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3843 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3844 disassembler, even when there is no BFD. Does something like
3845 "gdb; target remote; disassmeble *0x123" work? */
3846 gdb_assert (exec_bfd
!= NULL
);
3847 print_insn
= cris_get_disassembler (exec_bfd
);
3848 gdb_assert (print_insn
!= NULL
);
3849 return print_insn (addr
, info
);
3852 /* Copied from <asm/elf.h>. */
3853 typedef unsigned long elf_greg_t
;
3855 /* Same as user_regs_struct struct in <asm/user.h>. */
3856 #define CRISV10_ELF_NGREG 35
3857 typedef elf_greg_t elf_gregset_t
[CRISV10_ELF_NGREG
];
3859 #define CRISV32_ELF_NGREG 32
3860 typedef elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3862 /* Unpack an elf_gregset_t into GDB's register cache. */
3865 cris_supply_gregset (struct regcache
*regcache
, elf_gregset_t
*gregsetp
)
3867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3869 elf_greg_t
*regp
= *gregsetp
;
3870 static char zerobuf
[4] = {0};
3872 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3873 knows about the actual size of each register so that's no problem. */
3874 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3876 regcache_raw_supply (regcache
, i
, (char *)®p
[i
]);
3879 if (tdep
->cris_version
== 32)
3881 /* Needed to set pseudo-register PC for CRISv32. */
3882 /* FIXME: If ERP is in a delay slot at this point then the PC will
3883 be wrong. Issue a warning to alert the user. */
3884 regcache_raw_supply (regcache
, PC_REGNUM
,
3885 (char *)®p
[ERP_REGNUM
]);
3887 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3888 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3892 /* Use a local version of this function to get the correct types for
3893 regsets, until multi-arch core support is ready. */
3896 fetch_core_registers (struct regcache
*regcache
,
3897 char *core_reg_sect
, unsigned core_reg_size
,
3898 int which
, CORE_ADDR reg_addr
)
3900 elf_gregset_t gregset
;
3905 if (core_reg_size
!= sizeof (elf_gregset_t
)
3906 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3908 warning (_("wrong size gregset struct in core file"));
3912 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3913 cris_supply_gregset (regcache
, &gregset
);
3917 /* We've covered all the kinds of registers we know about here,
3918 so this must be something we wouldn't know what to do with
3919 anyway. Just ignore it. */
3924 static struct core_fns cris_elf_core_fns
=
3926 bfd_target_elf_flavour
, /* core_flavour */
3927 default_check_format
, /* check_format */
3928 default_core_sniffer
, /* core_sniffer */
3929 fetch_core_registers
, /* core_read_registers */
3933 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3936 _initialize_cris_tdep (void)
3938 static struct cmd_list_element
*cris_set_cmdlist
;
3939 static struct cmd_list_element
*cris_show_cmdlist
;
3941 struct cmd_list_element
*c
;
3943 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3945 /* CRIS-specific user-commands. */
3946 add_setshow_uinteger_cmd ("cris-version", class_support
,
3947 &usr_cmd_cris_version
,
3948 _("Set the current CRIS version."),
3949 _("Show the current CRIS version."),
3951 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3954 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3955 &setlist
, &showlist
);
3957 add_setshow_enum_cmd ("cris-mode", class_support
,
3958 cris_modes
, &usr_cmd_cris_mode
,
3959 _("Set the current CRIS mode."),
3960 _("Show the current CRIS mode."),
3962 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3963 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3965 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3966 &setlist
, &showlist
);
3968 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3969 &usr_cmd_cris_dwarf2_cfi
,
3970 _("Set the usage of Dwarf-2 CFI for CRIS."),
3971 _("Show the usage of Dwarf-2 CFI for CRIS."),
3972 _("Set this to \"off\" if using gcc-cris < R59."),
3973 set_cris_dwarf2_cfi
,
3974 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI for CRIS is %d. */
3975 &setlist
, &showlist
);
3977 deprecated_add_core_fns (&cris_elf_core_fns
);
3980 /* Prints out all target specific values. */
3983 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3985 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3988 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3989 tdep
->cris_version
);
3990 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
3992 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3993 tdep
->cris_dwarf2_cfi
);
3998 set_cris_version (char *ignore_args
, int from_tty
,
3999 struct cmd_list_element
*c
)
4001 struct gdbarch_info info
;
4003 usr_cmd_cris_version_valid
= 1;
4005 /* Update the current architecture, if needed. */
4006 gdbarch_info_init (&info
);
4007 if (!gdbarch_update_p (info
))
4008 internal_error (__FILE__
, __LINE__
,
4009 _("cris_gdbarch_update: failed to update architecture."));
4013 set_cris_mode (char *ignore_args
, int from_tty
,
4014 struct cmd_list_element
*c
)
4016 struct gdbarch_info info
;
4018 /* Update the current architecture, if needed. */
4019 gdbarch_info_init (&info
);
4020 if (!gdbarch_update_p (info
))
4021 internal_error (__FILE__
, __LINE__
,
4022 "cris_gdbarch_update: failed to update architecture.");
4026 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
4027 struct cmd_list_element
*c
)
4029 struct gdbarch_info info
;
4031 /* Update the current architecture, if needed. */
4032 gdbarch_info_init (&info
);
4033 if (!gdbarch_update_p (info
))
4034 internal_error (__FILE__
, __LINE__
,
4035 _("cris_gdbarch_update: failed to update architecture."));
4038 static struct gdbarch
*
4039 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4041 struct gdbarch
*gdbarch
;
4042 struct gdbarch_tdep
*tdep
;
4045 if (usr_cmd_cris_version_valid
)
4047 /* Trust the user's CRIS version setting. */
4048 cris_version
= usr_cmd_cris_version
;
4050 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4056 /* Assume it's CRIS version 10. */
4060 /* Make the current settings visible to the user. */
4061 usr_cmd_cris_version
= cris_version
;
4063 /* Find a candidate among the list of pre-declared architectures. */
4064 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4066 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4068 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4069 == usr_cmd_cris_version
)
4070 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4071 == usr_cmd_cris_mode
)
4072 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4073 == usr_cmd_cris_dwarf2_cfi
))
4074 return arches
->gdbarch
;
4077 /* No matching architecture was found. Create a new one. */
4078 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4079 gdbarch
= gdbarch_alloc (&info
, tdep
);
4081 tdep
->cris_version
= usr_cmd_cris_version
;
4082 tdep
->cris_mode
= usr_cmd_cris_mode
;
4083 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4085 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4086 switch (info
.byte_order
)
4088 case BFD_ENDIAN_LITTLE
:
4092 case BFD_ENDIAN_BIG
:
4093 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: big endian byte order in info"));
4097 internal_error (__FILE__
, __LINE__
, _("cris_gdbarch_init: unknown byte order in info"));
4100 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4101 set_gdbarch_deprecated_reg_struct_has_addr (gdbarch
,
4102 cris_reg_struct_has_addr
);
4103 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
4105 set_gdbarch_sp_regnum (gdbarch
, 14);
4107 /* Length of ordinary registers used in push_word and a few other
4108 places. register_size() is the real way to know how big a
4111 set_gdbarch_double_bit (gdbarch
, 64);
4112 /* The default definition of a long double is 2 * gdbarch_double_bit,
4113 which means we have to set this explicitly. */
4114 set_gdbarch_long_double_bit (gdbarch
, 64);
4116 /* The total amount of space needed to store (in an array called registers)
4117 GDB's copy of the machine's register state. Note: We can not use
4118 cris_register_size at this point, since it relies on current_gdbarch
4120 switch (tdep
->cris_version
)
4128 /* Old versions; not supported. */
4129 internal_error (__FILE__
, __LINE__
,
4130 _("cris_gdbarch_init: unsupported CRIS version"));
4135 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4136 P7 (32 bits), and P15 (32 bits) have been implemented. */
4137 set_gdbarch_pc_regnum (gdbarch
, 15);
4138 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4139 /* There are 32 registers (some of which may not be implemented). */
4140 set_gdbarch_num_regs (gdbarch
, 32);
4141 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4142 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4143 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4145 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4149 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4150 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4151 and pseudo-register PC (32 bits). */
4152 set_gdbarch_pc_regnum (gdbarch
, 32);
4153 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4154 /* 32 registers + pseudo-register PC + 16 support registers. */
4155 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4156 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4158 set_gdbarch_cannot_store_register
4159 (gdbarch
, crisv32_cannot_store_register
);
4160 set_gdbarch_cannot_fetch_register
4161 (gdbarch
, crisv32_cannot_fetch_register
);
4163 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4165 set_gdbarch_single_step_through_delay
4166 (gdbarch
, crisv32_single_step_through_delay
);
4171 internal_error (__FILE__
, __LINE__
,
4172 _("cris_gdbarch_init: unknown CRIS version"));
4175 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4176 have the same ABI). */
4177 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4178 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4179 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4180 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4182 /* The stack grows downward. */
4183 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4185 set_gdbarch_breakpoint_from_pc (gdbarch
, cris_breakpoint_from_pc
);
4187 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4188 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4189 set_gdbarch_unwind_dummy_id (gdbarch
, cris_unwind_dummy_id
);
4191 if (tdep
->cris_dwarf2_cfi
== 1)
4193 /* Hook in the Dwarf-2 frame sniffer. */
4194 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4195 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4196 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
4199 if (tdep
->cris_mode
!= cris_mode_guru
)
4201 frame_unwind_append_sniffer (gdbarch
, cris_sigtramp_frame_sniffer
);
4204 frame_unwind_append_sniffer (gdbarch
, cris_frame_sniffer
);
4205 frame_base_set_default (gdbarch
, &cris_frame_base
);
4207 set_solib_svr4_fetch_link_map_offsets
4208 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
4210 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4211 disassembler, even when there is no BFD. Does something like
4212 "gdb; target remote; disassmeble *0x123" work? */
4213 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);