[ARC] Fix typo in extension instruction name.
[deliverable/binutils-gdb.git] / gdb / cris-tdep.c
1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
2
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
4
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
7
8 This file is part of GDB.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
29 #include "symtab.h"
30 #include "inferior.h"
31 #include "gdbtypes.h"
32 #include "gdbcore.h"
33 #include "gdbcmd.h"
34 #include "target.h"
35 #include "value.h"
36 #include "opcode/cris.h"
37 #include "osabi.h"
38 #include "arch-utils.h"
39 #include "regcache.h"
40
41 #include "objfiles.h"
42
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
45 #include "dis-asm.h"
46
47 #include "cris-tdep.h"
48
49 enum cris_num_regs
50 {
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
52 NUM_FREGS = 0,
53
54 /* There are 16 general registers. */
55 NUM_GENREGS = 16,
56
57 /* There are 16 special registers. */
58 NUM_SPECREGS = 16,
59
60 /* CRISv32 has a pseudo PC register, not noted here. */
61
62 /* CRISv32 has 16 support registers. */
63 NUM_SUPPREGS = 16
64 };
65
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
78
79 enum cris_regnums
80 {
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
83 CRIS_FP_REGNUM = 8,
84 /* ABI related registers. */
85 STR_REGNUM = 9,
86 RET_REGNUM = 10,
87 ARG1_REGNUM = 10,
88 ARG2_REGNUM = 11,
89 ARG3_REGNUM = 12,
90 ARG4_REGNUM = 13,
91
92 /* Registers which happen to be common. */
93 VR_REGNUM = 17,
94 MOF_REGNUM = 23,
95 SRP_REGNUM = 27,
96
97 /* CRISv10 et al. specific registers. */
98 P0_REGNUM = 16,
99 P4_REGNUM = 20,
100 CCR_REGNUM = 21,
101 P8_REGNUM = 24,
102 IBR_REGNUM = 25,
103 IRP_REGNUM = 26,
104 BAR_REGNUM = 28,
105 DCCR_REGNUM = 29,
106 BRP_REGNUM = 30,
107 USP_REGNUM = 31,
108
109 /* CRISv32 specific registers. */
110 ACR_REGNUM = 15,
111 BZ_REGNUM = 16,
112 PID_REGNUM = 18,
113 SRS_REGNUM = 19,
114 WZ_REGNUM = 20,
115 EXS_REGNUM = 21,
116 EDA_REGNUM = 22,
117 DZ_REGNUM = 24,
118 EBP_REGNUM = 25,
119 ERP_REGNUM = 26,
120 NRP_REGNUM = 28,
121 CCS_REGNUM = 29,
122 CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
123 SPC_REGNUM = 31,
124 CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
125
126 S0_REGNUM = 33,
127 S1_REGNUM = 34,
128 S2_REGNUM = 35,
129 S3_REGNUM = 36,
130 S4_REGNUM = 37,
131 S5_REGNUM = 38,
132 S6_REGNUM = 39,
133 S7_REGNUM = 40,
134 S8_REGNUM = 41,
135 S9_REGNUM = 42,
136 S10_REGNUM = 43,
137 S11_REGNUM = 44,
138 S12_REGNUM = 45,
139 S13_REGNUM = 46,
140 S14_REGNUM = 47,
141 S15_REGNUM = 48,
142 };
143
144 extern const struct cris_spec_reg cris_spec_regs[];
145
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static unsigned int usr_cmd_cris_version;
149
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid = 0;
152
153 static const char cris_mode_normal[] = "normal";
154 static const char cris_mode_guru[] = "guru";
155 static const char *const cris_modes[] = {
156 cris_mode_normal,
157 cris_mode_guru,
158 0
159 };
160
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode = cris_mode_normal;
164
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi = 1;
167
168 /* Sigtramp identification code copied from i386-linux-tdep.c. */
169
170 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
171 #define SIGTRAMP_OFFSET0 0
172 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
173 #define SIGTRAMP_OFFSET1 4
174
175 static const unsigned short sigtramp_code[] =
176 {
177 SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
178 SIGTRAMP_INSN1 /* break 13 */
179 };
180
181 #define SIGTRAMP_LEN (sizeof sigtramp_code)
182
183 /* Note: same length as normal sigtramp code. */
184
185 static const unsigned short rt_sigtramp_code[] =
186 {
187 SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
188 SIGTRAMP_INSN1 /* break 13 */
189 };
190
191 /* If PC is in a sigtramp routine, return the address of the start of
192 the routine. Otherwise, return 0. */
193
194 static CORE_ADDR
195 cris_sigtramp_start (struct frame_info *this_frame)
196 {
197 CORE_ADDR pc = get_frame_pc (this_frame);
198 gdb_byte buf[SIGTRAMP_LEN];
199
200 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
201 return 0;
202
203 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
204 {
205 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
206 return 0;
207
208 pc -= SIGTRAMP_OFFSET1;
209 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
210 return 0;
211 }
212
213 if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
214 return 0;
215
216 return pc;
217 }
218
219 /* If PC is in a RT sigtramp routine, return the address of the start of
220 the routine. Otherwise, return 0. */
221
222 static CORE_ADDR
223 cris_rt_sigtramp_start (struct frame_info *this_frame)
224 {
225 CORE_ADDR pc = get_frame_pc (this_frame);
226 gdb_byte buf[SIGTRAMP_LEN];
227
228 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
229 return 0;
230
231 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
232 {
233 if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
234 return 0;
235
236 pc -= SIGTRAMP_OFFSET1;
237 if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
238 return 0;
239 }
240
241 if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
242 return 0;
243
244 return pc;
245 }
246
247 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
248 return the address of the associated sigcontext structure. */
249
250 static CORE_ADDR
251 cris_sigcontext_addr (struct frame_info *this_frame)
252 {
253 struct gdbarch *gdbarch = get_frame_arch (this_frame);
254 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
255 CORE_ADDR pc;
256 CORE_ADDR sp;
257 gdb_byte buf[4];
258
259 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
260 sp = extract_unsigned_integer (buf, 4, byte_order);
261
262 /* Look for normal sigtramp frame first. */
263 pc = cris_sigtramp_start (this_frame);
264 if (pc)
265 {
266 /* struct signal_frame (arch/cris/kernel/signal.c) contains
267 struct sigcontext as its first member, meaning the SP points to
268 it already. */
269 return sp;
270 }
271
272 pc = cris_rt_sigtramp_start (this_frame);
273 if (pc)
274 {
275 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
276 a struct ucontext, which in turn contains a struct sigcontext.
277 Magic digging:
278 4 + 4 + 128 to struct ucontext, then
279 4 + 4 + 12 to struct sigcontext. */
280 return (sp + 156);
281 }
282
283 error (_("Couldn't recognize signal trampoline."));
284 return 0;
285 }
286
287 struct cris_unwind_cache
288 {
289 /* The previous frame's inner most stack address. Used as this
290 frame ID's stack_addr. */
291 CORE_ADDR prev_sp;
292 /* The frame's base, optionally used by the high-level debug info. */
293 CORE_ADDR base;
294 int size;
295 /* How far the SP and r8 (FP) have been offset from the start of
296 the stack frame (as defined by the previous frame's stack
297 pointer). */
298 LONGEST sp_offset;
299 LONGEST r8_offset;
300 int uses_frame;
301
302 /* From old frame_extra_info struct. */
303 CORE_ADDR return_pc;
304 int leaf_function;
305
306 /* Table indicating the location of each and every register. */
307 struct trad_frame_saved_reg *saved_regs;
308 };
309
310 static struct cris_unwind_cache *
311 cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
312 void **this_cache)
313 {
314 struct gdbarch *gdbarch = get_frame_arch (this_frame);
315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
316 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
317 struct cris_unwind_cache *info;
318 CORE_ADDR addr;
319 gdb_byte buf[4];
320 int i;
321
322 if ((*this_cache))
323 return (struct cris_unwind_cache *) (*this_cache);
324
325 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
326 (*this_cache) = info;
327 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
328
329 /* Zero all fields. */
330 info->prev_sp = 0;
331 info->base = 0;
332 info->size = 0;
333 info->sp_offset = 0;
334 info->r8_offset = 0;
335 info->uses_frame = 0;
336 info->return_pc = 0;
337 info->leaf_function = 0;
338
339 get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
340 info->base = extract_unsigned_integer (buf, 4, byte_order);
341
342 addr = cris_sigcontext_addr (this_frame);
343
344 /* Layout of the sigcontext struct:
345 struct sigcontext {
346 struct pt_regs regs;
347 unsigned long oldmask;
348 unsigned long usp;
349 }; */
350
351 if (tdep->cris_version == 10)
352 {
353 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
354 struct pt_regs. */
355 for (i = 0; i <= 13; i++)
356 info->saved_regs[i].addr = addr + ((15 - i) * 4);
357
358 info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
359 info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
360 info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
361 /* Note: IRP is off by 2 at this point. There's no point in correcting
362 it though since that will mean that the backtrace will show a PC
363 different from what is shown when stopped. */
364 info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
365 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
366 = info->saved_regs[IRP_REGNUM];
367 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
368 }
369 else
370 {
371 /* CRISv32. */
372 /* R0 to R13 are stored in order at offset (1 * 4) in
373 struct pt_regs. */
374 for (i = 0; i <= 13; i++)
375 info->saved_regs[i].addr = addr + ((i + 1) * 4);
376
377 info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
378 info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
379 info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
380 info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
381 info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
382 info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
383 info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
384 info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
385 info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
386
387 /* FIXME: If ERP is in a delay slot at this point then the PC will
388 be wrong at this point. This problem manifests itself in the
389 sigaltstack.exp test case, which occasionally generates FAILs when
390 the signal is received while in a delay slot.
391
392 This could be solved by a couple of read_memory_unsigned_integer and a
393 trad_frame_set_value. */
394 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
395 = info->saved_regs[ERP_REGNUM];
396
397 info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
398 = addr + (25 * 4);
399 }
400
401 return info;
402 }
403
404 static void
405 cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
406 struct frame_id *this_id)
407 {
408 struct cris_unwind_cache *cache =
409 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
410 (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
411 }
412
413 /* Forward declaration. */
414
415 static struct value *cris_frame_prev_register (struct frame_info *this_frame,
416 void **this_cache, int regnum);
417 static struct value *
418 cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
419 void **this_cache, int regnum)
420 {
421 /* Make sure we've initialized the cache. */
422 cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
423 return cris_frame_prev_register (this_frame, this_cache, regnum);
424 }
425
426 static int
427 cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
428 struct frame_info *this_frame,
429 void **this_cache)
430 {
431 if (cris_sigtramp_start (this_frame)
432 || cris_rt_sigtramp_start (this_frame))
433 return 1;
434
435 return 0;
436 }
437
438 static const struct frame_unwind cris_sigtramp_frame_unwind =
439 {
440 SIGTRAMP_FRAME,
441 default_frame_unwind_stop_reason,
442 cris_sigtramp_frame_this_id,
443 cris_sigtramp_frame_prev_register,
444 NULL,
445 cris_sigtramp_frame_sniffer
446 };
447
448 static int
449 crisv32_single_step_through_delay (struct gdbarch *gdbarch,
450 struct frame_info *this_frame)
451 {
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
453 ULONGEST erp;
454 int ret = 0;
455
456 if (tdep->cris_mode == cris_mode_guru)
457 erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
458 else
459 erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
460
461 if (erp & 0x1)
462 {
463 /* In delay slot - check if there's a breakpoint at the preceding
464 instruction. */
465 if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
466 ret = 1;
467 }
468 return ret;
469 }
470
471 /* The instruction environment needed to find single-step breakpoints. */
472
473 typedef
474 struct instruction_environment
475 {
476 unsigned long reg[NUM_GENREGS];
477 unsigned long preg[NUM_SPECREGS];
478 unsigned long branch_break_address;
479 unsigned long delay_slot_pc;
480 unsigned long prefix_value;
481 int branch_found;
482 int prefix_found;
483 int invalid;
484 int slot_needed;
485 int delay_slot_pc_active;
486 int xflag_found;
487 int disable_interrupt;
488 enum bfd_endian byte_order;
489 } inst_env_type;
490
491 /* Machine-dependencies in CRIS for opcodes. */
492
493 /* Instruction sizes. */
494 enum cris_instruction_sizes
495 {
496 INST_BYTE_SIZE = 0,
497 INST_WORD_SIZE = 1,
498 INST_DWORD_SIZE = 2
499 };
500
501 /* Addressing modes. */
502 enum cris_addressing_modes
503 {
504 REGISTER_MODE = 1,
505 INDIRECT_MODE = 2,
506 AUTOINC_MODE = 3
507 };
508
509 /* Prefix addressing modes. */
510 enum cris_prefix_addressing_modes
511 {
512 PREFIX_INDEX_MODE = 2,
513 PREFIX_ASSIGN_MODE = 3,
514
515 /* Handle immediate byte offset addressing mode prefix format. */
516 PREFIX_OFFSET_MODE = 2
517 };
518
519 /* Masks for opcodes. */
520 enum cris_opcode_masks
521 {
522 BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
523 SIGNED_EXTEND_BIT_MASK = 0x2,
524 SIGNED_BYTE_MASK = 0x80,
525 SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
526 SIGNED_WORD_MASK = 0x8000,
527 SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
528 SIGNED_DWORD_MASK = 0x80000000,
529 SIGNED_QUICK_VALUE_MASK = 0x20,
530 SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
531 };
532
533 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
534 Bit 15 - 12 Operand2
535 11 - 10 Mode
536 9 - 6 Opcode
537 5 - 4 Size
538 3 - 0 Operand1 */
539
540 static int
541 cris_get_operand2 (unsigned short insn)
542 {
543 return ((insn & 0xF000) >> 12);
544 }
545
546 static int
547 cris_get_mode (unsigned short insn)
548 {
549 return ((insn & 0x0C00) >> 10);
550 }
551
552 static int
553 cris_get_opcode (unsigned short insn)
554 {
555 return ((insn & 0x03C0) >> 6);
556 }
557
558 static int
559 cris_get_size (unsigned short insn)
560 {
561 return ((insn & 0x0030) >> 4);
562 }
563
564 static int
565 cris_get_operand1 (unsigned short insn)
566 {
567 return (insn & 0x000F);
568 }
569
570 /* Additional functions in order to handle opcodes. */
571
572 static int
573 cris_get_quick_value (unsigned short insn)
574 {
575 return (insn & 0x003F);
576 }
577
578 static int
579 cris_get_bdap_quick_offset (unsigned short insn)
580 {
581 return (insn & 0x00FF);
582 }
583
584 static int
585 cris_get_branch_short_offset (unsigned short insn)
586 {
587 return (insn & 0x00FF);
588 }
589
590 static int
591 cris_get_asr_shift_steps (unsigned long value)
592 {
593 return (value & 0x3F);
594 }
595
596 static int
597 cris_get_clear_size (unsigned short insn)
598 {
599 return ((insn) & 0xC000);
600 }
601
602 static int
603 cris_is_signed_extend_bit_on (unsigned short insn)
604 {
605 return (((insn) & 0x20) == 0x20);
606 }
607
608 static int
609 cris_is_xflag_bit_on (unsigned short insn)
610 {
611 return (((insn) & 0x1000) == 0x1000);
612 }
613
614 static void
615 cris_set_size_to_dword (unsigned short *insn)
616 {
617 *insn &= 0xFFCF;
618 *insn |= 0x20;
619 }
620
621 static signed char
622 cris_get_signed_offset (unsigned short insn)
623 {
624 return ((signed char) (insn & 0x00FF));
625 }
626
627 /* Calls an op function given the op-type, working on the insn and the
628 inst_env. */
629 static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
630 inst_env_type *);
631
632 static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
633 struct gdbarch_list *);
634
635 static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
636
637 static void set_cris_version (char *ignore_args, int from_tty,
638 struct cmd_list_element *c);
639
640 static void set_cris_mode (char *ignore_args, int from_tty,
641 struct cmd_list_element *c);
642
643 static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
644 struct cmd_list_element *c);
645
646 static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
647 struct frame_info *this_frame,
648 struct cris_unwind_cache *info);
649
650 static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
651 struct frame_info *this_frame,
652 struct cris_unwind_cache *info);
653
654 static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
655 struct frame_info *next_frame);
656
657 static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
658 struct frame_info *next_frame);
659
660 /* When arguments must be pushed onto the stack, they go on in reverse
661 order. The below implements a FILO (stack) to do this.
662 Copied from d10v-tdep.c. */
663
664 struct stack_item
665 {
666 int len;
667 struct stack_item *prev;
668 gdb_byte *data;
669 };
670
671 static struct stack_item *
672 push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
673 {
674 struct stack_item *si = XNEW (struct stack_item);
675 si->data = (gdb_byte *) xmalloc (len);
676 si->len = len;
677 si->prev = prev;
678 memcpy (si->data, contents, len);
679 return si;
680 }
681
682 static struct stack_item *
683 pop_stack_item (struct stack_item *si)
684 {
685 struct stack_item *dead = si;
686 si = si->prev;
687 xfree (dead->data);
688 xfree (dead);
689 return si;
690 }
691
692 /* Put here the code to store, into fi->saved_regs, the addresses of
693 the saved registers of frame described by FRAME_INFO. This
694 includes special registers such as pc and fp saved in special ways
695 in the stack frame. sp is even more special: the address we return
696 for it IS the sp for the next frame. */
697
698 static struct cris_unwind_cache *
699 cris_frame_unwind_cache (struct frame_info *this_frame,
700 void **this_prologue_cache)
701 {
702 struct gdbarch *gdbarch = get_frame_arch (this_frame);
703 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
704 struct cris_unwind_cache *info;
705
706 if ((*this_prologue_cache))
707 return (struct cris_unwind_cache *) (*this_prologue_cache);
708
709 info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
710 (*this_prologue_cache) = info;
711 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
712
713 /* Zero all fields. */
714 info->prev_sp = 0;
715 info->base = 0;
716 info->size = 0;
717 info->sp_offset = 0;
718 info->r8_offset = 0;
719 info->uses_frame = 0;
720 info->return_pc = 0;
721 info->leaf_function = 0;
722
723 /* Prologue analysis does the rest... */
724 if (tdep->cris_version == 32)
725 crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
726 else
727 cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
728
729 return info;
730 }
731
732 /* Given a GDB frame, determine the address of the calling function's
733 frame. This will be used to create a new GDB frame struct. */
734
735 static void
736 cris_frame_this_id (struct frame_info *this_frame,
737 void **this_prologue_cache,
738 struct frame_id *this_id)
739 {
740 struct cris_unwind_cache *info
741 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
742 CORE_ADDR base;
743 CORE_ADDR func;
744 struct frame_id id;
745
746 /* The FUNC is easy. */
747 func = get_frame_func (this_frame);
748
749 /* Hopefully the prologue analysis either correctly determined the
750 frame's base (which is the SP from the previous frame), or set
751 that base to "NULL". */
752 base = info->prev_sp;
753 if (base == 0)
754 return;
755
756 id = frame_id_build (base, func);
757
758 (*this_id) = id;
759 }
760
761 static struct value *
762 cris_frame_prev_register (struct frame_info *this_frame,
763 void **this_prologue_cache, int regnum)
764 {
765 struct cris_unwind_cache *info
766 = cris_frame_unwind_cache (this_frame, this_prologue_cache);
767 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
768 }
769
770 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
771 frame. The frame ID's base needs to match the TOS value saved by
772 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
773
774 static struct frame_id
775 cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
776 {
777 CORE_ADDR sp;
778 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
779 return frame_id_build (sp, get_frame_pc (this_frame));
780 }
781
782 static CORE_ADDR
783 cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
784 {
785 /* Align to the size of an instruction (so that they can safely be
786 pushed onto the stack). */
787 return sp & ~3;
788 }
789
790 static CORE_ADDR
791 cris_push_dummy_code (struct gdbarch *gdbarch,
792 CORE_ADDR sp, CORE_ADDR funaddr,
793 struct value **args, int nargs,
794 struct type *value_type,
795 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
796 struct regcache *regcache)
797 {
798 /* Allocate space sufficient for a breakpoint. */
799 sp = (sp - 4) & ~3;
800 /* Store the address of that breakpoint */
801 *bp_addr = sp;
802 /* CRIS always starts the call at the callee's entry point. */
803 *real_pc = funaddr;
804 return sp;
805 }
806
807 static CORE_ADDR
808 cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
809 struct regcache *regcache, CORE_ADDR bp_addr,
810 int nargs, struct value **args, CORE_ADDR sp,
811 int struct_return, CORE_ADDR struct_addr)
812 {
813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
814 int stack_offset;
815 int argreg;
816 int argnum;
817
818 /* The function's arguments and memory allocated by gdb for the arguments to
819 point at reside in separate areas on the stack.
820 Both frame pointers grow toward higher addresses. */
821 CORE_ADDR fp_arg;
822 CORE_ADDR fp_mem;
823
824 struct stack_item *si = NULL;
825
826 /* Push the return address. */
827 regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
828
829 /* Are we returning a value using a structure return or a normal value
830 return? struct_addr is the address of the reserved space for the return
831 structure to be written on the stack. */
832 if (struct_return)
833 {
834 regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
835 }
836
837 /* Now load as many as possible of the first arguments into registers,
838 and push the rest onto the stack. */
839 argreg = ARG1_REGNUM;
840 stack_offset = 0;
841
842 for (argnum = 0; argnum < nargs; argnum++)
843 {
844 int len;
845 const gdb_byte *val;
846 int reg_demand;
847 int i;
848
849 len = TYPE_LENGTH (value_type (args[argnum]));
850 val = value_contents (args[argnum]);
851
852 /* How may registers worth of storage do we need for this argument? */
853 reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
854
855 if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
856 {
857 /* Data passed by value. Fits in available register(s). */
858 for (i = 0; i < reg_demand; i++)
859 {
860 regcache_cooked_write (regcache, argreg, val);
861 argreg++;
862 val += 4;
863 }
864 }
865 else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
866 {
867 /* Data passed by value. Does not fit in available register(s).
868 Use the register(s) first, then the stack. */
869 for (i = 0; i < reg_demand; i++)
870 {
871 if (argreg <= ARG4_REGNUM)
872 {
873 regcache_cooked_write (regcache, argreg, val);
874 argreg++;
875 val += 4;
876 }
877 else
878 {
879 /* Push item for later so that pushed arguments
880 come in the right order. */
881 si = push_stack_item (si, val, 4);
882 val += 4;
883 }
884 }
885 }
886 else if (len > (2 * 4))
887 {
888 /* Data passed by reference. Push copy of data onto stack
889 and pass pointer to this copy as argument. */
890 sp = (sp - len) & ~3;
891 write_memory (sp, val, len);
892
893 if (argreg <= ARG4_REGNUM)
894 {
895 regcache_cooked_write_unsigned (regcache, argreg, sp);
896 argreg++;
897 }
898 else
899 {
900 gdb_byte buf[4];
901 store_unsigned_integer (buf, 4, byte_order, sp);
902 si = push_stack_item (si, buf, 4);
903 }
904 }
905 else
906 {
907 /* Data passed by value. No available registers. Put it on
908 the stack. */
909 si = push_stack_item (si, val, len);
910 }
911 }
912
913 while (si)
914 {
915 /* fp_arg must be word-aligned (i.e., don't += len) to match
916 the function prologue. */
917 sp = (sp - si->len) & ~3;
918 write_memory (sp, si->data, si->len);
919 si = pop_stack_item (si);
920 }
921
922 /* Finally, update the SP register. */
923 regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
924
925 return sp;
926 }
927
928 static const struct frame_unwind cris_frame_unwind =
929 {
930 NORMAL_FRAME,
931 default_frame_unwind_stop_reason,
932 cris_frame_this_id,
933 cris_frame_prev_register,
934 NULL,
935 default_frame_sniffer
936 };
937
938 static CORE_ADDR
939 cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
940 {
941 struct cris_unwind_cache *info
942 = cris_frame_unwind_cache (this_frame, this_cache);
943 return info->base;
944 }
945
946 static const struct frame_base cris_frame_base =
947 {
948 &cris_frame_unwind,
949 cris_frame_base_address,
950 cris_frame_base_address,
951 cris_frame_base_address
952 };
953
954 /* Frames information. The definition of the struct frame_info is
955
956 CORE_ADDR frame
957 CORE_ADDR pc
958 enum frame_type type;
959 CORE_ADDR return_pc
960 int leaf_function
961
962 If the compilation option -fno-omit-frame-pointer is present the
963 variable frame will be set to the content of R8 which is the frame
964 pointer register.
965
966 The variable pc contains the address where execution is performed
967 in the present frame. The innermost frame contains the current content
968 of the register PC. All other frames contain the content of the
969 register PC in the next frame.
970
971 The variable `type' indicates the frame's type: normal, SIGTRAMP
972 (associated with a signal handler), dummy (associated with a dummy
973 frame).
974
975 The variable return_pc contains the address where execution should be
976 resumed when the present frame has finished, the return address.
977
978 The variable leaf_function is 1 if the return address is in the register
979 SRP, and 0 if it is on the stack.
980
981 Prologue instructions C-code.
982 The prologue may consist of (-fno-omit-frame-pointer)
983 1) 2)
984 push srp
985 push r8 push r8
986 move.d sp,r8 move.d sp,r8
987 subq X,sp subq X,sp
988 movem rY,[sp] movem rY,[sp]
989 move.S rZ,[r8-U] move.S rZ,[r8-U]
990
991 where 1 is a non-terminal function, and 2 is a leaf-function.
992
993 Note that this assumption is extremely brittle, and will break at the
994 slightest change in GCC's prologue.
995
996 If local variables are declared or register contents are saved on stack
997 the subq-instruction will be present with X as the number of bytes
998 needed for storage. The reshuffle with respect to r8 may be performed
999 with any size S (b, w, d) and any of the general registers Z={0..13}.
1000 The offset U should be representable by a signed 8-bit value in all cases.
1001 Thus, the prefix word is assumed to be immediate byte offset mode followed
1002 by another word containing the instruction.
1003
1004 Degenerate cases:
1005 3)
1006 push r8
1007 move.d sp,r8
1008 move.d r8,sp
1009 pop r8
1010
1011 Prologue instructions C++-code.
1012 Case 1) and 2) in the C-code may be followed by
1013
1014 move.d r10,rS ; this
1015 move.d r11,rT ; P1
1016 move.d r12,rU ; P2
1017 move.d r13,rV ; P3
1018 move.S [r8+U],rZ ; P4
1019
1020 if any of the call parameters are stored. The host expects these
1021 instructions to be executed in order to get the call parameters right. */
1022
1023 /* Examine the prologue of a function. The variable ip is the address of
1024 the first instruction of the prologue. The variable limit is the address
1025 of the first instruction after the prologue. The variable fi contains the
1026 information in struct frame_info. The variable frameless_p controls whether
1027 the entire prologue is examined (0) or just enough instructions to
1028 determine that it is a prologue (1). */
1029
1030 static CORE_ADDR
1031 cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1032 struct cris_unwind_cache *info)
1033 {
1034 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1035 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1036
1037 /* Present instruction. */
1038 unsigned short insn;
1039
1040 /* Next instruction, lookahead. */
1041 unsigned short insn_next;
1042 int regno;
1043
1044 /* Is there a push fp? */
1045 int have_fp;
1046
1047 /* Number of byte on stack used for local variables and movem. */
1048 int val;
1049
1050 /* Highest register number in a movem. */
1051 int regsave;
1052
1053 /* move.d r<source_register>,rS */
1054 short source_register;
1055
1056 /* Scan limit. */
1057 int limit;
1058
1059 /* This frame is with respect to a leaf until a push srp is found. */
1060 if (info)
1061 {
1062 info->leaf_function = 1;
1063 }
1064
1065 /* Assume nothing on stack. */
1066 val = 0;
1067 regsave = -1;
1068
1069 /* If we were called without a this_frame, that means we were called
1070 from cris_skip_prologue which already tried to find the end of the
1071 prologue through the symbol information. 64 instructions past current
1072 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1073 limit = this_frame ? get_frame_pc (this_frame) : pc + 64;
1074
1075 /* Find the prologue instructions. */
1076 while (pc > 0 && pc < limit)
1077 {
1078 insn = read_memory_unsigned_integer (pc, 2, byte_order);
1079 pc += 2;
1080 if (insn == 0xE1FC)
1081 {
1082 /* push <reg> 32 bit instruction. */
1083 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1084 pc += 2;
1085 regno = cris_get_operand2 (insn_next);
1086 if (info)
1087 {
1088 info->sp_offset += 4;
1089 }
1090 /* This check, meant to recognize srp, used to be regno ==
1091 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1092 if (insn_next == 0xBE7E)
1093 {
1094 if (info)
1095 {
1096 info->leaf_function = 0;
1097 }
1098 }
1099 else if (insn_next == 0x8FEE)
1100 {
1101 /* push $r8 */
1102 if (info)
1103 {
1104 info->r8_offset = info->sp_offset;
1105 }
1106 }
1107 }
1108 else if (insn == 0x866E)
1109 {
1110 /* move.d sp,r8 */
1111 if (info)
1112 {
1113 info->uses_frame = 1;
1114 }
1115 continue;
1116 }
1117 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1118 && cris_get_mode (insn) == 0x0000
1119 && cris_get_opcode (insn) == 0x000A)
1120 {
1121 /* subq <val>,sp */
1122 if (info)
1123 {
1124 info->sp_offset += cris_get_quick_value (insn);
1125 }
1126 }
1127 else if (cris_get_mode (insn) == 0x0002
1128 && cris_get_opcode (insn) == 0x000F
1129 && cris_get_size (insn) == 0x0003
1130 && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch))
1131 {
1132 /* movem r<regsave>,[sp] */
1133 regsave = cris_get_operand2 (insn);
1134 }
1135 else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch)
1136 && ((insn & 0x0F00) >> 8) == 0x0001
1137 && (cris_get_signed_offset (insn) < 0))
1138 {
1139 /* Immediate byte offset addressing prefix word with sp as base
1140 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1141 is between 64 and 128.
1142 movem r<regsave>,[sp=sp-<val>] */
1143 if (info)
1144 {
1145 info->sp_offset += -cris_get_signed_offset (insn);
1146 }
1147 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1148 pc += 2;
1149 if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE
1150 && cris_get_opcode (insn_next) == 0x000F
1151 && cris_get_size (insn_next) == 0x0003
1152 && cris_get_operand1 (insn_next) == gdbarch_sp_regnum
1153 (gdbarch))
1154 {
1155 regsave = cris_get_operand2 (insn_next);
1156 }
1157 else
1158 {
1159 /* The prologue ended before the limit was reached. */
1160 pc -= 4;
1161 break;
1162 }
1163 }
1164 else if (cris_get_mode (insn) == 0x0001
1165 && cris_get_opcode (insn) == 0x0009
1166 && cris_get_size (insn) == 0x0002)
1167 {
1168 /* move.d r<10..13>,r<0..15> */
1169 source_register = cris_get_operand1 (insn);
1170
1171 /* FIXME? In the glibc solibs, the prologue might contain something
1172 like (this example taken from relocate_doit):
1173 move.d $pc,$r0
1174 sub.d 0xfffef426,$r0
1175 which isn't covered by the source_register check below. Question
1176 is whether to add a check for this combo, or make better use of
1177 the limit variable instead. */
1178 if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM)
1179 {
1180 /* The prologue ended before the limit was reached. */
1181 pc -= 2;
1182 break;
1183 }
1184 }
1185 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1186 /* The size is a fixed-size. */
1187 && ((insn & 0x0F00) >> 8) == 0x0001
1188 /* A negative offset. */
1189 && (cris_get_signed_offset (insn) < 0))
1190 {
1191 /* move.S rZ,[r8-U] (?) */
1192 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1193 pc += 2;
1194 regno = cris_get_operand2 (insn_next);
1195 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1196 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1197 && cris_get_opcode (insn_next) == 0x000F)
1198 {
1199 /* move.S rZ,[r8-U] */
1200 continue;
1201 }
1202 else
1203 {
1204 /* The prologue ended before the limit was reached. */
1205 pc -= 4;
1206 break;
1207 }
1208 }
1209 else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM
1210 /* The size is a fixed-size. */
1211 && ((insn & 0x0F00) >> 8) == 0x0001
1212 /* A positive offset. */
1213 && (cris_get_signed_offset (insn) > 0))
1214 {
1215 /* move.S [r8+U],rZ (?) */
1216 insn_next = read_memory_unsigned_integer (pc, 2, byte_order);
1217 pc += 2;
1218 regno = cris_get_operand2 (insn_next);
1219 if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1220 && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE
1221 && cris_get_opcode (insn_next) == 0x0009
1222 && cris_get_operand1 (insn_next) == regno)
1223 {
1224 /* move.S [r8+U],rZ */
1225 continue;
1226 }
1227 else
1228 {
1229 /* The prologue ended before the limit was reached. */
1230 pc -= 4;
1231 break;
1232 }
1233 }
1234 else
1235 {
1236 /* The prologue ended before the limit was reached. */
1237 pc -= 2;
1238 break;
1239 }
1240 }
1241
1242 /* We only want to know the end of the prologue when this_frame and info
1243 are NULL (called from cris_skip_prologue i.e.). */
1244 if (this_frame == NULL && info == NULL)
1245 {
1246 return pc;
1247 }
1248
1249 info->size = info->sp_offset;
1250
1251 /* Compute the previous frame's stack pointer (which is also the
1252 frame's ID's stack address), and this frame's base pointer. */
1253 if (info->uses_frame)
1254 {
1255 ULONGEST this_base;
1256 /* The SP was moved to the FP. This indicates that a new frame
1257 was created. Get THIS frame's FP value by unwinding it from
1258 the next frame. */
1259 this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM);
1260 info->base = this_base;
1261 info->saved_regs[CRIS_FP_REGNUM].addr = info->base;
1262
1263 /* The FP points at the last saved register. Adjust the FP back
1264 to before the first saved register giving the SP. */
1265 info->prev_sp = info->base + info->r8_offset;
1266 }
1267 else
1268 {
1269 ULONGEST this_base;
1270 /* Assume that the FP is this frame's SP but with that pushed
1271 stack space added back. */
1272 this_base = get_frame_register_unsigned (this_frame,
1273 gdbarch_sp_regnum (gdbarch));
1274 info->base = this_base;
1275 info->prev_sp = info->base + info->size;
1276 }
1277
1278 /* Calculate the addresses for the saved registers on the stack. */
1279 /* FIXME: The address calculation should really be done on the fly while
1280 we're analyzing the prologue (we only hold one regsave value as it is
1281 now). */
1282 val = info->sp_offset;
1283
1284 for (regno = regsave; regno >= 0; regno--)
1285 {
1286 info->saved_regs[regno].addr = info->base + info->r8_offset - val;
1287 val -= 4;
1288 }
1289
1290 /* The previous frame's SP needed to be computed. Save the computed
1291 value. */
1292 trad_frame_set_value (info->saved_regs,
1293 gdbarch_sp_regnum (gdbarch), info->prev_sp);
1294
1295 if (!info->leaf_function)
1296 {
1297 /* SRP saved on the stack. But where? */
1298 if (info->r8_offset == 0)
1299 {
1300 /* R8 not pushed yet. */
1301 info->saved_regs[SRP_REGNUM].addr = info->base;
1302 }
1303 else
1304 {
1305 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1306 info->saved_regs[SRP_REGNUM].addr = info->base + 4;
1307 }
1308 }
1309
1310 /* The PC is found in SRP (the actual register or located on the stack). */
1311 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1312 = info->saved_regs[SRP_REGNUM];
1313
1314 return pc;
1315 }
1316
1317 static CORE_ADDR
1318 crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame,
1319 struct cris_unwind_cache *info)
1320 {
1321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1322 ULONGEST this_base;
1323
1324 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1325 meant to be a full-fledged prologue scanner. It is only needed for
1326 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1327
1328 * PLT stubs (library calls)
1329 * call dummys
1330 * signal trampolines
1331
1332 For those cases, it is assumed that there is no actual prologue; that
1333 the stack pointer is not adjusted, and (as a consequence) the return
1334 address is not pushed onto the stack. */
1335
1336 /* We only want to know the end of the prologue when this_frame and info
1337 are NULL (called from cris_skip_prologue i.e.). */
1338 if (this_frame == NULL && info == NULL)
1339 {
1340 return pc;
1341 }
1342
1343 /* The SP is assumed to be unaltered. */
1344 this_base = get_frame_register_unsigned (this_frame,
1345 gdbarch_sp_regnum (gdbarch));
1346 info->base = this_base;
1347 info->prev_sp = this_base;
1348
1349 /* The PC is assumed to be found in SRP. */
1350 info->saved_regs[gdbarch_pc_regnum (gdbarch)]
1351 = info->saved_regs[SRP_REGNUM];
1352
1353 return pc;
1354 }
1355
1356 /* Advance pc beyond any function entry prologue instructions at pc
1357 to reach some "real" code. */
1358
1359 /* Given a PC value corresponding to the start of a function, return the PC
1360 of the first instruction after the function prologue. */
1361
1362 static CORE_ADDR
1363 cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1364 {
1365 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1366 CORE_ADDR func_addr, func_end;
1367 struct symtab_and_line sal;
1368 CORE_ADDR pc_after_prologue;
1369
1370 /* If we have line debugging information, then the end of the prologue
1371 should the first assembly instruction of the first source line. */
1372 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1373 {
1374 sal = find_pc_line (func_addr, 0);
1375 if (sal.end > 0 && sal.end < func_end)
1376 return sal.end;
1377 }
1378
1379 if (tdep->cris_version == 32)
1380 pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL);
1381 else
1382 pc_after_prologue = cris_scan_prologue (pc, NULL, NULL);
1383
1384 return pc_after_prologue;
1385 }
1386
1387 static CORE_ADDR
1388 cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1389 {
1390 ULONGEST pc;
1391 pc = frame_unwind_register_unsigned (next_frame,
1392 gdbarch_pc_regnum (gdbarch));
1393 return pc;
1394 }
1395
1396 static CORE_ADDR
1397 cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1398 {
1399 ULONGEST sp;
1400 sp = frame_unwind_register_unsigned (next_frame,
1401 gdbarch_sp_regnum (gdbarch));
1402 return sp;
1403 }
1404
1405 /* Use the program counter to determine the contents and size of a breakpoint
1406 instruction. It returns a pointer to a string of bytes that encode a
1407 breakpoint instruction, stores the length of the string to *lenptr, and
1408 adjusts pcptr (if necessary) to point to the actual memory location where
1409 the breakpoint should be inserted. */
1410
1411 static const unsigned char *
1412 cris_breakpoint_from_pc (struct gdbarch *gdbarch,
1413 CORE_ADDR *pcptr, int *lenptr)
1414 {
1415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1416 static unsigned char break8_insn[] = {0x38, 0xe9};
1417 static unsigned char break15_insn[] = {0x3f, 0xe9};
1418 *lenptr = 2;
1419
1420 if (tdep->cris_mode == cris_mode_guru)
1421 return break15_insn;
1422 else
1423 return break8_insn;
1424 }
1425
1426 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1427 0 otherwise. */
1428
1429 static int
1430 cris_spec_reg_applicable (struct gdbarch *gdbarch,
1431 struct cris_spec_reg spec_reg)
1432 {
1433 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1434 unsigned int version = tdep->cris_version;
1435
1436 switch (spec_reg.applicable_version)
1437 {
1438 case cris_ver_version_all:
1439 return 1;
1440 case cris_ver_warning:
1441 /* Indeterminate/obsolete. */
1442 return 0;
1443 case cris_ver_v0_3:
1444 return (version >= 0 && version <= 3);
1445 case cris_ver_v3p:
1446 return (version >= 3);
1447 case cris_ver_v8:
1448 return (version == 8 || version == 9);
1449 case cris_ver_v8p:
1450 return (version >= 8);
1451 case cris_ver_v0_10:
1452 return (version >= 0 && version <= 10);
1453 case cris_ver_v3_10:
1454 return (version >= 3 && version <= 10);
1455 case cris_ver_v8_10:
1456 return (version >= 8 && version <= 10);
1457 case cris_ver_v10:
1458 return (version == 10);
1459 case cris_ver_v10p:
1460 return (version >= 10);
1461 case cris_ver_v32p:
1462 return (version >= 32);
1463 default:
1464 /* Invalid cris version. */
1465 return 0;
1466 }
1467 }
1468
1469 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1470 register, -1 for an invalid register. */
1471
1472 static int
1473 cris_register_size (struct gdbarch *gdbarch, int regno)
1474 {
1475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1476 int i;
1477 int spec_regno;
1478
1479 if (regno >= 0 && regno < NUM_GENREGS)
1480 {
1481 /* General registers (R0 - R15) are 32 bits. */
1482 return 4;
1483 }
1484 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1485 {
1486 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1487 Adjust regno accordingly. */
1488 spec_regno = regno - NUM_GENREGS;
1489
1490 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1491 {
1492 if (cris_spec_regs[i].number == spec_regno
1493 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1494 /* Go with the first applicable register. */
1495 return cris_spec_regs[i].reg_size;
1496 }
1497 /* Special register not applicable to this CRIS version. */
1498 return 0;
1499 }
1500 else if (regno >= gdbarch_pc_regnum (gdbarch)
1501 && regno < gdbarch_num_regs (gdbarch))
1502 {
1503 /* This will apply to CRISv32 only where there are additional registers
1504 after the special registers (pseudo PC and support registers). */
1505 return 4;
1506 }
1507
1508
1509 return -1;
1510 }
1511
1512 /* Nonzero if regno should not be fetched from the target. This is the case
1513 for unimplemented (size 0) and non-existant registers. */
1514
1515 static int
1516 cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1517 {
1518 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1519 || (cris_register_size (gdbarch, regno) == 0));
1520 }
1521
1522 /* Nonzero if regno should not be written to the target, for various
1523 reasons. */
1524
1525 static int
1526 cris_cannot_store_register (struct gdbarch *gdbarch, int regno)
1527 {
1528 /* There are three kinds of registers we refuse to write to.
1529 1. Those that not implemented.
1530 2. Those that are read-only (depends on the processor mode).
1531 3. Those registers to which a write has no effect. */
1532
1533 if (regno < 0
1534 || regno >= gdbarch_num_regs (gdbarch)
1535 || cris_register_size (gdbarch, regno) == 0)
1536 /* Not implemented. */
1537 return 1;
1538
1539 else if (regno == VR_REGNUM)
1540 /* Read-only. */
1541 return 1;
1542
1543 else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM)
1544 /* Writing has no effect. */
1545 return 1;
1546
1547 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1548 agent decide whether they are writable. */
1549
1550 return 0;
1551 }
1552
1553 /* Nonzero if regno should not be fetched from the target. This is the case
1554 for unimplemented (size 0) and non-existant registers. */
1555
1556 static int
1557 crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
1558 {
1559 return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch))
1560 || (cris_register_size (gdbarch, regno) == 0));
1561 }
1562
1563 /* Nonzero if regno should not be written to the target, for various
1564 reasons. */
1565
1566 static int
1567 crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno)
1568 {
1569 /* There are three kinds of registers we refuse to write to.
1570 1. Those that not implemented.
1571 2. Those that are read-only (depends on the processor mode).
1572 3. Those registers to which a write has no effect. */
1573
1574 if (regno < 0
1575 || regno >= gdbarch_num_regs (gdbarch)
1576 || cris_register_size (gdbarch, regno) == 0)
1577 /* Not implemented. */
1578 return 1;
1579
1580 else if (regno == VR_REGNUM)
1581 /* Read-only. */
1582 return 1;
1583
1584 else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
1585 /* Writing has no effect. */
1586 return 1;
1587
1588 /* Many special registers are read-only in user mode. Let the debug
1589 agent decide whether they are writable. */
1590
1591 return 0;
1592 }
1593
1594 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1595 of data in register regno. */
1596
1597 static struct type *
1598 cris_register_type (struct gdbarch *gdbarch, int regno)
1599 {
1600 if (regno == gdbarch_pc_regnum (gdbarch))
1601 return builtin_type (gdbarch)->builtin_func_ptr;
1602 else if (regno == gdbarch_sp_regnum (gdbarch)
1603 || regno == CRIS_FP_REGNUM)
1604 return builtin_type (gdbarch)->builtin_data_ptr;
1605 else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch))
1606 || (regno >= MOF_REGNUM && regno <= USP_REGNUM))
1607 /* Note: R8 taken care of previous clause. */
1608 return builtin_type (gdbarch)->builtin_uint32;
1609 else if (regno >= P4_REGNUM && regno <= CCR_REGNUM)
1610 return builtin_type (gdbarch)->builtin_uint16;
1611 else if (regno >= P0_REGNUM && regno <= VR_REGNUM)
1612 return builtin_type (gdbarch)->builtin_uint8;
1613 else
1614 /* Invalid (unimplemented) register. */
1615 return builtin_type (gdbarch)->builtin_int0;
1616 }
1617
1618 static struct type *
1619 crisv32_register_type (struct gdbarch *gdbarch, int regno)
1620 {
1621 if (regno == gdbarch_pc_regnum (gdbarch))
1622 return builtin_type (gdbarch)->builtin_func_ptr;
1623 else if (regno == gdbarch_sp_regnum (gdbarch)
1624 || regno == CRIS_FP_REGNUM)
1625 return builtin_type (gdbarch)->builtin_data_ptr;
1626 else if ((regno >= 0 && regno <= ACR_REGNUM)
1627 || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
1628 || (regno == PID_REGNUM)
1629 || (regno >= S0_REGNUM && regno <= S15_REGNUM))
1630 /* Note: R8 and SP taken care of by previous clause. */
1631 return builtin_type (gdbarch)->builtin_uint32;
1632 else if (regno == WZ_REGNUM)
1633 return builtin_type (gdbarch)->builtin_uint16;
1634 else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
1635 return builtin_type (gdbarch)->builtin_uint8;
1636 else
1637 {
1638 /* Invalid (unimplemented) register. Should not happen as there are
1639 no unimplemented CRISv32 registers. */
1640 warning (_("crisv32_register_type: unknown regno %d"), regno);
1641 return builtin_type (gdbarch)->builtin_int0;
1642 }
1643 }
1644
1645 /* Stores a function return value of type type, where valbuf is the address
1646 of the value to be stored. */
1647
1648 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1649
1650 static void
1651 cris_store_return_value (struct type *type, struct regcache *regcache,
1652 const gdb_byte *valbuf)
1653 {
1654 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1655 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1656 ULONGEST val;
1657 int len = TYPE_LENGTH (type);
1658
1659 if (len <= 4)
1660 {
1661 /* Put the return value in R10. */
1662 val = extract_unsigned_integer (valbuf, len, byte_order);
1663 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1664 }
1665 else if (len <= 8)
1666 {
1667 /* Put the return value in R10 and R11. */
1668 val = extract_unsigned_integer (valbuf, 4, byte_order);
1669 regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val);
1670 val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
1671 regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val);
1672 }
1673 else
1674 error (_("cris_store_return_value: type length too large."));
1675 }
1676
1677 /* Return the name of register regno as a string. Return NULL for an
1678 invalid or unimplemented register. */
1679
1680 static const char *
1681 cris_special_register_name (struct gdbarch *gdbarch, int regno)
1682 {
1683 int spec_regno;
1684 int i;
1685
1686 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1687 Adjust regno accordingly. */
1688 spec_regno = regno - NUM_GENREGS;
1689
1690 /* Assume nothing about the layout of the cris_spec_regs struct
1691 when searching. */
1692 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1693 {
1694 if (cris_spec_regs[i].number == spec_regno
1695 && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i]))
1696 /* Go with the first applicable register. */
1697 return cris_spec_regs[i].name;
1698 }
1699 /* Special register not applicable to this CRIS version. */
1700 return NULL;
1701 }
1702
1703 static const char *
1704 cris_register_name (struct gdbarch *gdbarch, int regno)
1705 {
1706 static char *cris_genreg_names[] =
1707 { "r0", "r1", "r2", "r3", \
1708 "r4", "r5", "r6", "r7", \
1709 "r8", "r9", "r10", "r11", \
1710 "r12", "r13", "sp", "pc" };
1711
1712 if (regno >= 0 && regno < NUM_GENREGS)
1713 {
1714 /* General register. */
1715 return cris_genreg_names[regno];
1716 }
1717 else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch))
1718 {
1719 return cris_special_register_name (gdbarch, regno);
1720 }
1721 else
1722 {
1723 /* Invalid register. */
1724 return NULL;
1725 }
1726 }
1727
1728 static const char *
1729 crisv32_register_name (struct gdbarch *gdbarch, int regno)
1730 {
1731 static char *crisv32_genreg_names[] =
1732 { "r0", "r1", "r2", "r3", \
1733 "r4", "r5", "r6", "r7", \
1734 "r8", "r9", "r10", "r11", \
1735 "r12", "r13", "sp", "acr"
1736 };
1737
1738 static char *crisv32_sreg_names[] =
1739 { "s0", "s1", "s2", "s3", \
1740 "s4", "s5", "s6", "s7", \
1741 "s8", "s9", "s10", "s11", \
1742 "s12", "s13", "s14", "s15"
1743 };
1744
1745 if (regno >= 0 && regno < NUM_GENREGS)
1746 {
1747 /* General register. */
1748 return crisv32_genreg_names[regno];
1749 }
1750 else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
1751 {
1752 return cris_special_register_name (gdbarch, regno);
1753 }
1754 else if (regno == gdbarch_pc_regnum (gdbarch))
1755 {
1756 return "pc";
1757 }
1758 else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
1759 {
1760 return crisv32_sreg_names[regno - S0_REGNUM];
1761 }
1762 else
1763 {
1764 /* Invalid register. */
1765 return NULL;
1766 }
1767 }
1768
1769 /* Convert DWARF register number REG to the appropriate register
1770 number used by GDB. */
1771
1772 static int
1773 cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1774 {
1775 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1776 numbering, MOF is 18).
1777 Adapted from gcc/config/cris/cris.h. */
1778 static int cris_dwarf_regmap[] = {
1779 0, 1, 2, 3,
1780 4, 5, 6, 7,
1781 8, 9, 10, 11,
1782 12, 13, 14, 15,
1783 27, -1, -1, -1,
1784 -1, -1, -1, 23,
1785 -1, -1, -1, 27,
1786 -1, -1, -1, -1
1787 };
1788 int regnum = -1;
1789
1790 if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap))
1791 regnum = cris_dwarf_regmap[reg];
1792
1793 return regnum;
1794 }
1795
1796 /* DWARF-2 frame support. */
1797
1798 static void
1799 cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1800 struct dwarf2_frame_state_reg *reg,
1801 struct frame_info *this_frame)
1802 {
1803 /* The return address column. */
1804 if (regnum == gdbarch_pc_regnum (gdbarch))
1805 reg->how = DWARF2_FRAME_REG_RA;
1806
1807 /* The call frame address. */
1808 else if (regnum == gdbarch_sp_regnum (gdbarch))
1809 reg->how = DWARF2_FRAME_REG_CFA;
1810 }
1811
1812 /* Extract from an array regbuf containing the raw register state a function
1813 return value of type type, and copy that, in virtual format, into
1814 valbuf. */
1815
1816 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1817
1818 static void
1819 cris_extract_return_value (struct type *type, struct regcache *regcache,
1820 gdb_byte *valbuf)
1821 {
1822 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1823 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1824 ULONGEST val;
1825 int len = TYPE_LENGTH (type);
1826
1827 if (len <= 4)
1828 {
1829 /* Get the return value from R10. */
1830 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1831 store_unsigned_integer (valbuf, len, byte_order, val);
1832 }
1833 else if (len <= 8)
1834 {
1835 /* Get the return value from R10 and R11. */
1836 regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val);
1837 store_unsigned_integer (valbuf, 4, byte_order, val);
1838 regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val);
1839 store_unsigned_integer (valbuf + 4, len - 4, byte_order, val);
1840 }
1841 else
1842 error (_("cris_extract_return_value: type length too large"));
1843 }
1844
1845 /* Handle the CRIS return value convention. */
1846
1847 static enum return_value_convention
1848 cris_return_value (struct gdbarch *gdbarch, struct value *function,
1849 struct type *type, struct regcache *regcache,
1850 gdb_byte *readbuf, const gdb_byte *writebuf)
1851 {
1852 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1853 || TYPE_CODE (type) == TYPE_CODE_UNION
1854 || TYPE_LENGTH (type) > 8)
1855 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1856 goes on the stack. */
1857 return RETURN_VALUE_STRUCT_CONVENTION;
1858
1859 if (readbuf)
1860 cris_extract_return_value (type, regcache, readbuf);
1861 if (writebuf)
1862 cris_store_return_value (type, regcache, writebuf);
1863
1864 return RETURN_VALUE_REGISTER_CONVENTION;
1865 }
1866
1867 /* Calculates a value that measures how good inst_args constraints an
1868 instruction. It stems from cris_constraint, found in cris-dis.c. */
1869
1870 static int
1871 constraint (unsigned int insn, const char *inst_args,
1872 inst_env_type *inst_env)
1873 {
1874 int retval = 0;
1875 int tmp, i;
1876
1877 const gdb_byte *s = (const gdb_byte *) inst_args;
1878
1879 for (; *s; s++)
1880 switch (*s)
1881 {
1882 case 'm':
1883 if ((insn & 0x30) == 0x30)
1884 return -1;
1885 break;
1886
1887 case 'S':
1888 /* A prefix operand. */
1889 if (inst_env->prefix_found)
1890 break;
1891 else
1892 return -1;
1893
1894 case 'B':
1895 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1896 valid "push" size. In case of special register, it may be != 4. */
1897 if (inst_env->prefix_found)
1898 break;
1899 else
1900 return -1;
1901
1902 case 'D':
1903 retval = (((insn >> 0xC) & 0xF) == (insn & 0xF));
1904 if (!retval)
1905 return -1;
1906 else
1907 retval += 4;
1908 break;
1909
1910 case 'P':
1911 tmp = (insn >> 0xC) & 0xF;
1912
1913 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1914 {
1915 /* Since we match four bits, we will give a value of
1916 4 - 1 = 3 in a match. If there is a corresponding
1917 exact match of a special register in another pattern, it
1918 will get a value of 4, which will be higher. This should
1919 be correct in that an exact pattern would match better that
1920 a general pattern.
1921 Note that there is a reason for not returning zero; the
1922 pattern for "clear" is partly matched in the bit-pattern
1923 (the two lower bits must be zero), while the bit-pattern
1924 for a move from a special register is matched in the
1925 register constraint.
1926 This also means we will will have a race condition if
1927 there is a partly match in three bits in the bit pattern. */
1928 if (tmp == cris_spec_regs[i].number)
1929 {
1930 retval += 3;
1931 break;
1932 }
1933 }
1934
1935 if (cris_spec_regs[i].name == NULL)
1936 return -1;
1937 break;
1938 }
1939 return retval;
1940 }
1941
1942 /* Returns the number of bits set in the variable value. */
1943
1944 static int
1945 number_of_bits (unsigned int value)
1946 {
1947 int number_of_bits = 0;
1948
1949 while (value != 0)
1950 {
1951 number_of_bits += 1;
1952 value &= (value - 1);
1953 }
1954 return number_of_bits;
1955 }
1956
1957 /* Finds the address that should contain the single step breakpoint(s).
1958 It stems from code in cris-dis.c. */
1959
1960 static int
1961 find_cris_op (unsigned short insn, inst_env_type *inst_env)
1962 {
1963 int i;
1964 int max_level_of_match = -1;
1965 int max_matched = -1;
1966 int level_of_match;
1967
1968 for (i = 0; cris_opcodes[i].name != NULL; i++)
1969 {
1970 if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
1971 && ((cris_opcodes[i].lose & insn) == 0)
1972 /* Only CRISv10 instructions, please. */
1973 && (cris_opcodes[i].applicable_version != cris_ver_v32p))
1974 {
1975 level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
1976 if (level_of_match >= 0)
1977 {
1978 level_of_match +=
1979 number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose);
1980 if (level_of_match > max_level_of_match)
1981 {
1982 max_matched = i;
1983 max_level_of_match = level_of_match;
1984 if (level_of_match == 16)
1985 {
1986 /* All bits matched, cannot find better. */
1987 break;
1988 }
1989 }
1990 }
1991 }
1992 }
1993 return max_matched;
1994 }
1995
1996 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1997 actually an internal error. */
1998
1999 static int
2000 find_step_target (struct frame_info *frame, inst_env_type *inst_env)
2001 {
2002 int i;
2003 int offset;
2004 unsigned short insn;
2005 struct gdbarch *gdbarch = get_frame_arch (frame);
2006 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2007
2008 /* Create a local register image and set the initial state. */
2009 for (i = 0; i < NUM_GENREGS; i++)
2010 {
2011 inst_env->reg[i] =
2012 (unsigned long) get_frame_register_unsigned (frame, i);
2013 }
2014 offset = NUM_GENREGS;
2015 for (i = 0; i < NUM_SPECREGS; i++)
2016 {
2017 inst_env->preg[i] =
2018 (unsigned long) get_frame_register_unsigned (frame, offset + i);
2019 }
2020 inst_env->branch_found = 0;
2021 inst_env->slot_needed = 0;
2022 inst_env->delay_slot_pc_active = 0;
2023 inst_env->prefix_found = 0;
2024 inst_env->invalid = 0;
2025 inst_env->xflag_found = 0;
2026 inst_env->disable_interrupt = 0;
2027 inst_env->byte_order = byte_order;
2028
2029 /* Look for a step target. */
2030 do
2031 {
2032 /* Read an instruction from the client. */
2033 insn = read_memory_unsigned_integer
2034 (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order);
2035
2036 /* If the instruction is not in a delay slot the new content of the
2037 PC is [PC] + 2. If the instruction is in a delay slot it is not
2038 that simple. Since a instruction in a delay slot cannot change
2039 the content of the PC, it does not matter what value PC will have.
2040 Just make sure it is a valid instruction. */
2041 if (!inst_env->delay_slot_pc_active)
2042 {
2043 inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2;
2044 }
2045 else
2046 {
2047 inst_env->delay_slot_pc_active = 0;
2048 inst_env->reg[gdbarch_pc_regnum (gdbarch)]
2049 = inst_env->delay_slot_pc;
2050 }
2051 /* Analyse the present instruction. */
2052 i = find_cris_op (insn, inst_env);
2053 if (i == -1)
2054 {
2055 inst_env->invalid = 1;
2056 }
2057 else
2058 {
2059 cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env);
2060 }
2061 } while (!inst_env->invalid
2062 && (inst_env->prefix_found || inst_env->xflag_found
2063 || inst_env->slot_needed));
2064 return i;
2065 }
2066
2067 /* There is no hardware single-step support. The function find_step_target
2068 digs through the opcodes in order to find all possible targets.
2069 Either one ordinary target or two targets for branches may be found. */
2070
2071 static int
2072 cris_software_single_step (struct frame_info *frame)
2073 {
2074 struct gdbarch *gdbarch = get_frame_arch (frame);
2075 struct address_space *aspace = get_frame_address_space (frame);
2076 inst_env_type inst_env;
2077
2078 /* Analyse the present instruction environment and insert
2079 breakpoints. */
2080 int status = find_step_target (frame, &inst_env);
2081 if (status == -1)
2082 {
2083 /* Could not find a target. Things are likely to go downhill
2084 from here. */
2085 warning (_("CRIS software single step could not find a step target."));
2086 }
2087 else
2088 {
2089 /* Insert at most two breakpoints. One for the next PC content
2090 and possibly another one for a branch, jump, etc. */
2091 CORE_ADDR next_pc
2092 = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
2093 insert_single_step_breakpoint (gdbarch, aspace, next_pc);
2094 if (inst_env.branch_found
2095 && (CORE_ADDR) inst_env.branch_break_address != next_pc)
2096 {
2097 CORE_ADDR branch_target_address
2098 = (CORE_ADDR) inst_env.branch_break_address;
2099 insert_single_step_breakpoint (gdbarch,
2100 aspace, branch_target_address);
2101 }
2102 }
2103
2104 return 1;
2105 }
2106
2107 /* Calculates the prefix value for quick offset addressing mode. */
2108
2109 static void
2110 quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2111 {
2112 /* It's invalid to be in a delay slot. You can't have a prefix to this
2113 instruction (not 100% sure). */
2114 if (inst_env->slot_needed || inst_env->prefix_found)
2115 {
2116 inst_env->invalid = 1;
2117 return;
2118 }
2119
2120 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2121 inst_env->prefix_value += cris_get_bdap_quick_offset (inst);
2122
2123 /* A prefix doesn't change the xflag_found. But the rest of the flags
2124 need updating. */
2125 inst_env->slot_needed = 0;
2126 inst_env->prefix_found = 1;
2127 }
2128
2129 /* Updates the autoincrement register. The size of the increment is derived
2130 from the size of the operation. The PC is always kept aligned on even
2131 word addresses. */
2132
2133 static void
2134 process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
2135 {
2136 if (size == INST_BYTE_SIZE)
2137 {
2138 inst_env->reg[cris_get_operand1 (inst)] += 1;
2139
2140 /* The PC must be word aligned, so increase the PC with one
2141 word even if the size is byte. */
2142 if (cris_get_operand1 (inst) == REG_PC)
2143 {
2144 inst_env->reg[REG_PC] += 1;
2145 }
2146 }
2147 else if (size == INST_WORD_SIZE)
2148 {
2149 inst_env->reg[cris_get_operand1 (inst)] += 2;
2150 }
2151 else if (size == INST_DWORD_SIZE)
2152 {
2153 inst_env->reg[cris_get_operand1 (inst)] += 4;
2154 }
2155 else
2156 {
2157 /* Invalid size. */
2158 inst_env->invalid = 1;
2159 }
2160 }
2161
2162 /* Just a forward declaration. */
2163
2164 static unsigned long get_data_from_address (unsigned short *inst,
2165 CORE_ADDR address,
2166 enum bfd_endian byte_order);
2167
2168 /* Calculates the prefix value for the general case of offset addressing
2169 mode. */
2170
2171 static void
2172 bdap_prefix (unsigned short inst, inst_env_type *inst_env)
2173 {
2174 /* It's invalid to be in a delay slot. */
2175 if (inst_env->slot_needed || inst_env->prefix_found)
2176 {
2177 inst_env->invalid = 1;
2178 return;
2179 }
2180
2181 /* The calculation of prefix_value used to be after process_autoincrement,
2182 but that fails for an instruction such as jsr [$r0+12] which is encoded
2183 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2184 mustn't be incremented until we have read it and what it points at. */
2185 inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)];
2186
2187 /* The offset is an indirection of the contents of the operand1 register. */
2188 inst_env->prefix_value +=
2189 get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)],
2190 inst_env->byte_order);
2191
2192 if (cris_get_mode (inst) == AUTOINC_MODE)
2193 {
2194 process_autoincrement (cris_get_size (inst), inst, inst_env);
2195 }
2196
2197 /* A prefix doesn't change the xflag_found. But the rest of the flags
2198 need updating. */
2199 inst_env->slot_needed = 0;
2200 inst_env->prefix_found = 1;
2201 }
2202
2203 /* Calculates the prefix value for the index addressing mode. */
2204
2205 static void
2206 biap_prefix (unsigned short inst, inst_env_type *inst_env)
2207 {
2208 /* It's invalid to be in a delay slot. I can't see that it's possible to
2209 have a prefix to this instruction. So I will treat this as invalid. */
2210 if (inst_env->slot_needed || inst_env->prefix_found)
2211 {
2212 inst_env->invalid = 1;
2213 return;
2214 }
2215
2216 inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)];
2217
2218 /* The offset is the operand2 value shifted the size of the instruction
2219 to the left. */
2220 inst_env->prefix_value +=
2221 inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst);
2222
2223 /* If the PC is operand1 (base) the address used is the address after
2224 the main instruction, i.e. address + 2 (the PC is already compensated
2225 for the prefix operation). */
2226 if (cris_get_operand1 (inst) == REG_PC)
2227 {
2228 inst_env->prefix_value += 2;
2229 }
2230
2231 /* A prefix doesn't change the xflag_found. But the rest of the flags
2232 need updating. */
2233 inst_env->slot_needed = 0;
2234 inst_env->xflag_found = 0;
2235 inst_env->prefix_found = 1;
2236 }
2237
2238 /* Calculates the prefix value for the double indirect addressing mode. */
2239
2240 static void
2241 dip_prefix (unsigned short inst, inst_env_type *inst_env)
2242 {
2243
2244 CORE_ADDR address;
2245
2246 /* It's invalid to be in a delay slot. */
2247 if (inst_env->slot_needed || inst_env->prefix_found)
2248 {
2249 inst_env->invalid = 1;
2250 return;
2251 }
2252
2253 /* The prefix value is one dereference of the contents of the operand1
2254 register. */
2255 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2256 inst_env->prefix_value
2257 = read_memory_unsigned_integer (address, 4, inst_env->byte_order);
2258
2259 /* Check if the mode is autoincrement. */
2260 if (cris_get_mode (inst) == AUTOINC_MODE)
2261 {
2262 inst_env->reg[cris_get_operand1 (inst)] += 4;
2263 }
2264
2265 /* A prefix doesn't change the xflag_found. But the rest of the flags
2266 need updating. */
2267 inst_env->slot_needed = 0;
2268 inst_env->xflag_found = 0;
2269 inst_env->prefix_found = 1;
2270 }
2271
2272 /* Finds the destination for a branch with 8-bits offset. */
2273
2274 static void
2275 eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2276 {
2277
2278 short offset;
2279
2280 /* If we have a prefix or are in a delay slot it's bad. */
2281 if (inst_env->slot_needed || inst_env->prefix_found)
2282 {
2283 inst_env->invalid = 1;
2284 return;
2285 }
2286
2287 /* We have a branch, find out where the branch will land. */
2288 offset = cris_get_branch_short_offset (inst);
2289
2290 /* Check if the offset is signed. */
2291 if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK)
2292 {
2293 offset |= 0xFF00;
2294 }
2295
2296 /* The offset ends with the sign bit, set it to zero. The address
2297 should always be word aligned. */
2298 offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
2299
2300 inst_env->branch_found = 1;
2301 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2302
2303 inst_env->slot_needed = 1;
2304 inst_env->prefix_found = 0;
2305 inst_env->xflag_found = 0;
2306 inst_env->disable_interrupt = 1;
2307 }
2308
2309 /* Finds the destination for a branch with 16-bits offset. */
2310
2311 static void
2312 sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
2313 {
2314 short offset;
2315
2316 /* If we have a prefix or is in a delay slot it's bad. */
2317 if (inst_env->slot_needed || inst_env->prefix_found)
2318 {
2319 inst_env->invalid = 1;
2320 return;
2321 }
2322
2323 /* We have a branch, find out the offset for the branch. */
2324 offset = read_memory_integer (inst_env->reg[REG_PC], 2,
2325 inst_env->byte_order);
2326
2327 /* The instruction is one word longer than normal, so add one word
2328 to the PC. */
2329 inst_env->reg[REG_PC] += 2;
2330
2331 inst_env->branch_found = 1;
2332 inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
2333
2334
2335 inst_env->slot_needed = 1;
2336 inst_env->prefix_found = 0;
2337 inst_env->xflag_found = 0;
2338 inst_env->disable_interrupt = 1;
2339 }
2340
2341 /* Handles the ABS instruction. */
2342
2343 static void
2344 abs_op (unsigned short inst, inst_env_type *inst_env)
2345 {
2346
2347 long value;
2348
2349 /* ABS can't have a prefix, so it's bad if it does. */
2350 if (inst_env->prefix_found)
2351 {
2352 inst_env->invalid = 1;
2353 return;
2354 }
2355
2356 /* Check if the operation affects the PC. */
2357 if (cris_get_operand2 (inst) == REG_PC)
2358 {
2359
2360 /* It's invalid to change to the PC if we are in a delay slot. */
2361 if (inst_env->slot_needed)
2362 {
2363 inst_env->invalid = 1;
2364 return;
2365 }
2366
2367 value = (long) inst_env->reg[REG_PC];
2368
2369 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2370 if (value != SIGNED_DWORD_MASK)
2371 {
2372 value = -value;
2373 inst_env->reg[REG_PC] = (long) value;
2374 }
2375 }
2376
2377 inst_env->slot_needed = 0;
2378 inst_env->prefix_found = 0;
2379 inst_env->xflag_found = 0;
2380 inst_env->disable_interrupt = 0;
2381 }
2382
2383 /* Handles the ADDI instruction. */
2384
2385 static void
2386 addi_op (unsigned short inst, inst_env_type *inst_env)
2387 {
2388 /* It's invalid to have the PC as base register. And ADDI can't have
2389 a prefix. */
2390 if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
2391 {
2392 inst_env->invalid = 1;
2393 return;
2394 }
2395
2396 inst_env->slot_needed = 0;
2397 inst_env->prefix_found = 0;
2398 inst_env->xflag_found = 0;
2399 inst_env->disable_interrupt = 0;
2400 }
2401
2402 /* Handles the ASR instruction. */
2403
2404 static void
2405 asr_op (unsigned short inst, inst_env_type *inst_env)
2406 {
2407 int shift_steps;
2408 unsigned long value;
2409 unsigned long signed_extend_mask = 0;
2410
2411 /* ASR can't have a prefix, so check that it doesn't. */
2412 if (inst_env->prefix_found)
2413 {
2414 inst_env->invalid = 1;
2415 return;
2416 }
2417
2418 /* Check if the PC is the target register. */
2419 if (cris_get_operand2 (inst) == REG_PC)
2420 {
2421 /* It's invalid to change the PC in a delay slot. */
2422 if (inst_env->slot_needed)
2423 {
2424 inst_env->invalid = 1;
2425 return;
2426 }
2427 /* Get the number of bits to shift. */
2428 shift_steps
2429 = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
2430 value = inst_env->reg[REG_PC];
2431
2432 /* Find out how many bits the operation should apply to. */
2433 if (cris_get_size (inst) == INST_BYTE_SIZE)
2434 {
2435 if (value & SIGNED_BYTE_MASK)
2436 {
2437 signed_extend_mask = 0xFF;
2438 signed_extend_mask = signed_extend_mask >> shift_steps;
2439 signed_extend_mask = ~signed_extend_mask;
2440 }
2441 value = value >> shift_steps;
2442 value |= signed_extend_mask;
2443 value &= 0xFF;
2444 inst_env->reg[REG_PC] &= 0xFFFFFF00;
2445 inst_env->reg[REG_PC] |= value;
2446 }
2447 else if (cris_get_size (inst) == INST_WORD_SIZE)
2448 {
2449 if (value & SIGNED_WORD_MASK)
2450 {
2451 signed_extend_mask = 0xFFFF;
2452 signed_extend_mask = signed_extend_mask >> shift_steps;
2453 signed_extend_mask = ~signed_extend_mask;
2454 }
2455 value = value >> shift_steps;
2456 value |= signed_extend_mask;
2457 value &= 0xFFFF;
2458 inst_env->reg[REG_PC] &= 0xFFFF0000;
2459 inst_env->reg[REG_PC] |= value;
2460 }
2461 else if (cris_get_size (inst) == INST_DWORD_SIZE)
2462 {
2463 if (value & SIGNED_DWORD_MASK)
2464 {
2465 signed_extend_mask = 0xFFFFFFFF;
2466 signed_extend_mask = signed_extend_mask >> shift_steps;
2467 signed_extend_mask = ~signed_extend_mask;
2468 }
2469 value = value >> shift_steps;
2470 value |= signed_extend_mask;
2471 inst_env->reg[REG_PC] = value;
2472 }
2473 }
2474 inst_env->slot_needed = 0;
2475 inst_env->prefix_found = 0;
2476 inst_env->xflag_found = 0;
2477 inst_env->disable_interrupt = 0;
2478 }
2479
2480 /* Handles the ASRQ instruction. */
2481
2482 static void
2483 asrq_op (unsigned short inst, inst_env_type *inst_env)
2484 {
2485
2486 int shift_steps;
2487 unsigned long value;
2488 unsigned long signed_extend_mask = 0;
2489
2490 /* ASRQ can't have a prefix, so check that it doesn't. */
2491 if (inst_env->prefix_found)
2492 {
2493 inst_env->invalid = 1;
2494 return;
2495 }
2496
2497 /* Check if the PC is the target register. */
2498 if (cris_get_operand2 (inst) == REG_PC)
2499 {
2500
2501 /* It's invalid to change the PC in a delay slot. */
2502 if (inst_env->slot_needed)
2503 {
2504 inst_env->invalid = 1;
2505 return;
2506 }
2507 /* The shift size is given as a 5 bit quick value, i.e. we don't
2508 want the sign bit of the quick value. */
2509 shift_steps = cris_get_asr_shift_steps (inst);
2510 value = inst_env->reg[REG_PC];
2511 if (value & SIGNED_DWORD_MASK)
2512 {
2513 signed_extend_mask = 0xFFFFFFFF;
2514 signed_extend_mask = signed_extend_mask >> shift_steps;
2515 signed_extend_mask = ~signed_extend_mask;
2516 }
2517 value = value >> shift_steps;
2518 value |= signed_extend_mask;
2519 inst_env->reg[REG_PC] = value;
2520 }
2521 inst_env->slot_needed = 0;
2522 inst_env->prefix_found = 0;
2523 inst_env->xflag_found = 0;
2524 inst_env->disable_interrupt = 0;
2525 }
2526
2527 /* Handles the AX, EI and SETF instruction. */
2528
2529 static void
2530 ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env)
2531 {
2532 if (inst_env->prefix_found)
2533 {
2534 inst_env->invalid = 1;
2535 return;
2536 }
2537 /* Check if the instruction is setting the X flag. */
2538 if (cris_is_xflag_bit_on (inst))
2539 {
2540 inst_env->xflag_found = 1;
2541 }
2542 else
2543 {
2544 inst_env->xflag_found = 0;
2545 }
2546 inst_env->slot_needed = 0;
2547 inst_env->prefix_found = 0;
2548 inst_env->disable_interrupt = 1;
2549 }
2550
2551 /* Checks if the instruction is in assign mode. If so, it updates the assign
2552 register. Note that check_assign assumes that the caller has checked that
2553 there is a prefix to this instruction. The mode check depends on this. */
2554
2555 static void
2556 check_assign (unsigned short inst, inst_env_type *inst_env)
2557 {
2558 /* Check if it's an assign addressing mode. */
2559 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2560 {
2561 /* Assign the prefix value to operand 1. */
2562 inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value;
2563 }
2564 }
2565
2566 /* Handles the 2-operand BOUND instruction. */
2567
2568 static void
2569 two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2570 {
2571 /* It's invalid to have the PC as the index operand. */
2572 if (cris_get_operand2 (inst) == REG_PC)
2573 {
2574 inst_env->invalid = 1;
2575 return;
2576 }
2577 /* Check if we have a prefix. */
2578 if (inst_env->prefix_found)
2579 {
2580 check_assign (inst, inst_env);
2581 }
2582 /* Check if this is an autoincrement mode. */
2583 else if (cris_get_mode (inst) == AUTOINC_MODE)
2584 {
2585 /* It's invalid to change the PC in a delay slot. */
2586 if (inst_env->slot_needed)
2587 {
2588 inst_env->invalid = 1;
2589 return;
2590 }
2591 process_autoincrement (cris_get_size (inst), inst, inst_env);
2592 }
2593 inst_env->slot_needed = 0;
2594 inst_env->prefix_found = 0;
2595 inst_env->xflag_found = 0;
2596 inst_env->disable_interrupt = 0;
2597 }
2598
2599 /* Handles the 3-operand BOUND instruction. */
2600
2601 static void
2602 three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
2603 {
2604 /* It's an error if we haven't got a prefix. And it's also an error
2605 if the PC is the destination register. */
2606 if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
2607 {
2608 inst_env->invalid = 1;
2609 return;
2610 }
2611 inst_env->slot_needed = 0;
2612 inst_env->prefix_found = 0;
2613 inst_env->xflag_found = 0;
2614 inst_env->disable_interrupt = 0;
2615 }
2616
2617 /* Clears the status flags in inst_env. */
2618
2619 static void
2620 btst_nop_op (unsigned short inst, inst_env_type *inst_env)
2621 {
2622 /* It's an error if we have got a prefix. */
2623 if (inst_env->prefix_found)
2624 {
2625 inst_env->invalid = 1;
2626 return;
2627 }
2628
2629 inst_env->slot_needed = 0;
2630 inst_env->prefix_found = 0;
2631 inst_env->xflag_found = 0;
2632 inst_env->disable_interrupt = 0;
2633 }
2634
2635 /* Clears the status flags in inst_env. */
2636
2637 static void
2638 clearf_di_op (unsigned short inst, inst_env_type *inst_env)
2639 {
2640 /* It's an error if we have got a prefix. */
2641 if (inst_env->prefix_found)
2642 {
2643 inst_env->invalid = 1;
2644 return;
2645 }
2646
2647 inst_env->slot_needed = 0;
2648 inst_env->prefix_found = 0;
2649 inst_env->xflag_found = 0;
2650 inst_env->disable_interrupt = 1;
2651 }
2652
2653 /* Handles the CLEAR instruction if it's in register mode. */
2654
2655 static void
2656 reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
2657 {
2658 /* Check if the target is the PC. */
2659 if (cris_get_operand2 (inst) == REG_PC)
2660 {
2661 /* The instruction will clear the instruction's size bits. */
2662 int clear_size = cris_get_clear_size (inst);
2663 if (clear_size == INST_BYTE_SIZE)
2664 {
2665 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
2666 }
2667 if (clear_size == INST_WORD_SIZE)
2668 {
2669 inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
2670 }
2671 if (clear_size == INST_DWORD_SIZE)
2672 {
2673 inst_env->delay_slot_pc = 0x0;
2674 }
2675 /* The jump will be delayed with one delay slot. So we need a delay
2676 slot. */
2677 inst_env->slot_needed = 1;
2678 inst_env->delay_slot_pc_active = 1;
2679 }
2680 else
2681 {
2682 /* The PC will not change => no delay slot. */
2683 inst_env->slot_needed = 0;
2684 }
2685 inst_env->prefix_found = 0;
2686 inst_env->xflag_found = 0;
2687 inst_env->disable_interrupt = 0;
2688 }
2689
2690 /* Handles the TEST instruction if it's in register mode. */
2691
2692 static void
2693 reg_mode_test_op (unsigned short inst, inst_env_type *inst_env)
2694 {
2695 /* It's an error if we have got a prefix. */
2696 if (inst_env->prefix_found)
2697 {
2698 inst_env->invalid = 1;
2699 return;
2700 }
2701 inst_env->slot_needed = 0;
2702 inst_env->prefix_found = 0;
2703 inst_env->xflag_found = 0;
2704 inst_env->disable_interrupt = 0;
2705
2706 }
2707
2708 /* Handles the CLEAR and TEST instruction if the instruction isn't
2709 in register mode. */
2710
2711 static void
2712 none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env)
2713 {
2714 /* Check if we are in a prefix mode. */
2715 if (inst_env->prefix_found)
2716 {
2717 /* The only way the PC can change is if this instruction is in
2718 assign addressing mode. */
2719 check_assign (inst, inst_env);
2720 }
2721 /* Indirect mode can't change the PC so just check if the mode is
2722 autoincrement. */
2723 else if (cris_get_mode (inst) == AUTOINC_MODE)
2724 {
2725 process_autoincrement (cris_get_size (inst), inst, inst_env);
2726 }
2727 inst_env->slot_needed = 0;
2728 inst_env->prefix_found = 0;
2729 inst_env->xflag_found = 0;
2730 inst_env->disable_interrupt = 0;
2731 }
2732
2733 /* Checks that the PC isn't the destination register or the instructions has
2734 a prefix. */
2735
2736 static void
2737 dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
2738 {
2739 /* It's invalid to have the PC as the destination. The instruction can't
2740 have a prefix. */
2741 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2742 {
2743 inst_env->invalid = 1;
2744 return;
2745 }
2746
2747 inst_env->slot_needed = 0;
2748 inst_env->prefix_found = 0;
2749 inst_env->xflag_found = 0;
2750 inst_env->disable_interrupt = 0;
2751 }
2752
2753 /* Checks that the instruction doesn't have a prefix. */
2754
2755 static void
2756 break_op (unsigned short inst, inst_env_type *inst_env)
2757 {
2758 /* The instruction can't have a prefix. */
2759 if (inst_env->prefix_found)
2760 {
2761 inst_env->invalid = 1;
2762 return;
2763 }
2764
2765 inst_env->slot_needed = 0;
2766 inst_env->prefix_found = 0;
2767 inst_env->xflag_found = 0;
2768 inst_env->disable_interrupt = 1;
2769 }
2770
2771 /* Checks that the PC isn't the destination register and that the instruction
2772 doesn't have a prefix. */
2773
2774 static void
2775 scc_op (unsigned short inst, inst_env_type *inst_env)
2776 {
2777 /* It's invalid to have the PC as the destination. The instruction can't
2778 have a prefix. */
2779 if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
2780 {
2781 inst_env->invalid = 1;
2782 return;
2783 }
2784
2785 inst_env->slot_needed = 0;
2786 inst_env->prefix_found = 0;
2787 inst_env->xflag_found = 0;
2788 inst_env->disable_interrupt = 1;
2789 }
2790
2791 /* Handles the register mode JUMP instruction. */
2792
2793 static void
2794 reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2795 {
2796 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2797 you can't have a prefix. */
2798 if ((inst_env->slot_needed) || (inst_env->prefix_found))
2799 {
2800 inst_env->invalid = 1;
2801 return;
2802 }
2803
2804 /* Just change the PC. */
2805 inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
2806 inst_env->slot_needed = 0;
2807 inst_env->prefix_found = 0;
2808 inst_env->xflag_found = 0;
2809 inst_env->disable_interrupt = 1;
2810 }
2811
2812 /* Handles the JUMP instruction for all modes except register. */
2813
2814 static void
2815 none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
2816 {
2817 unsigned long newpc;
2818 CORE_ADDR address;
2819
2820 /* It's invalid to do a JUMP in a delay slot. */
2821 if (inst_env->slot_needed)
2822 {
2823 inst_env->invalid = 1;
2824 }
2825 else
2826 {
2827 /* Check if we have a prefix. */
2828 if (inst_env->prefix_found)
2829 {
2830 check_assign (inst, inst_env);
2831
2832 /* Get the new value for the PC. */
2833 newpc =
2834 read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value,
2835 4, inst_env->byte_order);
2836 }
2837 else
2838 {
2839 /* Get the new value for the PC. */
2840 address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)];
2841 newpc = read_memory_unsigned_integer (address,
2842 4, inst_env->byte_order);
2843
2844 /* Check if we should increment a register. */
2845 if (cris_get_mode (inst) == AUTOINC_MODE)
2846 {
2847 inst_env->reg[cris_get_operand1 (inst)] += 4;
2848 }
2849 }
2850 inst_env->reg[REG_PC] = newpc;
2851 }
2852 inst_env->slot_needed = 0;
2853 inst_env->prefix_found = 0;
2854 inst_env->xflag_found = 0;
2855 inst_env->disable_interrupt = 1;
2856 }
2857
2858 /* Handles moves to special registers (aka P-register) for all modes. */
2859
2860 static void
2861 move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2862 inst_env_type *inst_env)
2863 {
2864 if (inst_env->prefix_found)
2865 {
2866 /* The instruction has a prefix that means we are only interested if
2867 the instruction is in assign mode. */
2868 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2869 {
2870 /* The prefix handles the problem if we are in a delay slot. */
2871 if (cris_get_operand1 (inst) == REG_PC)
2872 {
2873 /* Just take care of the assign. */
2874 check_assign (inst, inst_env);
2875 }
2876 }
2877 }
2878 else if (cris_get_mode (inst) == AUTOINC_MODE)
2879 {
2880 /* The instruction doesn't have a prefix, the only case left that we
2881 are interested in is the autoincrement mode. */
2882 if (cris_get_operand1 (inst) == REG_PC)
2883 {
2884 /* If the PC is to be incremented it's invalid to be in a
2885 delay slot. */
2886 if (inst_env->slot_needed)
2887 {
2888 inst_env->invalid = 1;
2889 return;
2890 }
2891
2892 /* The increment depends on the size of the special register. */
2893 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2894 {
2895 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2896 }
2897 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2898 {
2899 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2900 }
2901 else
2902 {
2903 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2904 }
2905 }
2906 }
2907 inst_env->slot_needed = 0;
2908 inst_env->prefix_found = 0;
2909 inst_env->xflag_found = 0;
2910 inst_env->disable_interrupt = 1;
2911 }
2912
2913 /* Handles moves from special registers (aka P-register) for all modes
2914 except register. */
2915
2916 static void
2917 none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
2918 inst_env_type *inst_env)
2919 {
2920 if (inst_env->prefix_found)
2921 {
2922 /* The instruction has a prefix that means we are only interested if
2923 the instruction is in assign mode. */
2924 if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
2925 {
2926 /* The prefix handles the problem if we are in a delay slot. */
2927 if (cris_get_operand1 (inst) == REG_PC)
2928 {
2929 /* Just take care of the assign. */
2930 check_assign (inst, inst_env);
2931 }
2932 }
2933 }
2934 /* The instruction doesn't have a prefix, the only case left that we
2935 are interested in is the autoincrement mode. */
2936 else if (cris_get_mode (inst) == AUTOINC_MODE)
2937 {
2938 if (cris_get_operand1 (inst) == REG_PC)
2939 {
2940 /* If the PC is to be incremented it's invalid to be in a
2941 delay slot. */
2942 if (inst_env->slot_needed)
2943 {
2944 inst_env->invalid = 1;
2945 return;
2946 }
2947
2948 /* The increment depends on the size of the special register. */
2949 if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1)
2950 {
2951 process_autoincrement (INST_BYTE_SIZE, inst, inst_env);
2952 }
2953 else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2)
2954 {
2955 process_autoincrement (INST_WORD_SIZE, inst, inst_env);
2956 }
2957 else
2958 {
2959 process_autoincrement (INST_DWORD_SIZE, inst, inst_env);
2960 }
2961 }
2962 }
2963 inst_env->slot_needed = 0;
2964 inst_env->prefix_found = 0;
2965 inst_env->xflag_found = 0;
2966 inst_env->disable_interrupt = 1;
2967 }
2968
2969 /* Handles moves from special registers (aka P-register) when the mode
2970 is register. */
2971
2972 static void
2973 reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
2974 {
2975 /* Register mode move from special register can't have a prefix. */
2976 if (inst_env->prefix_found)
2977 {
2978 inst_env->invalid = 1;
2979 return;
2980 }
2981
2982 if (cris_get_operand1 (inst) == REG_PC)
2983 {
2984 /* It's invalid to change the PC in a delay slot. */
2985 if (inst_env->slot_needed)
2986 {
2987 inst_env->invalid = 1;
2988 return;
2989 }
2990 /* The destination is the PC, the jump will have a delay slot. */
2991 inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)];
2992 inst_env->slot_needed = 1;
2993 inst_env->delay_slot_pc_active = 1;
2994 }
2995 else
2996 {
2997 /* If the destination isn't PC, there will be no jump. */
2998 inst_env->slot_needed = 0;
2999 }
3000 inst_env->prefix_found = 0;
3001 inst_env->xflag_found = 0;
3002 inst_env->disable_interrupt = 1;
3003 }
3004
3005 /* Handles the MOVEM from memory to general register instruction. */
3006
3007 static void
3008 move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
3009 {
3010 if (inst_env->prefix_found)
3011 {
3012 /* The prefix handles the problem if we are in a delay slot. Is the
3013 MOVEM instruction going to change the PC? */
3014 if (cris_get_operand2 (inst) >= REG_PC)
3015 {
3016 inst_env->reg[REG_PC] =
3017 read_memory_unsigned_integer (inst_env->prefix_value,
3018 4, inst_env->byte_order);
3019 }
3020 /* The assign value is the value after the increment. Normally, the
3021 assign value is the value before the increment. */
3022 if ((cris_get_operand1 (inst) == REG_PC)
3023 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3024 {
3025 inst_env->reg[REG_PC] = inst_env->prefix_value;
3026 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3027 }
3028 }
3029 else
3030 {
3031 /* Is the MOVEM instruction going to change the PC? */
3032 if (cris_get_operand2 (inst) == REG_PC)
3033 {
3034 /* It's invalid to change the PC in a delay slot. */
3035 if (inst_env->slot_needed)
3036 {
3037 inst_env->invalid = 1;
3038 return;
3039 }
3040 inst_env->reg[REG_PC] =
3041 read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
3042 4, inst_env->byte_order);
3043 }
3044 /* The increment is not depending on the size, instead it's depending
3045 on the number of registers loaded from memory. */
3046 if ((cris_get_operand1 (inst) == REG_PC)
3047 && (cris_get_mode (inst) == AUTOINC_MODE))
3048 {
3049 /* It's invalid to change the PC in a delay slot. */
3050 if (inst_env->slot_needed)
3051 {
3052 inst_env->invalid = 1;
3053 return;
3054 }
3055 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3056 }
3057 }
3058 inst_env->slot_needed = 0;
3059 inst_env->prefix_found = 0;
3060 inst_env->xflag_found = 0;
3061 inst_env->disable_interrupt = 0;
3062 }
3063
3064 /* Handles the MOVEM to memory from general register instruction. */
3065
3066 static void
3067 move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
3068 {
3069 if (inst_env->prefix_found)
3070 {
3071 /* The assign value is the value after the increment. Normally, the
3072 assign value is the value before the increment. */
3073 if ((cris_get_operand1 (inst) == REG_PC)
3074 && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
3075 {
3076 /* The prefix handles the problem if we are in a delay slot. */
3077 inst_env->reg[REG_PC] = inst_env->prefix_value;
3078 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3079 }
3080 }
3081 else
3082 {
3083 /* The increment is not depending on the size, instead it's depending
3084 on the number of registers loaded to memory. */
3085 if ((cris_get_operand1 (inst) == REG_PC)
3086 && (cris_get_mode (inst) == AUTOINC_MODE))
3087 {
3088 /* It's invalid to change the PC in a delay slot. */
3089 if (inst_env->slot_needed)
3090 {
3091 inst_env->invalid = 1;
3092 return;
3093 }
3094 inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
3095 }
3096 }
3097 inst_env->slot_needed = 0;
3098 inst_env->prefix_found = 0;
3099 inst_env->xflag_found = 0;
3100 inst_env->disable_interrupt = 0;
3101 }
3102
3103 /* Handles the intructions that's not yet implemented, by setting
3104 inst_env->invalid to true. */
3105
3106 static void
3107 not_implemented_op (unsigned short inst, inst_env_type *inst_env)
3108 {
3109 inst_env->invalid = 1;
3110 }
3111
3112 /* Handles the XOR instruction. */
3113
3114 static void
3115 xor_op (unsigned short inst, inst_env_type *inst_env)
3116 {
3117 /* XOR can't have a prefix. */
3118 if (inst_env->prefix_found)
3119 {
3120 inst_env->invalid = 1;
3121 return;
3122 }
3123
3124 /* Check if the PC is the target. */
3125 if (cris_get_operand2 (inst) == REG_PC)
3126 {
3127 /* It's invalid to change the PC in a delay slot. */
3128 if (inst_env->slot_needed)
3129 {
3130 inst_env->invalid = 1;
3131 return;
3132 }
3133 inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
3134 }
3135 inst_env->slot_needed = 0;
3136 inst_env->prefix_found = 0;
3137 inst_env->xflag_found = 0;
3138 inst_env->disable_interrupt = 0;
3139 }
3140
3141 /* Handles the MULS instruction. */
3142
3143 static void
3144 muls_op (unsigned short inst, inst_env_type *inst_env)
3145 {
3146 /* MULS/U can't have a prefix. */
3147 if (inst_env->prefix_found)
3148 {
3149 inst_env->invalid = 1;
3150 return;
3151 }
3152
3153 /* Consider it invalid if the PC is the target. */
3154 if (cris_get_operand2 (inst) == REG_PC)
3155 {
3156 inst_env->invalid = 1;
3157 return;
3158 }
3159 inst_env->slot_needed = 0;
3160 inst_env->prefix_found = 0;
3161 inst_env->xflag_found = 0;
3162 inst_env->disable_interrupt = 0;
3163 }
3164
3165 /* Handles the MULU instruction. */
3166
3167 static void
3168 mulu_op (unsigned short inst, inst_env_type *inst_env)
3169 {
3170 /* MULS/U can't have a prefix. */
3171 if (inst_env->prefix_found)
3172 {
3173 inst_env->invalid = 1;
3174 return;
3175 }
3176
3177 /* Consider it invalid if the PC is the target. */
3178 if (cris_get_operand2 (inst) == REG_PC)
3179 {
3180 inst_env->invalid = 1;
3181 return;
3182 }
3183 inst_env->slot_needed = 0;
3184 inst_env->prefix_found = 0;
3185 inst_env->xflag_found = 0;
3186 inst_env->disable_interrupt = 0;
3187 }
3188
3189 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3190 The MOVE instruction is the move from source to register. */
3191
3192 static void
3193 add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
3194 unsigned long source1, unsigned long source2)
3195 {
3196 unsigned long pc_mask;
3197 unsigned long operation_mask;
3198
3199 /* Find out how many bits the operation should apply to. */
3200 if (cris_get_size (inst) == INST_BYTE_SIZE)
3201 {
3202 pc_mask = 0xFFFFFF00;
3203 operation_mask = 0xFF;
3204 }
3205 else if (cris_get_size (inst) == INST_WORD_SIZE)
3206 {
3207 pc_mask = 0xFFFF0000;
3208 operation_mask = 0xFFFF;
3209 }
3210 else if (cris_get_size (inst) == INST_DWORD_SIZE)
3211 {
3212 pc_mask = 0x0;
3213 operation_mask = 0xFFFFFFFF;
3214 }
3215 else
3216 {
3217 /* The size is out of range. */
3218 inst_env->invalid = 1;
3219 return;
3220 }
3221
3222 /* The instruction just works on uw_operation_mask bits. */
3223 source2 &= operation_mask;
3224 source1 &= operation_mask;
3225
3226 /* Now calculate the result. The opcode's 3 first bits separates
3227 the different actions. */
3228 switch (cris_get_opcode (inst) & 7)
3229 {
3230 case 0: /* add */
3231 source1 += source2;
3232 break;
3233
3234 case 1: /* move */
3235 source1 = source2;
3236 break;
3237
3238 case 2: /* subtract */
3239 source1 -= source2;
3240 break;
3241
3242 case 3: /* compare */
3243 break;
3244
3245 case 4: /* and */
3246 source1 &= source2;
3247 break;
3248
3249 case 5: /* or */
3250 source1 |= source2;
3251 break;
3252
3253 default:
3254 inst_env->invalid = 1;
3255 return;
3256
3257 break;
3258 }
3259
3260 /* Make sure that the result doesn't contain more than the instruction
3261 size bits. */
3262 source2 &= operation_mask;
3263
3264 /* Calculate the new breakpoint address. */
3265 inst_env->reg[REG_PC] &= pc_mask;
3266 inst_env->reg[REG_PC] |= source1;
3267
3268 }
3269
3270 /* Extends the value from either byte or word size to a dword. If the mode
3271 is zero extend then the value is extended with zero. If instead the mode
3272 is signed extend the sign bit of the value is taken into consideration. */
3273
3274 static unsigned long
3275 do_sign_or_zero_extend (unsigned long value, unsigned short *inst)
3276 {
3277 /* The size can be either byte or word, check which one it is.
3278 Don't check the highest bit, it's indicating if it's a zero
3279 or sign extend. */
3280 if (cris_get_size (*inst) & INST_WORD_SIZE)
3281 {
3282 /* Word size. */
3283 value &= 0xFFFF;
3284
3285 /* Check if the instruction is signed extend. If so, check if value has
3286 the sign bit on. */
3287 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK))
3288 {
3289 value |= SIGNED_WORD_EXTEND_MASK;
3290 }
3291 }
3292 else
3293 {
3294 /* Byte size. */
3295 value &= 0xFF;
3296
3297 /* Check if the instruction is signed extend. If so, check if value has
3298 the sign bit on. */
3299 if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK))
3300 {
3301 value |= SIGNED_BYTE_EXTEND_MASK;
3302 }
3303 }
3304 /* The size should now be dword. */
3305 cris_set_size_to_dword (inst);
3306 return value;
3307 }
3308
3309 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3310 instruction. The MOVE instruction is the move from source to register. */
3311
3312 static void
3313 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3314 inst_env_type *inst_env)
3315 {
3316 unsigned long operand1;
3317 unsigned long operand2;
3318
3319 /* It's invalid to have a prefix to the instruction. This is a register
3320 mode instruction and can't have a prefix. */
3321 if (inst_env->prefix_found)
3322 {
3323 inst_env->invalid = 1;
3324 return;
3325 }
3326 /* Check if the instruction has PC as its target. */
3327 if (cris_get_operand2 (inst) == REG_PC)
3328 {
3329 if (inst_env->slot_needed)
3330 {
3331 inst_env->invalid = 1;
3332 return;
3333 }
3334 /* The instruction has the PC as its target register. */
3335 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3336 operand2 = inst_env->reg[REG_PC];
3337
3338 /* Check if it's a extend, signed or zero instruction. */
3339 if (cris_get_opcode (inst) < 4)
3340 {
3341 operand1 = do_sign_or_zero_extend (operand1, &inst);
3342 }
3343 /* Calculate the PC value after the instruction, i.e. where the
3344 breakpoint should be. The order of the udw_operands is vital. */
3345 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3346 }
3347 inst_env->slot_needed = 0;
3348 inst_env->prefix_found = 0;
3349 inst_env->xflag_found = 0;
3350 inst_env->disable_interrupt = 0;
3351 }
3352
3353 /* Returns the data contained at address. The size of the data is derived from
3354 the size of the operation. If the instruction is a zero or signed
3355 extend instruction, the size field is changed in instruction. */
3356
3357 static unsigned long
3358 get_data_from_address (unsigned short *inst, CORE_ADDR address,
3359 enum bfd_endian byte_order)
3360 {
3361 int size = cris_get_size (*inst);
3362 unsigned long value;
3363
3364 /* If it's an extend instruction we don't want the signed extend bit,
3365 because it influences the size. */
3366 if (cris_get_opcode (*inst) < 4)
3367 {
3368 size &= ~SIGNED_EXTEND_BIT_MASK;
3369 }
3370 /* Is there a need for checking the size? Size should contain the number of
3371 bytes to read. */
3372 size = 1 << size;
3373 value = read_memory_unsigned_integer (address, size, byte_order);
3374
3375 /* Check if it's an extend, signed or zero instruction. */
3376 if (cris_get_opcode (*inst) < 4)
3377 {
3378 value = do_sign_or_zero_extend (value, inst);
3379 }
3380 return value;
3381 }
3382
3383 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3384 instructions. The MOVE instruction is the move from source to register. */
3385
3386 static void
3387 handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
3388 inst_env_type *inst_env)
3389 {
3390 unsigned long operand2;
3391 unsigned long operand3;
3392
3393 check_assign (inst, inst_env);
3394 if (cris_get_operand2 (inst) == REG_PC)
3395 {
3396 operand2 = inst_env->reg[REG_PC];
3397
3398 /* Get the value of the third operand. */
3399 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3400 inst_env->byte_order);
3401
3402 /* Calculate the PC value after the instruction, i.e. where the
3403 breakpoint should be. The order of the udw_operands is vital. */
3404 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3405 }
3406 inst_env->slot_needed = 0;
3407 inst_env->prefix_found = 0;
3408 inst_env->xflag_found = 0;
3409 inst_env->disable_interrupt = 0;
3410 }
3411
3412 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3413 OR instructions. Note that for this to work as expected, the calling
3414 function must have made sure that there is a prefix to this instruction. */
3415
3416 static void
3417 three_operand_add_sub_cmp_and_or_op (unsigned short inst,
3418 inst_env_type *inst_env)
3419 {
3420 unsigned long operand2;
3421 unsigned long operand3;
3422
3423 if (cris_get_operand1 (inst) == REG_PC)
3424 {
3425 /* The PC will be changed by the instruction. */
3426 operand2 = inst_env->reg[cris_get_operand2 (inst)];
3427
3428 /* Get the value of the third operand. */
3429 operand3 = get_data_from_address (&inst, inst_env->prefix_value,
3430 inst_env->byte_order);
3431
3432 /* Calculate the PC value after the instruction, i.e. where the
3433 breakpoint should be. */
3434 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3435 }
3436 inst_env->slot_needed = 0;
3437 inst_env->prefix_found = 0;
3438 inst_env->xflag_found = 0;
3439 inst_env->disable_interrupt = 0;
3440 }
3441
3442 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3443 instructions. The MOVE instruction is the move from source to register. */
3444
3445 static void
3446 handle_prefix_index_mode_for_aritm_op (unsigned short inst,
3447 inst_env_type *inst_env)
3448 {
3449 if (cris_get_operand1 (inst) != cris_get_operand2 (inst))
3450 {
3451 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3452 SUB, AND or OR something weird is going on (if everything works these
3453 instructions should end up in the three operand version). */
3454 inst_env->invalid = 1;
3455 return;
3456 }
3457 else
3458 {
3459 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3460 so use it. */
3461 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3462 }
3463 inst_env->slot_needed = 0;
3464 inst_env->prefix_found = 0;
3465 inst_env->xflag_found = 0;
3466 inst_env->disable_interrupt = 0;
3467 }
3468
3469 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3470 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3471 source to register. */
3472
3473 static void
3474 handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
3475 inst_env_type *inst_env)
3476 {
3477 unsigned long operand1;
3478 unsigned long operand2;
3479 unsigned long operand3;
3480 int size;
3481
3482 /* The instruction is either an indirect or autoincrement addressing mode.
3483 Check if the destination register is the PC. */
3484 if (cris_get_operand2 (inst) == REG_PC)
3485 {
3486 /* Must be done here, get_data_from_address may change the size
3487 field. */
3488 size = cris_get_size (inst);
3489 operand2 = inst_env->reg[REG_PC];
3490
3491 /* Get the value of the third operand, i.e. the indirect operand. */
3492 operand1 = inst_env->reg[cris_get_operand1 (inst)];
3493 operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order);
3494
3495 /* Calculate the PC value after the instruction, i.e. where the
3496 breakpoint should be. The order of the udw_operands is vital. */
3497 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3);
3498 }
3499 /* If this is an autoincrement addressing mode, check if the increment
3500 changes the PC. */
3501 if ((cris_get_operand1 (inst) == REG_PC)
3502 && (cris_get_mode (inst) == AUTOINC_MODE))
3503 {
3504 /* Get the size field. */
3505 size = cris_get_size (inst);
3506
3507 /* If it's an extend instruction we don't want the signed extend bit,
3508 because it influences the size. */
3509 if (cris_get_opcode (inst) < 4)
3510 {
3511 size &= ~SIGNED_EXTEND_BIT_MASK;
3512 }
3513 process_autoincrement (size, inst, inst_env);
3514 }
3515 inst_env->slot_needed = 0;
3516 inst_env->prefix_found = 0;
3517 inst_env->xflag_found = 0;
3518 inst_env->disable_interrupt = 0;
3519 }
3520
3521 /* Handles the two-operand addressing mode, all modes except register, for
3522 the ADD, SUB CMP, AND and OR instruction. */
3523
3524 static void
3525 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
3526 inst_env_type *inst_env)
3527 {
3528 if (inst_env->prefix_found)
3529 {
3530 if (cris_get_mode (inst) == PREFIX_INDEX_MODE)
3531 {
3532 handle_prefix_index_mode_for_aritm_op (inst, inst_env);
3533 }
3534 else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
3535 {
3536 handle_prefix_assign_mode_for_aritm_op (inst, inst_env);
3537 }
3538 else
3539 {
3540 /* The mode is invalid for a prefixed base instruction. */
3541 inst_env->invalid = 1;
3542 return;
3543 }
3544 }
3545 else
3546 {
3547 handle_inc_and_index_mode_for_aritm_op (inst, inst_env);
3548 }
3549 }
3550
3551 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3552
3553 static void
3554 quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
3555 {
3556 unsigned long operand1;
3557 unsigned long operand2;
3558
3559 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3560 instruction and can't have a prefix. */
3561 if (inst_env->prefix_found)
3562 {
3563 inst_env->invalid = 1;
3564 return;
3565 }
3566
3567 /* Check if the instruction has PC as its target. */
3568 if (cris_get_operand2 (inst) == REG_PC)
3569 {
3570 if (inst_env->slot_needed)
3571 {
3572 inst_env->invalid = 1;
3573 return;
3574 }
3575 operand1 = cris_get_quick_value (inst);
3576 operand2 = inst_env->reg[REG_PC];
3577
3578 /* The size should now be dword. */
3579 cris_set_size_to_dword (&inst);
3580
3581 /* Calculate the PC value after the instruction, i.e. where the
3582 breakpoint should be. */
3583 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3584 }
3585 inst_env->slot_needed = 0;
3586 inst_env->prefix_found = 0;
3587 inst_env->xflag_found = 0;
3588 inst_env->disable_interrupt = 0;
3589 }
3590
3591 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3592
3593 static void
3594 quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
3595 {
3596 unsigned long operand1;
3597 unsigned long operand2;
3598
3599 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3600 instruction and can't have a prefix. */
3601 if (inst_env->prefix_found)
3602 {
3603 inst_env->invalid = 1;
3604 return;
3605 }
3606 /* Check if the instruction has PC as its target. */
3607 if (cris_get_operand2 (inst) == REG_PC)
3608 {
3609 if (inst_env->slot_needed)
3610 {
3611 inst_env->invalid = 1;
3612 return;
3613 }
3614 /* The instruction has the PC as its target register. */
3615 operand1 = cris_get_quick_value (inst);
3616 operand2 = inst_env->reg[REG_PC];
3617
3618 /* The quick value is signed, so check if we must do a signed extend. */
3619 if (operand1 & SIGNED_QUICK_VALUE_MASK)
3620 {
3621 /* sign extend */
3622 operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK;
3623 }
3624 /* The size should now be dword. */
3625 cris_set_size_to_dword (&inst);
3626
3627 /* Calculate the PC value after the instruction, i.e. where the
3628 breakpoint should be. */
3629 add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1);
3630 }
3631 inst_env->slot_needed = 0;
3632 inst_env->prefix_found = 0;
3633 inst_env->xflag_found = 0;
3634 inst_env->disable_interrupt = 0;
3635 }
3636
3637 /* Translate op_type to a function and call it. */
3638
3639 static void
3640 cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type,
3641 unsigned short inst, inst_env_type *inst_env)
3642 {
3643 switch (op_type)
3644 {
3645 case cris_not_implemented_op:
3646 not_implemented_op (inst, inst_env);
3647 break;
3648
3649 case cris_abs_op:
3650 abs_op (inst, inst_env);
3651 break;
3652
3653 case cris_addi_op:
3654 addi_op (inst, inst_env);
3655 break;
3656
3657 case cris_asr_op:
3658 asr_op (inst, inst_env);
3659 break;
3660
3661 case cris_asrq_op:
3662 asrq_op (inst, inst_env);
3663 break;
3664
3665 case cris_ax_ei_setf_op:
3666 ax_ei_setf_op (inst, inst_env);
3667 break;
3668
3669 case cris_bdap_prefix:
3670 bdap_prefix (inst, inst_env);
3671 break;
3672
3673 case cris_biap_prefix:
3674 biap_prefix (inst, inst_env);
3675 break;
3676
3677 case cris_break_op:
3678 break_op (inst, inst_env);
3679 break;
3680
3681 case cris_btst_nop_op:
3682 btst_nop_op (inst, inst_env);
3683 break;
3684
3685 case cris_clearf_di_op:
3686 clearf_di_op (inst, inst_env);
3687 break;
3688
3689 case cris_dip_prefix:
3690 dip_prefix (inst, inst_env);
3691 break;
3692
3693 case cris_dstep_logshift_mstep_neg_not_op:
3694 dstep_logshift_mstep_neg_not_op (inst, inst_env);
3695 break;
3696
3697 case cris_eight_bit_offset_branch_op:
3698 eight_bit_offset_branch_op (inst, inst_env);
3699 break;
3700
3701 case cris_move_mem_to_reg_movem_op:
3702 move_mem_to_reg_movem_op (inst, inst_env);
3703 break;
3704
3705 case cris_move_reg_to_mem_movem_op:
3706 move_reg_to_mem_movem_op (inst, inst_env);
3707 break;
3708
3709 case cris_move_to_preg_op:
3710 move_to_preg_op (gdbarch, inst, inst_env);
3711 break;
3712
3713 case cris_muls_op:
3714 muls_op (inst, inst_env);
3715 break;
3716
3717 case cris_mulu_op:
3718 mulu_op (inst, inst_env);
3719 break;
3720
3721 case cris_none_reg_mode_add_sub_cmp_and_or_move_op:
3722 none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3723 break;
3724
3725 case cris_none_reg_mode_clear_test_op:
3726 none_reg_mode_clear_test_op (inst, inst_env);
3727 break;
3728
3729 case cris_none_reg_mode_jump_op:
3730 none_reg_mode_jump_op (inst, inst_env);
3731 break;
3732
3733 case cris_none_reg_mode_move_from_preg_op:
3734 none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env);
3735 break;
3736
3737 case cris_quick_mode_add_sub_op:
3738 quick_mode_add_sub_op (inst, inst_env);
3739 break;
3740
3741 case cris_quick_mode_and_cmp_move_or_op:
3742 quick_mode_and_cmp_move_or_op (inst, inst_env);
3743 break;
3744
3745 case cris_quick_mode_bdap_prefix:
3746 quick_mode_bdap_prefix (inst, inst_env);
3747 break;
3748
3749 case cris_reg_mode_add_sub_cmp_and_or_move_op:
3750 reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env);
3751 break;
3752
3753 case cris_reg_mode_clear_op:
3754 reg_mode_clear_op (inst, inst_env);
3755 break;
3756
3757 case cris_reg_mode_jump_op:
3758 reg_mode_jump_op (inst, inst_env);
3759 break;
3760
3761 case cris_reg_mode_move_from_preg_op:
3762 reg_mode_move_from_preg_op (inst, inst_env);
3763 break;
3764
3765 case cris_reg_mode_test_op:
3766 reg_mode_test_op (inst, inst_env);
3767 break;
3768
3769 case cris_scc_op:
3770 scc_op (inst, inst_env);
3771 break;
3772
3773 case cris_sixteen_bit_offset_branch_op:
3774 sixteen_bit_offset_branch_op (inst, inst_env);
3775 break;
3776
3777 case cris_three_operand_add_sub_cmp_and_or_op:
3778 three_operand_add_sub_cmp_and_or_op (inst, inst_env);
3779 break;
3780
3781 case cris_three_operand_bound_op:
3782 three_operand_bound_op (inst, inst_env);
3783 break;
3784
3785 case cris_two_operand_bound_op:
3786 two_operand_bound_op (inst, inst_env);
3787 break;
3788
3789 case cris_xor_op:
3790 xor_op (inst, inst_env);
3791 break;
3792 }
3793 }
3794
3795 /* This wrapper is to avoid cris_get_assembler being called before
3796 exec_bfd has been set. */
3797
3798 static int
3799 cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info)
3800 {
3801 int (*print_insn) (bfd_vma addr, struct disassemble_info *info);
3802 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3803 disassembler, even when there is no BFD. Does something like
3804 "gdb; target remote; disassmeble *0x123" work? */
3805 gdb_assert (exec_bfd != NULL);
3806 print_insn = cris_get_disassembler (exec_bfd);
3807 gdb_assert (print_insn != NULL);
3808 return print_insn (addr, info);
3809 }
3810
3811 /* Originally from <asm/elf.h>. */
3812 typedef unsigned char cris_elf_greg_t[4];
3813
3814 /* Same as user_regs_struct struct in <asm/user.h>. */
3815 #define CRISV10_ELF_NGREG 35
3816 typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG];
3817
3818 #define CRISV32_ELF_NGREG 32
3819 typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];
3820
3821 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3822
3823 static void
3824 cris_supply_gregset (struct regcache *regcache, cris_elf_gregset_t *gregsetp)
3825 {
3826 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3827 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3828 int i;
3829 cris_elf_greg_t *regp = *gregsetp;
3830
3831 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3832 knows about the actual size of each register so that's no problem. */
3833 for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++)
3834 {
3835 regcache_raw_supply (regcache, i, (char *)&regp[i]);
3836 }
3837
3838 if (tdep->cris_version == 32)
3839 {
3840 /* Needed to set pseudo-register PC for CRISv32. */
3841 /* FIXME: If ERP is in a delay slot at this point then the PC will
3842 be wrong. Issue a warning to alert the user. */
3843 regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch),
3844 (char *)&regp[ERP_REGNUM]);
3845
3846 if (*(char *)&regp[ERP_REGNUM] & 0x1)
3847 fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
3848 }
3849 }
3850
3851 /* Use a local version of this function to get the correct types for
3852 regsets, until multi-arch core support is ready. */
3853
3854 static void
3855 fetch_core_registers (struct regcache *regcache,
3856 char *core_reg_sect, unsigned core_reg_size,
3857 int which, CORE_ADDR reg_addr)
3858 {
3859 cris_elf_gregset_t gregset;
3860
3861 switch (which)
3862 {
3863 case 0:
3864 if (core_reg_size != sizeof (cris_elf_gregset_t)
3865 && core_reg_size != sizeof (crisv32_elf_gregset_t))
3866 {
3867 warning (_("wrong size gregset struct in core file"));
3868 }
3869 else
3870 {
3871 memcpy (&gregset, core_reg_sect, sizeof (gregset));
3872 cris_supply_gregset (regcache, &gregset);
3873 }
3874
3875 default:
3876 /* We've covered all the kinds of registers we know about here,
3877 so this must be something we wouldn't know what to do with
3878 anyway. Just ignore it. */
3879 break;
3880 }
3881 }
3882
3883 static struct core_fns cris_elf_core_fns =
3884 {
3885 bfd_target_elf_flavour, /* core_flavour */
3886 default_check_format, /* check_format */
3887 default_core_sniffer, /* core_sniffer */
3888 fetch_core_registers, /* core_read_registers */
3889 NULL /* next */
3890 };
3891
3892 extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */
3893
3894 void
3895 _initialize_cris_tdep (void)
3896 {
3897 struct cmd_list_element *c;
3898
3899 gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep);
3900
3901 /* CRIS-specific user-commands. */
3902 add_setshow_zuinteger_cmd ("cris-version", class_support,
3903 &usr_cmd_cris_version,
3904 _("Set the current CRIS version."),
3905 _("Show the current CRIS version."),
3906 _("\
3907 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3908 Defaults to 10. "),
3909 set_cris_version,
3910 NULL, /* FIXME: i18n: Current CRIS version
3911 is %s. */
3912 &setlist, &showlist);
3913
3914 add_setshow_enum_cmd ("cris-mode", class_support,
3915 cris_modes, &usr_cmd_cris_mode,
3916 _("Set the current CRIS mode."),
3917 _("Show the current CRIS mode."),
3918 _("\
3919 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3920 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3921 set_cris_mode,
3922 NULL, /* FIXME: i18n: Current CRIS version is %s. */
3923 &setlist, &showlist);
3924
3925 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support,
3926 &usr_cmd_cris_dwarf2_cfi,
3927 _("Set the usage of Dwarf-2 CFI for CRIS."),
3928 _("Show the usage of Dwarf-2 CFI for CRIS."),
3929 _("Set this to \"off\" if using gcc-cris < R59."),
3930 set_cris_dwarf2_cfi,
3931 NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI
3932 for CRIS is %d. */
3933 &setlist, &showlist);
3934
3935 deprecated_add_core_fns (&cris_elf_core_fns);
3936 }
3937
3938 /* Prints out all target specific values. */
3939
3940 static void
3941 cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3942 {
3943 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3944 if (tdep != NULL)
3945 {
3946 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n",
3947 tdep->cris_version);
3948 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n",
3949 tdep->cris_mode);
3950 fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3951 tdep->cris_dwarf2_cfi);
3952 }
3953 }
3954
3955 static void
3956 set_cris_version (char *ignore_args, int from_tty,
3957 struct cmd_list_element *c)
3958 {
3959 struct gdbarch_info info;
3960
3961 usr_cmd_cris_version_valid = 1;
3962
3963 /* Update the current architecture, if needed. */
3964 gdbarch_info_init (&info);
3965 if (!gdbarch_update_p (info))
3966 internal_error (__FILE__, __LINE__,
3967 _("cris_gdbarch_update: failed to update architecture."));
3968 }
3969
3970 static void
3971 set_cris_mode (char *ignore_args, int from_tty,
3972 struct cmd_list_element *c)
3973 {
3974 struct gdbarch_info info;
3975
3976 /* Update the current architecture, if needed. */
3977 gdbarch_info_init (&info);
3978 if (!gdbarch_update_p (info))
3979 internal_error (__FILE__, __LINE__,
3980 "cris_gdbarch_update: failed to update architecture.");
3981 }
3982
3983 static void
3984 set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
3985 struct cmd_list_element *c)
3986 {
3987 struct gdbarch_info info;
3988
3989 /* Update the current architecture, if needed. */
3990 gdbarch_info_init (&info);
3991 if (!gdbarch_update_p (info))
3992 internal_error (__FILE__, __LINE__,
3993 _("cris_gdbarch_update: failed to update architecture."));
3994 }
3995
3996 static struct gdbarch *
3997 cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3998 {
3999 struct gdbarch *gdbarch;
4000 struct gdbarch_tdep *tdep;
4001 unsigned int cris_version;
4002
4003 if (usr_cmd_cris_version_valid)
4004 {
4005 /* Trust the user's CRIS version setting. */
4006 cris_version = usr_cmd_cris_version;
4007 }
4008 else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
4009 {
4010 cris_version = 32;
4011 }
4012 else
4013 {
4014 /* Assume it's CRIS version 10. */
4015 cris_version = 10;
4016 }
4017
4018 /* Make the current settings visible to the user. */
4019 usr_cmd_cris_version = cris_version;
4020
4021 /* Find a candidate among the list of pre-declared architectures. */
4022 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4023 arches != NULL;
4024 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4025 {
4026 if ((gdbarch_tdep (arches->gdbarch)->cris_version
4027 == usr_cmd_cris_version)
4028 && (gdbarch_tdep (arches->gdbarch)->cris_mode
4029 == usr_cmd_cris_mode)
4030 && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi
4031 == usr_cmd_cris_dwarf2_cfi))
4032 return arches->gdbarch;
4033 }
4034
4035 /* No matching architecture was found. Create a new one. */
4036 tdep = XNEW (struct gdbarch_tdep);
4037 gdbarch = gdbarch_alloc (&info, tdep);
4038
4039 tdep->cris_version = usr_cmd_cris_version;
4040 tdep->cris_mode = usr_cmd_cris_mode;
4041 tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi;
4042
4043 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4044 switch (info.byte_order)
4045 {
4046 case BFD_ENDIAN_LITTLE:
4047 /* Ok. */
4048 break;
4049
4050 case BFD_ENDIAN_BIG:
4051 /* Cris is always little endian, but the user could have forced
4052 big endian with "set endian". */
4053 return 0;
4054
4055 default:
4056 internal_error (__FILE__, __LINE__,
4057 _("cris_gdbarch_init: unknown byte order in info"));
4058 }
4059
4060 set_gdbarch_return_value (gdbarch, cris_return_value);
4061
4062 set_gdbarch_sp_regnum (gdbarch, 14);
4063
4064 /* Length of ordinary registers used in push_word and a few other
4065 places. register_size() is the real way to know how big a
4066 register is. */
4067
4068 set_gdbarch_double_bit (gdbarch, 64);
4069 /* The default definition of a long double is 2 * gdbarch_double_bit,
4070 which means we have to set this explicitly. */
4071 set_gdbarch_long_double_bit (gdbarch, 64);
4072
4073 /* The total amount of space needed to store (in an array called registers)
4074 GDB's copy of the machine's register state. Note: We can not use
4075 cris_register_size at this point, since it relies on gdbarch
4076 being set. */
4077 switch (tdep->cris_version)
4078 {
4079 case 0:
4080 case 1:
4081 case 2:
4082 case 3:
4083 case 8:
4084 case 9:
4085 /* Old versions; not supported. */
4086 return 0;
4087
4088 case 10:
4089 case 11:
4090 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4091 P7 (32 bits), and P15 (32 bits) have been implemented. */
4092 set_gdbarch_pc_regnum (gdbarch, 15);
4093 set_gdbarch_register_type (gdbarch, cris_register_type);
4094 /* There are 32 registers (some of which may not be implemented). */
4095 set_gdbarch_num_regs (gdbarch, 32);
4096 set_gdbarch_register_name (gdbarch, cris_register_name);
4097 set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
4098 set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
4099
4100 set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
4101 break;
4102
4103 case 32:
4104 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4105 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4106 and pseudo-register PC (32 bits). */
4107 set_gdbarch_pc_regnum (gdbarch, 32);
4108 set_gdbarch_register_type (gdbarch, crisv32_register_type);
4109 /* 32 registers + pseudo-register PC + 16 support registers. */
4110 set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
4111 set_gdbarch_register_name (gdbarch, crisv32_register_name);
4112
4113 set_gdbarch_cannot_store_register
4114 (gdbarch, crisv32_cannot_store_register);
4115 set_gdbarch_cannot_fetch_register
4116 (gdbarch, crisv32_cannot_fetch_register);
4117
4118 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4119
4120 set_gdbarch_single_step_through_delay
4121 (gdbarch, crisv32_single_step_through_delay);
4122
4123 break;
4124
4125 default:
4126 /* Unknown version. */
4127 return 0;
4128 }
4129
4130 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4131 have the same ABI). */
4132 set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
4133 set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
4134 set_gdbarch_frame_align (gdbarch, cris_frame_align);
4135 set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);
4136
4137 /* The stack grows downward. */
4138 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4139
4140 set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc);
4141
4142 set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc);
4143 set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp);
4144 set_gdbarch_dummy_id (gdbarch, cris_dummy_id);
4145
4146 if (tdep->cris_dwarf2_cfi == 1)
4147 {
4148 /* Hook in the Dwarf-2 frame sniffer. */
4149 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum);
4150 dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg);
4151 dwarf2_append_unwinders (gdbarch);
4152 }
4153
4154 if (tdep->cris_mode != cris_mode_guru)
4155 {
4156 frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind);
4157 }
4158
4159 frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind);
4160 frame_base_set_default (gdbarch, &cris_frame_base);
4161
4162 /* Hook in ABI-specific overrides, if they have been registered. */
4163 gdbarch_init_osabi (info, gdbarch);
4164
4165 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4166 disassembler, even when there is no BFD. Does something like
4167 "gdb; target remote; disassmeble *0x123" work? */
4168 set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler);
4169
4170 return gdbarch;
4171 }
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