1 /* Target dependent code for CRIS, for GDB, the GNU debugger.
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5 Contributed by Axis Communications AB.
6 Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
28 #include "dwarf2-frame.h"
36 #include "opcode/cris.h"
38 #include "arch-utils.h"
43 #include "solib.h" /* Support for shared libraries. */
44 #include "solib-svr4.h"
47 #include "cris-tdep.h"
51 /* There are no floating point registers. Used in gdbserver low-linux.c. */
54 /* There are 16 general registers. */
57 /* There are 16 special registers. */
60 /* CRISv32 has a pseudo PC register, not noted here. */
62 /* CRISv32 has 16 support registers. */
66 /* Register numbers of various important registers.
67 CRIS_FP_REGNUM Contains address of executing stack frame.
68 STR_REGNUM Contains the address of structure return values.
69 RET_REGNUM Contains the return value when shorter than or equal to 32 bits
70 ARG1_REGNUM Contains the first parameter to a function.
71 ARG2_REGNUM Contains the second parameter to a function.
72 ARG3_REGNUM Contains the third parameter to a function.
73 ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
74 gdbarch_sp_regnum Contains address of top of stack.
75 gdbarch_pc_regnum Contains address of next instruction.
76 SRP_REGNUM Subroutine return pointer register.
77 BRP_REGNUM Breakpoint return pointer register. */
81 /* Enums with respect to the general registers, valid for all
82 CRIS versions. The frame pointer is always in R8. */
84 /* ABI related registers. */
92 /* Registers which happen to be common. */
97 /* CRISv10 et al. specific registers. */
109 /* CRISv32 specific registers. */
122 CRISV32USP_REGNUM
= 30, /* Shares name but not number with CRISv10. */
124 CRISV32PC_REGNUM
= 32, /* Shares name but not number with CRISv10. */
144 extern const struct cris_spec_reg cris_spec_regs
[];
146 /* CRIS version, set via the user command 'set cris-version'. Affects
147 register names and sizes. */
148 static unsigned int usr_cmd_cris_version
;
150 /* Indicates whether to trust the above variable. */
151 static int usr_cmd_cris_version_valid
= 0;
153 static const char cris_mode_normal
[] = "normal";
154 static const char cris_mode_guru
[] = "guru";
155 static const char *const cris_modes
[] = {
161 /* CRIS mode, set via the user command 'set cris-mode'. Affects
162 type of break instruction among other things. */
163 static const char *usr_cmd_cris_mode
= cris_mode_normal
;
165 /* Whether to make use of Dwarf-2 CFI (default on). */
166 static int usr_cmd_cris_dwarf2_cfi
= 1;
168 /* Sigtramp identification code copied from i386-linux-tdep.c. */
170 #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
171 #define SIGTRAMP_OFFSET0 0
172 #define SIGTRAMP_INSN1 0xe93d /* break 13 */
173 #define SIGTRAMP_OFFSET1 4
175 static const unsigned short sigtramp_code
[] =
177 SIGTRAMP_INSN0
, 0x0077, /* movu.w $0x77, $r9 */
178 SIGTRAMP_INSN1
/* break 13 */
181 #define SIGTRAMP_LEN (sizeof sigtramp_code)
183 /* Note: same length as normal sigtramp code. */
185 static const unsigned short rt_sigtramp_code
[] =
187 SIGTRAMP_INSN0
, 0x00ad, /* movu.w $0xad, $r9 */
188 SIGTRAMP_INSN1
/* break 13 */
191 /* If PC is in a sigtramp routine, return the address of the start of
192 the routine. Otherwise, return 0. */
195 cris_sigtramp_start (struct frame_info
*this_frame
)
197 CORE_ADDR pc
= get_frame_pc (this_frame
);
198 gdb_byte buf
[SIGTRAMP_LEN
];
200 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
203 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
205 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
208 pc
-= SIGTRAMP_OFFSET1
;
209 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
213 if (memcmp (buf
, sigtramp_code
, SIGTRAMP_LEN
) != 0)
219 /* If PC is in a RT sigtramp routine, return the address of the start of
220 the routine. Otherwise, return 0. */
223 cris_rt_sigtramp_start (struct frame_info
*this_frame
)
225 CORE_ADDR pc
= get_frame_pc (this_frame
);
226 gdb_byte buf
[SIGTRAMP_LEN
];
228 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
231 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN0
)
233 if (((buf
[1] << 8) + buf
[0]) != SIGTRAMP_INSN1
)
236 pc
-= SIGTRAMP_OFFSET1
;
237 if (!safe_frame_unwind_memory (this_frame
, pc
, buf
, SIGTRAMP_LEN
))
241 if (memcmp (buf
, rt_sigtramp_code
, SIGTRAMP_LEN
) != 0)
247 /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
248 return the address of the associated sigcontext structure. */
251 cris_sigcontext_addr (struct frame_info
*this_frame
)
253 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
254 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
259 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
260 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
262 /* Look for normal sigtramp frame first. */
263 pc
= cris_sigtramp_start (this_frame
);
266 /* struct signal_frame (arch/cris/kernel/signal.c) contains
267 struct sigcontext as its first member, meaning the SP points to
272 pc
= cris_rt_sigtramp_start (this_frame
);
275 /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
276 a struct ucontext, which in turn contains a struct sigcontext.
278 4 + 4 + 128 to struct ucontext, then
279 4 + 4 + 12 to struct sigcontext. */
283 error (_("Couldn't recognize signal trampoline."));
287 struct cris_unwind_cache
289 /* The previous frame's inner most stack address. Used as this
290 frame ID's stack_addr. */
292 /* The frame's base, optionally used by the high-level debug info. */
295 /* How far the SP and r8 (FP) have been offset from the start of
296 the stack frame (as defined by the previous frame's stack
302 /* From old frame_extra_info struct. */
306 /* Table indicating the location of each and every register. */
307 struct trad_frame_saved_reg
*saved_regs
;
310 static struct cris_unwind_cache
*
311 cris_sigtramp_frame_unwind_cache (struct frame_info
*this_frame
,
314 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
315 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
316 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
317 struct cris_unwind_cache
*info
;
323 return (struct cris_unwind_cache
*) (*this_cache
);
325 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
326 (*this_cache
) = info
;
327 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
329 /* Zero all fields. */
335 info
->uses_frame
= 0;
337 info
->leaf_function
= 0;
339 get_frame_register (this_frame
, gdbarch_sp_regnum (gdbarch
), buf
);
340 info
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
342 addr
= cris_sigcontext_addr (this_frame
);
344 /* Layout of the sigcontext struct:
347 unsigned long oldmask;
351 if (tdep
->cris_version
== 10)
353 /* R0 to R13 are stored in reverse order at offset (2 * 4) in
355 for (i
= 0; i
<= 13; i
++)
356 info
->saved_regs
[i
].addr
= addr
+ ((15 - i
) * 4);
358 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (16 * 4);
359 info
->saved_regs
[DCCR_REGNUM
].addr
= addr
+ (17 * 4);
360 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (18 * 4);
361 /* Note: IRP is off by 2 at this point. There's no point in correcting
362 it though since that will mean that the backtrace will show a PC
363 different from what is shown when stopped. */
364 info
->saved_regs
[IRP_REGNUM
].addr
= addr
+ (19 * 4);
365 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
366 = info
->saved_regs
[IRP_REGNUM
];
367 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
= addr
+ (24 * 4);
372 /* R0 to R13 are stored in order at offset (1 * 4) in
374 for (i
= 0; i
<= 13; i
++)
375 info
->saved_regs
[i
].addr
= addr
+ ((i
+ 1) * 4);
377 info
->saved_regs
[ACR_REGNUM
].addr
= addr
+ (15 * 4);
378 info
->saved_regs
[SRS_REGNUM
].addr
= addr
+ (16 * 4);
379 info
->saved_regs
[MOF_REGNUM
].addr
= addr
+ (17 * 4);
380 info
->saved_regs
[SPC_REGNUM
].addr
= addr
+ (18 * 4);
381 info
->saved_regs
[CCS_REGNUM
].addr
= addr
+ (19 * 4);
382 info
->saved_regs
[SRP_REGNUM
].addr
= addr
+ (20 * 4);
383 info
->saved_regs
[ERP_REGNUM
].addr
= addr
+ (21 * 4);
384 info
->saved_regs
[EXS_REGNUM
].addr
= addr
+ (22 * 4);
385 info
->saved_regs
[EDA_REGNUM
].addr
= addr
+ (23 * 4);
387 /* FIXME: If ERP is in a delay slot at this point then the PC will
388 be wrong at this point. This problem manifests itself in the
389 sigaltstack.exp test case, which occasionally generates FAILs when
390 the signal is received while in a delay slot.
392 This could be solved by a couple of read_memory_unsigned_integer and a
393 trad_frame_set_value. */
394 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
395 = info
->saved_regs
[ERP_REGNUM
];
397 info
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].addr
405 cris_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
406 struct frame_id
*this_id
)
408 struct cris_unwind_cache
*cache
=
409 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
410 (*this_id
) = frame_id_build (cache
->base
, get_frame_pc (this_frame
));
413 /* Forward declaration. */
415 static struct value
*cris_frame_prev_register (struct frame_info
*this_frame
,
416 void **this_cache
, int regnum
);
417 static struct value
*
418 cris_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
419 void **this_cache
, int regnum
)
421 /* Make sure we've initialized the cache. */
422 cris_sigtramp_frame_unwind_cache (this_frame
, this_cache
);
423 return cris_frame_prev_register (this_frame
, this_cache
, regnum
);
427 cris_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
428 struct frame_info
*this_frame
,
431 if (cris_sigtramp_start (this_frame
)
432 || cris_rt_sigtramp_start (this_frame
))
438 static const struct frame_unwind cris_sigtramp_frame_unwind
=
441 default_frame_unwind_stop_reason
,
442 cris_sigtramp_frame_this_id
,
443 cris_sigtramp_frame_prev_register
,
445 cris_sigtramp_frame_sniffer
449 crisv32_single_step_through_delay (struct gdbarch
*gdbarch
,
450 struct frame_info
*this_frame
)
452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
456 if (tdep
->cris_mode
== cris_mode_guru
)
457 erp
= get_frame_register_unsigned (this_frame
, NRP_REGNUM
);
459 erp
= get_frame_register_unsigned (this_frame
, ERP_REGNUM
);
463 /* In delay slot - check if there's a breakpoint at the preceding
465 if (breakpoint_here_p (get_frame_address_space (this_frame
), erp
& ~0x1))
471 /* The instruction environment needed to find single-step breakpoints. */
474 struct instruction_environment
476 unsigned long reg
[NUM_GENREGS
];
477 unsigned long preg
[NUM_SPECREGS
];
478 unsigned long branch_break_address
;
479 unsigned long delay_slot_pc
;
480 unsigned long prefix_value
;
485 int delay_slot_pc_active
;
487 int disable_interrupt
;
488 enum bfd_endian byte_order
;
491 /* Machine-dependencies in CRIS for opcodes. */
493 /* Instruction sizes. */
494 enum cris_instruction_sizes
501 /* Addressing modes. */
502 enum cris_addressing_modes
509 /* Prefix addressing modes. */
510 enum cris_prefix_addressing_modes
512 PREFIX_INDEX_MODE
= 2,
513 PREFIX_ASSIGN_MODE
= 3,
515 /* Handle immediate byte offset addressing mode prefix format. */
516 PREFIX_OFFSET_MODE
= 2
519 /* Masks for opcodes. */
520 enum cris_opcode_masks
522 BRANCH_SIGNED_SHORT_OFFSET_MASK
= 0x1,
523 SIGNED_EXTEND_BIT_MASK
= 0x2,
524 SIGNED_BYTE_MASK
= 0x80,
525 SIGNED_BYTE_EXTEND_MASK
= 0xFFFFFF00,
526 SIGNED_WORD_MASK
= 0x8000,
527 SIGNED_WORD_EXTEND_MASK
= 0xFFFF0000,
528 SIGNED_DWORD_MASK
= 0x80000000,
529 SIGNED_QUICK_VALUE_MASK
= 0x20,
530 SIGNED_QUICK_VALUE_EXTEND_MASK
= 0xFFFFFFC0
533 /* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
541 cris_get_operand2 (unsigned short insn
)
543 return ((insn
& 0xF000) >> 12);
547 cris_get_mode (unsigned short insn
)
549 return ((insn
& 0x0C00) >> 10);
553 cris_get_opcode (unsigned short insn
)
555 return ((insn
& 0x03C0) >> 6);
559 cris_get_size (unsigned short insn
)
561 return ((insn
& 0x0030) >> 4);
565 cris_get_operand1 (unsigned short insn
)
567 return (insn
& 0x000F);
570 /* Additional functions in order to handle opcodes. */
573 cris_get_quick_value (unsigned short insn
)
575 return (insn
& 0x003F);
579 cris_get_bdap_quick_offset (unsigned short insn
)
581 return (insn
& 0x00FF);
585 cris_get_branch_short_offset (unsigned short insn
)
587 return (insn
& 0x00FF);
591 cris_get_asr_shift_steps (unsigned long value
)
593 return (value
& 0x3F);
597 cris_get_clear_size (unsigned short insn
)
599 return ((insn
) & 0xC000);
603 cris_is_signed_extend_bit_on (unsigned short insn
)
605 return (((insn
) & 0x20) == 0x20);
609 cris_is_xflag_bit_on (unsigned short insn
)
611 return (((insn
) & 0x1000) == 0x1000);
615 cris_set_size_to_dword (unsigned short *insn
)
622 cris_get_signed_offset (unsigned short insn
)
624 return ((signed char) (insn
& 0x00FF));
627 /* Calls an op function given the op-type, working on the insn and the
629 static void cris_gdb_func (struct gdbarch
*, enum cris_op_type
, unsigned short,
632 static struct gdbarch
*cris_gdbarch_init (struct gdbarch_info
,
633 struct gdbarch_list
*);
635 static void cris_dump_tdep (struct gdbarch
*, struct ui_file
*);
637 static void set_cris_version (char *ignore_args
, int from_tty
,
638 struct cmd_list_element
*c
);
640 static void set_cris_mode (char *ignore_args
, int from_tty
,
641 struct cmd_list_element
*c
);
643 static void set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
644 struct cmd_list_element
*c
);
646 static CORE_ADDR
cris_scan_prologue (CORE_ADDR pc
,
647 struct frame_info
*this_frame
,
648 struct cris_unwind_cache
*info
);
650 static CORE_ADDR
crisv32_scan_prologue (CORE_ADDR pc
,
651 struct frame_info
*this_frame
,
652 struct cris_unwind_cache
*info
);
654 static CORE_ADDR
cris_unwind_pc (struct gdbarch
*gdbarch
,
655 struct frame_info
*next_frame
);
657 static CORE_ADDR
cris_unwind_sp (struct gdbarch
*gdbarch
,
658 struct frame_info
*next_frame
);
660 /* When arguments must be pushed onto the stack, they go on in reverse
661 order. The below implements a FILO (stack) to do this.
662 Copied from d10v-tdep.c. */
667 struct stack_item
*prev
;
671 static struct stack_item
*
672 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
674 struct stack_item
*si
= XNEW (struct stack_item
);
675 si
->data
= (gdb_byte
*) xmalloc (len
);
678 memcpy (si
->data
, contents
, len
);
682 static struct stack_item
*
683 pop_stack_item (struct stack_item
*si
)
685 struct stack_item
*dead
= si
;
692 /* Put here the code to store, into fi->saved_regs, the addresses of
693 the saved registers of frame described by FRAME_INFO. This
694 includes special registers such as pc and fp saved in special ways
695 in the stack frame. sp is even more special: the address we return
696 for it IS the sp for the next frame. */
698 static struct cris_unwind_cache
*
699 cris_frame_unwind_cache (struct frame_info
*this_frame
,
700 void **this_prologue_cache
)
702 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
703 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
704 struct cris_unwind_cache
*info
;
706 if ((*this_prologue_cache
))
707 return (struct cris_unwind_cache
*) (*this_prologue_cache
);
709 info
= FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache
);
710 (*this_prologue_cache
) = info
;
711 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
713 /* Zero all fields. */
719 info
->uses_frame
= 0;
721 info
->leaf_function
= 0;
723 /* Prologue analysis does the rest... */
724 if (tdep
->cris_version
== 32)
725 crisv32_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
727 cris_scan_prologue (get_frame_func (this_frame
), this_frame
, info
);
732 /* Given a GDB frame, determine the address of the calling function's
733 frame. This will be used to create a new GDB frame struct. */
736 cris_frame_this_id (struct frame_info
*this_frame
,
737 void **this_prologue_cache
,
738 struct frame_id
*this_id
)
740 struct cris_unwind_cache
*info
741 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
746 /* The FUNC is easy. */
747 func
= get_frame_func (this_frame
);
749 /* Hopefully the prologue analysis either correctly determined the
750 frame's base (which is the SP from the previous frame), or set
751 that base to "NULL". */
752 base
= info
->prev_sp
;
756 id
= frame_id_build (base
, func
);
761 static struct value
*
762 cris_frame_prev_register (struct frame_info
*this_frame
,
763 void **this_prologue_cache
, int regnum
)
765 struct cris_unwind_cache
*info
766 = cris_frame_unwind_cache (this_frame
, this_prologue_cache
);
767 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
770 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
771 frame. The frame ID's base needs to match the TOS value saved by
772 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
774 static struct frame_id
775 cris_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
778 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
779 return frame_id_build (sp
, get_frame_pc (this_frame
));
783 cris_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
785 /* Align to the size of an instruction (so that they can safely be
786 pushed onto the stack). */
791 cris_push_dummy_code (struct gdbarch
*gdbarch
,
792 CORE_ADDR sp
, CORE_ADDR funaddr
,
793 struct value
**args
, int nargs
,
794 struct type
*value_type
,
795 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
796 struct regcache
*regcache
)
798 /* Allocate space sufficient for a breakpoint. */
800 /* Store the address of that breakpoint */
802 /* CRIS always starts the call at the callee's entry point. */
808 cris_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
809 struct regcache
*regcache
, CORE_ADDR bp_addr
,
810 int nargs
, struct value
**args
, CORE_ADDR sp
,
811 int struct_return
, CORE_ADDR struct_addr
)
813 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
817 struct stack_item
*si
= NULL
;
819 /* Push the return address. */
820 regcache_cooked_write_unsigned (regcache
, SRP_REGNUM
, bp_addr
);
822 /* Are we returning a value using a structure return or a normal value
823 return? struct_addr is the address of the reserved space for the return
824 structure to be written on the stack. */
827 regcache_cooked_write_unsigned (regcache
, STR_REGNUM
, struct_addr
);
830 /* Now load as many as possible of the first arguments into registers,
831 and push the rest onto the stack. */
832 argreg
= ARG1_REGNUM
;
834 for (argnum
= 0; argnum
< nargs
; argnum
++)
841 len
= TYPE_LENGTH (value_type (args
[argnum
]));
842 val
= value_contents (args
[argnum
]);
844 /* How may registers worth of storage do we need for this argument? */
845 reg_demand
= (len
/ 4) + (len
% 4 != 0 ? 1 : 0);
847 if (len
<= (2 * 4) && (argreg
+ reg_demand
- 1 <= ARG4_REGNUM
))
849 /* Data passed by value. Fits in available register(s). */
850 for (i
= 0; i
< reg_demand
; i
++)
852 regcache_cooked_write (regcache
, argreg
, val
);
857 else if (len
<= (2 * 4) && argreg
<= ARG4_REGNUM
)
859 /* Data passed by value. Does not fit in available register(s).
860 Use the register(s) first, then the stack. */
861 for (i
= 0; i
< reg_demand
; i
++)
863 if (argreg
<= ARG4_REGNUM
)
865 regcache_cooked_write (regcache
, argreg
, val
);
871 /* Push item for later so that pushed arguments
872 come in the right order. */
873 si
= push_stack_item (si
, val
, 4);
878 else if (len
> (2 * 4))
880 /* Data passed by reference. Push copy of data onto stack
881 and pass pointer to this copy as argument. */
882 sp
= (sp
- len
) & ~3;
883 write_memory (sp
, val
, len
);
885 if (argreg
<= ARG4_REGNUM
)
887 regcache_cooked_write_unsigned (regcache
, argreg
, sp
);
893 store_unsigned_integer (buf
, 4, byte_order
, sp
);
894 si
= push_stack_item (si
, buf
, 4);
899 /* Data passed by value. No available registers. Put it on
901 si
= push_stack_item (si
, val
, len
);
907 /* fp_arg must be word-aligned (i.e., don't += len) to match
908 the function prologue. */
909 sp
= (sp
- si
->len
) & ~3;
910 write_memory (sp
, si
->data
, si
->len
);
911 si
= pop_stack_item (si
);
914 /* Finally, update the SP register. */
915 regcache_cooked_write_unsigned (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
920 static const struct frame_unwind cris_frame_unwind
=
923 default_frame_unwind_stop_reason
,
925 cris_frame_prev_register
,
927 default_frame_sniffer
931 cris_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
933 struct cris_unwind_cache
*info
934 = cris_frame_unwind_cache (this_frame
, this_cache
);
938 static const struct frame_base cris_frame_base
=
941 cris_frame_base_address
,
942 cris_frame_base_address
,
943 cris_frame_base_address
946 /* Frames information. The definition of the struct frame_info is
950 enum frame_type type;
954 If the compilation option -fno-omit-frame-pointer is present the
955 variable frame will be set to the content of R8 which is the frame
958 The variable pc contains the address where execution is performed
959 in the present frame. The innermost frame contains the current content
960 of the register PC. All other frames contain the content of the
961 register PC in the next frame.
963 The variable `type' indicates the frame's type: normal, SIGTRAMP
964 (associated with a signal handler), dummy (associated with a dummy
967 The variable return_pc contains the address where execution should be
968 resumed when the present frame has finished, the return address.
970 The variable leaf_function is 1 if the return address is in the register
971 SRP, and 0 if it is on the stack.
973 Prologue instructions C-code.
974 The prologue may consist of (-fno-omit-frame-pointer)
978 move.d sp,r8 move.d sp,r8
980 movem rY,[sp] movem rY,[sp]
981 move.S rZ,[r8-U] move.S rZ,[r8-U]
983 where 1 is a non-terminal function, and 2 is a leaf-function.
985 Note that this assumption is extremely brittle, and will break at the
986 slightest change in GCC's prologue.
988 If local variables are declared or register contents are saved on stack
989 the subq-instruction will be present with X as the number of bytes
990 needed for storage. The reshuffle with respect to r8 may be performed
991 with any size S (b, w, d) and any of the general registers Z={0..13}.
992 The offset U should be representable by a signed 8-bit value in all cases.
993 Thus, the prefix word is assumed to be immediate byte offset mode followed
994 by another word containing the instruction.
1003 Prologue instructions C++-code.
1004 Case 1) and 2) in the C-code may be followed by
1006 move.d r10,rS ; this
1010 move.S [r8+U],rZ ; P4
1012 if any of the call parameters are stored. The host expects these
1013 instructions to be executed in order to get the call parameters right. */
1015 /* Examine the prologue of a function. The variable ip is the address of
1016 the first instruction of the prologue. The variable limit is the address
1017 of the first instruction after the prologue. The variable fi contains the
1018 information in struct frame_info. The variable frameless_p controls whether
1019 the entire prologue is examined (0) or just enough instructions to
1020 determine that it is a prologue (1). */
1023 cris_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1024 struct cris_unwind_cache
*info
)
1026 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1027 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1029 /* Present instruction. */
1030 unsigned short insn
;
1032 /* Next instruction, lookahead. */
1033 unsigned short insn_next
;
1036 /* Number of byte on stack used for local variables and movem. */
1039 /* Highest register number in a movem. */
1042 /* move.d r<source_register>,rS */
1043 short source_register
;
1048 /* This frame is with respect to a leaf until a push srp is found. */
1051 info
->leaf_function
= 1;
1054 /* Assume nothing on stack. */
1058 /* If we were called without a this_frame, that means we were called
1059 from cris_skip_prologue which already tried to find the end of the
1060 prologue through the symbol information. 64 instructions past current
1061 pc is arbitrarily chosen, but at least it means we'll stop eventually. */
1062 limit
= this_frame
? get_frame_pc (this_frame
) : pc
+ 64;
1064 /* Find the prologue instructions. */
1065 while (pc
> 0 && pc
< limit
)
1067 insn
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1071 /* push <reg> 32 bit instruction. */
1072 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1074 regno
= cris_get_operand2 (insn_next
);
1077 info
->sp_offset
+= 4;
1079 /* This check, meant to recognize srp, used to be regno ==
1080 (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */
1081 if (insn_next
== 0xBE7E)
1085 info
->leaf_function
= 0;
1088 else if (insn_next
== 0x8FEE)
1093 info
->r8_offset
= info
->sp_offset
;
1097 else if (insn
== 0x866E)
1102 info
->uses_frame
= 1;
1106 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1107 && cris_get_mode (insn
) == 0x0000
1108 && cris_get_opcode (insn
) == 0x000A)
1113 info
->sp_offset
+= cris_get_quick_value (insn
);
1116 else if (cris_get_mode (insn
) == 0x0002
1117 && cris_get_opcode (insn
) == 0x000F
1118 && cris_get_size (insn
) == 0x0003
1119 && cris_get_operand1 (insn
) == gdbarch_sp_regnum (gdbarch
))
1121 /* movem r<regsave>,[sp] */
1122 regsave
= cris_get_operand2 (insn
);
1124 else if (cris_get_operand2 (insn
) == gdbarch_sp_regnum (gdbarch
)
1125 && ((insn
& 0x0F00) >> 8) == 0x0001
1126 && (cris_get_signed_offset (insn
) < 0))
1128 /* Immediate byte offset addressing prefix word with sp as base
1129 register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val>
1130 is between 64 and 128.
1131 movem r<regsave>,[sp=sp-<val>] */
1134 info
->sp_offset
+= -cris_get_signed_offset (insn
);
1136 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1138 if (cris_get_mode (insn_next
) == PREFIX_ASSIGN_MODE
1139 && cris_get_opcode (insn_next
) == 0x000F
1140 && cris_get_size (insn_next
) == 0x0003
1141 && cris_get_operand1 (insn_next
) == gdbarch_sp_regnum
1144 regsave
= cris_get_operand2 (insn_next
);
1148 /* The prologue ended before the limit was reached. */
1153 else if (cris_get_mode (insn
) == 0x0001
1154 && cris_get_opcode (insn
) == 0x0009
1155 && cris_get_size (insn
) == 0x0002)
1157 /* move.d r<10..13>,r<0..15> */
1158 source_register
= cris_get_operand1 (insn
);
1160 /* FIXME? In the glibc solibs, the prologue might contain something
1161 like (this example taken from relocate_doit):
1163 sub.d 0xfffef426,$r0
1164 which isn't covered by the source_register check below. Question
1165 is whether to add a check for this combo, or make better use of
1166 the limit variable instead. */
1167 if (source_register
< ARG1_REGNUM
|| source_register
> ARG4_REGNUM
)
1169 /* The prologue ended before the limit was reached. */
1174 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1175 /* The size is a fixed-size. */
1176 && ((insn
& 0x0F00) >> 8) == 0x0001
1177 /* A negative offset. */
1178 && (cris_get_signed_offset (insn
) < 0))
1180 /* move.S rZ,[r8-U] (?) */
1181 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1183 regno
= cris_get_operand2 (insn_next
);
1184 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1185 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1186 && cris_get_opcode (insn_next
) == 0x000F)
1188 /* move.S rZ,[r8-U] */
1193 /* The prologue ended before the limit was reached. */
1198 else if (cris_get_operand2 (insn
) == CRIS_FP_REGNUM
1199 /* The size is a fixed-size. */
1200 && ((insn
& 0x0F00) >> 8) == 0x0001
1201 /* A positive offset. */
1202 && (cris_get_signed_offset (insn
) > 0))
1204 /* move.S [r8+U],rZ (?) */
1205 insn_next
= read_memory_unsigned_integer (pc
, 2, byte_order
);
1207 regno
= cris_get_operand2 (insn_next
);
1208 if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1209 && cris_get_mode (insn_next
) == PREFIX_OFFSET_MODE
1210 && cris_get_opcode (insn_next
) == 0x0009
1211 && cris_get_operand1 (insn_next
) == regno
)
1213 /* move.S [r8+U],rZ */
1218 /* The prologue ended before the limit was reached. */
1225 /* The prologue ended before the limit was reached. */
1231 /* We only want to know the end of the prologue when this_frame and info
1232 are NULL (called from cris_skip_prologue i.e.). */
1233 if (this_frame
== NULL
&& info
== NULL
)
1238 info
->size
= info
->sp_offset
;
1240 /* Compute the previous frame's stack pointer (which is also the
1241 frame's ID's stack address), and this frame's base pointer. */
1242 if (info
->uses_frame
)
1245 /* The SP was moved to the FP. This indicates that a new frame
1246 was created. Get THIS frame's FP value by unwinding it from
1248 this_base
= get_frame_register_unsigned (this_frame
, CRIS_FP_REGNUM
);
1249 info
->base
= this_base
;
1250 info
->saved_regs
[CRIS_FP_REGNUM
].addr
= info
->base
;
1252 /* The FP points at the last saved register. Adjust the FP back
1253 to before the first saved register giving the SP. */
1254 info
->prev_sp
= info
->base
+ info
->r8_offset
;
1259 /* Assume that the FP is this frame's SP but with that pushed
1260 stack space added back. */
1261 this_base
= get_frame_register_unsigned (this_frame
,
1262 gdbarch_sp_regnum (gdbarch
));
1263 info
->base
= this_base
;
1264 info
->prev_sp
= info
->base
+ info
->size
;
1267 /* Calculate the addresses for the saved registers on the stack. */
1268 /* FIXME: The address calculation should really be done on the fly while
1269 we're analyzing the prologue (we only hold one regsave value as it is
1271 val
= info
->sp_offset
;
1273 for (regno
= regsave
; regno
>= 0; regno
--)
1275 info
->saved_regs
[regno
].addr
= info
->base
+ info
->r8_offset
- val
;
1279 /* The previous frame's SP needed to be computed. Save the computed
1281 trad_frame_set_value (info
->saved_regs
,
1282 gdbarch_sp_regnum (gdbarch
), info
->prev_sp
);
1284 if (!info
->leaf_function
)
1286 /* SRP saved on the stack. But where? */
1287 if (info
->r8_offset
== 0)
1289 /* R8 not pushed yet. */
1290 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
;
1294 /* R8 pushed, but SP may or may not be moved to R8 yet. */
1295 info
->saved_regs
[SRP_REGNUM
].addr
= info
->base
+ 4;
1299 /* The PC is found in SRP (the actual register or located on the stack). */
1300 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1301 = info
->saved_regs
[SRP_REGNUM
];
1307 crisv32_scan_prologue (CORE_ADDR pc
, struct frame_info
*this_frame
,
1308 struct cris_unwind_cache
*info
)
1310 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1313 /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not
1314 meant to be a full-fledged prologue scanner. It is only needed for
1315 the cases where we end up in code always lacking DWARF-2 CFI, notably:
1317 * PLT stubs (library calls)
1319 * signal trampolines
1321 For those cases, it is assumed that there is no actual prologue; that
1322 the stack pointer is not adjusted, and (as a consequence) the return
1323 address is not pushed onto the stack. */
1325 /* We only want to know the end of the prologue when this_frame and info
1326 are NULL (called from cris_skip_prologue i.e.). */
1327 if (this_frame
== NULL
&& info
== NULL
)
1332 /* The SP is assumed to be unaltered. */
1333 this_base
= get_frame_register_unsigned (this_frame
,
1334 gdbarch_sp_regnum (gdbarch
));
1335 info
->base
= this_base
;
1336 info
->prev_sp
= this_base
;
1338 /* The PC is assumed to be found in SRP. */
1339 info
->saved_regs
[gdbarch_pc_regnum (gdbarch
)]
1340 = info
->saved_regs
[SRP_REGNUM
];
1345 /* Advance pc beyond any function entry prologue instructions at pc
1346 to reach some "real" code. */
1348 /* Given a PC value corresponding to the start of a function, return the PC
1349 of the first instruction after the function prologue. */
1352 cris_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1355 CORE_ADDR func_addr
, func_end
;
1356 struct symtab_and_line sal
;
1357 CORE_ADDR pc_after_prologue
;
1359 /* If we have line debugging information, then the end of the prologue
1360 should the first assembly instruction of the first source line. */
1361 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1363 sal
= find_pc_line (func_addr
, 0);
1364 if (sal
.end
> 0 && sal
.end
< func_end
)
1368 if (tdep
->cris_version
== 32)
1369 pc_after_prologue
= crisv32_scan_prologue (pc
, NULL
, NULL
);
1371 pc_after_prologue
= cris_scan_prologue (pc
, NULL
, NULL
);
1373 return pc_after_prologue
;
1377 cris_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1380 pc
= frame_unwind_register_unsigned (next_frame
,
1381 gdbarch_pc_regnum (gdbarch
));
1386 cris_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1389 sp
= frame_unwind_register_unsigned (next_frame
,
1390 gdbarch_sp_regnum (gdbarch
));
1395 cris_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1400 static const gdb_byte
*
1401 cris_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1403 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1404 static unsigned char break8_insn
[] = {0x38, 0xe9};
1405 static unsigned char break15_insn
[] = {0x3f, 0xe9};
1409 if (tdep
->cris_mode
== cris_mode_guru
)
1410 return break15_insn
;
1415 /* Use the program counter to determine the contents and size of a breakpoint
1416 instruction. It returns a pointer to a string of bytes that encode a
1417 breakpoint instruction, stores the length of the string to *lenptr, and
1418 adjusts pcptr (if necessary) to point to the actual memory location where
1419 the breakpoint should be inserted. */
1421 GDBARCH_BREAKPOINT_FROM_PC (cris
)
1423 /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version,
1427 cris_spec_reg_applicable (struct gdbarch
*gdbarch
,
1428 struct cris_spec_reg spec_reg
)
1430 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1431 unsigned int version
= tdep
->cris_version
;
1433 switch (spec_reg
.applicable_version
)
1435 case cris_ver_version_all
:
1437 case cris_ver_warning
:
1438 /* Indeterminate/obsolete. */
1441 return (version
>= 0 && version
<= 3);
1443 return (version
>= 3);
1445 return (version
== 8 || version
== 9);
1447 return (version
>= 8);
1448 case cris_ver_v0_10
:
1449 return (version
>= 0 && version
<= 10);
1450 case cris_ver_v3_10
:
1451 return (version
>= 3 && version
<= 10);
1452 case cris_ver_v8_10
:
1453 return (version
>= 8 && version
<= 10);
1455 return (version
== 10);
1457 return (version
>= 10);
1459 return (version
>= 32);
1461 /* Invalid cris version. */
1466 /* Returns the register size in unit byte. Returns 0 for an unimplemented
1467 register, -1 for an invalid register. */
1470 cris_register_size (struct gdbarch
*gdbarch
, int regno
)
1475 if (regno
>= 0 && regno
< NUM_GENREGS
)
1477 /* General registers (R0 - R15) are 32 bits. */
1480 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1482 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1483 Adjust regno accordingly. */
1484 spec_regno
= regno
- NUM_GENREGS
;
1486 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1488 if (cris_spec_regs
[i
].number
== spec_regno
1489 && cris_spec_reg_applicable (gdbarch
, cris_spec_regs
[i
]))
1490 /* Go with the first applicable register. */
1491 return cris_spec_regs
[i
].reg_size
;
1493 /* Special register not applicable to this CRIS version. */
1496 else if (regno
>= gdbarch_pc_regnum (gdbarch
)
1497 && regno
< gdbarch_num_regs (gdbarch
))
1499 /* This will apply to CRISv32 only where there are additional registers
1500 after the special registers (pseudo PC and support registers). */
1508 /* Nonzero if regno should not be fetched from the target. This is the case
1509 for unimplemented (size 0) and non-existant registers. */
1512 cris_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1514 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1515 || (cris_register_size (gdbarch
, regno
) == 0));
1518 /* Nonzero if regno should not be written to the target, for various
1522 cris_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1524 /* There are three kinds of registers we refuse to write to.
1525 1. Those that not implemented.
1526 2. Those that are read-only (depends on the processor mode).
1527 3. Those registers to which a write has no effect. */
1530 || regno
>= gdbarch_num_regs (gdbarch
)
1531 || cris_register_size (gdbarch
, regno
) == 0)
1532 /* Not implemented. */
1535 else if (regno
== VR_REGNUM
)
1539 else if (regno
== P0_REGNUM
|| regno
== P4_REGNUM
|| regno
== P8_REGNUM
)
1540 /* Writing has no effect. */
1543 /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug
1544 agent decide whether they are writable. */
1549 /* Nonzero if regno should not be fetched from the target. This is the case
1550 for unimplemented (size 0) and non-existant registers. */
1553 crisv32_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
1555 return ((regno
< 0 || regno
>= gdbarch_num_regs (gdbarch
))
1556 || (cris_register_size (gdbarch
, regno
) == 0));
1559 /* Nonzero if regno should not be written to the target, for various
1563 crisv32_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
1565 /* There are three kinds of registers we refuse to write to.
1566 1. Those that not implemented.
1567 2. Those that are read-only (depends on the processor mode).
1568 3. Those registers to which a write has no effect. */
1571 || regno
>= gdbarch_num_regs (gdbarch
)
1572 || cris_register_size (gdbarch
, regno
) == 0)
1573 /* Not implemented. */
1576 else if (regno
== VR_REGNUM
)
1580 else if (regno
== BZ_REGNUM
|| regno
== WZ_REGNUM
|| regno
== DZ_REGNUM
)
1581 /* Writing has no effect. */
1584 /* Many special registers are read-only in user mode. Let the debug
1585 agent decide whether they are writable. */
1590 /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
1591 of data in register regno. */
1593 static struct type
*
1594 cris_register_type (struct gdbarch
*gdbarch
, int regno
)
1596 if (regno
== gdbarch_pc_regnum (gdbarch
))
1597 return builtin_type (gdbarch
)->builtin_func_ptr
;
1598 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1599 || regno
== CRIS_FP_REGNUM
)
1600 return builtin_type (gdbarch
)->builtin_data_ptr
;
1601 else if ((regno
>= 0 && regno
< gdbarch_sp_regnum (gdbarch
))
1602 || (regno
>= MOF_REGNUM
&& regno
<= USP_REGNUM
))
1603 /* Note: R8 taken care of previous clause. */
1604 return builtin_type (gdbarch
)->builtin_uint32
;
1605 else if (regno
>= P4_REGNUM
&& regno
<= CCR_REGNUM
)
1606 return builtin_type (gdbarch
)->builtin_uint16
;
1607 else if (regno
>= P0_REGNUM
&& regno
<= VR_REGNUM
)
1608 return builtin_type (gdbarch
)->builtin_uint8
;
1610 /* Invalid (unimplemented) register. */
1611 return builtin_type (gdbarch
)->builtin_int0
;
1614 static struct type
*
1615 crisv32_register_type (struct gdbarch
*gdbarch
, int regno
)
1617 if (regno
== gdbarch_pc_regnum (gdbarch
))
1618 return builtin_type (gdbarch
)->builtin_func_ptr
;
1619 else if (regno
== gdbarch_sp_regnum (gdbarch
)
1620 || regno
== CRIS_FP_REGNUM
)
1621 return builtin_type (gdbarch
)->builtin_data_ptr
;
1622 else if ((regno
>= 0 && regno
<= ACR_REGNUM
)
1623 || (regno
>= EXS_REGNUM
&& regno
<= SPC_REGNUM
)
1624 || (regno
== PID_REGNUM
)
1625 || (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
))
1626 /* Note: R8 and SP taken care of by previous clause. */
1627 return builtin_type (gdbarch
)->builtin_uint32
;
1628 else if (regno
== WZ_REGNUM
)
1629 return builtin_type (gdbarch
)->builtin_uint16
;
1630 else if (regno
== BZ_REGNUM
|| regno
== VR_REGNUM
|| regno
== SRS_REGNUM
)
1631 return builtin_type (gdbarch
)->builtin_uint8
;
1634 /* Invalid (unimplemented) register. Should not happen as there are
1635 no unimplemented CRISv32 registers. */
1636 warning (_("crisv32_register_type: unknown regno %d"), regno
);
1637 return builtin_type (gdbarch
)->builtin_int0
;
1641 /* Stores a function return value of type type, where valbuf is the address
1642 of the value to be stored. */
1644 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1647 cris_store_return_value (struct type
*type
, struct regcache
*regcache
,
1648 const gdb_byte
*valbuf
)
1650 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1651 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1653 int len
= TYPE_LENGTH (type
);
1657 /* Put the return value in R10. */
1658 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1659 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1663 /* Put the return value in R10 and R11. */
1664 val
= extract_unsigned_integer (valbuf
, 4, byte_order
);
1665 regcache_cooked_write_unsigned (regcache
, ARG1_REGNUM
, val
);
1666 val
= extract_unsigned_integer (valbuf
+ 4, len
- 4, byte_order
);
1667 regcache_cooked_write_unsigned (regcache
, ARG2_REGNUM
, val
);
1670 error (_("cris_store_return_value: type length too large."));
1673 /* Return the name of register regno as a string. Return NULL for an
1674 invalid or unimplemented register. */
1677 cris_special_register_name (struct gdbarch
*gdbarch
, int regno
)
1682 /* Special register (R16 - R31). cris_spec_regs is zero-based.
1683 Adjust regno accordingly. */
1684 spec_regno
= regno
- NUM_GENREGS
;
1686 /* Assume nothing about the layout of the cris_spec_regs struct
1688 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1690 if (cris_spec_regs
[i
].number
== spec_regno
1691 && cris_spec_reg_applicable (gdbarch
, cris_spec_regs
[i
]))
1692 /* Go with the first applicable register. */
1693 return cris_spec_regs
[i
].name
;
1695 /* Special register not applicable to this CRIS version. */
1700 cris_register_name (struct gdbarch
*gdbarch
, int regno
)
1702 static char *cris_genreg_names
[] =
1703 { "r0", "r1", "r2", "r3", \
1704 "r4", "r5", "r6", "r7", \
1705 "r8", "r9", "r10", "r11", \
1706 "r12", "r13", "sp", "pc" };
1708 if (regno
>= 0 && regno
< NUM_GENREGS
)
1710 /* General register. */
1711 return cris_genreg_names
[regno
];
1713 else if (regno
>= NUM_GENREGS
&& regno
< gdbarch_num_regs (gdbarch
))
1715 return cris_special_register_name (gdbarch
, regno
);
1719 /* Invalid register. */
1725 crisv32_register_name (struct gdbarch
*gdbarch
, int regno
)
1727 static char *crisv32_genreg_names
[] =
1728 { "r0", "r1", "r2", "r3", \
1729 "r4", "r5", "r6", "r7", \
1730 "r8", "r9", "r10", "r11", \
1731 "r12", "r13", "sp", "acr"
1734 static char *crisv32_sreg_names
[] =
1735 { "s0", "s1", "s2", "s3", \
1736 "s4", "s5", "s6", "s7", \
1737 "s8", "s9", "s10", "s11", \
1738 "s12", "s13", "s14", "s15"
1741 if (regno
>= 0 && regno
< NUM_GENREGS
)
1743 /* General register. */
1744 return crisv32_genreg_names
[regno
];
1746 else if (regno
>= NUM_GENREGS
&& regno
< (NUM_GENREGS
+ NUM_SPECREGS
))
1748 return cris_special_register_name (gdbarch
, regno
);
1750 else if (regno
== gdbarch_pc_regnum (gdbarch
))
1754 else if (regno
>= S0_REGNUM
&& regno
<= S15_REGNUM
)
1756 return crisv32_sreg_names
[regno
- S0_REGNUM
];
1760 /* Invalid register. */
1765 /* Convert DWARF register number REG to the appropriate register
1766 number used by GDB. */
1769 cris_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1771 /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register
1772 numbering, MOF is 18).
1773 Adapted from gcc/config/cris/cris.h. */
1774 static int cris_dwarf_regmap
[] = {
1786 if (reg
>= 0 && reg
< ARRAY_SIZE (cris_dwarf_regmap
))
1787 regnum
= cris_dwarf_regmap
[reg
];
1792 /* DWARF-2 frame support. */
1795 cris_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1796 struct dwarf2_frame_state_reg
*reg
,
1797 struct frame_info
*this_frame
)
1799 /* The return address column. */
1800 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1801 reg
->how
= DWARF2_FRAME_REG_RA
;
1803 /* The call frame address. */
1804 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1805 reg
->how
= DWARF2_FRAME_REG_CFA
;
1808 /* Extract from an array regbuf containing the raw register state a function
1809 return value of type type, and copy that, in virtual format, into
1812 /* In the CRIS ABI, R10 and R11 are used to store return values. */
1815 cris_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1818 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1819 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1821 int len
= TYPE_LENGTH (type
);
1825 /* Get the return value from R10. */
1826 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1827 store_unsigned_integer (valbuf
, len
, byte_order
, val
);
1831 /* Get the return value from R10 and R11. */
1832 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &val
);
1833 store_unsigned_integer (valbuf
, 4, byte_order
, val
);
1834 regcache_cooked_read_unsigned (regcache
, ARG2_REGNUM
, &val
);
1835 store_unsigned_integer (valbuf
+ 4, len
- 4, byte_order
, val
);
1838 error (_("cris_extract_return_value: type length too large"));
1841 /* Handle the CRIS return value convention. */
1843 static enum return_value_convention
1844 cris_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1845 struct type
*type
, struct regcache
*regcache
,
1846 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1848 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1849 || TYPE_CODE (type
) == TYPE_CODE_UNION
1850 || TYPE_LENGTH (type
) > 8)
1851 /* Structs, unions, and anything larger than 8 bytes (2 registers)
1852 goes on the stack. */
1853 return RETURN_VALUE_STRUCT_CONVENTION
;
1856 cris_extract_return_value (type
, regcache
, readbuf
);
1858 cris_store_return_value (type
, regcache
, writebuf
);
1860 return RETURN_VALUE_REGISTER_CONVENTION
;
1863 /* Calculates a value that measures how good inst_args constraints an
1864 instruction. It stems from cris_constraint, found in cris-dis.c. */
1867 constraint (unsigned int insn
, const char *inst_args
,
1868 inst_env_type
*inst_env
)
1873 const gdb_byte
*s
= (const gdb_byte
*) inst_args
;
1879 if ((insn
& 0x30) == 0x30)
1884 /* A prefix operand. */
1885 if (inst_env
->prefix_found
)
1891 /* A "push" prefix. (This check was REMOVED by san 970921.) Check for
1892 valid "push" size. In case of special register, it may be != 4. */
1893 if (inst_env
->prefix_found
)
1899 retval
= (((insn
>> 0xC) & 0xF) == (insn
& 0xF));
1907 tmp
= (insn
>> 0xC) & 0xF;
1909 for (i
= 0; cris_spec_regs
[i
].name
!= NULL
; i
++)
1911 /* Since we match four bits, we will give a value of
1912 4 - 1 = 3 in a match. If there is a corresponding
1913 exact match of a special register in another pattern, it
1914 will get a value of 4, which will be higher. This should
1915 be correct in that an exact pattern would match better that
1917 Note that there is a reason for not returning zero; the
1918 pattern for "clear" is partly matched in the bit-pattern
1919 (the two lower bits must be zero), while the bit-pattern
1920 for a move from a special register is matched in the
1921 register constraint.
1922 This also means we will will have a race condition if
1923 there is a partly match in three bits in the bit pattern. */
1924 if (tmp
== cris_spec_regs
[i
].number
)
1931 if (cris_spec_regs
[i
].name
== NULL
)
1938 /* Returns the number of bits set in the variable value. */
1941 number_of_bits (unsigned int value
)
1943 int number_of_bits
= 0;
1947 number_of_bits
+= 1;
1948 value
&= (value
- 1);
1950 return number_of_bits
;
1953 /* Finds the address that should contain the single step breakpoint(s).
1954 It stems from code in cris-dis.c. */
1957 find_cris_op (unsigned short insn
, inst_env_type
*inst_env
)
1960 int max_level_of_match
= -1;
1961 int max_matched
= -1;
1964 for (i
= 0; cris_opcodes
[i
].name
!= NULL
; i
++)
1966 if (((cris_opcodes
[i
].match
& insn
) == cris_opcodes
[i
].match
)
1967 && ((cris_opcodes
[i
].lose
& insn
) == 0)
1968 /* Only CRISv10 instructions, please. */
1969 && (cris_opcodes
[i
].applicable_version
!= cris_ver_v32p
))
1971 level_of_match
= constraint (insn
, cris_opcodes
[i
].args
, inst_env
);
1972 if (level_of_match
>= 0)
1975 number_of_bits (cris_opcodes
[i
].match
| cris_opcodes
[i
].lose
);
1976 if (level_of_match
> max_level_of_match
)
1979 max_level_of_match
= level_of_match
;
1980 if (level_of_match
== 16)
1982 /* All bits matched, cannot find better. */
1992 /* Attempts to find single-step breakpoints. Returns -1 on failure which is
1993 actually an internal error. */
1996 find_step_target (struct frame_info
*frame
, inst_env_type
*inst_env
)
2000 unsigned short insn
;
2001 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2002 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2004 /* Create a local register image and set the initial state. */
2005 for (i
= 0; i
< NUM_GENREGS
; i
++)
2008 (unsigned long) get_frame_register_unsigned (frame
, i
);
2010 offset
= NUM_GENREGS
;
2011 for (i
= 0; i
< NUM_SPECREGS
; i
++)
2014 (unsigned long) get_frame_register_unsigned (frame
, offset
+ i
);
2016 inst_env
->branch_found
= 0;
2017 inst_env
->slot_needed
= 0;
2018 inst_env
->delay_slot_pc_active
= 0;
2019 inst_env
->prefix_found
= 0;
2020 inst_env
->invalid
= 0;
2021 inst_env
->xflag_found
= 0;
2022 inst_env
->disable_interrupt
= 0;
2023 inst_env
->byte_order
= byte_order
;
2025 /* Look for a step target. */
2028 /* Read an instruction from the client. */
2029 insn
= read_memory_unsigned_integer
2030 (inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)], 2, byte_order
);
2032 /* If the instruction is not in a delay slot the new content of the
2033 PC is [PC] + 2. If the instruction is in a delay slot it is not
2034 that simple. Since a instruction in a delay slot cannot change
2035 the content of the PC, it does not matter what value PC will have.
2036 Just make sure it is a valid instruction. */
2037 if (!inst_env
->delay_slot_pc_active
)
2039 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)] += 2;
2043 inst_env
->delay_slot_pc_active
= 0;
2044 inst_env
->reg
[gdbarch_pc_regnum (gdbarch
)]
2045 = inst_env
->delay_slot_pc
;
2047 /* Analyse the present instruction. */
2048 i
= find_cris_op (insn
, inst_env
);
2051 inst_env
->invalid
= 1;
2055 cris_gdb_func (gdbarch
, cris_opcodes
[i
].op
, insn
, inst_env
);
2057 } while (!inst_env
->invalid
2058 && (inst_env
->prefix_found
|| inst_env
->xflag_found
2059 || inst_env
->slot_needed
));
2063 /* There is no hardware single-step support. The function find_step_target
2064 digs through the opcodes in order to find all possible targets.
2065 Either one ordinary target or two targets for branches may be found. */
2068 cris_software_single_step (struct frame_info
*frame
)
2070 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2071 struct address_space
*aspace
= get_frame_address_space (frame
);
2072 inst_env_type inst_env
;
2074 /* Analyse the present instruction environment and insert
2076 int status
= find_step_target (frame
, &inst_env
);
2079 /* Could not find a target. Things are likely to go downhill
2081 warning (_("CRIS software single step could not find a step target."));
2085 /* Insert at most two breakpoints. One for the next PC content
2086 and possibly another one for a branch, jump, etc. */
2088 = (CORE_ADDR
) inst_env
.reg
[gdbarch_pc_regnum (gdbarch
)];
2089 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2090 if (inst_env
.branch_found
2091 && (CORE_ADDR
) inst_env
.branch_break_address
!= next_pc
)
2093 CORE_ADDR branch_target_address
2094 = (CORE_ADDR
) inst_env
.branch_break_address
;
2095 insert_single_step_breakpoint (gdbarch
,
2096 aspace
, branch_target_address
);
2103 /* Calculates the prefix value for quick offset addressing mode. */
2106 quick_mode_bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2108 /* It's invalid to be in a delay slot. You can't have a prefix to this
2109 instruction (not 100% sure). */
2110 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2112 inst_env
->invalid
= 1;
2116 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2117 inst_env
->prefix_value
+= cris_get_bdap_quick_offset (inst
);
2119 /* A prefix doesn't change the xflag_found. But the rest of the flags
2121 inst_env
->slot_needed
= 0;
2122 inst_env
->prefix_found
= 1;
2125 /* Updates the autoincrement register. The size of the increment is derived
2126 from the size of the operation. The PC is always kept aligned on even
2130 process_autoincrement (int size
, unsigned short inst
, inst_env_type
*inst_env
)
2132 if (size
== INST_BYTE_SIZE
)
2134 inst_env
->reg
[cris_get_operand1 (inst
)] += 1;
2136 /* The PC must be word aligned, so increase the PC with one
2137 word even if the size is byte. */
2138 if (cris_get_operand1 (inst
) == REG_PC
)
2140 inst_env
->reg
[REG_PC
] += 1;
2143 else if (size
== INST_WORD_SIZE
)
2145 inst_env
->reg
[cris_get_operand1 (inst
)] += 2;
2147 else if (size
== INST_DWORD_SIZE
)
2149 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2154 inst_env
->invalid
= 1;
2158 /* Just a forward declaration. */
2160 static unsigned long get_data_from_address (unsigned short *inst
,
2162 enum bfd_endian byte_order
);
2164 /* Calculates the prefix value for the general case of offset addressing
2168 bdap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2170 /* It's invalid to be in a delay slot. */
2171 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2173 inst_env
->invalid
= 1;
2177 /* The calculation of prefix_value used to be after process_autoincrement,
2178 but that fails for an instruction such as jsr [$r0+12] which is encoded
2179 as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it
2180 mustn't be incremented until we have read it and what it points at. */
2181 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand2 (inst
)];
2183 /* The offset is an indirection of the contents of the operand1 register. */
2184 inst_env
->prefix_value
+=
2185 get_data_from_address (&inst
, inst_env
->reg
[cris_get_operand1 (inst
)],
2186 inst_env
->byte_order
);
2188 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2190 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2193 /* A prefix doesn't change the xflag_found. But the rest of the flags
2195 inst_env
->slot_needed
= 0;
2196 inst_env
->prefix_found
= 1;
2199 /* Calculates the prefix value for the index addressing mode. */
2202 biap_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2204 /* It's invalid to be in a delay slot. I can't see that it's possible to
2205 have a prefix to this instruction. So I will treat this as invalid. */
2206 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2208 inst_env
->invalid
= 1;
2212 inst_env
->prefix_value
= inst_env
->reg
[cris_get_operand1 (inst
)];
2214 /* The offset is the operand2 value shifted the size of the instruction
2216 inst_env
->prefix_value
+=
2217 inst_env
->reg
[cris_get_operand2 (inst
)] << cris_get_size (inst
);
2219 /* If the PC is operand1 (base) the address used is the address after
2220 the main instruction, i.e. address + 2 (the PC is already compensated
2221 for the prefix operation). */
2222 if (cris_get_operand1 (inst
) == REG_PC
)
2224 inst_env
->prefix_value
+= 2;
2227 /* A prefix doesn't change the xflag_found. But the rest of the flags
2229 inst_env
->slot_needed
= 0;
2230 inst_env
->xflag_found
= 0;
2231 inst_env
->prefix_found
= 1;
2234 /* Calculates the prefix value for the double indirect addressing mode. */
2237 dip_prefix (unsigned short inst
, inst_env_type
*inst_env
)
2242 /* It's invalid to be in a delay slot. */
2243 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2245 inst_env
->invalid
= 1;
2249 /* The prefix value is one dereference of the contents of the operand1
2251 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2252 inst_env
->prefix_value
2253 = read_memory_unsigned_integer (address
, 4, inst_env
->byte_order
);
2255 /* Check if the mode is autoincrement. */
2256 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2258 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2261 /* A prefix doesn't change the xflag_found. But the rest of the flags
2263 inst_env
->slot_needed
= 0;
2264 inst_env
->xflag_found
= 0;
2265 inst_env
->prefix_found
= 1;
2268 /* Finds the destination for a branch with 8-bits offset. */
2271 eight_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2276 /* If we have a prefix or are in a delay slot it's bad. */
2277 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2279 inst_env
->invalid
= 1;
2283 /* We have a branch, find out where the branch will land. */
2284 offset
= cris_get_branch_short_offset (inst
);
2286 /* Check if the offset is signed. */
2287 if (offset
& BRANCH_SIGNED_SHORT_OFFSET_MASK
)
2292 /* The offset ends with the sign bit, set it to zero. The address
2293 should always be word aligned. */
2294 offset
&= ~BRANCH_SIGNED_SHORT_OFFSET_MASK
;
2296 inst_env
->branch_found
= 1;
2297 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2299 inst_env
->slot_needed
= 1;
2300 inst_env
->prefix_found
= 0;
2301 inst_env
->xflag_found
= 0;
2302 inst_env
->disable_interrupt
= 1;
2305 /* Finds the destination for a branch with 16-bits offset. */
2308 sixteen_bit_offset_branch_op (unsigned short inst
, inst_env_type
*inst_env
)
2312 /* If we have a prefix or is in a delay slot it's bad. */
2313 if (inst_env
->slot_needed
|| inst_env
->prefix_found
)
2315 inst_env
->invalid
= 1;
2319 /* We have a branch, find out the offset for the branch. */
2320 offset
= read_memory_integer (inst_env
->reg
[REG_PC
], 2,
2321 inst_env
->byte_order
);
2323 /* The instruction is one word longer than normal, so add one word
2325 inst_env
->reg
[REG_PC
] += 2;
2327 inst_env
->branch_found
= 1;
2328 inst_env
->branch_break_address
= inst_env
->reg
[REG_PC
] + offset
;
2331 inst_env
->slot_needed
= 1;
2332 inst_env
->prefix_found
= 0;
2333 inst_env
->xflag_found
= 0;
2334 inst_env
->disable_interrupt
= 1;
2337 /* Handles the ABS instruction. */
2340 abs_op (unsigned short inst
, inst_env_type
*inst_env
)
2345 /* ABS can't have a prefix, so it's bad if it does. */
2346 if (inst_env
->prefix_found
)
2348 inst_env
->invalid
= 1;
2352 /* Check if the operation affects the PC. */
2353 if (cris_get_operand2 (inst
) == REG_PC
)
2356 /* It's invalid to change to the PC if we are in a delay slot. */
2357 if (inst_env
->slot_needed
)
2359 inst_env
->invalid
= 1;
2363 value
= (long) inst_env
->reg
[REG_PC
];
2365 /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
2366 if (value
!= SIGNED_DWORD_MASK
)
2369 inst_env
->reg
[REG_PC
] = (long) value
;
2373 inst_env
->slot_needed
= 0;
2374 inst_env
->prefix_found
= 0;
2375 inst_env
->xflag_found
= 0;
2376 inst_env
->disable_interrupt
= 0;
2379 /* Handles the ADDI instruction. */
2382 addi_op (unsigned short inst
, inst_env_type
*inst_env
)
2384 /* It's invalid to have the PC as base register. And ADDI can't have
2386 if (inst_env
->prefix_found
|| (cris_get_operand1 (inst
) == REG_PC
))
2388 inst_env
->invalid
= 1;
2392 inst_env
->slot_needed
= 0;
2393 inst_env
->prefix_found
= 0;
2394 inst_env
->xflag_found
= 0;
2395 inst_env
->disable_interrupt
= 0;
2398 /* Handles the ASR instruction. */
2401 asr_op (unsigned short inst
, inst_env_type
*inst_env
)
2404 unsigned long value
;
2405 unsigned long signed_extend_mask
= 0;
2407 /* ASR can't have a prefix, so check that it doesn't. */
2408 if (inst_env
->prefix_found
)
2410 inst_env
->invalid
= 1;
2414 /* Check if the PC is the target register. */
2415 if (cris_get_operand2 (inst
) == REG_PC
)
2417 /* It's invalid to change the PC in a delay slot. */
2418 if (inst_env
->slot_needed
)
2420 inst_env
->invalid
= 1;
2423 /* Get the number of bits to shift. */
2425 = cris_get_asr_shift_steps (inst_env
->reg
[cris_get_operand1 (inst
)]);
2426 value
= inst_env
->reg
[REG_PC
];
2428 /* Find out how many bits the operation should apply to. */
2429 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
2431 if (value
& SIGNED_BYTE_MASK
)
2433 signed_extend_mask
= 0xFF;
2434 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2435 signed_extend_mask
= ~signed_extend_mask
;
2437 value
= value
>> shift_steps
;
2438 value
|= signed_extend_mask
;
2440 inst_env
->reg
[REG_PC
] &= 0xFFFFFF00;
2441 inst_env
->reg
[REG_PC
] |= value
;
2443 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
2445 if (value
& SIGNED_WORD_MASK
)
2447 signed_extend_mask
= 0xFFFF;
2448 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2449 signed_extend_mask
= ~signed_extend_mask
;
2451 value
= value
>> shift_steps
;
2452 value
|= signed_extend_mask
;
2454 inst_env
->reg
[REG_PC
] &= 0xFFFF0000;
2455 inst_env
->reg
[REG_PC
] |= value
;
2457 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
2459 if (value
& SIGNED_DWORD_MASK
)
2461 signed_extend_mask
= 0xFFFFFFFF;
2462 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2463 signed_extend_mask
= ~signed_extend_mask
;
2465 value
= value
>> shift_steps
;
2466 value
|= signed_extend_mask
;
2467 inst_env
->reg
[REG_PC
] = value
;
2470 inst_env
->slot_needed
= 0;
2471 inst_env
->prefix_found
= 0;
2472 inst_env
->xflag_found
= 0;
2473 inst_env
->disable_interrupt
= 0;
2476 /* Handles the ASRQ instruction. */
2479 asrq_op (unsigned short inst
, inst_env_type
*inst_env
)
2483 unsigned long value
;
2484 unsigned long signed_extend_mask
= 0;
2486 /* ASRQ can't have a prefix, so check that it doesn't. */
2487 if (inst_env
->prefix_found
)
2489 inst_env
->invalid
= 1;
2493 /* Check if the PC is the target register. */
2494 if (cris_get_operand2 (inst
) == REG_PC
)
2497 /* It's invalid to change the PC in a delay slot. */
2498 if (inst_env
->slot_needed
)
2500 inst_env
->invalid
= 1;
2503 /* The shift size is given as a 5 bit quick value, i.e. we don't
2504 want the sign bit of the quick value. */
2505 shift_steps
= cris_get_asr_shift_steps (inst
);
2506 value
= inst_env
->reg
[REG_PC
];
2507 if (value
& SIGNED_DWORD_MASK
)
2509 signed_extend_mask
= 0xFFFFFFFF;
2510 signed_extend_mask
= signed_extend_mask
>> shift_steps
;
2511 signed_extend_mask
= ~signed_extend_mask
;
2513 value
= value
>> shift_steps
;
2514 value
|= signed_extend_mask
;
2515 inst_env
->reg
[REG_PC
] = value
;
2517 inst_env
->slot_needed
= 0;
2518 inst_env
->prefix_found
= 0;
2519 inst_env
->xflag_found
= 0;
2520 inst_env
->disable_interrupt
= 0;
2523 /* Handles the AX, EI and SETF instruction. */
2526 ax_ei_setf_op (unsigned short inst
, inst_env_type
*inst_env
)
2528 if (inst_env
->prefix_found
)
2530 inst_env
->invalid
= 1;
2533 /* Check if the instruction is setting the X flag. */
2534 if (cris_is_xflag_bit_on (inst
))
2536 inst_env
->xflag_found
= 1;
2540 inst_env
->xflag_found
= 0;
2542 inst_env
->slot_needed
= 0;
2543 inst_env
->prefix_found
= 0;
2544 inst_env
->disable_interrupt
= 1;
2547 /* Checks if the instruction is in assign mode. If so, it updates the assign
2548 register. Note that check_assign assumes that the caller has checked that
2549 there is a prefix to this instruction. The mode check depends on this. */
2552 check_assign (unsigned short inst
, inst_env_type
*inst_env
)
2554 /* Check if it's an assign addressing mode. */
2555 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2557 /* Assign the prefix value to operand 1. */
2558 inst_env
->reg
[cris_get_operand1 (inst
)] = inst_env
->prefix_value
;
2562 /* Handles the 2-operand BOUND instruction. */
2565 two_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2567 /* It's invalid to have the PC as the index operand. */
2568 if (cris_get_operand2 (inst
) == REG_PC
)
2570 inst_env
->invalid
= 1;
2573 /* Check if we have a prefix. */
2574 if (inst_env
->prefix_found
)
2576 check_assign (inst
, inst_env
);
2578 /* Check if this is an autoincrement mode. */
2579 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2581 /* It's invalid to change the PC in a delay slot. */
2582 if (inst_env
->slot_needed
)
2584 inst_env
->invalid
= 1;
2587 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2589 inst_env
->slot_needed
= 0;
2590 inst_env
->prefix_found
= 0;
2591 inst_env
->xflag_found
= 0;
2592 inst_env
->disable_interrupt
= 0;
2595 /* Handles the 3-operand BOUND instruction. */
2598 three_operand_bound_op (unsigned short inst
, inst_env_type
*inst_env
)
2600 /* It's an error if we haven't got a prefix. And it's also an error
2601 if the PC is the destination register. */
2602 if ((!inst_env
->prefix_found
) || (cris_get_operand1 (inst
) == REG_PC
))
2604 inst_env
->invalid
= 1;
2607 inst_env
->slot_needed
= 0;
2608 inst_env
->prefix_found
= 0;
2609 inst_env
->xflag_found
= 0;
2610 inst_env
->disable_interrupt
= 0;
2613 /* Clears the status flags in inst_env. */
2616 btst_nop_op (unsigned short inst
, inst_env_type
*inst_env
)
2618 /* It's an error if we have got a prefix. */
2619 if (inst_env
->prefix_found
)
2621 inst_env
->invalid
= 1;
2625 inst_env
->slot_needed
= 0;
2626 inst_env
->prefix_found
= 0;
2627 inst_env
->xflag_found
= 0;
2628 inst_env
->disable_interrupt
= 0;
2631 /* Clears the status flags in inst_env. */
2634 clearf_di_op (unsigned short inst
, inst_env_type
*inst_env
)
2636 /* It's an error if we have got a prefix. */
2637 if (inst_env
->prefix_found
)
2639 inst_env
->invalid
= 1;
2643 inst_env
->slot_needed
= 0;
2644 inst_env
->prefix_found
= 0;
2645 inst_env
->xflag_found
= 0;
2646 inst_env
->disable_interrupt
= 1;
2649 /* Handles the CLEAR instruction if it's in register mode. */
2652 reg_mode_clear_op (unsigned short inst
, inst_env_type
*inst_env
)
2654 /* Check if the target is the PC. */
2655 if (cris_get_operand2 (inst
) == REG_PC
)
2657 /* The instruction will clear the instruction's size bits. */
2658 int clear_size
= cris_get_clear_size (inst
);
2659 if (clear_size
== INST_BYTE_SIZE
)
2661 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFFFF00;
2663 if (clear_size
== INST_WORD_SIZE
)
2665 inst_env
->delay_slot_pc
= inst_env
->reg
[REG_PC
] & 0xFFFF0000;
2667 if (clear_size
== INST_DWORD_SIZE
)
2669 inst_env
->delay_slot_pc
= 0x0;
2671 /* The jump will be delayed with one delay slot. So we need a delay
2673 inst_env
->slot_needed
= 1;
2674 inst_env
->delay_slot_pc_active
= 1;
2678 /* The PC will not change => no delay slot. */
2679 inst_env
->slot_needed
= 0;
2681 inst_env
->prefix_found
= 0;
2682 inst_env
->xflag_found
= 0;
2683 inst_env
->disable_interrupt
= 0;
2686 /* Handles the TEST instruction if it's in register mode. */
2689 reg_mode_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2691 /* It's an error if we have got a prefix. */
2692 if (inst_env
->prefix_found
)
2694 inst_env
->invalid
= 1;
2697 inst_env
->slot_needed
= 0;
2698 inst_env
->prefix_found
= 0;
2699 inst_env
->xflag_found
= 0;
2700 inst_env
->disable_interrupt
= 0;
2704 /* Handles the CLEAR and TEST instruction if the instruction isn't
2705 in register mode. */
2708 none_reg_mode_clear_test_op (unsigned short inst
, inst_env_type
*inst_env
)
2710 /* Check if we are in a prefix mode. */
2711 if (inst_env
->prefix_found
)
2713 /* The only way the PC can change is if this instruction is in
2714 assign addressing mode. */
2715 check_assign (inst
, inst_env
);
2717 /* Indirect mode can't change the PC so just check if the mode is
2719 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2721 process_autoincrement (cris_get_size (inst
), inst
, inst_env
);
2723 inst_env
->slot_needed
= 0;
2724 inst_env
->prefix_found
= 0;
2725 inst_env
->xflag_found
= 0;
2726 inst_env
->disable_interrupt
= 0;
2729 /* Checks that the PC isn't the destination register or the instructions has
2733 dstep_logshift_mstep_neg_not_op (unsigned short inst
, inst_env_type
*inst_env
)
2735 /* It's invalid to have the PC as the destination. The instruction can't
2737 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2739 inst_env
->invalid
= 1;
2743 inst_env
->slot_needed
= 0;
2744 inst_env
->prefix_found
= 0;
2745 inst_env
->xflag_found
= 0;
2746 inst_env
->disable_interrupt
= 0;
2749 /* Checks that the instruction doesn't have a prefix. */
2752 break_op (unsigned short inst
, inst_env_type
*inst_env
)
2754 /* The instruction can't have a prefix. */
2755 if (inst_env
->prefix_found
)
2757 inst_env
->invalid
= 1;
2761 inst_env
->slot_needed
= 0;
2762 inst_env
->prefix_found
= 0;
2763 inst_env
->xflag_found
= 0;
2764 inst_env
->disable_interrupt
= 1;
2767 /* Checks that the PC isn't the destination register and that the instruction
2768 doesn't have a prefix. */
2771 scc_op (unsigned short inst
, inst_env_type
*inst_env
)
2773 /* It's invalid to have the PC as the destination. The instruction can't
2775 if ((cris_get_operand2 (inst
) == REG_PC
) || inst_env
->prefix_found
)
2777 inst_env
->invalid
= 1;
2781 inst_env
->slot_needed
= 0;
2782 inst_env
->prefix_found
= 0;
2783 inst_env
->xflag_found
= 0;
2784 inst_env
->disable_interrupt
= 1;
2787 /* Handles the register mode JUMP instruction. */
2790 reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2792 /* It's invalid to do a JUMP in a delay slot. The mode is register, so
2793 you can't have a prefix. */
2794 if ((inst_env
->slot_needed
) || (inst_env
->prefix_found
))
2796 inst_env
->invalid
= 1;
2800 /* Just change the PC. */
2801 inst_env
->reg
[REG_PC
] = inst_env
->reg
[cris_get_operand1 (inst
)];
2802 inst_env
->slot_needed
= 0;
2803 inst_env
->prefix_found
= 0;
2804 inst_env
->xflag_found
= 0;
2805 inst_env
->disable_interrupt
= 1;
2808 /* Handles the JUMP instruction for all modes except register. */
2811 none_reg_mode_jump_op (unsigned short inst
, inst_env_type
*inst_env
)
2813 unsigned long newpc
;
2816 /* It's invalid to do a JUMP in a delay slot. */
2817 if (inst_env
->slot_needed
)
2819 inst_env
->invalid
= 1;
2823 /* Check if we have a prefix. */
2824 if (inst_env
->prefix_found
)
2826 check_assign (inst
, inst_env
);
2828 /* Get the new value for the PC. */
2830 read_memory_unsigned_integer ((CORE_ADDR
) inst_env
->prefix_value
,
2831 4, inst_env
->byte_order
);
2835 /* Get the new value for the PC. */
2836 address
= (CORE_ADDR
) inst_env
->reg
[cris_get_operand1 (inst
)];
2837 newpc
= read_memory_unsigned_integer (address
,
2838 4, inst_env
->byte_order
);
2840 /* Check if we should increment a register. */
2841 if (cris_get_mode (inst
) == AUTOINC_MODE
)
2843 inst_env
->reg
[cris_get_operand1 (inst
)] += 4;
2846 inst_env
->reg
[REG_PC
] = newpc
;
2848 inst_env
->slot_needed
= 0;
2849 inst_env
->prefix_found
= 0;
2850 inst_env
->xflag_found
= 0;
2851 inst_env
->disable_interrupt
= 1;
2854 /* Handles moves to special registers (aka P-register) for all modes. */
2857 move_to_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2858 inst_env_type
*inst_env
)
2860 if (inst_env
->prefix_found
)
2862 /* The instruction has a prefix that means we are only interested if
2863 the instruction is in assign mode. */
2864 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2866 /* The prefix handles the problem if we are in a delay slot. */
2867 if (cris_get_operand1 (inst
) == REG_PC
)
2869 /* Just take care of the assign. */
2870 check_assign (inst
, inst_env
);
2874 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2876 /* The instruction doesn't have a prefix, the only case left that we
2877 are interested in is the autoincrement mode. */
2878 if (cris_get_operand1 (inst
) == REG_PC
)
2880 /* If the PC is to be incremented it's invalid to be in a
2882 if (inst_env
->slot_needed
)
2884 inst_env
->invalid
= 1;
2888 /* The increment depends on the size of the special register. */
2889 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
2891 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2893 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
2895 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2899 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2903 inst_env
->slot_needed
= 0;
2904 inst_env
->prefix_found
= 0;
2905 inst_env
->xflag_found
= 0;
2906 inst_env
->disable_interrupt
= 1;
2909 /* Handles moves from special registers (aka P-register) for all modes
2913 none_reg_mode_move_from_preg_op (struct gdbarch
*gdbarch
, unsigned short inst
,
2914 inst_env_type
*inst_env
)
2916 if (inst_env
->prefix_found
)
2918 /* The instruction has a prefix that means we are only interested if
2919 the instruction is in assign mode. */
2920 if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
2922 /* The prefix handles the problem if we are in a delay slot. */
2923 if (cris_get_operand1 (inst
) == REG_PC
)
2925 /* Just take care of the assign. */
2926 check_assign (inst
, inst_env
);
2930 /* The instruction doesn't have a prefix, the only case left that we
2931 are interested in is the autoincrement mode. */
2932 else if (cris_get_mode (inst
) == AUTOINC_MODE
)
2934 if (cris_get_operand1 (inst
) == REG_PC
)
2936 /* If the PC is to be incremented it's invalid to be in a
2938 if (inst_env
->slot_needed
)
2940 inst_env
->invalid
= 1;
2944 /* The increment depends on the size of the special register. */
2945 if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 1)
2947 process_autoincrement (INST_BYTE_SIZE
, inst
, inst_env
);
2949 else if (cris_register_size (gdbarch
, cris_get_operand2 (inst
)) == 2)
2951 process_autoincrement (INST_WORD_SIZE
, inst
, inst_env
);
2955 process_autoincrement (INST_DWORD_SIZE
, inst
, inst_env
);
2959 inst_env
->slot_needed
= 0;
2960 inst_env
->prefix_found
= 0;
2961 inst_env
->xflag_found
= 0;
2962 inst_env
->disable_interrupt
= 1;
2965 /* Handles moves from special registers (aka P-register) when the mode
2969 reg_mode_move_from_preg_op (unsigned short inst
, inst_env_type
*inst_env
)
2971 /* Register mode move from special register can't have a prefix. */
2972 if (inst_env
->prefix_found
)
2974 inst_env
->invalid
= 1;
2978 if (cris_get_operand1 (inst
) == REG_PC
)
2980 /* It's invalid to change the PC in a delay slot. */
2981 if (inst_env
->slot_needed
)
2983 inst_env
->invalid
= 1;
2986 /* The destination is the PC, the jump will have a delay slot. */
2987 inst_env
->delay_slot_pc
= inst_env
->preg
[cris_get_operand2 (inst
)];
2988 inst_env
->slot_needed
= 1;
2989 inst_env
->delay_slot_pc_active
= 1;
2993 /* If the destination isn't PC, there will be no jump. */
2994 inst_env
->slot_needed
= 0;
2996 inst_env
->prefix_found
= 0;
2997 inst_env
->xflag_found
= 0;
2998 inst_env
->disable_interrupt
= 1;
3001 /* Handles the MOVEM from memory to general register instruction. */
3004 move_mem_to_reg_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3006 if (inst_env
->prefix_found
)
3008 /* The prefix handles the problem if we are in a delay slot. Is the
3009 MOVEM instruction going to change the PC? */
3010 if (cris_get_operand2 (inst
) >= REG_PC
)
3012 inst_env
->reg
[REG_PC
] =
3013 read_memory_unsigned_integer (inst_env
->prefix_value
,
3014 4, inst_env
->byte_order
);
3016 /* The assign value is the value after the increment. Normally, the
3017 assign value is the value before the increment. */
3018 if ((cris_get_operand1 (inst
) == REG_PC
)
3019 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3021 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3022 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3027 /* Is the MOVEM instruction going to change the PC? */
3028 if (cris_get_operand2 (inst
) == REG_PC
)
3030 /* It's invalid to change the PC in a delay slot. */
3031 if (inst_env
->slot_needed
)
3033 inst_env
->invalid
= 1;
3036 inst_env
->reg
[REG_PC
] =
3037 read_memory_unsigned_integer (inst_env
->reg
[cris_get_operand1 (inst
)],
3038 4, inst_env
->byte_order
);
3040 /* The increment is not depending on the size, instead it's depending
3041 on the number of registers loaded from memory. */
3042 if ((cris_get_operand1 (inst
) == REG_PC
)
3043 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3045 /* It's invalid to change the PC in a delay slot. */
3046 if (inst_env
->slot_needed
)
3048 inst_env
->invalid
= 1;
3051 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3054 inst_env
->slot_needed
= 0;
3055 inst_env
->prefix_found
= 0;
3056 inst_env
->xflag_found
= 0;
3057 inst_env
->disable_interrupt
= 0;
3060 /* Handles the MOVEM to memory from general register instruction. */
3063 move_reg_to_mem_movem_op (unsigned short inst
, inst_env_type
*inst_env
)
3065 if (inst_env
->prefix_found
)
3067 /* The assign value is the value after the increment. Normally, the
3068 assign value is the value before the increment. */
3069 if ((cris_get_operand1 (inst
) == REG_PC
)
3070 && (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
))
3072 /* The prefix handles the problem if we are in a delay slot. */
3073 inst_env
->reg
[REG_PC
] = inst_env
->prefix_value
;
3074 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3079 /* The increment is not depending on the size, instead it's depending
3080 on the number of registers loaded to memory. */
3081 if ((cris_get_operand1 (inst
) == REG_PC
)
3082 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3084 /* It's invalid to change the PC in a delay slot. */
3085 if (inst_env
->slot_needed
)
3087 inst_env
->invalid
= 1;
3090 inst_env
->reg
[REG_PC
] += 4 * (cris_get_operand2 (inst
) + 1);
3093 inst_env
->slot_needed
= 0;
3094 inst_env
->prefix_found
= 0;
3095 inst_env
->xflag_found
= 0;
3096 inst_env
->disable_interrupt
= 0;
3099 /* Handles the intructions that's not yet implemented, by setting
3100 inst_env->invalid to true. */
3103 not_implemented_op (unsigned short inst
, inst_env_type
*inst_env
)
3105 inst_env
->invalid
= 1;
3108 /* Handles the XOR instruction. */
3111 xor_op (unsigned short inst
, inst_env_type
*inst_env
)
3113 /* XOR can't have a prefix. */
3114 if (inst_env
->prefix_found
)
3116 inst_env
->invalid
= 1;
3120 /* Check if the PC is the target. */
3121 if (cris_get_operand2 (inst
) == REG_PC
)
3123 /* It's invalid to change the PC in a delay slot. */
3124 if (inst_env
->slot_needed
)
3126 inst_env
->invalid
= 1;
3129 inst_env
->reg
[REG_PC
] ^= inst_env
->reg
[cris_get_operand1 (inst
)];
3131 inst_env
->slot_needed
= 0;
3132 inst_env
->prefix_found
= 0;
3133 inst_env
->xflag_found
= 0;
3134 inst_env
->disable_interrupt
= 0;
3137 /* Handles the MULS instruction. */
3140 muls_op (unsigned short inst
, inst_env_type
*inst_env
)
3142 /* MULS/U can't have a prefix. */
3143 if (inst_env
->prefix_found
)
3145 inst_env
->invalid
= 1;
3149 /* Consider it invalid if the PC is the target. */
3150 if (cris_get_operand2 (inst
) == REG_PC
)
3152 inst_env
->invalid
= 1;
3155 inst_env
->slot_needed
= 0;
3156 inst_env
->prefix_found
= 0;
3157 inst_env
->xflag_found
= 0;
3158 inst_env
->disable_interrupt
= 0;
3161 /* Handles the MULU instruction. */
3164 mulu_op (unsigned short inst
, inst_env_type
*inst_env
)
3166 /* MULS/U can't have a prefix. */
3167 if (inst_env
->prefix_found
)
3169 inst_env
->invalid
= 1;
3173 /* Consider it invalid if the PC is the target. */
3174 if (cris_get_operand2 (inst
) == REG_PC
)
3176 inst_env
->invalid
= 1;
3179 inst_env
->slot_needed
= 0;
3180 inst_env
->prefix_found
= 0;
3181 inst_env
->xflag_found
= 0;
3182 inst_env
->disable_interrupt
= 0;
3185 /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE.
3186 The MOVE instruction is the move from source to register. */
3189 add_sub_cmp_and_or_move_action (unsigned short inst
, inst_env_type
*inst_env
,
3190 unsigned long source1
, unsigned long source2
)
3192 unsigned long pc_mask
;
3193 unsigned long operation_mask
;
3195 /* Find out how many bits the operation should apply to. */
3196 if (cris_get_size (inst
) == INST_BYTE_SIZE
)
3198 pc_mask
= 0xFFFFFF00;
3199 operation_mask
= 0xFF;
3201 else if (cris_get_size (inst
) == INST_WORD_SIZE
)
3203 pc_mask
= 0xFFFF0000;
3204 operation_mask
= 0xFFFF;
3206 else if (cris_get_size (inst
) == INST_DWORD_SIZE
)
3209 operation_mask
= 0xFFFFFFFF;
3213 /* The size is out of range. */
3214 inst_env
->invalid
= 1;
3218 /* The instruction just works on uw_operation_mask bits. */
3219 source2
&= operation_mask
;
3220 source1
&= operation_mask
;
3222 /* Now calculate the result. The opcode's 3 first bits separates
3223 the different actions. */
3224 switch (cris_get_opcode (inst
) & 7)
3234 case 2: /* subtract */
3238 case 3: /* compare */
3250 inst_env
->invalid
= 1;
3256 /* Make sure that the result doesn't contain more than the instruction
3258 source2
&= operation_mask
;
3260 /* Calculate the new breakpoint address. */
3261 inst_env
->reg
[REG_PC
] &= pc_mask
;
3262 inst_env
->reg
[REG_PC
] |= source1
;
3266 /* Extends the value from either byte or word size to a dword. If the mode
3267 is zero extend then the value is extended with zero. If instead the mode
3268 is signed extend the sign bit of the value is taken into consideration. */
3270 static unsigned long
3271 do_sign_or_zero_extend (unsigned long value
, unsigned short *inst
)
3273 /* The size can be either byte or word, check which one it is.
3274 Don't check the highest bit, it's indicating if it's a zero
3276 if (cris_get_size (*inst
) & INST_WORD_SIZE
)
3281 /* Check if the instruction is signed extend. If so, check if value has
3283 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_WORD_MASK
))
3285 value
|= SIGNED_WORD_EXTEND_MASK
;
3293 /* Check if the instruction is signed extend. If so, check if value has
3295 if (cris_is_signed_extend_bit_on (*inst
) && (value
& SIGNED_BYTE_MASK
))
3297 value
|= SIGNED_BYTE_EXTEND_MASK
;
3300 /* The size should now be dword. */
3301 cris_set_size_to_dword (inst
);
3305 /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE
3306 instruction. The MOVE instruction is the move from source to register. */
3309 reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3310 inst_env_type
*inst_env
)
3312 unsigned long operand1
;
3313 unsigned long operand2
;
3315 /* It's invalid to have a prefix to the instruction. This is a register
3316 mode instruction and can't have a prefix. */
3317 if (inst_env
->prefix_found
)
3319 inst_env
->invalid
= 1;
3322 /* Check if the instruction has PC as its target. */
3323 if (cris_get_operand2 (inst
) == REG_PC
)
3325 if (inst_env
->slot_needed
)
3327 inst_env
->invalid
= 1;
3330 /* The instruction has the PC as its target register. */
3331 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3332 operand2
= inst_env
->reg
[REG_PC
];
3334 /* Check if it's a extend, signed or zero instruction. */
3335 if (cris_get_opcode (inst
) < 4)
3337 operand1
= do_sign_or_zero_extend (operand1
, &inst
);
3339 /* Calculate the PC value after the instruction, i.e. where the
3340 breakpoint should be. The order of the udw_operands is vital. */
3341 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3343 inst_env
->slot_needed
= 0;
3344 inst_env
->prefix_found
= 0;
3345 inst_env
->xflag_found
= 0;
3346 inst_env
->disable_interrupt
= 0;
3349 /* Returns the data contained at address. The size of the data is derived from
3350 the size of the operation. If the instruction is a zero or signed
3351 extend instruction, the size field is changed in instruction. */
3353 static unsigned long
3354 get_data_from_address (unsigned short *inst
, CORE_ADDR address
,
3355 enum bfd_endian byte_order
)
3357 int size
= cris_get_size (*inst
);
3358 unsigned long value
;
3360 /* If it's an extend instruction we don't want the signed extend bit,
3361 because it influences the size. */
3362 if (cris_get_opcode (*inst
) < 4)
3364 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3366 /* Is there a need for checking the size? Size should contain the number of
3369 value
= read_memory_unsigned_integer (address
, size
, byte_order
);
3371 /* Check if it's an extend, signed or zero instruction. */
3372 if (cris_get_opcode (*inst
) < 4)
3374 value
= do_sign_or_zero_extend (value
, inst
);
3379 /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3380 instructions. The MOVE instruction is the move from source to register. */
3383 handle_prefix_assign_mode_for_aritm_op (unsigned short inst
,
3384 inst_env_type
*inst_env
)
3386 unsigned long operand2
;
3387 unsigned long operand3
;
3389 check_assign (inst
, inst_env
);
3390 if (cris_get_operand2 (inst
) == REG_PC
)
3392 operand2
= inst_env
->reg
[REG_PC
];
3394 /* Get the value of the third operand. */
3395 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
,
3396 inst_env
->byte_order
);
3398 /* Calculate the PC value after the instruction, i.e. where the
3399 breakpoint should be. The order of the udw_operands is vital. */
3400 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3402 inst_env
->slot_needed
= 0;
3403 inst_env
->prefix_found
= 0;
3404 inst_env
->xflag_found
= 0;
3405 inst_env
->disable_interrupt
= 0;
3408 /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and
3409 OR instructions. Note that for this to work as expected, the calling
3410 function must have made sure that there is a prefix to this instruction. */
3413 three_operand_add_sub_cmp_and_or_op (unsigned short inst
,
3414 inst_env_type
*inst_env
)
3416 unsigned long operand2
;
3417 unsigned long operand3
;
3419 if (cris_get_operand1 (inst
) == REG_PC
)
3421 /* The PC will be changed by the instruction. */
3422 operand2
= inst_env
->reg
[cris_get_operand2 (inst
)];
3424 /* Get the value of the third operand. */
3425 operand3
= get_data_from_address (&inst
, inst_env
->prefix_value
,
3426 inst_env
->byte_order
);
3428 /* Calculate the PC value after the instruction, i.e. where the
3429 breakpoint should be. */
3430 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3432 inst_env
->slot_needed
= 0;
3433 inst_env
->prefix_found
= 0;
3434 inst_env
->xflag_found
= 0;
3435 inst_env
->disable_interrupt
= 0;
3438 /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE
3439 instructions. The MOVE instruction is the move from source to register. */
3442 handle_prefix_index_mode_for_aritm_op (unsigned short inst
,
3443 inst_env_type
*inst_env
)
3445 if (cris_get_operand1 (inst
) != cris_get_operand2 (inst
))
3447 /* If the instruction is MOVE it's invalid. If the instruction is ADD,
3448 SUB, AND or OR something weird is going on (if everything works these
3449 instructions should end up in the three operand version). */
3450 inst_env
->invalid
= 1;
3455 /* three_operand_add_sub_cmp_and_or does the same as we should do here
3457 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3459 inst_env
->slot_needed
= 0;
3460 inst_env
->prefix_found
= 0;
3461 inst_env
->xflag_found
= 0;
3462 inst_env
->disable_interrupt
= 0;
3465 /* Handles the autoincrement and indirect addresing mode for the ADD, SUB,
3466 CMP, AND OR and MOVE instruction. The MOVE instruction is the move from
3467 source to register. */
3470 handle_inc_and_index_mode_for_aritm_op (unsigned short inst
,
3471 inst_env_type
*inst_env
)
3473 unsigned long operand1
;
3474 unsigned long operand2
;
3475 unsigned long operand3
;
3478 /* The instruction is either an indirect or autoincrement addressing mode.
3479 Check if the destination register is the PC. */
3480 if (cris_get_operand2 (inst
) == REG_PC
)
3482 /* Must be done here, get_data_from_address may change the size
3484 size
= cris_get_size (inst
);
3485 operand2
= inst_env
->reg
[REG_PC
];
3487 /* Get the value of the third operand, i.e. the indirect operand. */
3488 operand1
= inst_env
->reg
[cris_get_operand1 (inst
)];
3489 operand3
= get_data_from_address (&inst
, operand1
, inst_env
->byte_order
);
3491 /* Calculate the PC value after the instruction, i.e. where the
3492 breakpoint should be. The order of the udw_operands is vital. */
3493 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand3
);
3495 /* If this is an autoincrement addressing mode, check if the increment
3497 if ((cris_get_operand1 (inst
) == REG_PC
)
3498 && (cris_get_mode (inst
) == AUTOINC_MODE
))
3500 /* Get the size field. */
3501 size
= cris_get_size (inst
);
3503 /* If it's an extend instruction we don't want the signed extend bit,
3504 because it influences the size. */
3505 if (cris_get_opcode (inst
) < 4)
3507 size
&= ~SIGNED_EXTEND_BIT_MASK
;
3509 process_autoincrement (size
, inst
, inst_env
);
3511 inst_env
->slot_needed
= 0;
3512 inst_env
->prefix_found
= 0;
3513 inst_env
->xflag_found
= 0;
3514 inst_env
->disable_interrupt
= 0;
3517 /* Handles the two-operand addressing mode, all modes except register, for
3518 the ADD, SUB CMP, AND and OR instruction. */
3521 none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst
,
3522 inst_env_type
*inst_env
)
3524 if (inst_env
->prefix_found
)
3526 if (cris_get_mode (inst
) == PREFIX_INDEX_MODE
)
3528 handle_prefix_index_mode_for_aritm_op (inst
, inst_env
);
3530 else if (cris_get_mode (inst
) == PREFIX_ASSIGN_MODE
)
3532 handle_prefix_assign_mode_for_aritm_op (inst
, inst_env
);
3536 /* The mode is invalid for a prefixed base instruction. */
3537 inst_env
->invalid
= 1;
3543 handle_inc_and_index_mode_for_aritm_op (inst
, inst_env
);
3547 /* Handles the quick addressing mode for the ADD and SUB instruction. */
3550 quick_mode_add_sub_op (unsigned short inst
, inst_env_type
*inst_env
)
3552 unsigned long operand1
;
3553 unsigned long operand2
;
3555 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3556 instruction and can't have a prefix. */
3557 if (inst_env
->prefix_found
)
3559 inst_env
->invalid
= 1;
3563 /* Check if the instruction has PC as its target. */
3564 if (cris_get_operand2 (inst
) == REG_PC
)
3566 if (inst_env
->slot_needed
)
3568 inst_env
->invalid
= 1;
3571 operand1
= cris_get_quick_value (inst
);
3572 operand2
= inst_env
->reg
[REG_PC
];
3574 /* The size should now be dword. */
3575 cris_set_size_to_dword (&inst
);
3577 /* Calculate the PC value after the instruction, i.e. where the
3578 breakpoint should be. */
3579 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3581 inst_env
->slot_needed
= 0;
3582 inst_env
->prefix_found
= 0;
3583 inst_env
->xflag_found
= 0;
3584 inst_env
->disable_interrupt
= 0;
3587 /* Handles the quick addressing mode for the CMP, AND and OR instruction. */
3590 quick_mode_and_cmp_move_or_op (unsigned short inst
, inst_env_type
*inst_env
)
3592 unsigned long operand1
;
3593 unsigned long operand2
;
3595 /* It's a bad idea to be in a prefix instruction now. This is a quick mode
3596 instruction and can't have a prefix. */
3597 if (inst_env
->prefix_found
)
3599 inst_env
->invalid
= 1;
3602 /* Check if the instruction has PC as its target. */
3603 if (cris_get_operand2 (inst
) == REG_PC
)
3605 if (inst_env
->slot_needed
)
3607 inst_env
->invalid
= 1;
3610 /* The instruction has the PC as its target register. */
3611 operand1
= cris_get_quick_value (inst
);
3612 operand2
= inst_env
->reg
[REG_PC
];
3614 /* The quick value is signed, so check if we must do a signed extend. */
3615 if (operand1
& SIGNED_QUICK_VALUE_MASK
)
3618 operand1
|= SIGNED_QUICK_VALUE_EXTEND_MASK
;
3620 /* The size should now be dword. */
3621 cris_set_size_to_dword (&inst
);
3623 /* Calculate the PC value after the instruction, i.e. where the
3624 breakpoint should be. */
3625 add_sub_cmp_and_or_move_action (inst
, inst_env
, operand2
, operand1
);
3627 inst_env
->slot_needed
= 0;
3628 inst_env
->prefix_found
= 0;
3629 inst_env
->xflag_found
= 0;
3630 inst_env
->disable_interrupt
= 0;
3633 /* Translate op_type to a function and call it. */
3636 cris_gdb_func (struct gdbarch
*gdbarch
, enum cris_op_type op_type
,
3637 unsigned short inst
, inst_env_type
*inst_env
)
3641 case cris_not_implemented_op
:
3642 not_implemented_op (inst
, inst_env
);
3646 abs_op (inst
, inst_env
);
3650 addi_op (inst
, inst_env
);
3654 asr_op (inst
, inst_env
);
3658 asrq_op (inst
, inst_env
);
3661 case cris_ax_ei_setf_op
:
3662 ax_ei_setf_op (inst
, inst_env
);
3665 case cris_bdap_prefix
:
3666 bdap_prefix (inst
, inst_env
);
3669 case cris_biap_prefix
:
3670 biap_prefix (inst
, inst_env
);
3674 break_op (inst
, inst_env
);
3677 case cris_btst_nop_op
:
3678 btst_nop_op (inst
, inst_env
);
3681 case cris_clearf_di_op
:
3682 clearf_di_op (inst
, inst_env
);
3685 case cris_dip_prefix
:
3686 dip_prefix (inst
, inst_env
);
3689 case cris_dstep_logshift_mstep_neg_not_op
:
3690 dstep_logshift_mstep_neg_not_op (inst
, inst_env
);
3693 case cris_eight_bit_offset_branch_op
:
3694 eight_bit_offset_branch_op (inst
, inst_env
);
3697 case cris_move_mem_to_reg_movem_op
:
3698 move_mem_to_reg_movem_op (inst
, inst_env
);
3701 case cris_move_reg_to_mem_movem_op
:
3702 move_reg_to_mem_movem_op (inst
, inst_env
);
3705 case cris_move_to_preg_op
:
3706 move_to_preg_op (gdbarch
, inst
, inst_env
);
3710 muls_op (inst
, inst_env
);
3714 mulu_op (inst
, inst_env
);
3717 case cris_none_reg_mode_add_sub_cmp_and_or_move_op
:
3718 none_reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3721 case cris_none_reg_mode_clear_test_op
:
3722 none_reg_mode_clear_test_op (inst
, inst_env
);
3725 case cris_none_reg_mode_jump_op
:
3726 none_reg_mode_jump_op (inst
, inst_env
);
3729 case cris_none_reg_mode_move_from_preg_op
:
3730 none_reg_mode_move_from_preg_op (gdbarch
, inst
, inst_env
);
3733 case cris_quick_mode_add_sub_op
:
3734 quick_mode_add_sub_op (inst
, inst_env
);
3737 case cris_quick_mode_and_cmp_move_or_op
:
3738 quick_mode_and_cmp_move_or_op (inst
, inst_env
);
3741 case cris_quick_mode_bdap_prefix
:
3742 quick_mode_bdap_prefix (inst
, inst_env
);
3745 case cris_reg_mode_add_sub_cmp_and_or_move_op
:
3746 reg_mode_add_sub_cmp_and_or_move_op (inst
, inst_env
);
3749 case cris_reg_mode_clear_op
:
3750 reg_mode_clear_op (inst
, inst_env
);
3753 case cris_reg_mode_jump_op
:
3754 reg_mode_jump_op (inst
, inst_env
);
3757 case cris_reg_mode_move_from_preg_op
:
3758 reg_mode_move_from_preg_op (inst
, inst_env
);
3761 case cris_reg_mode_test_op
:
3762 reg_mode_test_op (inst
, inst_env
);
3766 scc_op (inst
, inst_env
);
3769 case cris_sixteen_bit_offset_branch_op
:
3770 sixteen_bit_offset_branch_op (inst
, inst_env
);
3773 case cris_three_operand_add_sub_cmp_and_or_op
:
3774 three_operand_add_sub_cmp_and_or_op (inst
, inst_env
);
3777 case cris_three_operand_bound_op
:
3778 three_operand_bound_op (inst
, inst_env
);
3781 case cris_two_operand_bound_op
:
3782 two_operand_bound_op (inst
, inst_env
);
3786 xor_op (inst
, inst_env
);
3791 /* This wrapper is to avoid cris_get_assembler being called before
3792 exec_bfd has been set. */
3795 cris_delayed_get_disassembler (bfd_vma addr
, struct disassemble_info
*info
)
3797 int (*print_insn
) (bfd_vma addr
, struct disassemble_info
*info
);
3798 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
3799 disassembler, even when there is no BFD. Does something like
3800 "gdb; target remote; disassmeble *0x123" work? */
3801 gdb_assert (exec_bfd
!= NULL
);
3802 print_insn
= cris_get_disassembler (exec_bfd
);
3803 gdb_assert (print_insn
!= NULL
);
3804 return print_insn (addr
, info
);
3807 /* Originally from <asm/elf.h>. */
3808 typedef unsigned char cris_elf_greg_t
[4];
3810 /* Same as user_regs_struct struct in <asm/user.h>. */
3811 #define CRISV10_ELF_NGREG 35
3812 typedef cris_elf_greg_t cris_elf_gregset_t
[CRISV10_ELF_NGREG
];
3814 #define CRISV32_ELF_NGREG 32
3815 typedef cris_elf_greg_t crisv32_elf_gregset_t
[CRISV32_ELF_NGREG
];
3817 /* Unpack a cris_elf_gregset_t into GDB's register cache. */
3820 cris_supply_gregset (struct regcache
*regcache
, cris_elf_gregset_t
*gregsetp
)
3822 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3823 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3825 cris_elf_greg_t
*regp
= *gregsetp
;
3827 /* The kernel dumps all 32 registers as unsigned longs, but supply_register
3828 knows about the actual size of each register so that's no problem. */
3829 for (i
= 0; i
< NUM_GENREGS
+ NUM_SPECREGS
; i
++)
3831 regcache_raw_supply (regcache
, i
, (char *)®p
[i
]);
3834 if (tdep
->cris_version
== 32)
3836 /* Needed to set pseudo-register PC for CRISv32. */
3837 /* FIXME: If ERP is in a delay slot at this point then the PC will
3838 be wrong. Issue a warning to alert the user. */
3839 regcache_raw_supply (regcache
, gdbarch_pc_regnum (gdbarch
),
3840 (char *)®p
[ERP_REGNUM
]);
3842 if (*(char *)®p
[ERP_REGNUM
] & 0x1)
3843 fprintf_unfiltered (gdb_stderr
, "Warning: PC in delay slot\n");
3847 /* Use a local version of this function to get the correct types for
3848 regsets, until multi-arch core support is ready. */
3851 fetch_core_registers (struct regcache
*regcache
,
3852 char *core_reg_sect
, unsigned core_reg_size
,
3853 int which
, CORE_ADDR reg_addr
)
3855 cris_elf_gregset_t gregset
;
3860 if (core_reg_size
!= sizeof (cris_elf_gregset_t
)
3861 && core_reg_size
!= sizeof (crisv32_elf_gregset_t
))
3863 warning (_("wrong size gregset struct in core file"));
3867 memcpy (&gregset
, core_reg_sect
, sizeof (gregset
));
3868 cris_supply_gregset (regcache
, &gregset
);
3872 /* We've covered all the kinds of registers we know about here,
3873 so this must be something we wouldn't know what to do with
3874 anyway. Just ignore it. */
3879 static struct core_fns cris_elf_core_fns
=
3881 bfd_target_elf_flavour
, /* core_flavour */
3882 default_check_format
, /* check_format */
3883 default_core_sniffer
, /* core_sniffer */
3884 fetch_core_registers
, /* core_read_registers */
3888 extern initialize_file_ftype _initialize_cris_tdep
; /* -Wmissing-prototypes */
3891 _initialize_cris_tdep (void)
3893 gdbarch_register (bfd_arch_cris
, cris_gdbarch_init
, cris_dump_tdep
);
3895 /* CRIS-specific user-commands. */
3896 add_setshow_zuinteger_cmd ("cris-version", class_support
,
3897 &usr_cmd_cris_version
,
3898 _("Set the current CRIS version."),
3899 _("Show the current CRIS version."),
3901 Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\
3904 NULL
, /* FIXME: i18n: Current CRIS version
3906 &setlist
, &showlist
);
3908 add_setshow_enum_cmd ("cris-mode", class_support
,
3909 cris_modes
, &usr_cmd_cris_mode
,
3910 _("Set the current CRIS mode."),
3911 _("Show the current CRIS mode."),
3913 Set to CRIS_MODE_GURU when debugging in guru mode.\n\
3914 Makes GDB use the NRP register instead of the ERP register in certain cases."),
3916 NULL
, /* FIXME: i18n: Current CRIS version is %s. */
3917 &setlist
, &showlist
);
3919 add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support
,
3920 &usr_cmd_cris_dwarf2_cfi
,
3921 _("Set the usage of Dwarf-2 CFI for CRIS."),
3922 _("Show the usage of Dwarf-2 CFI for CRIS."),
3923 _("Set this to \"off\" if using gcc-cris < R59."),
3924 set_cris_dwarf2_cfi
,
3925 NULL
, /* FIXME: i18n: Usage of Dwarf-2 CFI
3927 &setlist
, &showlist
);
3929 deprecated_add_core_fns (&cris_elf_core_fns
);
3932 /* Prints out all target specific values. */
3935 cris_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3940 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_version = %i\n",
3941 tdep
->cris_version
);
3942 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_mode = %s\n",
3944 fprintf_unfiltered (file
, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n",
3945 tdep
->cris_dwarf2_cfi
);
3950 set_cris_version (char *ignore_args
, int from_tty
,
3951 struct cmd_list_element
*c
)
3953 struct gdbarch_info info
;
3955 usr_cmd_cris_version_valid
= 1;
3957 /* Update the current architecture, if needed. */
3958 gdbarch_info_init (&info
);
3959 if (!gdbarch_update_p (info
))
3960 internal_error (__FILE__
, __LINE__
,
3961 _("cris_gdbarch_update: failed to update architecture."));
3965 set_cris_mode (char *ignore_args
, int from_tty
,
3966 struct cmd_list_element
*c
)
3968 struct gdbarch_info info
;
3970 /* Update the current architecture, if needed. */
3971 gdbarch_info_init (&info
);
3972 if (!gdbarch_update_p (info
))
3973 internal_error (__FILE__
, __LINE__
,
3974 "cris_gdbarch_update: failed to update architecture.");
3978 set_cris_dwarf2_cfi (char *ignore_args
, int from_tty
,
3979 struct cmd_list_element
*c
)
3981 struct gdbarch_info info
;
3983 /* Update the current architecture, if needed. */
3984 gdbarch_info_init (&info
);
3985 if (!gdbarch_update_p (info
))
3986 internal_error (__FILE__
, __LINE__
,
3987 _("cris_gdbarch_update: failed to update architecture."));
3990 static struct gdbarch
*
3991 cris_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3993 struct gdbarch
*gdbarch
;
3994 struct gdbarch_tdep
*tdep
;
3995 unsigned int cris_version
;
3997 if (usr_cmd_cris_version_valid
)
3999 /* Trust the user's CRIS version setting. */
4000 cris_version
= usr_cmd_cris_version
;
4002 else if (info
.abfd
&& bfd_get_mach (info
.abfd
) == bfd_mach_cris_v32
)
4008 /* Assume it's CRIS version 10. */
4012 /* Make the current settings visible to the user. */
4013 usr_cmd_cris_version
= cris_version
;
4015 /* Find a candidate among the list of pre-declared architectures. */
4016 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4018 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4020 if ((gdbarch_tdep (arches
->gdbarch
)->cris_version
4021 == usr_cmd_cris_version
)
4022 && (gdbarch_tdep (arches
->gdbarch
)->cris_mode
4023 == usr_cmd_cris_mode
)
4024 && (gdbarch_tdep (arches
->gdbarch
)->cris_dwarf2_cfi
4025 == usr_cmd_cris_dwarf2_cfi
))
4026 return arches
->gdbarch
;
4029 /* No matching architecture was found. Create a new one. */
4030 tdep
= XNEW (struct gdbarch_tdep
);
4031 gdbarch
= gdbarch_alloc (&info
, tdep
);
4033 tdep
->cris_version
= usr_cmd_cris_version
;
4034 tdep
->cris_mode
= usr_cmd_cris_mode
;
4035 tdep
->cris_dwarf2_cfi
= usr_cmd_cris_dwarf2_cfi
;
4037 /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */
4038 switch (info
.byte_order
)
4040 case BFD_ENDIAN_LITTLE
:
4044 case BFD_ENDIAN_BIG
:
4045 /* Cris is always little endian, but the user could have forced
4046 big endian with "set endian". */
4050 internal_error (__FILE__
, __LINE__
,
4051 _("cris_gdbarch_init: unknown byte order in info"));
4054 set_gdbarch_return_value (gdbarch
, cris_return_value
);
4056 set_gdbarch_sp_regnum (gdbarch
, 14);
4058 /* Length of ordinary registers used in push_word and a few other
4059 places. register_size() is the real way to know how big a
4062 set_gdbarch_double_bit (gdbarch
, 64);
4063 /* The default definition of a long double is 2 * gdbarch_double_bit,
4064 which means we have to set this explicitly. */
4065 set_gdbarch_long_double_bit (gdbarch
, 64);
4067 /* The total amount of space needed to store (in an array called registers)
4068 GDB's copy of the machine's register state. Note: We can not use
4069 cris_register_size at this point, since it relies on gdbarch
4071 switch (tdep
->cris_version
)
4079 /* Old versions; not supported. */
4084 /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100,
4085 P7 (32 bits), and P15 (32 bits) have been implemented. */
4086 set_gdbarch_pc_regnum (gdbarch
, 15);
4087 set_gdbarch_register_type (gdbarch
, cris_register_type
);
4088 /* There are 32 registers (some of which may not be implemented). */
4089 set_gdbarch_num_regs (gdbarch
, 32);
4090 set_gdbarch_register_name (gdbarch
, cris_register_name
);
4091 set_gdbarch_cannot_store_register (gdbarch
, cris_cannot_store_register
);
4092 set_gdbarch_cannot_fetch_register (gdbarch
, cris_cannot_fetch_register
);
4094 set_gdbarch_software_single_step (gdbarch
, cris_software_single_step
);
4098 /* CRIS v32. General registers R0 - R15 (32 bits), special registers
4099 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
4100 and pseudo-register PC (32 bits). */
4101 set_gdbarch_pc_regnum (gdbarch
, 32);
4102 set_gdbarch_register_type (gdbarch
, crisv32_register_type
);
4103 /* 32 registers + pseudo-register PC + 16 support registers. */
4104 set_gdbarch_num_regs (gdbarch
, 32 + 1 + 16);
4105 set_gdbarch_register_name (gdbarch
, crisv32_register_name
);
4107 set_gdbarch_cannot_store_register
4108 (gdbarch
, crisv32_cannot_store_register
);
4109 set_gdbarch_cannot_fetch_register
4110 (gdbarch
, crisv32_cannot_fetch_register
);
4112 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4114 set_gdbarch_single_step_through_delay
4115 (gdbarch
, crisv32_single_step_through_delay
);
4120 /* Unknown version. */
4124 /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
4125 have the same ABI). */
4126 set_gdbarch_push_dummy_code (gdbarch
, cris_push_dummy_code
);
4127 set_gdbarch_push_dummy_call (gdbarch
, cris_push_dummy_call
);
4128 set_gdbarch_frame_align (gdbarch
, cris_frame_align
);
4129 set_gdbarch_skip_prologue (gdbarch
, cris_skip_prologue
);
4131 /* The stack grows downward. */
4132 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4134 SET_GDBARCH_BREAKPOINT_MANIPULATION (cris
);
4136 set_gdbarch_unwind_pc (gdbarch
, cris_unwind_pc
);
4137 set_gdbarch_unwind_sp (gdbarch
, cris_unwind_sp
);
4138 set_gdbarch_dummy_id (gdbarch
, cris_dummy_id
);
4140 if (tdep
->cris_dwarf2_cfi
== 1)
4142 /* Hook in the Dwarf-2 frame sniffer. */
4143 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, cris_dwarf2_reg_to_regnum
);
4144 dwarf2_frame_set_init_reg (gdbarch
, cris_dwarf2_frame_init_reg
);
4145 dwarf2_append_unwinders (gdbarch
);
4148 if (tdep
->cris_mode
!= cris_mode_guru
)
4150 frame_unwind_append_unwinder (gdbarch
, &cris_sigtramp_frame_unwind
);
4153 frame_unwind_append_unwinder (gdbarch
, &cris_frame_unwind
);
4154 frame_base_set_default (gdbarch
, &cris_frame_base
);
4156 /* Hook in ABI-specific overrides, if they have been registered. */
4157 gdbarch_init_osabi (info
, gdbarch
);
4159 /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS
4160 disassembler, even when there is no BFD. Does something like
4161 "gdb; target remote; disassmeble *0x123" work? */
4162 set_gdbarch_print_insn (gdbarch
, cris_delayed_get_disassembler
);