1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
48 #include "gdb_assert.h"
54 unsigned long (*dmap_register
) (void *regcache
, int nr
);
55 unsigned long (*imap_register
) (void *regcache
, int nr
);
58 /* These are the addresses the D10V-EVA board maps data and
59 instruction memory to. */
62 DMEM_START
= 0x2000000,
63 IMEM_START
= 0x1000000,
64 STACK_START
= 0x200bffe
67 /* d10v register names. */
82 /* d10v calling convention. */
83 ARG1_REGNUM
= R0_REGNUM
,
84 ARGN_REGNUM
= R3_REGNUM
,
85 RET1_REGNUM
= R0_REGNUM
,
89 nr_dmap_regs (struct gdbarch
*gdbarch
)
91 return gdbarch_tdep (gdbarch
)->nr_dmap_regs
;
95 a0_regnum (struct gdbarch
*gdbarch
)
97 return gdbarch_tdep (gdbarch
)->a0_regnum
;
100 /* Local functions */
102 extern void _initialize_d10v_tdep (void);
104 static CORE_ADDR
d10v_read_sp (void);
106 static void d10v_eva_prepare_to_trace (void);
108 static void d10v_eva_get_trace_data (void);
111 d10v_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
113 /* Align to the size of an instruction (so that they can safely be
114 pushed onto the stack. */
118 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
119 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
120 and TYPE is the type (which is known to be struct, union or array).
122 The d10v returns anything less than 8 bytes in size in
126 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
130 /* The d10v only passes a struct in a register when that structure
131 has an alignment that matches the size of a register. */
132 /* If the structure doesn't fit in 4 registers, put it on the
134 if (TYPE_LENGTH (type
) > 8)
136 /* If the struct contains only one field, don't put it on the stack
137 - gcc can fit it in one or more registers. */
138 if (TYPE_NFIELDS (type
) == 1)
140 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
141 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
143 /* If the alignment changes, just assume it goes on the
145 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
148 /* If the alignment is suitable for the d10v's 16 bit registers,
149 don't put it on the stack. */
150 if (alignment
== 2 || alignment
== 4)
156 static const unsigned char *
157 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
159 static unsigned char breakpoint
[] =
160 {0x2f, 0x90, 0x5e, 0x00};
161 *lenptr
= sizeof (breakpoint
);
165 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
166 when the reg_nr isn't valid. */
170 TS2_IMAP0_REGNUM
= 32,
171 TS2_DMAP_REGNUM
= 34,
172 TS2_NR_DMAP_REGS
= 1,
177 d10v_ts2_register_name (int reg_nr
)
179 static char *register_names
[] =
181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
182 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
183 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
184 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
185 "imap0", "imap1", "dmap", "a0", "a1"
189 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
191 return register_names
[reg_nr
];
196 TS3_IMAP0_REGNUM
= 36,
197 TS3_DMAP0_REGNUM
= 38,
198 TS3_NR_DMAP_REGS
= 4,
203 d10v_ts3_register_name (int reg_nr
)
205 static char *register_names
[] =
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
210 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
214 "dmap0", "dmap1", "dmap2", "dmap3"
218 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
220 return register_names
[reg_nr
];
223 /* Access the DMAP/IMAP registers in a target independent way.
225 Divide the D10V's 64k data space into four 16k segments:
226 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
229 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
230 0x7fff) always map to the on-chip data RAM, and the fourth always
231 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
232 unified memory or instruction memory, under the control of the
233 single DMAP register.
235 On the TS3, there are four DMAP registers, each of which controls
236 one of the segments. */
239 d10v_ts2_dmap_register (void *regcache
, int reg_nr
)
249 regcache_cooked_read_unsigned (regcache
, TS2_DMAP_REGNUM
, ®
);
258 d10v_ts3_dmap_register (void *regcache
, int reg_nr
)
261 regcache_cooked_read_unsigned (regcache
, TS3_DMAP0_REGNUM
+ reg_nr
, ®
);
266 d10v_ts2_imap_register (void *regcache
, int reg_nr
)
269 regcache_cooked_read_unsigned (regcache
, TS2_IMAP0_REGNUM
+ reg_nr
, ®
);
274 d10v_ts3_imap_register (void *regcache
, int reg_nr
)
277 regcache_cooked_read_unsigned (regcache
, TS3_IMAP0_REGNUM
+ reg_nr
, ®
);
281 /* MAP GDB's internal register numbering (determined by the layout fo
282 the REGISTER_BYTE array) onto the simulator's register
286 d10v_ts2_register_sim_regno (int nr
)
288 /* Only makes sense to supply raw registers. */
289 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
290 if (nr
>= TS2_IMAP0_REGNUM
291 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
292 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
293 if (nr
== TS2_DMAP_REGNUM
)
294 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
295 if (nr
>= TS2_A0_REGNUM
296 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
297 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
302 d10v_ts3_register_sim_regno (int nr
)
304 /* Only makes sense to supply raw registers. */
305 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
306 if (nr
>= TS3_IMAP0_REGNUM
307 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
308 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
309 if (nr
>= TS3_DMAP0_REGNUM
310 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
311 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
312 if (nr
>= TS3_A0_REGNUM
313 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
314 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
318 /* Return the GDB type object for the "standard" data type
319 of data in register N. */
322 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
324 if (reg_nr
== D10V_PC_REGNUM
)
325 return builtin_type_void_func_ptr
;
326 if (reg_nr
== D10V_SP_REGNUM
|| reg_nr
== D10V_FP_REGNUM
)
327 return builtin_type_void_data_ptr
;
328 else if (reg_nr
>= a0_regnum (gdbarch
)
329 && reg_nr
< (a0_regnum (gdbarch
) + NR_A_REGS
))
330 return builtin_type_int64
;
332 return builtin_type_int16
;
336 d10v_daddr_p (CORE_ADDR x
)
338 return (((x
) & 0x3000000) == DMEM_START
);
342 d10v_iaddr_p (CORE_ADDR x
)
344 return (((x
) & 0x3000000) == IMEM_START
);
348 d10v_make_daddr (CORE_ADDR x
)
350 return ((x
) | DMEM_START
);
354 d10v_make_iaddr (CORE_ADDR x
)
356 if (d10v_iaddr_p (x
))
357 return x
; /* Idempotency -- x is already in the IMEM space. */
359 return (((x
) << 2) | IMEM_START
);
363 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
365 return (((x
) >> 2) & 0xffff);
369 d10v_convert_daddr_to_raw (CORE_ADDR x
)
371 return ((x
) & 0xffff);
375 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
377 /* Is it a code address? */
378 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
379 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
381 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
382 d10v_convert_iaddr_to_raw (addr
));
386 /* Strip off any upper segment bits. */
387 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
388 d10v_convert_daddr_to_raw (addr
));
393 d10v_pointer_to_address (struct type
*type
, const void *buf
)
395 CORE_ADDR addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
396 /* Is it a code address? */
397 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
398 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
399 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
400 return d10v_make_iaddr (addr
);
402 return d10v_make_daddr (addr
);
405 /* Don't do anything if we have an integer, this way users can type 'x
406 <addr>' w/o having gdb outsmart them. The internal gdb conversions
407 to the correct space are taken care of in the pointer_to_address
408 function. If we don't do this, 'x $fp' wouldn't work. */
410 d10v_integer_to_address (struct type
*type
, void *buf
)
413 val
= unpack_long (type
, buf
);
417 /* Write into appropriate registers a function return value
418 of type TYPE, given in virtual format.
420 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
423 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
426 /* Only char return values need to be shifted right within the first
428 if (TYPE_LENGTH (type
) == 1
429 && TYPE_CODE (type
) == TYPE_CODE_INT
)
432 tmp
[1] = *(bfd_byte
*)valbuf
;
433 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
438 /* A structure is never more than 8 bytes long. See
439 use_struct_convention(). */
440 gdb_assert (TYPE_LENGTH (type
) <= 8);
441 /* Write out most registers, stop loop before trying to write
442 out any dangling byte at the end of the buffer. */
443 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
445 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
446 (bfd_byte
*) valbuf
+ reg
* 2);
448 /* Write out any dangling byte at the end of the buffer. */
449 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
450 regcache_cooked_write_part (regcache
, reg
, 0, 1,
451 (bfd_byte
*) valbuf
+ reg
* 2);
455 /* Extract from an array REGBUF containing the (raw) register state
456 the address in which a function should return its structure value,
457 as a CORE_ADDR (or an expression that can be used as one). */
460 d10v_extract_struct_value_address (struct regcache
*regcache
)
463 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
464 return (addr
| DMEM_START
);
468 check_prologue (unsigned short op
)
471 if ((op
& 0x7E1F) == 0x6C1F)
475 if ((op
& 0x7E3F) == 0x6E1F)
479 if ((op
& 0x7FE1) == 0x01E1)
491 if ((op
& 0x7E1F) == 0x681E)
495 if ((op
& 0x7E3F) == 0x3A1E)
502 d10v_skip_prologue (CORE_ADDR pc
)
505 unsigned short op1
, op2
;
506 CORE_ADDR func_addr
, func_end
;
507 struct symtab_and_line sal
;
509 /* If we have line debugging information, then the end of the */
510 /* prologue should the first assembly instruction of the first source line */
511 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
513 sal
= find_pc_line (func_addr
, 0);
514 if (sal
.end
&& sal
.end
< func_end
)
518 if (target_read_memory (pc
, (char *) &op
, 4))
519 return pc
; /* Can't access it -- assume no prologue. */
523 op
= (unsigned long) read_memory_integer (pc
, 4);
524 if ((op
& 0xC0000000) == 0xC0000000)
526 /* long instruction */
527 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
528 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
529 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
534 /* short instructions */
535 if ((op
& 0xC0000000) == 0x80000000)
537 op2
= (op
& 0x3FFF8000) >> 15;
542 op1
= (op
& 0x3FFF8000) >> 15;
545 if (check_prologue (op1
))
547 if (!check_prologue (op2
))
549 /* if the previous opcode was really part of the prologue */
550 /* and not just a NOP, then we want to break after both instructions */
564 struct d10v_unwind_cache
566 /* The previous frame's inner most stack address. Used as this
567 frame ID's stack_addr. */
569 /* The frame's base, optionally used by the high-level debug info. */
572 CORE_ADDR
*saved_regs
;
573 /* How far the SP and r11 (FP) have been offset from the start of
574 the stack frame (as defined by the previous frame's stack
583 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
589 if ((op
& 0x7E1F) == 0x6C1F)
591 n
= (op
& 0x1E0) >> 5;
592 info
->sp_offset
-= 2;
593 info
->saved_regs
[n
] = info
->sp_offset
;
598 else if ((op
& 0x7E3F) == 0x6E1F)
600 n
= (op
& 0x1E0) >> 5;
601 info
->sp_offset
-= 4;
602 info
->saved_regs
[n
] = info
->sp_offset
;
603 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
608 if ((op
& 0x7FE1) == 0x01E1)
610 n
= (op
& 0x1E) >> 1;
613 info
->sp_offset
-= n
;
620 info
->uses_frame
= 1;
621 info
->r11_offset
= info
->sp_offset
;
626 if ((op
& 0x7E1F) == 0x6816)
628 n
= (op
& 0x1E0) >> 5;
629 info
->saved_regs
[n
] = info
->r11_offset
;
638 if ((op
& 0x7E1F) == 0x681E)
640 n
= (op
& 0x1E0) >> 5;
641 info
->saved_regs
[n
] = info
->sp_offset
;
646 if ((op
& 0x7E3F) == 0x3A1E)
648 n
= (op
& 0x1E0) >> 5;
649 info
->saved_regs
[n
] = info
->sp_offset
;
650 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
657 /* Put here the code to store, into fi->saved_regs, the addresses of
658 the saved registers of frame described by FRAME_INFO. This
659 includes special registers such as pc and fp saved in special ways
660 in the stack frame. sp is even more special: the address we return
661 for it IS the sp for the next frame. */
663 struct d10v_unwind_cache
*
664 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
665 void **this_prologue_cache
)
667 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
672 unsigned short op1
, op2
;
674 struct d10v_unwind_cache
*info
;
676 if ((*this_prologue_cache
))
677 return (*this_prologue_cache
);
679 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
680 (*this_prologue_cache
) = info
;
681 info
->saved_regs
= FRAME_OBSTACK_CALLOC (NUM_REGS
, CORE_ADDR
);
686 info
->uses_frame
= 0;
687 for (pc
= frame_func_unwind (next_frame
);
688 pc
> 0 && pc
< frame_pc_unwind (next_frame
);
691 op
= get_frame_memory_unsigned (next_frame
, pc
, 4);
692 if ((op
& 0xC0000000) == 0xC0000000)
694 /* long instruction */
695 if ((op
& 0x3FFF0000) == 0x01FF0000)
698 short n
= op
& 0xFFFF;
699 info
->sp_offset
+= n
;
701 else if ((op
& 0x3F0F0000) == 0x340F0000)
703 /* st rn, @(offset,sp) */
704 short offset
= op
& 0xFFFF;
705 short n
= (op
>> 20) & 0xF;
706 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
708 else if ((op
& 0x3F1F0000) == 0x350F0000)
710 /* st2w rn, @(offset,sp) */
711 short offset
= op
& 0xFFFF;
712 short n
= (op
>> 20) & 0xF;
713 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
714 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ offset
+ 2;
721 /* short instructions */
722 if ((op
& 0xC0000000) == 0x80000000)
724 op2
= (op
& 0x3FFF8000) >> 15;
729 op1
= (op
& 0x3FFF8000) >> 15;
732 if (!prologue_find_regs (info
, op1
, pc
)
733 || !prologue_find_regs (info
, op2
, pc
))
738 info
->size
= -info
->sp_offset
;
740 /* Compute the frame's base, and the previous frame's SP. */
741 if (info
->uses_frame
)
743 /* The SP was moved to the FP. This indicates that a new frame
744 was created. Get THIS frame's FP value by unwinding it from
746 frame_unwind_unsigned_register (next_frame
, D10V_FP_REGNUM
, &this_base
);
747 /* The FP points at the last saved register. Adjust the FP back
748 to before the first saved register giving the SP. */
749 prev_sp
= this_base
+ info
->size
;
751 else if (info
->saved_regs
[D10V_SP_REGNUM
])
753 /* The SP was saved (which is very unusual), the frame base is
754 just the PREV's frame's TOP-OF-STACK. */
756 = get_frame_memory_unsigned (next_frame
,
757 info
->saved_regs
[D10V_SP_REGNUM
],
758 register_size (gdbarch
, D10V_SP_REGNUM
));
763 /* Assume that the FP is this frame's SP but with that pushed
764 stack space added back. */
765 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &this_base
);
766 prev_sp
= this_base
+ info
->size
;
769 info
->base
= d10v_make_daddr (this_base
);
770 info
->prev_sp
= d10v_make_daddr (prev_sp
);
772 /* Adjust all the saved registers so that they contain addresses and
774 for (i
= 0; i
< NUM_REGS
- 1; i
++)
775 if (info
->saved_regs
[i
])
777 info
->saved_regs
[i
] = (info
->prev_sp
+ info
->saved_regs
[i
]);
780 /* The D10V_SP_REGNUM is special. Instead of the address of the SP, the
781 previous frame's SP value is saved. */
782 info
->saved_regs
[D10V_SP_REGNUM
] = info
->prev_sp
;
788 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
789 struct frame_info
*frame
, int regnum
, int all
)
791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
794 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
799 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
800 frame_read_unsigned_register (frame
, D10V_PC_REGNUM
, &pc
);
801 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
802 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s
);
803 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e
);
804 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c
);
805 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
806 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
807 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
812 for (group
= 0; group
< 16; group
+= 8)
815 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
816 for (r
= group
; r
< group
+ 8; r
++)
819 frame_read_unsigned_register (frame
, r
, &tmp
);
820 fprintf_filtered (file
, " %04lx", (long) tmp
);
822 fprintf_filtered (file
, "\n");
826 /* Note: The IMAP/DMAP registers don't participate in function
827 calls. Don't bother trying to unwind them. */
831 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
834 fprintf_filtered (file
, " ");
835 fprintf_filtered (file
, "IMAP%d %04lx", a
,
836 tdep
->imap_register (current_regcache
, a
));
838 if (nr_dmap_regs (gdbarch
) == 1)
839 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
840 fprintf_filtered (file
, " DMAP %04lx\n",
841 tdep
->dmap_register (current_regcache
, 2));
844 for (a
= 0; a
< nr_dmap_regs (gdbarch
); a
++)
846 fprintf_filtered (file
, " DMAP%d %04lx", a
,
847 tdep
->dmap_register (current_regcache
, a
));
849 fprintf_filtered (file
, "\n");
854 char num
[MAX_REGISTER_SIZE
];
856 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
857 for (a
= a0_regnum (gdbarch
); a
< a0_regnum (gdbarch
) + NR_A_REGS
; a
++)
860 fprintf_filtered (file
, " ");
861 frame_read_register (frame
, a
, num
);
862 for (i
= 0; i
< register_size (gdbarch
, a
); i
++)
864 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
868 fprintf_filtered (file
, "\n");
872 show_regs (char *args
, int from_tty
)
874 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
875 get_current_frame (), -1, 1);
879 d10v_read_pc (ptid_t ptid
)
885 save_ptid
= inferior_ptid
;
886 inferior_ptid
= ptid
;
887 pc
= (int) read_register (D10V_PC_REGNUM
);
888 inferior_ptid
= save_ptid
;
889 retval
= d10v_make_iaddr (pc
);
894 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
898 save_ptid
= inferior_ptid
;
899 inferior_ptid
= ptid
;
900 write_register (D10V_PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
901 inferior_ptid
= save_ptid
;
907 return (d10v_make_daddr (read_register (D10V_SP_REGNUM
)));
910 /* When arguments must be pushed onto the stack, they go on in reverse
911 order. The below implements a FILO (stack) to do this. */
916 struct stack_item
*prev
;
920 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
921 void *contents
, int len
);
922 static struct stack_item
*
923 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
925 struct stack_item
*si
;
926 si
= xmalloc (sizeof (struct stack_item
));
927 si
->data
= xmalloc (len
);
930 memcpy (si
->data
, contents
, len
);
934 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
935 static struct stack_item
*
936 pop_stack_item (struct stack_item
*si
)
938 struct stack_item
*dead
= si
;
947 d10v_push_dummy_code (struct gdbarch
*gdbarch
,
948 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
949 struct value
**args
, int nargs
,
950 struct type
*value_type
,
951 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
953 /* Allocate space sufficient for a breakpoint. */
955 /* Store the address of that breakpoint taking care to first convert
956 it into a code (IADDR) address from a stack (DADDR) address.
957 This of course assumes that the two virtual addresses map onto
958 the same real address. */
959 (*bp_addr
) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp
));
960 /* d10v always starts the call at the callee's entry point. */
961 (*real_pc
) = funaddr
;
966 d10v_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
967 struct regcache
*regcache
, CORE_ADDR bp_addr
,
968 int nargs
, struct value
**args
, CORE_ADDR sp
, int struct_return
,
969 CORE_ADDR struct_addr
)
972 int regnum
= ARG1_REGNUM
;
973 struct stack_item
*si
= NULL
;
976 /* Set the return address. For the d10v, the return breakpoint is
977 always at BP_ADDR. */
978 regcache_cooked_write_unsigned (regcache
, LR_REGNUM
,
979 d10v_convert_iaddr_to_raw (bp_addr
));
981 /* If STRUCT_RETURN is true, then the struct return address (in
982 STRUCT_ADDR) will consume the first argument-passing register.
983 Both adjust the register count and store that value. */
986 regcache_cooked_write_unsigned (regcache
, regnum
, struct_addr
);
990 /* Fill in registers and arg lists */
991 for (i
= 0; i
< nargs
; i
++)
993 struct value
*arg
= args
[i
];
994 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
995 char *contents
= VALUE_CONTENTS (arg
);
996 int len
= TYPE_LENGTH (type
);
997 int aligned_regnum
= (regnum
+ 1) & ~1;
999 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1000 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1001 /* fits in a single register, do not align */
1003 val
= extract_unsigned_integer (contents
, len
);
1004 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1006 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1007 /* value fits in remaining registers, store keeping left
1011 regnum
= aligned_regnum
;
1012 for (b
= 0; b
< (len
& ~1); b
+= 2)
1014 val
= extract_unsigned_integer (&contents
[b
], 2);
1015 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1019 val
= extract_unsigned_integer (&contents
[b
], 1);
1020 regcache_cooked_write_unsigned (regcache
, regnum
++, (val
<< 8));
1025 /* arg will go onto stack */
1026 regnum
= ARGN_REGNUM
+ 1;
1027 si
= push_stack_item (si
, contents
, len
);
1033 sp
= (sp
- si
->len
) & ~1;
1034 write_memory (sp
, si
->data
, si
->len
);
1035 si
= pop_stack_item (si
);
1038 /* Finally, update the SP register. */
1039 regcache_cooked_write_unsigned (regcache
, D10V_SP_REGNUM
,
1040 d10v_convert_daddr_to_raw (sp
));
1046 /* Given a return value in `regbuf' with a type `valtype',
1047 extract and copy its value into `valbuf'. */
1050 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1054 if (TYPE_LENGTH (type
) == 1)
1057 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1058 store_unsigned_integer (valbuf
, 1, c
);
1062 /* For return values of odd size, the first byte is in the
1063 least significant part of the first register. The
1064 remaining bytes in remaining registers. Interestingly, when
1065 such values are passed in, the last byte is in the most
1066 significant byte of that same register - wierd. */
1067 int reg
= RET1_REGNUM
;
1069 if (TYPE_LENGTH (type
) & 1)
1071 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1072 (bfd_byte
*)valbuf
+ off
);
1076 /* Transfer the remaining registers. */
1077 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1079 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1080 (bfd_byte
*) valbuf
+ off
);
1085 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1086 understands. Returns number of bytes that can be transfered
1087 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1088 (segmentation fault). Since the simulator knows all about how the
1089 VM system works, we just call that to do the translation. */
1092 remote_d10v_translate_xfer_address (struct gdbarch
*gdbarch
,
1093 struct regcache
*regcache
,
1094 CORE_ADDR memaddr
, int nr_bytes
,
1095 CORE_ADDR
*targ_addr
, int *targ_len
)
1097 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1100 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
, &out_addr
, regcache
,
1101 tdep
->dmap_register
, tdep
->imap_register
);
1102 *targ_addr
= out_addr
;
1103 *targ_len
= out_len
;
1107 /* The following code implements access to, and display of, the D10V's
1108 instruction trace buffer. The buffer consists of 64K or more
1109 4-byte words of data, of which each words includes an 8-bit count,
1110 an 8-bit segment number, and a 16-bit instruction address.
1112 In theory, the trace buffer is continuously capturing instruction
1113 data that the CPU presents on its "debug bus", but in practice, the
1114 ROMified GDB stub only enables tracing when it continues or steps
1115 the program, and stops tracing when the program stops; so it
1116 actually works for GDB to read the buffer counter out of memory and
1117 then read each trace word. The counter records where the tracing
1118 stops, but there is no record of where it started, so we remember
1119 the PC when we resumed and then search backwards in the trace
1120 buffer for a word that includes that address. This is not perfect,
1121 because you will miss trace data if the resumption PC is the target
1122 of a branch. (The value of the buffer counter is semi-random, any
1123 trace data from a previous program stop is gone.) */
1125 /* The address of the last word recorded in the trace buffer. */
1127 #define DBBC_ADDR (0xd80000)
1129 /* The base of the trace buffer, at least for the "Board_0". */
1131 #define TRACE_BUFFER_BASE (0xf40000)
1133 static void trace_command (char *, int);
1135 static void untrace_command (char *, int);
1137 static void trace_info (char *, int);
1139 static void tdisassemble_command (char *, int);
1141 static void display_trace (int, int);
1143 /* True when instruction traces are being collected. */
1147 /* Remembered PC. */
1149 static CORE_ADDR last_pc
;
1151 /* True when trace output should be displayed whenever program stops. */
1153 static int trace_display
;
1155 /* True when trace listing should include source lines. */
1157 static int default_trace_show_source
= 1;
1168 trace_command (char *args
, int from_tty
)
1170 /* Clear the host-side trace buffer, allocating space if needed. */
1171 trace_data
.size
= 0;
1172 if (trace_data
.counts
== NULL
)
1173 trace_data
.counts
= XCALLOC (65536, short);
1174 if (trace_data
.addrs
== NULL
)
1175 trace_data
.addrs
= XCALLOC (65536, CORE_ADDR
);
1179 printf_filtered ("Tracing is now on.\n");
1183 untrace_command (char *args
, int from_tty
)
1187 printf_filtered ("Tracing is now off.\n");
1191 trace_info (char *args
, int from_tty
)
1195 if (trace_data
.size
)
1197 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1199 for (i
= 0; i
< trace_data
.size
; ++i
)
1201 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1203 trace_data
.counts
[i
],
1204 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1205 paddr_nz (trace_data
.addrs
[i
]));
1209 printf_filtered ("No entries in trace buffer.\n");
1211 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1215 d10v_eva_prepare_to_trace (void)
1220 last_pc
= read_register (D10V_PC_REGNUM
);
1223 /* Collect trace data from the target board and format it into a form
1224 more useful for display. */
1227 d10v_eva_get_trace_data (void)
1229 int count
, i
, j
, oldsize
;
1230 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1231 unsigned int last_trace
, trace_word
, next_word
;
1232 unsigned int *tmpspace
;
1237 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1239 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1241 /* Collect buffer contents from the target, stopping when we reach
1242 the word recorded when execution resumed. */
1245 while (last_trace
> 0)
1249 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1250 trace_addr
= trace_word
& 0xffff;
1252 /* Ignore an apparently nonsensical entry. */
1253 if (trace_addr
== 0xffd5)
1255 tmpspace
[count
++] = trace_word
;
1256 if (trace_addr
== last_pc
)
1262 /* Move the data to the host-side trace buffer, adjusting counts to
1263 include the last instruction executed and transforming the address
1264 into something that GDB likes. */
1266 for (i
= 0; i
< count
; ++i
)
1268 trace_word
= tmpspace
[i
];
1269 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1270 trace_addr
= trace_word
& 0xffff;
1271 next_cnt
= (next_word
>> 24) & 0xff;
1272 j
= trace_data
.size
+ count
- i
- 1;
1273 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1274 trace_data
.counts
[j
] = next_cnt
+ 1;
1277 oldsize
= trace_data
.size
;
1278 trace_data
.size
+= count
;
1283 display_trace (oldsize
, trace_data
.size
);
1287 tdisassemble_command (char *arg
, int from_tty
)
1290 CORE_ADDR low
, high
;
1295 high
= trace_data
.size
;
1299 char *space_index
= strchr (arg
, ' ');
1300 if (space_index
== NULL
)
1302 low
= parse_and_eval_address (arg
);
1307 /* Two arguments. */
1308 *space_index
= '\0';
1309 low
= parse_and_eval_address (arg
);
1310 high
= parse_and_eval_address (space_index
+ 1);
1316 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1318 display_trace (low
, high
);
1320 printf_filtered ("End of trace dump.\n");
1321 gdb_flush (gdb_stdout
);
1325 display_trace (int low
, int high
)
1327 int i
, count
, trace_show_source
, first
, suppress
;
1328 CORE_ADDR next_address
;
1330 trace_show_source
= default_trace_show_source
;
1331 if (!have_full_symbols () && !have_partial_symbols ())
1333 trace_show_source
= 0;
1334 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1335 printf_filtered ("Trace will not display any source.\n");
1340 for (i
= low
; i
< high
; ++i
)
1342 next_address
= trace_data
.addrs
[i
];
1343 count
= trace_data
.counts
[i
];
1347 if (trace_show_source
)
1349 struct symtab_and_line sal
, sal_prev
;
1351 sal_prev
= find_pc_line (next_address
- 4, 0);
1352 sal
= find_pc_line (next_address
, 0);
1356 if (first
|| sal
.line
!= sal_prev
.line
)
1357 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1363 /* FIXME-32x64--assumes sal.pc fits in long. */
1364 printf_filtered ("No source file for address %s.\n",
1365 local_hex_string ((unsigned long) sal
.pc
));
1370 print_address (next_address
, gdb_stdout
);
1371 printf_filtered (":");
1372 printf_filtered ("\t");
1374 next_address
+= gdb_print_insn (next_address
, gdb_stdout
);
1375 printf_filtered ("\n");
1376 gdb_flush (gdb_stdout
);
1382 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1385 frame_unwind_unsigned_register (next_frame
, D10V_PC_REGNUM
, &pc
);
1386 return d10v_make_iaddr (pc
);
1389 /* Given a GDB frame, determine the address of the calling function's
1390 frame. This will be used to create a new GDB frame struct. */
1393 d10v_frame_this_id (struct frame_info
*next_frame
,
1394 void **this_prologue_cache
,
1395 struct frame_id
*this_id
)
1397 struct d10v_unwind_cache
*info
1398 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1403 /* The FUNC is easy. */
1404 func
= frame_func_unwind (next_frame
);
1406 /* This is meant to halt the backtrace at "_start". Make sure we
1407 don't halt it at a generic dummy frame. */
1408 if (func
<= IMEM_START
|| inside_entry_file (func
))
1411 /* Hopefully the prologue analysis either correctly determined the
1412 frame's base (which is the SP from the previous frame), or set
1413 that base to "NULL". */
1414 base
= info
->prev_sp
;
1415 if (base
== STACK_START
|| base
== 0)
1418 id
= frame_id_build (base
, func
);
1420 /* Check that we're not going round in circles with the same frame
1421 ID (but avoid applying the test to sentinel frames which do go
1422 round in circles). Can't use frame_id_eq() as that doesn't yet
1423 compare the frame's PC value. */
1424 if (frame_relative_level (next_frame
) >= 0
1425 && get_frame_type (next_frame
) != DUMMY_FRAME
1426 && frame_id_eq (get_frame_id (next_frame
), id
))
1433 saved_regs_unwinder (struct frame_info
*next_frame
,
1434 CORE_ADDR
*this_saved_regs
,
1435 int regnum
, int *optimizedp
,
1436 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1437 int *realnump
, void *bufferp
)
1439 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1440 if (this_saved_regs
[regnum
] != 0)
1442 if (regnum
== D10V_SP_REGNUM
)
1444 /* SP register treated specially. */
1449 if (bufferp
!= NULL
)
1450 store_unsigned_integer (bufferp
,
1451 register_size (gdbarch
, regnum
),
1452 this_saved_regs
[regnum
]);
1456 /* Any other register is saved in memory, fetch it but cache
1457 a local copy of its value. */
1459 *lvalp
= lval_memory
;
1460 *addrp
= this_saved_regs
[regnum
];
1462 if (bufferp
!= NULL
)
1464 /* Read the value in from memory. */
1465 get_frame_memory (next_frame
, this_saved_regs
[regnum
], bufferp
,
1466 register_size (gdbarch
, regnum
));
1472 /* No luck, assume this and the next frame have the same register
1473 value. If a value is needed, pass the request on down the chain;
1474 otherwise just return an indication that the value is in the same
1475 register as the next frame. */
1476 frame_register_unwind (next_frame
, regnum
, optimizedp
, lvalp
, addrp
,
1482 d10v_frame_prev_register (struct frame_info
*next_frame
,
1483 void **this_prologue_cache
,
1484 int regnum
, int *optimizedp
,
1485 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1486 int *realnump
, void *bufferp
)
1488 struct d10v_unwind_cache
*info
1489 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1490 if (regnum
== D10V_PC_REGNUM
)
1492 /* The call instruction saves the caller's PC in LR. The
1493 function prologue of the callee may then save the LR on the
1494 stack. Find that possibly saved LR value and return it. */
1495 saved_regs_unwinder (next_frame
, info
->saved_regs
, LR_REGNUM
, optimizedp
,
1496 lvalp
, addrp
, realnump
, bufferp
);
1500 saved_regs_unwinder (next_frame
, info
->saved_regs
, regnum
, optimizedp
,
1501 lvalp
, addrp
, realnump
, bufferp
);
1505 static const struct frame_unwind d10v_frame_unwind
= {
1508 d10v_frame_prev_register
1511 const struct frame_unwind
*
1512 d10v_frame_p (CORE_ADDR pc
)
1514 return &d10v_frame_unwind
;
1518 d10v_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1520 struct d10v_unwind_cache
*info
1521 = d10v_frame_unwind_cache (next_frame
, this_cache
);
1525 static const struct frame_base d10v_frame_base
= {
1527 d10v_frame_base_address
,
1528 d10v_frame_base_address
,
1529 d10v_frame_base_address
1532 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1533 dummy frame. The frame ID's base needs to match the TOS value
1534 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1537 static struct frame_id
1538 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1541 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &base
);
1542 return frame_id_build (d10v_make_daddr (base
), frame_pc_unwind (next_frame
));
1545 static gdbarch_init_ftype d10v_gdbarch_init
;
1547 static struct gdbarch
*
1548 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1550 struct gdbarch
*gdbarch
;
1552 struct gdbarch_tdep
*tdep
;
1553 gdbarch_register_name_ftype
*d10v_register_name
;
1554 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1556 /* Find a candidate among the list of pre-declared architectures. */
1557 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1559 return arches
->gdbarch
;
1561 /* None found, create a new architecture from the information
1563 tdep
= XMALLOC (struct gdbarch_tdep
);
1564 gdbarch
= gdbarch_alloc (&info
, tdep
);
1566 switch (info
.bfd_arch_info
->mach
)
1568 case bfd_mach_d10v_ts2
:
1570 d10v_register_name
= d10v_ts2_register_name
;
1571 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1572 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1573 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1574 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1575 tdep
->imap_register
= d10v_ts2_imap_register
;
1578 case bfd_mach_d10v_ts3
:
1580 d10v_register_name
= d10v_ts3_register_name
;
1581 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1582 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1583 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1584 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1585 tdep
->imap_register
= d10v_ts3_imap_register
;
1589 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1590 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1591 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1593 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1594 set_gdbarch_sp_regnum (gdbarch
, D10V_SP_REGNUM
);
1595 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1596 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1598 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1599 set_gdbarch_addr_bit (gdbarch
, 32);
1600 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1601 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1602 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1603 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1604 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1605 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1606 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1607 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1608 double'' is 64 bits. */
1609 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1610 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1611 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1612 switch (info
.byte_order
)
1614 case BFD_ENDIAN_BIG
:
1615 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1616 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1617 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1619 case BFD_ENDIAN_LITTLE
:
1620 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1621 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1622 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1625 internal_error (__FILE__
, __LINE__
,
1626 "d10v_gdbarch_init: bad byte order for float format");
1629 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1630 set_gdbarch_push_dummy_code (gdbarch
, d10v_push_dummy_code
);
1631 set_gdbarch_push_dummy_call (gdbarch
, d10v_push_dummy_call
);
1632 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1633 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1634 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1636 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1637 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1638 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1639 set_gdbarch_function_start_offset (gdbarch
, 0);
1640 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1642 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1644 set_gdbarch_frame_args_skip (gdbarch
, 0);
1645 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1647 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1648 set_gdbarch_frame_align (gdbarch
, d10v_frame_align
);
1650 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1652 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1654 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1655 frame_base_set_default (gdbarch
, &d10v_frame_base
);
1657 /* Methods for saving / extracting a dummy frame's ID. */
1658 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1659 set_gdbarch_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
1661 /* Return the unwound PC value. */
1662 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1664 set_gdbarch_print_insn (gdbarch
, print_insn_d10v
);
1670 _initialize_d10v_tdep (void)
1672 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1674 target_resume_hook
= d10v_eva_prepare_to_trace
;
1675 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1677 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1680 add_com ("itrace", class_support
, trace_command
,
1681 "Enable tracing of instruction execution.");
1683 add_com ("iuntrace", class_support
, untrace_command
,
1684 "Disable tracing of instruction execution.");
1686 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1687 "Disassemble the trace buffer.\n\
1688 Two optional arguments specify a range of trace buffer entries\n\
1689 as reported by info trace (NOT addresses!).");
1691 add_info ("itrace", trace_info
,
1692 "Display info about the trace data buffer.");
1694 add_setshow_boolean_cmd ("itracedisplay", no_class
, &trace_display
,
1695 "Set automatic display of trace.\n",
1696 "Show automatic display of trace.\n",
1697 NULL
, NULL
, &setlist
, &showlist
);
1698 add_setshow_boolean_cmd ("itracesource", no_class
,
1699 &default_trace_show_source
,
1700 "Set display of source code with trace.\n",
1701 "Show display of source code with trace.\n",
1702 NULL
, NULL
, &setlist
, &showlist
);