1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
48 #include "gdb_assert.h"
54 unsigned long (*dmap_register
) (void *regcache
, int nr
);
55 unsigned long (*imap_register
) (void *regcache
, int nr
);
58 /* These are the addresses the D10V-EVA board maps data and
59 instruction memory to. */
62 DMEM_START
= 0x2000000,
63 IMEM_START
= 0x1000000,
64 STACK_START
= 0x200bffe
67 /* d10v register names. */
82 /* d10v calling convention. */
83 ARG1_REGNUM
= R0_REGNUM
,
84 ARGN_REGNUM
= R3_REGNUM
,
85 RET1_REGNUM
= R0_REGNUM
,
89 nr_dmap_regs (struct gdbarch
*gdbarch
)
91 return gdbarch_tdep (gdbarch
)->nr_dmap_regs
;
95 a0_regnum (struct gdbarch
*gdbarch
)
97 return gdbarch_tdep (gdbarch
)->a0_regnum
;
100 /* Local functions */
102 extern void _initialize_d10v_tdep (void);
104 static CORE_ADDR
d10v_read_sp (void);
106 static void d10v_eva_prepare_to_trace (void);
108 static void d10v_eva_get_trace_data (void);
111 d10v_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
113 /* Align to the size of an instruction (so that they can safely be
114 pushed onto the stack. */
118 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
119 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
120 and TYPE is the type (which is known to be struct, union or array).
122 The d10v returns anything less than 8 bytes in size in
126 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
130 /* The d10v only passes a struct in a register when that structure
131 has an alignment that matches the size of a register. */
132 /* If the structure doesn't fit in 4 registers, put it on the
134 if (TYPE_LENGTH (type
) > 8)
136 /* If the struct contains only one field, don't put it on the stack
137 - gcc can fit it in one or more registers. */
138 if (TYPE_NFIELDS (type
) == 1)
140 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
141 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
143 /* If the alignment changes, just assume it goes on the
145 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
148 /* If the alignment is suitable for the d10v's 16 bit registers,
149 don't put it on the stack. */
150 if (alignment
== 2 || alignment
== 4)
156 static const unsigned char *
157 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
159 static unsigned char breakpoint
[] =
160 {0x2f, 0x90, 0x5e, 0x00};
161 *lenptr
= sizeof (breakpoint
);
165 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
166 when the reg_nr isn't valid. */
170 TS2_IMAP0_REGNUM
= 32,
171 TS2_DMAP_REGNUM
= 34,
172 TS2_NR_DMAP_REGS
= 1,
177 d10v_ts2_register_name (int reg_nr
)
179 static char *register_names
[] =
181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
182 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
183 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
184 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
185 "imap0", "imap1", "dmap", "a0", "a1"
189 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
191 return register_names
[reg_nr
];
196 TS3_IMAP0_REGNUM
= 36,
197 TS3_DMAP0_REGNUM
= 38,
198 TS3_NR_DMAP_REGS
= 4,
203 d10v_ts3_register_name (int reg_nr
)
205 static char *register_names
[] =
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
210 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
214 "dmap0", "dmap1", "dmap2", "dmap3"
218 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
220 return register_names
[reg_nr
];
223 /* Access the DMAP/IMAP registers in a target independent way.
225 Divide the D10V's 64k data space into four 16k segments:
226 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
229 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
230 0x7fff) always map to the on-chip data RAM, and the fourth always
231 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
232 unified memory or instruction memory, under the control of the
233 single DMAP register.
235 On the TS3, there are four DMAP registers, each of which controls
236 one of the segments. */
239 d10v_ts2_dmap_register (void *regcache
, int reg_nr
)
249 regcache_cooked_read_unsigned (regcache
, TS2_DMAP_REGNUM
, ®
);
258 d10v_ts3_dmap_register (void *regcache
, int reg_nr
)
261 regcache_cooked_read_unsigned (regcache
, TS3_DMAP0_REGNUM
+ reg_nr
, ®
);
266 d10v_ts2_imap_register (void *regcache
, int reg_nr
)
269 regcache_cooked_read_unsigned (regcache
, TS2_IMAP0_REGNUM
+ reg_nr
, ®
);
274 d10v_ts3_imap_register (void *regcache
, int reg_nr
)
277 regcache_cooked_read_unsigned (regcache
, TS3_IMAP0_REGNUM
+ reg_nr
, ®
);
281 /* MAP GDB's internal register numbering (determined by the layout fo
282 the REGISTER_BYTE array) onto the simulator's register
286 d10v_ts2_register_sim_regno (int nr
)
288 /* Only makes sense to supply raw registers. */
289 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
290 if (nr
>= TS2_IMAP0_REGNUM
291 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
292 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
293 if (nr
== TS2_DMAP_REGNUM
)
294 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
295 if (nr
>= TS2_A0_REGNUM
296 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
297 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
302 d10v_ts3_register_sim_regno (int nr
)
304 /* Only makes sense to supply raw registers. */
305 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
306 if (nr
>= TS3_IMAP0_REGNUM
307 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
308 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
309 if (nr
>= TS3_DMAP0_REGNUM
310 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
311 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
312 if (nr
>= TS3_A0_REGNUM
313 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
314 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
318 /* Return the GDB type object for the "standard" data type
319 of data in register N. */
322 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
324 if (reg_nr
== D10V_PC_REGNUM
)
325 return builtin_type_void_func_ptr
;
326 if (reg_nr
== D10V_SP_REGNUM
|| reg_nr
== D10V_FP_REGNUM
)
327 return builtin_type_void_data_ptr
;
328 else if (reg_nr
>= a0_regnum (gdbarch
)
329 && reg_nr
< (a0_regnum (gdbarch
) + NR_A_REGS
))
330 return builtin_type_int64
;
332 return builtin_type_int16
;
336 d10v_daddr_p (CORE_ADDR x
)
338 return (((x
) & 0x3000000) == DMEM_START
);
342 d10v_iaddr_p (CORE_ADDR x
)
344 return (((x
) & 0x3000000) == IMEM_START
);
348 d10v_make_daddr (CORE_ADDR x
)
350 return ((x
) | DMEM_START
);
354 d10v_make_iaddr (CORE_ADDR x
)
356 if (d10v_iaddr_p (x
))
357 return x
; /* Idempotency -- x is already in the IMEM space. */
359 return (((x
) << 2) | IMEM_START
);
363 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
365 return (((x
) >> 2) & 0xffff);
369 d10v_convert_daddr_to_raw (CORE_ADDR x
)
371 return ((x
) & 0xffff);
375 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
377 /* Is it a code address? */
378 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
379 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
381 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
382 d10v_convert_iaddr_to_raw (addr
));
386 /* Strip off any upper segment bits. */
387 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
388 d10v_convert_daddr_to_raw (addr
));
393 d10v_pointer_to_address (struct type
*type
, const void *buf
)
395 CORE_ADDR addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
396 /* Is it a code address? */
397 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
398 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
399 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
400 return d10v_make_iaddr (addr
);
402 return d10v_make_daddr (addr
);
405 /* Don't do anything if we have an integer, this way users can type 'x
406 <addr>' w/o having gdb outsmart them. The internal gdb conversions
407 to the correct space are taken care of in the pointer_to_address
408 function. If we don't do this, 'x $fp' wouldn't work. */
410 d10v_integer_to_address (struct type
*type
, void *buf
)
413 val
= unpack_long (type
, buf
);
417 /* Write into appropriate registers a function return value
418 of type TYPE, given in virtual format.
420 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
423 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
426 /* Only char return values need to be shifted right within the first
428 if (TYPE_LENGTH (type
) == 1
429 && TYPE_CODE (type
) == TYPE_CODE_INT
)
432 tmp
[1] = *(bfd_byte
*)valbuf
;
433 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
438 /* A structure is never more than 8 bytes long. See
439 use_struct_convention(). */
440 gdb_assert (TYPE_LENGTH (type
) <= 8);
441 /* Write out most registers, stop loop before trying to write
442 out any dangling byte at the end of the buffer. */
443 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
445 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
446 (bfd_byte
*) valbuf
+ reg
* 2);
448 /* Write out any dangling byte at the end of the buffer. */
449 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
450 regcache_cooked_write_part (regcache
, reg
, 0, 1,
451 (bfd_byte
*) valbuf
+ reg
* 2);
455 /* Extract from an array REGBUF containing the (raw) register state
456 the address in which a function should return its structure value,
457 as a CORE_ADDR (or an expression that can be used as one). */
460 d10v_extract_struct_value_address (struct regcache
*regcache
)
463 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
464 return (addr
| DMEM_START
);
468 check_prologue (unsigned short op
)
471 if ((op
& 0x7E1F) == 0x6C1F)
475 if ((op
& 0x7E3F) == 0x6E1F)
479 if ((op
& 0x7FE1) == 0x01E1)
491 if ((op
& 0x7E1F) == 0x681E)
495 if ((op
& 0x7E3F) == 0x3A1E)
502 d10v_skip_prologue (CORE_ADDR pc
)
505 unsigned short op1
, op2
;
506 CORE_ADDR func_addr
, func_end
;
507 struct symtab_and_line sal
;
509 /* If we have line debugging information, then the end of the */
510 /* prologue should the first assembly instruction of the first source line */
511 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
513 sal
= find_pc_line (func_addr
, 0);
514 if (sal
.end
&& sal
.end
< func_end
)
518 if (target_read_memory (pc
, (char *) &op
, 4))
519 return pc
; /* Can't access it -- assume no prologue. */
523 op
= (unsigned long) read_memory_integer (pc
, 4);
524 if ((op
& 0xC0000000) == 0xC0000000)
526 /* long instruction */
527 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
528 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
529 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
534 /* short instructions */
535 if ((op
& 0xC0000000) == 0x80000000)
537 op2
= (op
& 0x3FFF8000) >> 15;
542 op1
= (op
& 0x3FFF8000) >> 15;
545 if (check_prologue (op1
))
547 if (!check_prologue (op2
))
549 /* if the previous opcode was really part of the prologue */
550 /* and not just a NOP, then we want to break after both instructions */
564 struct d10v_unwind_cache
567 /* The previous frame's inner most stack address. Used as this
568 frame ID's stack_addr. */
570 /* The frame's base, optionally used by the high-level debug info. */
573 CORE_ADDR
*saved_regs
;
574 /* How far the SP and r11 (FP) have been offset from the start of
575 the stack frame (as defined by the previous frame's stack
584 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
590 if ((op
& 0x7E1F) == 0x6C1F)
592 n
= (op
& 0x1E0) >> 5;
593 info
->sp_offset
-= 2;
594 info
->saved_regs
[n
] = info
->sp_offset
;
599 else if ((op
& 0x7E3F) == 0x6E1F)
601 n
= (op
& 0x1E0) >> 5;
602 info
->sp_offset
-= 4;
603 info
->saved_regs
[n
] = info
->sp_offset
;
604 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
609 if ((op
& 0x7FE1) == 0x01E1)
611 n
= (op
& 0x1E) >> 1;
614 info
->sp_offset
-= n
;
621 info
->uses_frame
= 1;
622 info
->r11_offset
= info
->sp_offset
;
627 if ((op
& 0x7E1F) == 0x6816)
629 n
= (op
& 0x1E0) >> 5;
630 info
->saved_regs
[n
] = info
->r11_offset
;
639 if ((op
& 0x7E1F) == 0x681E)
641 n
= (op
& 0x1E0) >> 5;
642 info
->saved_regs
[n
] = info
->sp_offset
;
647 if ((op
& 0x7E3F) == 0x3A1E)
649 n
= (op
& 0x1E0) >> 5;
650 info
->saved_regs
[n
] = info
->sp_offset
;
651 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
658 /* Put here the code to store, into fi->saved_regs, the addresses of
659 the saved registers of frame described by FRAME_INFO. This
660 includes special registers such as pc and fp saved in special ways
661 in the stack frame. sp is even more special: the address we return
662 for it IS the sp for the next frame. */
664 struct d10v_unwind_cache
*
665 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
666 void **this_prologue_cache
)
672 unsigned short op1
, op2
;
674 struct d10v_unwind_cache
*info
;
676 if ((*this_prologue_cache
))
677 return (*this_prologue_cache
);
679 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
680 (*this_prologue_cache
) = info
;
681 info
->saved_regs
= FRAME_OBSTACK_CALLOC (NUM_REGS
, CORE_ADDR
);
687 info
->uses_frame
= 0;
688 for (pc
= frame_func_unwind (next_frame
);
689 pc
> 0 && pc
< frame_pc_unwind (next_frame
);
692 op
= (unsigned long) read_memory_integer (pc
, 4);
693 if ((op
& 0xC0000000) == 0xC0000000)
695 /* long instruction */
696 if ((op
& 0x3FFF0000) == 0x01FF0000)
699 short n
= op
& 0xFFFF;
700 info
->sp_offset
+= n
;
702 else if ((op
& 0x3F0F0000) == 0x340F0000)
704 /* st rn, @(offset,sp) */
705 short offset
= op
& 0xFFFF;
706 short n
= (op
>> 20) & 0xF;
707 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
709 else if ((op
& 0x3F1F0000) == 0x350F0000)
711 /* st2w rn, @(offset,sp) */
712 short offset
= op
& 0xFFFF;
713 short n
= (op
>> 20) & 0xF;
714 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
715 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ offset
+ 2;
722 /* short instructions */
723 if ((op
& 0xC0000000) == 0x80000000)
725 op2
= (op
& 0x3FFF8000) >> 15;
730 op1
= (op
& 0x3FFF8000) >> 15;
733 if (!prologue_find_regs (info
, op1
, pc
)
734 || !prologue_find_regs (info
, op2
, pc
))
739 info
->size
= -info
->sp_offset
;
741 /* Compute the frame's base, and the previous frame's SP. */
742 if (info
->uses_frame
)
744 /* The SP was moved to the FP. This indicates that a new frame
745 was created. Get THIS frame's FP value by unwinding it from
747 frame_unwind_unsigned_register (next_frame
, D10V_FP_REGNUM
, &this_base
);
748 /* The FP points at the last saved register. Adjust the FP back
749 to before the first saved register giving the SP. */
750 prev_sp
= this_base
+ info
->size
;
752 else if (info
->saved_regs
[D10V_SP_REGNUM
])
754 /* The SP was saved (which is very unusual), the frame base is
755 just the PREV's frame's TOP-OF-STACK. */
756 this_base
= read_memory_unsigned_integer (info
->saved_regs
[D10V_SP_REGNUM
],
757 register_size (current_gdbarch
,
763 /* Assume that the FP is this frame's SP but with that pushed
764 stack space added back. */
765 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &this_base
);
766 prev_sp
= this_base
+ info
->size
;
769 info
->base
= d10v_make_daddr (this_base
);
770 info
->prev_sp
= d10v_make_daddr (prev_sp
);
772 /* Adjust all the saved registers so that they contain addresses and
774 for (i
= 0; i
< NUM_REGS
- 1; i
++)
775 if (info
->saved_regs
[i
])
777 info
->saved_regs
[i
] = (info
->prev_sp
+ info
->saved_regs
[i
]);
780 if (info
->saved_regs
[LR_REGNUM
])
783 = read_memory_unsigned_integer (info
->saved_regs
[LR_REGNUM
],
784 register_size (current_gdbarch
, LR_REGNUM
));
785 info
->return_pc
= d10v_make_iaddr (return_pc
);
790 frame_unwind_unsigned_register (next_frame
, LR_REGNUM
, &return_pc
);
791 info
->return_pc
= d10v_make_iaddr (return_pc
);
794 /* The D10V_SP_REGNUM is special. Instead of the address of the SP, the
795 previous frame's SP value is saved. */
796 info
->saved_regs
[D10V_SP_REGNUM
] = info
->prev_sp
;
802 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
803 struct frame_info
*frame
, int regnum
, int all
)
805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
808 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
813 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
814 frame_read_unsigned_register (frame
, D10V_PC_REGNUM
, &pc
);
815 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
816 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s
);
817 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e
);
818 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c
);
819 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
820 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
821 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
826 for (group
= 0; group
< 16; group
+= 8)
829 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
830 for (r
= group
; r
< group
+ 8; r
++)
833 frame_read_unsigned_register (frame
, r
, &tmp
);
834 fprintf_filtered (file
, " %04lx", (long) tmp
);
836 fprintf_filtered (file
, "\n");
840 /* Note: The IMAP/DMAP registers don't participate in function
841 calls. Don't bother trying to unwind them. */
845 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
848 fprintf_filtered (file
, " ");
849 fprintf_filtered (file
, "IMAP%d %04lx", a
,
850 tdep
->imap_register (current_regcache
, a
));
852 if (nr_dmap_regs (gdbarch
) == 1)
853 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
854 fprintf_filtered (file
, " DMAP %04lx\n",
855 tdep
->dmap_register (current_regcache
, 2));
858 for (a
= 0; a
< nr_dmap_regs (gdbarch
); a
++)
860 fprintf_filtered (file
, " DMAP%d %04lx", a
,
861 tdep
->dmap_register (current_regcache
, a
));
863 fprintf_filtered (file
, "\n");
868 char num
[MAX_REGISTER_SIZE
];
870 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
871 for (a
= a0_regnum (gdbarch
); a
< a0_regnum (gdbarch
) + NR_A_REGS
; a
++)
874 fprintf_filtered (file
, " ");
875 frame_read_register (frame
, a
, num
);
876 for (i
= 0; i
< register_size (current_gdbarch
, a
); i
++)
878 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
882 fprintf_filtered (file
, "\n");
886 show_regs (char *args
, int from_tty
)
888 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
889 get_current_frame (), -1, 1);
893 d10v_read_pc (ptid_t ptid
)
899 save_ptid
= inferior_ptid
;
900 inferior_ptid
= ptid
;
901 pc
= (int) read_register (D10V_PC_REGNUM
);
902 inferior_ptid
= save_ptid
;
903 retval
= d10v_make_iaddr (pc
);
908 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
912 save_ptid
= inferior_ptid
;
913 inferior_ptid
= ptid
;
914 write_register (D10V_PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
915 inferior_ptid
= save_ptid
;
921 return (d10v_make_daddr (read_register (D10V_SP_REGNUM
)));
924 /* When arguments must be pushed onto the stack, they go on in reverse
925 order. The below implements a FILO (stack) to do this. */
930 struct stack_item
*prev
;
934 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
935 void *contents
, int len
);
936 static struct stack_item
*
937 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
939 struct stack_item
*si
;
940 si
= xmalloc (sizeof (struct stack_item
));
941 si
->data
= xmalloc (len
);
944 memcpy (si
->data
, contents
, len
);
948 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
949 static struct stack_item
*
950 pop_stack_item (struct stack_item
*si
)
952 struct stack_item
*dead
= si
;
961 d10v_push_dummy_code (struct gdbarch
*gdbarch
,
962 CORE_ADDR sp
, CORE_ADDR funaddr
, int using_gcc
,
963 struct value
**args
, int nargs
,
964 struct type
*value_type
,
965 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
967 /* Allocate space sufficient for a breakpoint. */
969 /* Store the address of that breakpoint taking care to first convert
970 it into a code (IADDR) address from a stack (DADDR) address.
971 This of course assumes that the two virtual addresses map onto
972 the same real address. */
973 (*bp_addr
) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp
));
974 /* d10v always starts the call at the callee's entry point. */
975 (*real_pc
) = funaddr
;
980 d10v_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
981 struct regcache
*regcache
, CORE_ADDR bp_addr
,
982 int nargs
, struct value
**args
, CORE_ADDR sp
, int struct_return
,
983 CORE_ADDR struct_addr
)
986 int regnum
= ARG1_REGNUM
;
987 struct stack_item
*si
= NULL
;
990 /* Set the return address. For the d10v, the return breakpoint is
991 always at BP_ADDR. */
992 regcache_cooked_write_unsigned (regcache
, LR_REGNUM
,
993 d10v_convert_iaddr_to_raw (bp_addr
));
995 /* If STRUCT_RETURN is true, then the struct return address (in
996 STRUCT_ADDR) will consume the first argument-passing register.
997 Both adjust the register count and store that value. */
1000 regcache_cooked_write_unsigned (regcache
, regnum
, struct_addr
);
1004 /* Fill in registers and arg lists */
1005 for (i
= 0; i
< nargs
; i
++)
1007 struct value
*arg
= args
[i
];
1008 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1009 char *contents
= VALUE_CONTENTS (arg
);
1010 int len
= TYPE_LENGTH (type
);
1011 int aligned_regnum
= (regnum
+ 1) & ~1;
1013 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1014 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1015 /* fits in a single register, do not align */
1017 val
= extract_unsigned_integer (contents
, len
);
1018 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1020 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1021 /* value fits in remaining registers, store keeping left
1025 regnum
= aligned_regnum
;
1026 for (b
= 0; b
< (len
& ~1); b
+= 2)
1028 val
= extract_unsigned_integer (&contents
[b
], 2);
1029 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1033 val
= extract_unsigned_integer (&contents
[b
], 1);
1034 regcache_cooked_write_unsigned (regcache
, regnum
++, (val
<< 8));
1039 /* arg will go onto stack */
1040 regnum
= ARGN_REGNUM
+ 1;
1041 si
= push_stack_item (si
, contents
, len
);
1047 sp
= (sp
- si
->len
) & ~1;
1048 write_memory (sp
, si
->data
, si
->len
);
1049 si
= pop_stack_item (si
);
1052 /* Finally, update the SP register. */
1053 regcache_cooked_write_unsigned (regcache
, D10V_SP_REGNUM
,
1054 d10v_convert_daddr_to_raw (sp
));
1060 /* Given a return value in `regbuf' with a type `valtype',
1061 extract and copy its value into `valbuf'. */
1064 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1068 if (TYPE_LENGTH (type
) == 1)
1071 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1072 store_unsigned_integer (valbuf
, 1, c
);
1076 /* For return values of odd size, the first byte is in the
1077 least significant part of the first register. The
1078 remaining bytes in remaining registers. Interestingly, when
1079 such values are passed in, the last byte is in the most
1080 significant byte of that same register - wierd. */
1081 int reg
= RET1_REGNUM
;
1083 if (TYPE_LENGTH (type
) & 1)
1085 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1086 (bfd_byte
*)valbuf
+ off
);
1090 /* Transfer the remaining registers. */
1091 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1093 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1094 (bfd_byte
*) valbuf
+ off
);
1099 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1100 understands. Returns number of bytes that can be transfered
1101 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1102 (segmentation fault). Since the simulator knows all about how the
1103 VM system works, we just call that to do the translation. */
1106 remote_d10v_translate_xfer_address (struct gdbarch
*gdbarch
,
1107 struct regcache
*regcache
,
1108 CORE_ADDR memaddr
, int nr_bytes
,
1109 CORE_ADDR
*targ_addr
, int *targ_len
)
1111 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1114 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
, &out_addr
, regcache
,
1115 tdep
->dmap_register
, tdep
->imap_register
);
1116 *targ_addr
= out_addr
;
1117 *targ_len
= out_len
;
1121 /* The following code implements access to, and display of, the D10V's
1122 instruction trace buffer. The buffer consists of 64K or more
1123 4-byte words of data, of which each words includes an 8-bit count,
1124 an 8-bit segment number, and a 16-bit instruction address.
1126 In theory, the trace buffer is continuously capturing instruction
1127 data that the CPU presents on its "debug bus", but in practice, the
1128 ROMified GDB stub only enables tracing when it continues or steps
1129 the program, and stops tracing when the program stops; so it
1130 actually works for GDB to read the buffer counter out of memory and
1131 then read each trace word. The counter records where the tracing
1132 stops, but there is no record of where it started, so we remember
1133 the PC when we resumed and then search backwards in the trace
1134 buffer for a word that includes that address. This is not perfect,
1135 because you will miss trace data if the resumption PC is the target
1136 of a branch. (The value of the buffer counter is semi-random, any
1137 trace data from a previous program stop is gone.) */
1139 /* The address of the last word recorded in the trace buffer. */
1141 #define DBBC_ADDR (0xd80000)
1143 /* The base of the trace buffer, at least for the "Board_0". */
1145 #define TRACE_BUFFER_BASE (0xf40000)
1147 static void trace_command (char *, int);
1149 static void untrace_command (char *, int);
1151 static void trace_info (char *, int);
1153 static void tdisassemble_command (char *, int);
1155 static void display_trace (int, int);
1157 /* True when instruction traces are being collected. */
1161 /* Remembered PC. */
1163 static CORE_ADDR last_pc
;
1165 /* True when trace output should be displayed whenever program stops. */
1167 static int trace_display
;
1169 /* True when trace listing should include source lines. */
1171 static int default_trace_show_source
= 1;
1182 trace_command (char *args
, int from_tty
)
1184 /* Clear the host-side trace buffer, allocating space if needed. */
1185 trace_data
.size
= 0;
1186 if (trace_data
.counts
== NULL
)
1187 trace_data
.counts
= XCALLOC (65536, short);
1188 if (trace_data
.addrs
== NULL
)
1189 trace_data
.addrs
= XCALLOC (65536, CORE_ADDR
);
1193 printf_filtered ("Tracing is now on.\n");
1197 untrace_command (char *args
, int from_tty
)
1201 printf_filtered ("Tracing is now off.\n");
1205 trace_info (char *args
, int from_tty
)
1209 if (trace_data
.size
)
1211 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1213 for (i
= 0; i
< trace_data
.size
; ++i
)
1215 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1217 trace_data
.counts
[i
],
1218 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1219 paddr_nz (trace_data
.addrs
[i
]));
1223 printf_filtered ("No entries in trace buffer.\n");
1225 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1229 d10v_eva_prepare_to_trace (void)
1234 last_pc
= read_register (D10V_PC_REGNUM
);
1237 /* Collect trace data from the target board and format it into a form
1238 more useful for display. */
1241 d10v_eva_get_trace_data (void)
1243 int count
, i
, j
, oldsize
;
1244 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1245 unsigned int last_trace
, trace_word
, next_word
;
1246 unsigned int *tmpspace
;
1251 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1253 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1255 /* Collect buffer contents from the target, stopping when we reach
1256 the word recorded when execution resumed. */
1259 while (last_trace
> 0)
1263 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1264 trace_addr
= trace_word
& 0xffff;
1266 /* Ignore an apparently nonsensical entry. */
1267 if (trace_addr
== 0xffd5)
1269 tmpspace
[count
++] = trace_word
;
1270 if (trace_addr
== last_pc
)
1276 /* Move the data to the host-side trace buffer, adjusting counts to
1277 include the last instruction executed and transforming the address
1278 into something that GDB likes. */
1280 for (i
= 0; i
< count
; ++i
)
1282 trace_word
= tmpspace
[i
];
1283 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1284 trace_addr
= trace_word
& 0xffff;
1285 next_cnt
= (next_word
>> 24) & 0xff;
1286 j
= trace_data
.size
+ count
- i
- 1;
1287 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1288 trace_data
.counts
[j
] = next_cnt
+ 1;
1291 oldsize
= trace_data
.size
;
1292 trace_data
.size
+= count
;
1297 display_trace (oldsize
, trace_data
.size
);
1301 tdisassemble_command (char *arg
, int from_tty
)
1304 CORE_ADDR low
, high
;
1309 high
= trace_data
.size
;
1313 char *space_index
= strchr (arg
, ' ');
1314 if (space_index
== NULL
)
1316 low
= parse_and_eval_address (arg
);
1321 /* Two arguments. */
1322 *space_index
= '\0';
1323 low
= parse_and_eval_address (arg
);
1324 high
= parse_and_eval_address (space_index
+ 1);
1330 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1332 display_trace (low
, high
);
1334 printf_filtered ("End of trace dump.\n");
1335 gdb_flush (gdb_stdout
);
1339 display_trace (int low
, int high
)
1341 int i
, count
, trace_show_source
, first
, suppress
;
1342 CORE_ADDR next_address
;
1344 trace_show_source
= default_trace_show_source
;
1345 if (!have_full_symbols () && !have_partial_symbols ())
1347 trace_show_source
= 0;
1348 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1349 printf_filtered ("Trace will not display any source.\n");
1354 for (i
= low
; i
< high
; ++i
)
1356 next_address
= trace_data
.addrs
[i
];
1357 count
= trace_data
.counts
[i
];
1361 if (trace_show_source
)
1363 struct symtab_and_line sal
, sal_prev
;
1365 sal_prev
= find_pc_line (next_address
- 4, 0);
1366 sal
= find_pc_line (next_address
, 0);
1370 if (first
|| sal
.line
!= sal_prev
.line
)
1371 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1377 /* FIXME-32x64--assumes sal.pc fits in long. */
1378 printf_filtered ("No source file for address %s.\n",
1379 local_hex_string ((unsigned long) sal
.pc
));
1384 print_address (next_address
, gdb_stdout
);
1385 printf_filtered (":");
1386 printf_filtered ("\t");
1388 next_address
+= gdb_print_insn (next_address
, gdb_stdout
);
1389 printf_filtered ("\n");
1390 gdb_flush (gdb_stdout
);
1396 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1399 frame_unwind_unsigned_register (next_frame
, D10V_PC_REGNUM
, &pc
);
1400 return d10v_make_iaddr (pc
);
1403 /* Given a GDB frame, determine the address of the calling function's
1404 frame. This will be used to create a new GDB frame struct. */
1407 d10v_frame_this_id (struct frame_info
*next_frame
,
1408 void **this_prologue_cache
,
1409 struct frame_id
*this_id
)
1411 struct d10v_unwind_cache
*info
1412 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1417 /* The FUNC is easy. */
1418 func
= frame_func_unwind (next_frame
);
1420 /* This is meant to halt the backtrace at "_start". Make sure we
1421 don't halt it at a generic dummy frame. */
1422 if (func
<= IMEM_START
|| inside_entry_file (func
))
1425 /* Hopefully the prologue analysis either correctly determined the
1426 frame's base (which is the SP from the previous frame), or set
1427 that base to "NULL". */
1428 base
= info
->prev_sp
;
1429 if (base
== STACK_START
|| base
== 0)
1432 id
= frame_id_build (base
, func
);
1434 /* Check that we're not going round in circles with the same frame
1435 ID (but avoid applying the test to sentinel frames which do go
1436 round in circles). Can't use frame_id_eq() as that doesn't yet
1437 compare the frame's PC value. */
1438 if (frame_relative_level (next_frame
) >= 0
1439 && get_frame_type (next_frame
) != DUMMY_FRAME
1440 && frame_id_eq (get_frame_id (next_frame
), id
))
1447 saved_regs_unwinder (struct frame_info
*next_frame
,
1448 CORE_ADDR
*this_saved_regs
,
1449 int regnum
, int *optimizedp
,
1450 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1451 int *realnump
, void *bufferp
)
1453 if (this_saved_regs
[regnum
] != 0)
1455 if (regnum
== D10V_SP_REGNUM
)
1457 /* SP register treated specially. */
1462 if (bufferp
!= NULL
)
1463 store_unsigned_integer (bufferp
,
1464 register_size (current_gdbarch
, regnum
),
1465 this_saved_regs
[regnum
]);
1469 /* Any other register is saved in memory, fetch it but cache
1470 a local copy of its value. */
1472 *lvalp
= lval_memory
;
1473 *addrp
= this_saved_regs
[regnum
];
1475 if (bufferp
!= NULL
)
1477 /* Read the value in from memory. */
1478 read_memory (this_saved_regs
[regnum
], bufferp
,
1479 register_size (current_gdbarch
, regnum
));
1485 /* No luck, assume this and the next frame have the same register
1486 value. If a value is needed, pass the request on down the chain;
1487 otherwise just return an indication that the value is in the same
1488 register as the next frame. */
1489 frame_register_unwind (next_frame
, regnum
, optimizedp
, lvalp
, addrp
,
1495 d10v_frame_prev_register (struct frame_info
*next_frame
,
1496 void **this_prologue_cache
,
1497 int regnum
, int *optimizedp
,
1498 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1499 int *realnump
, void *bufferp
)
1501 struct d10v_unwind_cache
*info
1502 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1503 if (regnum
== D10V_PC_REGNUM
)
1505 /* The call instruction saves the caller's PC in LR. The
1506 function prologue of the callee may then save the LR on the
1507 stack. Find that possibly saved LR value and return it. */
1508 saved_regs_unwinder (next_frame
, info
->saved_regs
, LR_REGNUM
, optimizedp
,
1509 lvalp
, addrp
, realnump
, bufferp
);
1513 saved_regs_unwinder (next_frame
, info
->saved_regs
, regnum
, optimizedp
,
1514 lvalp
, addrp
, realnump
, bufferp
);
1518 static const struct frame_unwind d10v_frame_unwind
= {
1521 d10v_frame_prev_register
1524 const struct frame_unwind
*
1525 d10v_frame_p (CORE_ADDR pc
)
1527 return &d10v_frame_unwind
;
1531 d10v_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1533 struct d10v_unwind_cache
*info
1534 = d10v_frame_unwind_cache (next_frame
, this_cache
);
1538 static const struct frame_base d10v_frame_base
= {
1540 d10v_frame_base_address
,
1541 d10v_frame_base_address
,
1542 d10v_frame_base_address
1545 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1546 dummy frame. The frame ID's base needs to match the TOS value
1547 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1550 static struct frame_id
1551 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1554 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &base
);
1555 return frame_id_build (d10v_make_daddr (base
), frame_pc_unwind (next_frame
));
1558 static gdbarch_init_ftype d10v_gdbarch_init
;
1560 static struct gdbarch
*
1561 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1563 struct gdbarch
*gdbarch
;
1565 struct gdbarch_tdep
*tdep
;
1566 gdbarch_register_name_ftype
*d10v_register_name
;
1567 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1569 /* Find a candidate among the list of pre-declared architectures. */
1570 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1572 return arches
->gdbarch
;
1574 /* None found, create a new architecture from the information
1576 tdep
= XMALLOC (struct gdbarch_tdep
);
1577 gdbarch
= gdbarch_alloc (&info
, tdep
);
1579 switch (info
.bfd_arch_info
->mach
)
1581 case bfd_mach_d10v_ts2
:
1583 d10v_register_name
= d10v_ts2_register_name
;
1584 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1585 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1586 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1587 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1588 tdep
->imap_register
= d10v_ts2_imap_register
;
1591 case bfd_mach_d10v_ts3
:
1593 d10v_register_name
= d10v_ts3_register_name
;
1594 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1595 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1596 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1597 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1598 tdep
->imap_register
= d10v_ts3_imap_register
;
1602 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1603 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1604 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1606 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1607 set_gdbarch_sp_regnum (gdbarch
, D10V_SP_REGNUM
);
1608 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1609 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1611 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1612 set_gdbarch_addr_bit (gdbarch
, 32);
1613 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1614 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1615 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1616 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1617 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1618 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1619 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1620 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1621 double'' is 64 bits. */
1622 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1623 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1624 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1625 switch (info
.byte_order
)
1627 case BFD_ENDIAN_BIG
:
1628 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1629 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1630 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1632 case BFD_ENDIAN_LITTLE
:
1633 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1634 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1635 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1638 internal_error (__FILE__
, __LINE__
,
1639 "d10v_gdbarch_init: bad byte order for float format");
1642 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1643 set_gdbarch_push_dummy_code (gdbarch
, d10v_push_dummy_code
);
1644 set_gdbarch_push_dummy_call (gdbarch
, d10v_push_dummy_call
);
1645 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1646 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1647 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1649 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1650 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1651 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1652 set_gdbarch_function_start_offset (gdbarch
, 0);
1653 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1655 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1657 set_gdbarch_frame_args_skip (gdbarch
, 0);
1658 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1660 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1661 set_gdbarch_frame_align (gdbarch
, d10v_frame_align
);
1663 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1665 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1667 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1668 frame_base_set_default (gdbarch
, &d10v_frame_base
);
1670 /* Methods for saving / extracting a dummy frame's ID. */
1671 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1672 set_gdbarch_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
1674 /* Return the unwound PC value. */
1675 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1677 set_gdbarch_print_insn (gdbarch
, print_insn_d10v
);
1683 _initialize_d10v_tdep (void)
1685 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1687 target_resume_hook
= d10v_eva_prepare_to_trace
;
1688 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1690 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1693 add_com ("itrace", class_support
, trace_command
,
1694 "Enable tracing of instruction execution.");
1696 add_com ("iuntrace", class_support
, untrace_command
,
1697 "Disable tracing of instruction execution.");
1699 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1700 "Disassemble the trace buffer.\n\
1701 Two optional arguments specify a range of trace buffer entries\n\
1702 as reported by info trace (NOT addresses!).");
1704 add_info ("itrace", trace_info
,
1705 "Display info about the trace data buffer.");
1707 add_setshow_boolean_cmd ("itracedisplay", no_class
, &trace_display
,
1708 "Set automatic display of trace.\n",
1709 "Show automatic display of trace.\n",
1710 NULL
, NULL
, &setlist
, &showlist
);
1711 add_setshow_boolean_cmd ("itracesource", no_class
,
1712 &default_trace_show_source
,
1713 "Set display of source code with trace.\n",
1714 "Show display of source code with trace.\n",
1715 NULL
, NULL
, &setlist
, &showlist
);