1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
32 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "floatformat.h"
43 #include "gdb/sim-d10v.h"
44 #include "sim-regno.h"
46 struct frame_extra_info
57 unsigned long (*dmap_register
) (int nr
);
58 unsigned long (*imap_register
) (int nr
);
61 /* These are the addresses the D10V-EVA board maps data and
62 instruction memory to. */
65 DMEM_START
= 0x2000000,
66 IMEM_START
= 0x1000000,
67 STACK_START
= 0x200bffe
70 /* d10v register names. */
85 /* d10v calling convention. */
86 ARG1_REGNUM
= R0_REGNUM
,
87 ARGN_REGNUM
= R3_REGNUM
,
88 RET1_REGNUM
= R0_REGNUM
,
91 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
92 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
96 extern void _initialize_d10v_tdep (void);
98 static CORE_ADDR
d10v_read_sp (void);
100 static CORE_ADDR
d10v_read_fp (void);
102 static void d10v_eva_prepare_to_trace (void);
104 static void d10v_eva_get_trace_data (void);
106 static int prologue_find_regs (unsigned short op
, struct frame_info
*fi
,
109 static void d10v_frame_init_saved_regs (struct frame_info
*);
111 static void do_d10v_pop_frame (struct frame_info
*fi
);
114 d10v_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*frame
)
116 if (chain
!= 0 && frame
!= NULL
)
118 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
119 return 1; /* Path back from a call dummy must be valid. */
120 return ((frame
)->pc
> IMEM_START
121 && !inside_main_func (frame
->pc
));
127 d10v_stack_align (CORE_ADDR len
)
129 return (len
+ 1) & ~1;
132 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
133 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
134 and TYPE is the type (which is known to be struct, union or array).
136 The d10v returns anything less than 8 bytes in size in
140 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
144 /* The d10v only passes a struct in a register when that structure
145 has an alignment that matches the size of a register. */
146 /* If the structure doesn't fit in 4 registers, put it on the
148 if (TYPE_LENGTH (type
) > 8)
150 /* If the struct contains only one field, don't put it on the stack
151 - gcc can fit it in one or more registers. */
152 if (TYPE_NFIELDS (type
) == 1)
154 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
155 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
157 /* If the alignment changes, just assume it goes on the
159 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
162 /* If the alignment is suitable for the d10v's 16 bit registers,
163 don't put it on the stack. */
164 if (alignment
== 2 || alignment
== 4)
170 static const unsigned char *
171 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
173 static unsigned char breakpoint
[] =
174 {0x2f, 0x90, 0x5e, 0x00};
175 *lenptr
= sizeof (breakpoint
);
179 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
180 when the reg_nr isn't valid. */
184 TS2_IMAP0_REGNUM
= 32,
185 TS2_DMAP_REGNUM
= 34,
186 TS2_NR_DMAP_REGS
= 1,
191 d10v_ts2_register_name (int reg_nr
)
193 static char *register_names
[] =
195 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
196 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
197 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
198 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
199 "imap0", "imap1", "dmap", "a0", "a1"
203 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
205 return register_names
[reg_nr
];
210 TS3_IMAP0_REGNUM
= 36,
211 TS3_DMAP0_REGNUM
= 38,
212 TS3_NR_DMAP_REGS
= 4,
217 d10v_ts3_register_name (int reg_nr
)
219 static char *register_names
[] =
221 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
222 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
223 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
224 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
228 "dmap0", "dmap1", "dmap2", "dmap3"
232 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
234 return register_names
[reg_nr
];
237 /* Access the DMAP/IMAP registers in a target independent way.
239 Divide the D10V's 64k data space into four 16k segments:
240 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
243 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
244 0x7fff) always map to the on-chip data RAM, and the fourth always
245 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
246 unified memory or instruction memory, under the control of the
247 single DMAP register.
249 On the TS3, there are four DMAP registers, each of which controls
250 one of the segments. */
253 d10v_ts2_dmap_register (int reg_nr
)
261 return read_register (TS2_DMAP_REGNUM
);
268 d10v_ts3_dmap_register (int reg_nr
)
270 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
274 d10v_dmap_register (int reg_nr
)
276 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
280 d10v_ts2_imap_register (int reg_nr
)
282 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
286 d10v_ts3_imap_register (int reg_nr
)
288 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
292 d10v_imap_register (int reg_nr
)
294 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
297 /* MAP GDB's internal register numbering (determined by the layout fo
298 the REGISTER_BYTE array) onto the simulator's register
302 d10v_ts2_register_sim_regno (int nr
)
304 if (legacy_register_sim_regno (nr
) < 0)
305 return legacy_register_sim_regno (nr
);
306 if (nr
>= TS2_IMAP0_REGNUM
307 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
308 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
309 if (nr
== TS2_DMAP_REGNUM
)
310 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
311 if (nr
>= TS2_A0_REGNUM
312 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
313 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
318 d10v_ts3_register_sim_regno (int nr
)
320 if (legacy_register_sim_regno (nr
) < 0)
321 return legacy_register_sim_regno (nr
);
322 if (nr
>= TS3_IMAP0_REGNUM
323 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
324 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
325 if (nr
>= TS3_DMAP0_REGNUM
326 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
327 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
328 if (nr
>= TS3_A0_REGNUM
329 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
330 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
334 /* Index within `registers' of the first byte of the space for
338 d10v_register_byte (int reg_nr
)
340 if (reg_nr
< A0_REGNUM
)
342 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
343 return (A0_REGNUM
* 2
344 + (reg_nr
- A0_REGNUM
) * 8);
346 return (A0_REGNUM
* 2
348 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
351 /* Number of bytes of storage in the actual machine representation for
355 d10v_register_raw_size (int reg_nr
)
357 if (reg_nr
< A0_REGNUM
)
359 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
365 /* Return the GDB type object for the "standard" data type
366 of data in register N. */
369 d10v_register_virtual_type (int reg_nr
)
371 if (reg_nr
== PC_REGNUM
)
372 return builtin_type_void_func_ptr
;
373 if (reg_nr
== _SP_REGNUM
|| reg_nr
== _FP_REGNUM
)
374 return builtin_type_void_data_ptr
;
375 else if (reg_nr
>= A0_REGNUM
376 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
377 return builtin_type_int64
;
379 return builtin_type_int16
;
383 d10v_daddr_p (CORE_ADDR x
)
385 return (((x
) & 0x3000000) == DMEM_START
);
389 d10v_iaddr_p (CORE_ADDR x
)
391 return (((x
) & 0x3000000) == IMEM_START
);
395 d10v_make_daddr (CORE_ADDR x
)
397 return ((x
) | DMEM_START
);
401 d10v_make_iaddr (CORE_ADDR x
)
403 if (d10v_iaddr_p (x
))
404 return x
; /* Idempotency -- x is already in the IMEM space. */
406 return (((x
) << 2) | IMEM_START
);
410 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
412 return (((x
) >> 2) & 0xffff);
416 d10v_convert_daddr_to_raw (CORE_ADDR x
)
418 return ((x
) & 0xffff);
422 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
424 /* Is it a code address? */
425 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
426 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
428 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
429 d10v_convert_iaddr_to_raw (addr
));
433 /* Strip off any upper segment bits. */
434 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
435 d10v_convert_daddr_to_raw (addr
));
440 d10v_pointer_to_address (struct type
*type
, void *buf
)
442 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
444 /* Is it a code address? */
445 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
446 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
447 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
448 return d10v_make_iaddr (addr
);
450 return d10v_make_daddr (addr
);
453 /* Don't do anything if we have an integer, this way users can type 'x
454 <addr>' w/o having gdb outsmart them. The internal gdb conversions
455 to the correct space are taken care of in the pointer_to_address
456 function. If we don't do this, 'x $fp' wouldn't work. */
458 d10v_integer_to_address (struct type
*type
, void *buf
)
461 val
= unpack_long (type
, buf
);
465 /* Store the address of the place in which to copy the structure the
466 subroutine will return. This is called from call_function.
468 We store structs through a pointer passed in the first Argument
472 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
474 write_register (ARG1_REGNUM
, (addr
));
477 /* Write into appropriate registers a function return value
478 of type TYPE, given in virtual format.
480 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
483 d10v_store_return_value (struct type
*type
, char *valbuf
)
485 write_register_bytes (REGISTER_BYTE (RET1_REGNUM
),
490 /* Extract from an array REGBUF containing the (raw) register state
491 the address in which a function should return its structure value,
492 as a CORE_ADDR (or an expression that can be used as one). */
495 d10v_extract_struct_value_address (char *regbuf
)
497 return (extract_address ((regbuf
) + REGISTER_BYTE (ARG1_REGNUM
),
498 REGISTER_RAW_SIZE (ARG1_REGNUM
))
503 d10v_frame_saved_pc (struct frame_info
*frame
)
505 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
506 return d10v_make_iaddr (generic_read_register_dummy (frame
->pc
,
510 return ((frame
)->extra_info
->return_pc
);
513 /* Immediately after a function call, return the saved pc. We can't
514 use frame->return_pc beause that is determined by reading R13 off
515 the stack and that may not be written yet. */
518 d10v_saved_pc_after_call (struct frame_info
*frame
)
520 return ((read_register (LR_REGNUM
) << 2)
524 /* Discard from the stack the innermost frame, restoring all saved
528 d10v_pop_frame (void)
530 generic_pop_current_frame (do_d10v_pop_frame
);
534 do_d10v_pop_frame (struct frame_info
*fi
)
541 /* fill out fsr with the address of where each */
542 /* register was stored in the frame */
543 d10v_frame_init_saved_regs (fi
);
545 /* now update the current registers with the old values */
546 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
548 if (fi
->saved_regs
[regnum
])
550 read_memory (fi
->saved_regs
[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
551 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
, REGISTER_RAW_SIZE (regnum
));
554 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
556 if (fi
->saved_regs
[regnum
])
558 write_register (regnum
, read_memory_unsigned_integer (fi
->saved_regs
[regnum
], REGISTER_RAW_SIZE (regnum
)));
561 if (fi
->saved_regs
[PSW_REGNUM
])
563 write_register (PSW_REGNUM
, read_memory_unsigned_integer (fi
->saved_regs
[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
566 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
567 write_register (SP_REGNUM
, fp
+ fi
->extra_info
->size
);
568 target_store_registers (-1);
569 flush_cached_frames ();
573 check_prologue (unsigned short op
)
576 if ((op
& 0x7E1F) == 0x6C1F)
580 if ((op
& 0x7E3F) == 0x6E1F)
584 if ((op
& 0x7FE1) == 0x01E1)
596 if ((op
& 0x7E1F) == 0x681E)
600 if ((op
& 0x7E3F) == 0x3A1E)
607 d10v_skip_prologue (CORE_ADDR pc
)
610 unsigned short op1
, op2
;
611 CORE_ADDR func_addr
, func_end
;
612 struct symtab_and_line sal
;
614 /* If we have line debugging information, then the end of the */
615 /* prologue should the first assembly instruction of the first source line */
616 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
618 sal
= find_pc_line (func_addr
, 0);
619 if (sal
.end
&& sal
.end
< func_end
)
623 if (target_read_memory (pc
, (char *) &op
, 4))
624 return pc
; /* Can't access it -- assume no prologue. */
628 op
= (unsigned long) read_memory_integer (pc
, 4);
629 if ((op
& 0xC0000000) == 0xC0000000)
631 /* long instruction */
632 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
633 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
634 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
639 /* short instructions */
640 if ((op
& 0xC0000000) == 0x80000000)
642 op2
= (op
& 0x3FFF8000) >> 15;
647 op1
= (op
& 0x3FFF8000) >> 15;
650 if (check_prologue (op1
))
652 if (!check_prologue (op2
))
654 /* if the previous opcode was really part of the prologue */
655 /* and not just a NOP, then we want to break after both instructions */
669 /* Given a GDB frame, determine the address of the calling function's frame.
670 This will be used to create a new GDB frame struct, and then
671 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
675 d10v_frame_chain (struct frame_info
*fi
)
679 /* A generic call dummy's frame is the same as caller's. */
680 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
683 d10v_frame_init_saved_regs (fi
);
686 if (fi
->extra_info
->return_pc
== IMEM_START
687 || inside_entry_file (fi
->extra_info
->return_pc
))
689 /* This is meant to halt the backtrace at "_start".
690 Make sure we don't halt it at a generic dummy frame. */
691 if (!PC_IN_CALL_DUMMY (fi
->extra_info
->return_pc
, 0, 0))
692 return (CORE_ADDR
) 0;
695 if (!fi
->saved_regs
[FP_REGNUM
])
697 if (!fi
->saved_regs
[SP_REGNUM
]
698 || fi
->saved_regs
[SP_REGNUM
] == STACK_START
)
699 return (CORE_ADDR
) 0;
701 return fi
->saved_regs
[SP_REGNUM
];
704 addr
= read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
705 REGISTER_RAW_SIZE (FP_REGNUM
));
707 return (CORE_ADDR
) 0;
709 return d10v_make_daddr (addr
);
712 static int next_addr
, uses_frame
;
715 prologue_find_regs (unsigned short op
, struct frame_info
*fi
, CORE_ADDR addr
)
720 if ((op
& 0x7E1F) == 0x6C1F)
722 n
= (op
& 0x1E0) >> 5;
724 fi
->saved_regs
[n
] = next_addr
;
729 else if ((op
& 0x7E3F) == 0x6E1F)
731 n
= (op
& 0x1E0) >> 5;
733 fi
->saved_regs
[n
] = next_addr
;
734 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
739 if ((op
& 0x7FE1) == 0x01E1)
741 n
= (op
& 0x1E) >> 1;
760 if ((op
& 0x7E1F) == 0x681E)
762 n
= (op
& 0x1E0) >> 5;
763 fi
->saved_regs
[n
] = next_addr
;
768 if ((op
& 0x7E3F) == 0x3A1E)
770 n
= (op
& 0x1E0) >> 5;
771 fi
->saved_regs
[n
] = next_addr
;
772 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
779 /* Put here the code to store, into fi->saved_regs, the addresses of
780 the saved registers of frame described by FRAME_INFO. This
781 includes special registers such as pc and fp saved in special ways
782 in the stack frame. sp is even more special: the address we return
783 for it IS the sp for the next frame. */
786 d10v_frame_init_saved_regs (struct frame_info
*fi
)
790 unsigned short op1
, op2
;
794 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
797 pc
= get_pc_function_start (fi
->pc
);
802 op
= (unsigned long) read_memory_integer (pc
, 4);
803 if ((op
& 0xC0000000) == 0xC0000000)
805 /* long instruction */
806 if ((op
& 0x3FFF0000) == 0x01FF0000)
809 short n
= op
& 0xFFFF;
812 else if ((op
& 0x3F0F0000) == 0x340F0000)
814 /* st rn, @(offset,sp) */
815 short offset
= op
& 0xFFFF;
816 short n
= (op
>> 20) & 0xF;
817 fi
->saved_regs
[n
] = next_addr
+ offset
;
819 else if ((op
& 0x3F1F0000) == 0x350F0000)
821 /* st2w rn, @(offset,sp) */
822 short offset
= op
& 0xFFFF;
823 short n
= (op
>> 20) & 0xF;
824 fi
->saved_regs
[n
] = next_addr
+ offset
;
825 fi
->saved_regs
[n
+ 1] = next_addr
+ offset
+ 2;
832 /* short instructions */
833 if ((op
& 0xC0000000) == 0x80000000)
835 op2
= (op
& 0x3FFF8000) >> 15;
840 op1
= (op
& 0x3FFF8000) >> 15;
843 if (!prologue_find_regs (op1
, fi
, pc
)
844 || !prologue_find_regs (op2
, fi
, pc
))
850 fi
->extra_info
->size
= -next_addr
;
853 fp
= d10v_read_sp ();
855 for (i
= 0; i
< NUM_REGS
- 1; i
++)
856 if (fi
->saved_regs
[i
])
858 fi
->saved_regs
[i
] = fp
- (next_addr
- fi
->saved_regs
[i
]);
861 if (fi
->saved_regs
[LR_REGNUM
])
864 = read_memory_unsigned_integer (fi
->saved_regs
[LR_REGNUM
],
865 REGISTER_RAW_SIZE (LR_REGNUM
));
866 fi
->extra_info
->return_pc
= d10v_make_iaddr (return_pc
);
870 fi
->extra_info
->return_pc
= d10v_make_iaddr (read_register (LR_REGNUM
));
873 /* The SP is not normally (ever?) saved, but check anyway */
874 if (!fi
->saved_regs
[SP_REGNUM
])
876 /* if the FP was saved, that means the current FP is valid, */
877 /* otherwise, it isn't being used, so we use the SP instead */
879 fi
->saved_regs
[SP_REGNUM
]
880 = d10v_read_fp () + fi
->extra_info
->size
;
883 fi
->saved_regs
[SP_REGNUM
] = fp
+ fi
->extra_info
->size
;
884 fi
->extra_info
->frameless
= 1;
885 fi
->saved_regs
[FP_REGNUM
] = 0;
891 d10v_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
893 fi
->extra_info
= (struct frame_extra_info
*)
894 frame_obstack_alloc (sizeof (struct frame_extra_info
));
895 frame_saved_regs_zalloc (fi
);
897 fi
->extra_info
->frameless
= 0;
898 fi
->extra_info
->size
= 0;
899 fi
->extra_info
->return_pc
= 0;
901 /* If fi->pc is zero, but this is not the outermost frame,
902 then let's snatch the return_pc from the callee, so that
903 PC_IN_CALL_DUMMY will work. */
904 if (fi
->pc
== 0 && fi
->level
!= 0 && fi
->next
!= NULL
)
905 fi
->pc
= d10v_frame_saved_pc (fi
->next
);
907 /* The call dummy doesn't save any registers on the stack, so we can
909 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
915 d10v_frame_init_saved_regs (fi
);
920 show_regs (char *args
, int from_tty
)
923 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
924 (long) read_register (PC_REGNUM
),
925 (long) d10v_make_iaddr (read_register (PC_REGNUM
)),
926 (long) read_register (PSW_REGNUM
),
927 (long) read_register (24),
928 (long) read_register (25),
929 (long) read_register (23));
930 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
931 (long) read_register (0),
932 (long) read_register (1),
933 (long) read_register (2),
934 (long) read_register (3),
935 (long) read_register (4),
936 (long) read_register (5),
937 (long) read_register (6),
938 (long) read_register (7));
939 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
940 (long) read_register (8),
941 (long) read_register (9),
942 (long) read_register (10),
943 (long) read_register (11),
944 (long) read_register (12),
945 (long) read_register (13),
946 (long) read_register (14),
947 (long) read_register (15));
948 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
951 printf_filtered (" ");
952 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
954 if (NR_DMAP_REGS
== 1)
955 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
958 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
960 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
962 printf_filtered ("\n");
964 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
965 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
967 char num
[MAX_REGISTER_RAW_SIZE
];
969 printf_filtered (" ");
970 read_register_gen (a
, (char *) &num
);
971 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
973 printf_filtered ("%02x", (num
[i
] & 0xff));
976 printf_filtered ("\n");
980 d10v_read_pc (ptid_t ptid
)
986 save_ptid
= inferior_ptid
;
987 inferior_ptid
= ptid
;
988 pc
= (int) read_register (PC_REGNUM
);
989 inferior_ptid
= save_ptid
;
990 retval
= d10v_make_iaddr (pc
);
995 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
999 save_ptid
= inferior_ptid
;
1000 inferior_ptid
= ptid
;
1001 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
1002 inferior_ptid
= save_ptid
;
1008 return (d10v_make_daddr (read_register (SP_REGNUM
)));
1012 d10v_write_sp (CORE_ADDR val
)
1014 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
1020 return (d10v_make_daddr (read_register (FP_REGNUM
)));
1023 /* Function: push_return_address (pc)
1024 Set up the return address for the inferior function call.
1025 Needed for targets where we don't actually execute a JSR/BSR instruction */
1028 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1030 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
1035 /* When arguments must be pushed onto the stack, they go on in reverse
1036 order. The below implements a FILO (stack) to do this. */
1041 struct stack_item
*prev
;
1045 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
1046 void *contents
, int len
);
1047 static struct stack_item
*
1048 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1050 struct stack_item
*si
;
1051 si
= xmalloc (sizeof (struct stack_item
));
1052 si
->data
= xmalloc (len
);
1055 memcpy (si
->data
, contents
, len
);
1059 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
1060 static struct stack_item
*
1061 pop_stack_item (struct stack_item
*si
)
1063 struct stack_item
*dead
= si
;
1072 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1073 int struct_return
, CORE_ADDR struct_addr
)
1076 int regnum
= ARG1_REGNUM
;
1077 struct stack_item
*si
= NULL
;
1079 /* Fill in registers and arg lists */
1080 for (i
= 0; i
< nargs
; i
++)
1082 struct value
*arg
= args
[i
];
1083 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1084 char *contents
= VALUE_CONTENTS (arg
);
1085 int len
= TYPE_LENGTH (type
);
1086 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1088 int aligned_regnum
= (regnum
+ 1) & ~1;
1089 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1090 /* fits in a single register, do not align */
1092 long val
= extract_unsigned_integer (contents
, len
);
1093 write_register (regnum
++, val
);
1095 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1096 /* value fits in remaining registers, store keeping left
1100 regnum
= aligned_regnum
;
1101 for (b
= 0; b
< (len
& ~1); b
+= 2)
1103 long val
= extract_unsigned_integer (&contents
[b
], 2);
1104 write_register (regnum
++, val
);
1108 long val
= extract_unsigned_integer (&contents
[b
], 1);
1109 write_register (regnum
++, (val
<< 8));
1114 /* arg will go onto stack */
1115 regnum
= ARGN_REGNUM
+ 1;
1116 si
= push_stack_item (si
, contents
, len
);
1123 sp
= (sp
- si
->len
) & ~1;
1124 write_memory (sp
, si
->data
, si
->len
);
1125 si
= pop_stack_item (si
);
1132 /* Given a return value in `regbuf' with a type `valtype',
1133 extract and copy its value into `valbuf'. */
1136 d10v_extract_return_value (struct type
*type
, char regbuf
[REGISTER_BYTES
],
1140 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1142 len
= TYPE_LENGTH (type
);
1145 unsigned short c
= extract_unsigned_integer (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1146 store_unsigned_integer (valbuf
, 1, c
);
1148 else if ((len
& 1) == 0)
1149 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
), len
);
1152 /* For return values of odd size, the first byte is in the
1153 least significant part of the first register. The
1154 remaining bytes in remaining registers. Interestingly,
1155 when such values are passed in, the last byte is in the
1156 most significant byte of that same register - wierd. */
1157 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
) + 1, len
);
1162 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1163 understands. Returns number of bytes that can be transfered
1164 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1165 (segmentation fault). Since the simulator knows all about how the
1166 VM system works, we just call that to do the translation. */
1169 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1170 CORE_ADDR
*targ_addr
, int *targ_len
)
1174 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1177 d10v_imap_register
);
1178 *targ_addr
= out_addr
;
1179 *targ_len
= out_len
;
1183 /* The following code implements access to, and display of, the D10V's
1184 instruction trace buffer. The buffer consists of 64K or more
1185 4-byte words of data, of which each words includes an 8-bit count,
1186 an 8-bit segment number, and a 16-bit instruction address.
1188 In theory, the trace buffer is continuously capturing instruction
1189 data that the CPU presents on its "debug bus", but in practice, the
1190 ROMified GDB stub only enables tracing when it continues or steps
1191 the program, and stops tracing when the program stops; so it
1192 actually works for GDB to read the buffer counter out of memory and
1193 then read each trace word. The counter records where the tracing
1194 stops, but there is no record of where it started, so we remember
1195 the PC when we resumed and then search backwards in the trace
1196 buffer for a word that includes that address. This is not perfect,
1197 because you will miss trace data if the resumption PC is the target
1198 of a branch. (The value of the buffer counter is semi-random, any
1199 trace data from a previous program stop is gone.) */
1201 /* The address of the last word recorded in the trace buffer. */
1203 #define DBBC_ADDR (0xd80000)
1205 /* The base of the trace buffer, at least for the "Board_0". */
1207 #define TRACE_BUFFER_BASE (0xf40000)
1209 static void trace_command (char *, int);
1211 static void untrace_command (char *, int);
1213 static void trace_info (char *, int);
1215 static void tdisassemble_command (char *, int);
1217 static void display_trace (int, int);
1219 /* True when instruction traces are being collected. */
1223 /* Remembered PC. */
1225 static CORE_ADDR last_pc
;
1227 /* True when trace output should be displayed whenever program stops. */
1229 static int trace_display
;
1231 /* True when trace listing should include source lines. */
1233 static int default_trace_show_source
= 1;
1244 trace_command (char *args
, int from_tty
)
1246 /* Clear the host-side trace buffer, allocating space if needed. */
1247 trace_data
.size
= 0;
1248 if (trace_data
.counts
== NULL
)
1249 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1250 if (trace_data
.addrs
== NULL
)
1251 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1255 printf_filtered ("Tracing is now on.\n");
1259 untrace_command (char *args
, int from_tty
)
1263 printf_filtered ("Tracing is now off.\n");
1267 trace_info (char *args
, int from_tty
)
1271 if (trace_data
.size
)
1273 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1275 for (i
= 0; i
< trace_data
.size
; ++i
)
1277 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1279 trace_data
.counts
[i
],
1280 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1281 paddr_nz (trace_data
.addrs
[i
]));
1285 printf_filtered ("No entries in trace buffer.\n");
1287 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1290 /* Print the instruction at address MEMADDR in debugged memory,
1291 on STREAM. Returns length of the instruction, in bytes. */
1294 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1296 /* If there's no disassembler, something is very wrong. */
1297 if (tm_print_insn
== NULL
)
1298 internal_error (__FILE__
, __LINE__
,
1299 "print_insn: no disassembler");
1301 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1302 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1304 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1305 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1309 d10v_eva_prepare_to_trace (void)
1314 last_pc
= read_register (PC_REGNUM
);
1317 /* Collect trace data from the target board and format it into a form
1318 more useful for display. */
1321 d10v_eva_get_trace_data (void)
1323 int count
, i
, j
, oldsize
;
1324 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1325 unsigned int last_trace
, trace_word
, next_word
;
1326 unsigned int *tmpspace
;
1331 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1333 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1335 /* Collect buffer contents from the target, stopping when we reach
1336 the word recorded when execution resumed. */
1339 while (last_trace
> 0)
1343 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1344 trace_addr
= trace_word
& 0xffff;
1346 /* Ignore an apparently nonsensical entry. */
1347 if (trace_addr
== 0xffd5)
1349 tmpspace
[count
++] = trace_word
;
1350 if (trace_addr
== last_pc
)
1356 /* Move the data to the host-side trace buffer, adjusting counts to
1357 include the last instruction executed and transforming the address
1358 into something that GDB likes. */
1360 for (i
= 0; i
< count
; ++i
)
1362 trace_word
= tmpspace
[i
];
1363 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1364 trace_addr
= trace_word
& 0xffff;
1365 next_cnt
= (next_word
>> 24) & 0xff;
1366 j
= trace_data
.size
+ count
- i
- 1;
1367 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1368 trace_data
.counts
[j
] = next_cnt
+ 1;
1371 oldsize
= trace_data
.size
;
1372 trace_data
.size
+= count
;
1377 display_trace (oldsize
, trace_data
.size
);
1381 tdisassemble_command (char *arg
, int from_tty
)
1384 CORE_ADDR low
, high
;
1390 high
= trace_data
.size
;
1392 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1394 low
= parse_and_eval_address (arg
);
1399 /* Two arguments. */
1400 *space_index
= '\0';
1401 low
= parse_and_eval_address (arg
);
1402 high
= parse_and_eval_address (space_index
+ 1);
1407 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1409 display_trace (low
, high
);
1411 printf_filtered ("End of trace dump.\n");
1412 gdb_flush (gdb_stdout
);
1416 display_trace (int low
, int high
)
1418 int i
, count
, trace_show_source
, first
, suppress
;
1419 CORE_ADDR next_address
;
1421 trace_show_source
= default_trace_show_source
;
1422 if (!have_full_symbols () && !have_partial_symbols ())
1424 trace_show_source
= 0;
1425 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1426 printf_filtered ("Trace will not display any source.\n");
1431 for (i
= low
; i
< high
; ++i
)
1433 next_address
= trace_data
.addrs
[i
];
1434 count
= trace_data
.counts
[i
];
1438 if (trace_show_source
)
1440 struct symtab_and_line sal
, sal_prev
;
1442 sal_prev
= find_pc_line (next_address
- 4, 0);
1443 sal
= find_pc_line (next_address
, 0);
1447 if (first
|| sal
.line
!= sal_prev
.line
)
1448 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1454 /* FIXME-32x64--assumes sal.pc fits in long. */
1455 printf_filtered ("No source file for address %s.\n",
1456 local_hex_string ((unsigned long) sal
.pc
));
1461 print_address (next_address
, gdb_stdout
);
1462 printf_filtered (":");
1463 printf_filtered ("\t");
1465 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1466 printf_filtered ("\n");
1467 gdb_flush (gdb_stdout
);
1473 static gdbarch_init_ftype d10v_gdbarch_init
;
1475 static struct gdbarch
*
1476 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1478 static LONGEST d10v_call_dummy_words
[] =
1480 struct gdbarch
*gdbarch
;
1482 struct gdbarch_tdep
*tdep
;
1483 gdbarch_register_name_ftype
*d10v_register_name
;
1484 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1486 /* Find a candidate among the list of pre-declared architectures. */
1487 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1489 return arches
->gdbarch
;
1491 /* None found, create a new architecture from the information
1493 tdep
= XMALLOC (struct gdbarch_tdep
);
1494 gdbarch
= gdbarch_alloc (&info
, tdep
);
1496 switch (info
.bfd_arch_info
->mach
)
1498 case bfd_mach_d10v_ts2
:
1500 d10v_register_name
= d10v_ts2_register_name
;
1501 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1502 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1503 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1504 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1505 tdep
->imap_register
= d10v_ts2_imap_register
;
1508 case bfd_mach_d10v_ts3
:
1510 d10v_register_name
= d10v_ts3_register_name
;
1511 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1512 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1513 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1514 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1515 tdep
->imap_register
= d10v_ts3_imap_register
;
1519 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1520 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1521 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1522 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1523 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1525 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1526 set_gdbarch_sp_regnum (gdbarch
, 15);
1527 set_gdbarch_fp_regnum (gdbarch
, 11);
1528 set_gdbarch_pc_regnum (gdbarch
, 18);
1529 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1530 set_gdbarch_register_size (gdbarch
, 2);
1531 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1532 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1533 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1534 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1535 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1536 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1537 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1539 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1540 set_gdbarch_addr_bit (gdbarch
, 32);
1541 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1542 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1543 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1544 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1545 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1546 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1547 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1548 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1549 double'' is 64 bits. */
1550 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1551 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1552 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1553 switch (info
.byte_order
)
1555 case BFD_ENDIAN_BIG
:
1556 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1557 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1558 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1560 case BFD_ENDIAN_LITTLE
:
1561 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1562 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1563 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1566 internal_error (__FILE__
, __LINE__
,
1567 "d10v_gdbarch_init: bad byte order for float format");
1570 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
1571 set_gdbarch_call_dummy_length (gdbarch
, 0);
1572 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
1573 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1574 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1575 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1576 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1577 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
1578 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1579 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1580 set_gdbarch_call_dummy_p (gdbarch
, 1);
1581 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1582 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
1583 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1585 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1586 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1587 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1588 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1590 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1591 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1592 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1593 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1595 set_gdbarch_frame_init_saved_regs (gdbarch
, d10v_frame_init_saved_regs
);
1596 set_gdbarch_init_extra_frame_info (gdbarch
, d10v_init_extra_frame_info
);
1598 set_gdbarch_pop_frame (gdbarch
, d10v_pop_frame
);
1600 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1601 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1602 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1603 set_gdbarch_function_start_offset (gdbarch
, 0);
1604 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1606 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1608 set_gdbarch_frame_args_skip (gdbarch
, 0);
1609 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1610 set_gdbarch_frame_chain (gdbarch
, d10v_frame_chain
);
1611 set_gdbarch_frame_chain_valid (gdbarch
, d10v_frame_chain_valid
);
1612 set_gdbarch_frame_saved_pc (gdbarch
, d10v_frame_saved_pc
);
1613 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
1614 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
1615 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1616 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1617 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1619 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1620 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1626 extern void (*target_resume_hook
) (void);
1627 extern void (*target_wait_loop_hook
) (void);
1630 _initialize_d10v_tdep (void)
1632 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1634 tm_print_insn
= print_insn_d10v
;
1636 target_resume_hook
= d10v_eva_prepare_to_trace
;
1637 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1639 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1641 add_com ("itrace", class_support
, trace_command
,
1642 "Enable tracing of instruction execution.");
1644 add_com ("iuntrace", class_support
, untrace_command
,
1645 "Disable tracing of instruction execution.");
1647 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1648 "Disassemble the trace buffer.\n\
1649 Two optional arguments specify a range of trace buffer entries\n\
1650 as reported by info trace (NOT addresses!).");
1652 add_info ("itrace", trace_info
,
1653 "Display info about the trace data buffer.");
1655 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1656 var_integer
, (char *) &trace_display
,
1657 "Set automatic display of trace.\n", &setlist
),
1659 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1660 var_integer
, (char *) &default_trace_show_source
,
1661 "Set display of source code with trace.\n", &setlist
),