1 /* Target-dependent code for Mitsubishi D10V, for GDB.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Contributed by Martin Hunt, hunt@cygnus.com */
31 #include "gdb_string.h"
38 #include "arch-utils.h"
41 #include "floatformat.h"
45 #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
47 struct frame_extra_info
58 unsigned long (*dmap_register
) (int nr
);
59 unsigned long (*imap_register
) (int nr
);
62 /* These are the addresses the D10V-EVA board maps data and
63 instruction memory to. */
65 #define DMEM_START 0x2000000
66 #define IMEM_START 0x1000000
67 #define STACK_START 0x0007ffe
69 /* d10v register names. */
79 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
80 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
82 /* d10v calling convention. */
84 #define ARG1_REGNUM R0_REGNUM
86 #define RET1_REGNUM R0_REGNUM
90 extern void _initialize_d10v_tdep (void);
92 static void d10v_eva_prepare_to_trace (void);
94 static void d10v_eva_get_trace_data (void);
96 static int prologue_find_regs (unsigned short op
, struct frame_info
*fi
,
99 static void d10v_frame_init_saved_regs (struct frame_info
*);
101 static void do_d10v_pop_frame (struct frame_info
*fi
);
104 d10v_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*frame
)
106 return ((chain
) != 0 && (frame
) != 0
107 && (frame
)->pc
> IMEM_START
108 && !inside_entry_file (FRAME_SAVED_PC (frame
)));
112 d10v_stack_align (CORE_ADDR len
)
114 return (len
+ 1) & ~1;
117 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
118 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
119 and TYPE is the type (which is known to be struct, union or array).
121 The d10v returns anything less than 8 bytes in size in
125 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
129 /* The d10v only passes a struct in a register when that structure
130 has an alignment that matches the size of a register. */
131 /* If the structure doesn't fit in 4 registers, put it on the
133 if (TYPE_LENGTH (type
) > 8)
135 /* If the struct contains only one field, don't put it on the stack
136 - gcc can fit it in one or more registers. */
137 if (TYPE_NFIELDS (type
) == 1)
139 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
140 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
142 /* If the alignment changes, just assume it goes on the
144 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
147 /* If the alignment is suitable for the d10v's 16 bit registers,
148 don't put it on the stack. */
149 if (alignment
== 2 || alignment
== 4)
155 static unsigned char *
156 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
158 static unsigned char breakpoint
[] =
159 {0x2f, 0x90, 0x5e, 0x00};
160 *lenptr
= sizeof (breakpoint
);
164 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
165 when the reg_nr isn't valid. */
169 TS2_IMAP0_REGNUM
= 32,
170 TS2_DMAP_REGNUM
= 34,
171 TS2_NR_DMAP_REGS
= 1,
176 d10v_ts2_register_name (int reg_nr
)
178 static char *register_names
[] =
180 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
182 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
183 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
184 "imap0", "imap1", "dmap", "a0", "a1"
188 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
190 return register_names
[reg_nr
];
195 TS3_IMAP0_REGNUM
= 36,
196 TS3_DMAP0_REGNUM
= 38,
197 TS3_NR_DMAP_REGS
= 4,
202 d10v_ts3_register_name (int reg_nr
)
204 static char *register_names
[] =
206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
209 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
213 "dmap0", "dmap1", "dmap2", "dmap3"
217 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
219 return register_names
[reg_nr
];
222 /* Access the DMAP/IMAP registers in a target independent way.
224 Divide the D10V's 64k data space into four 16k segments:
225 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
228 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
229 0x7fff) always map to the on-chip data RAM, and the fourth always
230 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
231 unified memory or instruction memory, under the control of the
232 single DMAP register.
234 On the TS3, there are four DMAP registers, each of which controls
235 one of the segments. */
238 d10v_ts2_dmap_register (int reg_nr
)
246 return read_register (TS2_DMAP_REGNUM
);
253 d10v_ts3_dmap_register (int reg_nr
)
255 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
259 d10v_dmap_register (int reg_nr
)
261 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
265 d10v_ts2_imap_register (int reg_nr
)
267 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
271 d10v_ts3_imap_register (int reg_nr
)
273 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
277 d10v_imap_register (int reg_nr
)
279 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
282 /* MAP GDB's internal register numbering (determined by the layout fo
283 the REGISTER_BYTE array) onto the simulator's register
287 d10v_ts2_register_sim_regno (int nr
)
289 if (nr
>= TS2_IMAP0_REGNUM
290 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
291 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
292 if (nr
== TS2_DMAP_REGNUM
)
293 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
294 if (nr
>= TS2_A0_REGNUM
295 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
296 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
301 d10v_ts3_register_sim_regno (int nr
)
303 if (nr
>= TS3_IMAP0_REGNUM
304 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
305 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
306 if (nr
>= TS3_DMAP0_REGNUM
307 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
308 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
309 if (nr
>= TS3_A0_REGNUM
310 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
311 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
315 /* Index within `registers' of the first byte of the space for
319 d10v_register_byte (int reg_nr
)
321 if (reg_nr
< A0_REGNUM
)
323 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
324 return (A0_REGNUM
* 2
325 + (reg_nr
- A0_REGNUM
) * 8);
327 return (A0_REGNUM
* 2
329 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
332 /* Number of bytes of storage in the actual machine representation for
336 d10v_register_raw_size (int reg_nr
)
338 if (reg_nr
< A0_REGNUM
)
340 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
346 /* Number of bytes of storage in the program's representation
350 d10v_register_virtual_size (int reg_nr
)
352 return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr
));
355 /* Return the GDB type object for the "standard" data type
356 of data in register N. */
359 d10v_register_virtual_type (int reg_nr
)
361 if (reg_nr
== PC_REGNUM
)
362 return builtin_type_void_func_ptr
;
363 else if (reg_nr
>= A0_REGNUM
364 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
365 return builtin_type_int64
;
367 return builtin_type_int16
;
371 d10v_make_daddr (CORE_ADDR x
)
373 return ((x
) | DMEM_START
);
377 d10v_make_iaddr (CORE_ADDR x
)
379 return (((x
) << 2) | IMEM_START
);
383 d10v_daddr_p (CORE_ADDR x
)
385 return (((x
) & 0x3000000) == DMEM_START
);
389 d10v_iaddr_p (CORE_ADDR x
)
391 return (((x
) & 0x3000000) == IMEM_START
);
396 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
398 return (((x
) >> 2) & 0xffff);
402 d10v_convert_daddr_to_raw (CORE_ADDR x
)
404 return ((x
) & 0xffff);
408 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
410 /* Is it a code address? */
411 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
412 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
415 if (! d10v_iaddr_p (addr
))
418 fprintf_unfiltered (gdb_stderr
, "address `");
419 print_address_numeric (addr
, 1, gdb_stderr
);
420 fprintf_unfiltered (gdb_stderr
, "' is not a code address\n");
424 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
425 d10v_convert_iaddr_to_raw (addr
));
429 /* Strip off any upper segment bits. */
430 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
431 d10v_convert_daddr_to_raw (addr
));
436 d10v_pointer_to_address (struct type
*type
, void *buf
)
438 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
440 /* Is it a code address? */
441 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
442 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
||
443 (TYPE_FLAGS (TYPE_TARGET_TYPE (type
)) & TYPE_FLAG_CODE_SPACE
) != 0)
444 return d10v_make_iaddr (addr
);
446 return d10v_make_daddr (addr
);
450 d10v_integer_to_address (struct type
*type
, void *buf
)
453 val
= unpack_long (type
, buf
);
454 if (TYPE_CODE (type
) == TYPE_CODE_INT
455 && TYPE_LENGTH (type
) <= TYPE_LENGTH (builtin_type_void_data_ptr
))
456 /* Convert small integers that would would be directly copied into
457 a pointer variable into an address pointing into data space. */
458 return d10v_make_daddr (val
& 0xffff);
460 /* The value is too large to fit in a pointer. Assume this was
461 intentional and that the user in fact specified a raw address. */
465 /* Store the address of the place in which to copy the structure the
466 subroutine will return. This is called from call_function.
468 We store structs through a pointer passed in the first Argument
472 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
474 write_register (ARG1_REGNUM
, (addr
));
477 /* Write into appropriate registers a function return value
478 of type TYPE, given in virtual format.
480 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
483 d10v_store_return_value (struct type
*type
, char *valbuf
)
485 write_register_bytes (REGISTER_BYTE (RET1_REGNUM
),
490 /* Extract from an array REGBUF containing the (raw) register state
491 the address in which a function should return its structure value,
492 as a CORE_ADDR (or an expression that can be used as one). */
495 d10v_extract_struct_value_address (char *regbuf
)
497 return (extract_address ((regbuf
) + REGISTER_BYTE (ARG1_REGNUM
),
498 REGISTER_RAW_SIZE (ARG1_REGNUM
))
503 d10v_frame_saved_pc (struct frame_info
*frame
)
505 return ((frame
)->extra_info
->return_pc
);
508 /* Immediately after a function call, return the saved pc. We can't
509 use frame->return_pc beause that is determined by reading R13 off
510 the stack and that may not be written yet. */
513 d10v_saved_pc_after_call (struct frame_info
*frame
)
515 return ((read_register (LR_REGNUM
) << 2)
519 /* Discard from the stack the innermost frame, restoring all saved
523 d10v_pop_frame (void)
525 generic_pop_current_frame (do_d10v_pop_frame
);
529 do_d10v_pop_frame (struct frame_info
*fi
)
536 /* fill out fsr with the address of where each */
537 /* register was stored in the frame */
538 d10v_frame_init_saved_regs (fi
);
540 /* now update the current registers with the old values */
541 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
543 if (fi
->saved_regs
[regnum
])
545 read_memory (fi
->saved_regs
[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
546 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
, REGISTER_RAW_SIZE (regnum
));
549 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
551 if (fi
->saved_regs
[regnum
])
553 write_register (regnum
, read_memory_unsigned_integer (fi
->saved_regs
[regnum
], REGISTER_RAW_SIZE (regnum
)));
556 if (fi
->saved_regs
[PSW_REGNUM
])
558 write_register (PSW_REGNUM
, read_memory_unsigned_integer (fi
->saved_regs
[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
561 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
562 write_register (SP_REGNUM
, fp
+ fi
->extra_info
->size
);
563 target_store_registers (-1);
564 flush_cached_frames ();
568 check_prologue (unsigned short op
)
571 if ((op
& 0x7E1F) == 0x6C1F)
575 if ((op
& 0x7E3F) == 0x6E1F)
579 if ((op
& 0x7FE1) == 0x01E1)
591 if ((op
& 0x7E1F) == 0x681E)
595 if ((op
& 0x7E3F) == 0x3A1E)
602 d10v_skip_prologue (CORE_ADDR pc
)
605 unsigned short op1
, op2
;
606 CORE_ADDR func_addr
, func_end
;
607 struct symtab_and_line sal
;
609 /* If we have line debugging information, then the end of the */
610 /* prologue should the first assembly instruction of the first source line */
611 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
613 sal
= find_pc_line (func_addr
, 0);
614 if (sal
.end
&& sal
.end
< func_end
)
618 if (target_read_memory (pc
, (char *) &op
, 4))
619 return pc
; /* Can't access it -- assume no prologue. */
623 op
= (unsigned long) read_memory_integer (pc
, 4);
624 if ((op
& 0xC0000000) == 0xC0000000)
626 /* long instruction */
627 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
628 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
629 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
634 /* short instructions */
635 if ((op
& 0xC0000000) == 0x80000000)
637 op2
= (op
& 0x3FFF8000) >> 15;
642 op1
= (op
& 0x3FFF8000) >> 15;
645 if (check_prologue (op1
))
647 if (!check_prologue (op2
))
649 /* if the previous opcode was really part of the prologue */
650 /* and not just a NOP, then we want to break after both instructions */
664 /* Given a GDB frame, determine the address of the calling function's frame.
665 This will be used to create a new GDB frame struct, and then
666 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
670 d10v_frame_chain (struct frame_info
*fi
)
672 d10v_frame_init_saved_regs (fi
);
674 if (fi
->extra_info
->return_pc
== IMEM_START
675 || inside_entry_file (fi
->extra_info
->return_pc
))
676 return (CORE_ADDR
) 0;
678 if (!fi
->saved_regs
[FP_REGNUM
])
680 if (!fi
->saved_regs
[SP_REGNUM
]
681 || fi
->saved_regs
[SP_REGNUM
] == STACK_START
)
682 return (CORE_ADDR
) 0;
684 return fi
->saved_regs
[SP_REGNUM
];
687 if (!read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
688 REGISTER_RAW_SIZE (FP_REGNUM
)))
689 return (CORE_ADDR
) 0;
691 return d10v_make_daddr (read_memory_unsigned_integer (fi
->saved_regs
[FP_REGNUM
],
692 REGISTER_RAW_SIZE (FP_REGNUM
)));
695 static int next_addr
, uses_frame
;
698 prologue_find_regs (unsigned short op
, struct frame_info
*fi
, CORE_ADDR addr
)
703 if ((op
& 0x7E1F) == 0x6C1F)
705 n
= (op
& 0x1E0) >> 5;
707 fi
->saved_regs
[n
] = next_addr
;
712 else if ((op
& 0x7E3F) == 0x6E1F)
714 n
= (op
& 0x1E0) >> 5;
716 fi
->saved_regs
[n
] = next_addr
;
717 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
722 if ((op
& 0x7FE1) == 0x01E1)
724 n
= (op
& 0x1E) >> 1;
743 if ((op
& 0x7E1F) == 0x681E)
745 n
= (op
& 0x1E0) >> 5;
746 fi
->saved_regs
[n
] = next_addr
;
751 if ((op
& 0x7E3F) == 0x3A1E)
753 n
= (op
& 0x1E0) >> 5;
754 fi
->saved_regs
[n
] = next_addr
;
755 fi
->saved_regs
[n
+ 1] = next_addr
+ 2;
762 /* Put here the code to store, into fi->saved_regs, the addresses of
763 the saved registers of frame described by FRAME_INFO. This
764 includes special registers such as pc and fp saved in special ways
765 in the stack frame. sp is even more special: the address we return
766 for it IS the sp for the next frame. */
769 d10v_frame_init_saved_regs (struct frame_info
*fi
)
773 unsigned short op1
, op2
;
777 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
780 pc
= get_pc_function_start (fi
->pc
);
785 op
= (unsigned long) read_memory_integer (pc
, 4);
786 if ((op
& 0xC0000000) == 0xC0000000)
788 /* long instruction */
789 if ((op
& 0x3FFF0000) == 0x01FF0000)
792 short n
= op
& 0xFFFF;
795 else if ((op
& 0x3F0F0000) == 0x340F0000)
797 /* st rn, @(offset,sp) */
798 short offset
= op
& 0xFFFF;
799 short n
= (op
>> 20) & 0xF;
800 fi
->saved_regs
[n
] = next_addr
+ offset
;
802 else if ((op
& 0x3F1F0000) == 0x350F0000)
804 /* st2w rn, @(offset,sp) */
805 short offset
= op
& 0xFFFF;
806 short n
= (op
>> 20) & 0xF;
807 fi
->saved_regs
[n
] = next_addr
+ offset
;
808 fi
->saved_regs
[n
+ 1] = next_addr
+ offset
+ 2;
815 /* short instructions */
816 if ((op
& 0xC0000000) == 0x80000000)
818 op2
= (op
& 0x3FFF8000) >> 15;
823 op1
= (op
& 0x3FFF8000) >> 15;
826 if (!prologue_find_regs (op1
, fi
, pc
) || !prologue_find_regs (op2
, fi
, pc
))
832 fi
->extra_info
->size
= -next_addr
;
835 fp
= d10v_make_daddr (read_register (SP_REGNUM
));
837 for (i
= 0; i
< NUM_REGS
- 1; i
++)
838 if (fi
->saved_regs
[i
])
840 fi
->saved_regs
[i
] = fp
- (next_addr
- fi
->saved_regs
[i
]);
843 if (fi
->saved_regs
[LR_REGNUM
])
845 CORE_ADDR return_pc
= read_memory_unsigned_integer (fi
->saved_regs
[LR_REGNUM
], REGISTER_RAW_SIZE (LR_REGNUM
));
846 fi
->extra_info
->return_pc
= d10v_make_iaddr (return_pc
);
850 fi
->extra_info
->return_pc
= d10v_make_iaddr (read_register (LR_REGNUM
));
853 /* th SP is not normally (ever?) saved, but check anyway */
854 if (!fi
->saved_regs
[SP_REGNUM
])
856 /* if the FP was saved, that means the current FP is valid, */
857 /* otherwise, it isn't being used, so we use the SP instead */
859 fi
->saved_regs
[SP_REGNUM
] = read_register (FP_REGNUM
) + fi
->extra_info
->size
;
862 fi
->saved_regs
[SP_REGNUM
] = fp
+ fi
->extra_info
->size
;
863 fi
->extra_info
->frameless
= 1;
864 fi
->saved_regs
[FP_REGNUM
] = 0;
870 d10v_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
872 fi
->extra_info
= (struct frame_extra_info
*)
873 frame_obstack_alloc (sizeof (struct frame_extra_info
));
874 frame_saved_regs_zalloc (fi
);
876 fi
->extra_info
->frameless
= 0;
877 fi
->extra_info
->size
= 0;
878 fi
->extra_info
->return_pc
= 0;
880 /* The call dummy doesn't save any registers on the stack, so we can
882 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
888 d10v_frame_init_saved_regs (fi
);
893 show_regs (char *args
, int from_tty
)
896 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
897 (long) read_register (PC_REGNUM
),
898 (long) d10v_make_iaddr (read_register (PC_REGNUM
)),
899 (long) read_register (PSW_REGNUM
),
900 (long) read_register (24),
901 (long) read_register (25),
902 (long) read_register (23));
903 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
904 (long) read_register (0),
905 (long) read_register (1),
906 (long) read_register (2),
907 (long) read_register (3),
908 (long) read_register (4),
909 (long) read_register (5),
910 (long) read_register (6),
911 (long) read_register (7));
912 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
913 (long) read_register (8),
914 (long) read_register (9),
915 (long) read_register (10),
916 (long) read_register (11),
917 (long) read_register (12),
918 (long) read_register (13),
919 (long) read_register (14),
920 (long) read_register (15));
921 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
924 printf_filtered (" ");
925 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
927 if (NR_DMAP_REGS
== 1)
928 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
931 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
933 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
935 printf_filtered ("\n");
937 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
938 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
940 char num
[MAX_REGISTER_RAW_SIZE
];
942 printf_filtered (" ");
943 read_register_gen (a
, (char *) &num
);
944 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
946 printf_filtered ("%02x", (num
[i
] & 0xff));
949 printf_filtered ("\n");
953 d10v_read_pc (ptid_t ptid
)
959 save_ptid
= inferior_ptid
;
960 inferior_ptid
= ptid
;
961 pc
= (int) read_register (PC_REGNUM
);
962 inferior_ptid
= save_ptid
;
963 retval
= d10v_make_iaddr (pc
);
968 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
972 save_ptid
= inferior_ptid
;
973 inferior_ptid
= ptid
;
974 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
975 inferior_ptid
= save_ptid
;
981 return (d10v_make_daddr (read_register (SP_REGNUM
)));
985 d10v_write_sp (CORE_ADDR val
)
987 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
991 d10v_write_fp (CORE_ADDR val
)
993 write_register (FP_REGNUM
, d10v_convert_daddr_to_raw (val
));
999 return (d10v_make_daddr (read_register (FP_REGNUM
)));
1002 /* Function: push_return_address (pc)
1003 Set up the return address for the inferior function call.
1004 Needed for targets where we don't actually execute a JSR/BSR instruction */
1007 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1009 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
1014 /* When arguments must be pushed onto the stack, they go on in reverse
1015 order. The below implements a FILO (stack) to do this. */
1020 struct stack_item
*prev
;
1024 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
1025 void *contents
, int len
);
1026 static struct stack_item
*
1027 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1029 struct stack_item
*si
;
1030 si
= xmalloc (sizeof (struct stack_item
));
1031 si
->data
= xmalloc (len
);
1034 memcpy (si
->data
, contents
, len
);
1038 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
1039 static struct stack_item
*
1040 pop_stack_item (struct stack_item
*si
)
1042 struct stack_item
*dead
= si
;
1051 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1052 int struct_return
, CORE_ADDR struct_addr
)
1055 int regnum
= ARG1_REGNUM
;
1056 struct stack_item
*si
= NULL
;
1058 /* Fill in registers and arg lists */
1059 for (i
= 0; i
< nargs
; i
++)
1061 struct value
*arg
= args
[i
];
1062 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1063 char *contents
= VALUE_CONTENTS (arg
);
1064 int len
= TYPE_LENGTH (type
);
1065 /* printf ("push: type=%d len=%d\n", type->code, len); */
1067 int aligned_regnum
= (regnum
+ 1) & ~1;
1068 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1069 /* fits in a single register, do not align */
1071 long val
= extract_unsigned_integer (contents
, len
);
1072 write_register (regnum
++, val
);
1074 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1075 /* value fits in remaining registers, store keeping left
1079 regnum
= aligned_regnum
;
1080 for (b
= 0; b
< (len
& ~1); b
+= 2)
1082 long val
= extract_unsigned_integer (&contents
[b
], 2);
1083 write_register (regnum
++, val
);
1087 long val
= extract_unsigned_integer (&contents
[b
], 1);
1088 write_register (regnum
++, (val
<< 8));
1093 /* arg will go onto stack */
1094 regnum
= ARGN_REGNUM
+ 1;
1095 si
= push_stack_item (si
, contents
, len
);
1102 sp
= (sp
- si
->len
) & ~1;
1103 write_memory (sp
, si
->data
, si
->len
);
1104 si
= pop_stack_item (si
);
1111 /* Given a return value in `regbuf' with a type `valtype',
1112 extract and copy its value into `valbuf'. */
1115 d10v_extract_return_value (struct type
*type
, char regbuf
[REGISTER_BYTES
],
1119 /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */
1121 len
= TYPE_LENGTH (type
);
1124 unsigned short c
= extract_unsigned_integer (regbuf
+ REGISTER_BYTE (RET1_REGNUM
), REGISTER_RAW_SIZE (RET1_REGNUM
));
1125 store_unsigned_integer (valbuf
, 1, c
);
1127 else if ((len
& 1) == 0)
1128 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
), len
);
1131 /* For return values of odd size, the first byte is in the
1132 least significant part of the first register. The
1133 remaining bytes in remaining registers. Interestingly,
1134 when such values are passed in, the last byte is in the
1135 most significant byte of that same register - wierd. */
1136 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (RET1_REGNUM
) + 1, len
);
1141 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1142 understands. Returns number of bytes that can be transfered
1143 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1144 (segmentation fault). Since the simulator knows all about how the
1145 VM system works, we just call that to do the translation. */
1148 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1149 CORE_ADDR
*targ_addr
, int *targ_len
)
1153 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1156 d10v_imap_register
);
1157 *targ_addr
= out_addr
;
1158 *targ_len
= out_len
;
1162 /* The following code implements access to, and display of, the D10V's
1163 instruction trace buffer. The buffer consists of 64K or more
1164 4-byte words of data, of which each words includes an 8-bit count,
1165 an 8-bit segment number, and a 16-bit instruction address.
1167 In theory, the trace buffer is continuously capturing instruction
1168 data that the CPU presents on its "debug bus", but in practice, the
1169 ROMified GDB stub only enables tracing when it continues or steps
1170 the program, and stops tracing when the program stops; so it
1171 actually works for GDB to read the buffer counter out of memory and
1172 then read each trace word. The counter records where the tracing
1173 stops, but there is no record of where it started, so we remember
1174 the PC when we resumed and then search backwards in the trace
1175 buffer for a word that includes that address. This is not perfect,
1176 because you will miss trace data if the resumption PC is the target
1177 of a branch. (The value of the buffer counter is semi-random, any
1178 trace data from a previous program stop is gone.) */
1180 /* The address of the last word recorded in the trace buffer. */
1182 #define DBBC_ADDR (0xd80000)
1184 /* The base of the trace buffer, at least for the "Board_0". */
1186 #define TRACE_BUFFER_BASE (0xf40000)
1188 static void trace_command (char *, int);
1190 static void untrace_command (char *, int);
1192 static void trace_info (char *, int);
1194 static void tdisassemble_command (char *, int);
1196 static void display_trace (int, int);
1198 /* True when instruction traces are being collected. */
1202 /* Remembered PC. */
1204 static CORE_ADDR last_pc
;
1206 /* True when trace output should be displayed whenever program stops. */
1208 static int trace_display
;
1210 /* True when trace listing should include source lines. */
1212 static int default_trace_show_source
= 1;
1223 trace_command (char *args
, int from_tty
)
1225 /* Clear the host-side trace buffer, allocating space if needed. */
1226 trace_data
.size
= 0;
1227 if (trace_data
.counts
== NULL
)
1228 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1229 if (trace_data
.addrs
== NULL
)
1230 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1234 printf_filtered ("Tracing is now on.\n");
1238 untrace_command (char *args
, int from_tty
)
1242 printf_filtered ("Tracing is now off.\n");
1246 trace_info (char *args
, int from_tty
)
1250 if (trace_data
.size
)
1252 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1254 for (i
= 0; i
< trace_data
.size
; ++i
)
1256 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1258 trace_data
.counts
[i
],
1259 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1260 paddr_nz (trace_data
.addrs
[i
]));
1264 printf_filtered ("No entries in trace buffer.\n");
1266 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1269 /* Print the instruction at address MEMADDR in debugged memory,
1270 on STREAM. Returns length of the instruction, in bytes. */
1273 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1275 /* If there's no disassembler, something is very wrong. */
1276 if (tm_print_insn
== NULL
)
1277 internal_error (__FILE__
, __LINE__
,
1278 "print_insn: no disassembler");
1280 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1281 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1283 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1284 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1288 d10v_eva_prepare_to_trace (void)
1293 last_pc
= read_register (PC_REGNUM
);
1296 /* Collect trace data from the target board and format it into a form
1297 more useful for display. */
1300 d10v_eva_get_trace_data (void)
1302 int count
, i
, j
, oldsize
;
1303 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1304 unsigned int last_trace
, trace_word
, next_word
;
1305 unsigned int *tmpspace
;
1310 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1312 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1314 /* Collect buffer contents from the target, stopping when we reach
1315 the word recorded when execution resumed. */
1318 while (last_trace
> 0)
1322 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1323 trace_addr
= trace_word
& 0xffff;
1325 /* Ignore an apparently nonsensical entry. */
1326 if (trace_addr
== 0xffd5)
1328 tmpspace
[count
++] = trace_word
;
1329 if (trace_addr
== last_pc
)
1335 /* Move the data to the host-side trace buffer, adjusting counts to
1336 include the last instruction executed and transforming the address
1337 into something that GDB likes. */
1339 for (i
= 0; i
< count
; ++i
)
1341 trace_word
= tmpspace
[i
];
1342 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1343 trace_addr
= trace_word
& 0xffff;
1344 next_cnt
= (next_word
>> 24) & 0xff;
1345 j
= trace_data
.size
+ count
- i
- 1;
1346 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1347 trace_data
.counts
[j
] = next_cnt
+ 1;
1350 oldsize
= trace_data
.size
;
1351 trace_data
.size
+= count
;
1356 display_trace (oldsize
, trace_data
.size
);
1360 tdisassemble_command (char *arg
, int from_tty
)
1363 CORE_ADDR low
, high
;
1369 high
= trace_data
.size
;
1371 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1373 low
= parse_and_eval_address (arg
);
1378 /* Two arguments. */
1379 *space_index
= '\0';
1380 low
= parse_and_eval_address (arg
);
1381 high
= parse_and_eval_address (space_index
+ 1);
1386 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1388 display_trace (low
, high
);
1390 printf_filtered ("End of trace dump.\n");
1391 gdb_flush (gdb_stdout
);
1395 display_trace (int low
, int high
)
1397 int i
, count
, trace_show_source
, first
, suppress
;
1398 CORE_ADDR next_address
;
1400 trace_show_source
= default_trace_show_source
;
1401 if (!have_full_symbols () && !have_partial_symbols ())
1403 trace_show_source
= 0;
1404 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1405 printf_filtered ("Trace will not display any source.\n");
1410 for (i
= low
; i
< high
; ++i
)
1412 next_address
= trace_data
.addrs
[i
];
1413 count
= trace_data
.counts
[i
];
1417 if (trace_show_source
)
1419 struct symtab_and_line sal
, sal_prev
;
1421 sal_prev
= find_pc_line (next_address
- 4, 0);
1422 sal
= find_pc_line (next_address
, 0);
1426 if (first
|| sal
.line
!= sal_prev
.line
)
1427 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1433 /* FIXME-32x64--assumes sal.pc fits in long. */
1434 printf_filtered ("No source file for address %s.\n",
1435 local_hex_string ((unsigned long) sal
.pc
));
1440 print_address (next_address
, gdb_stdout
);
1441 printf_filtered (":");
1442 printf_filtered ("\t");
1444 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1445 printf_filtered ("\n");
1446 gdb_flush (gdb_stdout
);
1452 static gdbarch_init_ftype d10v_gdbarch_init
;
1454 static struct gdbarch
*
1455 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1457 static LONGEST d10v_call_dummy_words
[] =
1459 struct gdbarch
*gdbarch
;
1461 struct gdbarch_tdep
*tdep
;
1462 gdbarch_register_name_ftype
*d10v_register_name
;
1463 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1465 /* Find a candidate among the list of pre-declared architectures. */
1466 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1468 return arches
->gdbarch
;
1470 /* None found, create a new architecture from the information
1472 tdep
= XMALLOC (struct gdbarch_tdep
);
1473 gdbarch
= gdbarch_alloc (&info
, tdep
);
1475 switch (info
.bfd_arch_info
->mach
)
1477 case bfd_mach_d10v_ts2
:
1479 d10v_register_name
= d10v_ts2_register_name
;
1480 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1481 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1482 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1483 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1484 tdep
->imap_register
= d10v_ts2_imap_register
;
1487 case bfd_mach_d10v_ts3
:
1489 d10v_register_name
= d10v_ts3_register_name
;
1490 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1491 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1492 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1493 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1494 tdep
->imap_register
= d10v_ts3_imap_register
;
1498 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1499 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1500 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1501 set_gdbarch_write_fp (gdbarch
, d10v_write_fp
);
1502 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1503 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1505 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1506 set_gdbarch_sp_regnum (gdbarch
, 15);
1507 set_gdbarch_fp_regnum (gdbarch
, 11);
1508 set_gdbarch_pc_regnum (gdbarch
, 18);
1509 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1510 set_gdbarch_register_size (gdbarch
, 2);
1511 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1512 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1513 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1514 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1515 set_gdbarch_register_virtual_size (gdbarch
, d10v_register_virtual_size
);
1516 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1517 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1519 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1520 set_gdbarch_addr_bit (gdbarch
, 32);
1521 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1522 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1523 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1524 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1525 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1526 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1527 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1528 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1529 double'' is 64 bits. */
1530 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1531 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1532 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1533 switch (info
.byte_order
)
1536 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1537 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1538 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1541 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1542 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1543 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1546 internal_error (__FILE__
, __LINE__
,
1547 "d10v_gdbarch_init: bad byte order for float format");
1550 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
1551 set_gdbarch_call_dummy_length (gdbarch
, 0);
1552 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
1553 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1554 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1555 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1556 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1557 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
1558 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1559 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1560 set_gdbarch_call_dummy_p (gdbarch
, 1);
1561 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1562 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
1563 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1565 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1566 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1567 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1568 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1570 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1571 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1572 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1573 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1575 set_gdbarch_frame_init_saved_regs (gdbarch
, d10v_frame_init_saved_regs
);
1576 set_gdbarch_init_extra_frame_info (gdbarch
, d10v_init_extra_frame_info
);
1578 set_gdbarch_pop_frame (gdbarch
, d10v_pop_frame
);
1580 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1581 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1582 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1583 set_gdbarch_function_start_offset (gdbarch
, 0);
1584 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1586 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1588 set_gdbarch_frame_args_skip (gdbarch
, 0);
1589 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1590 set_gdbarch_frame_chain (gdbarch
, d10v_frame_chain
);
1591 set_gdbarch_frame_chain_valid (gdbarch
, d10v_frame_chain_valid
);
1592 set_gdbarch_frame_saved_pc (gdbarch
, d10v_frame_saved_pc
);
1593 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
1594 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
1595 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1596 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1597 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1599 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1600 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1606 extern void (*target_resume_hook
) (void);
1607 extern void (*target_wait_loop_hook
) (void);
1610 _initialize_d10v_tdep (void)
1612 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1614 tm_print_insn
= print_insn_d10v
;
1616 target_resume_hook
= d10v_eva_prepare_to_trace
;
1617 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1619 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1621 add_com ("itrace", class_support
, trace_command
,
1622 "Enable tracing of instruction execution.");
1624 add_com ("iuntrace", class_support
, untrace_command
,
1625 "Disable tracing of instruction execution.");
1627 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1628 "Disassemble the trace buffer.\n\
1629 Two optional arguments specify a range of trace buffer entries\n\
1630 as reported by info trace (NOT addresses!).");
1632 add_info ("itrace", trace_info
,
1633 "Display info about the trace data buffer.");
1635 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1636 var_integer
, (char *) &trace_display
,
1637 "Set automatic display of trace.\n", &setlist
),
1639 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1640 var_integer
, (char *) &default_trace_show_source
,
1641 "Set display of source code with trace.\n", &setlist
),