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[deliverable/binutils-gdb.git] / gdb / d30v-tdep.c
1 /* Target-dependent code for Mitsubishi D30V, for GDB.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* Contributed by Martin Hunt, hunt@cygnus.com */
23
24 #include "defs.h"
25 #include "frame.h"
26 #include "obstack.h"
27 #include "symtab.h"
28 #include "gdbtypes.h"
29 #include "gdbcmd.h"
30 #include "gdbcore.h"
31 #include "gdb_string.h"
32 #include "value.h"
33 #include "inferior.h"
34 #include "dis-asm.h"
35 #include "symfile.h"
36 #include "objfiles.h"
37 #include "regcache.h"
38
39 #include "language.h" /* For local_hex_string() */
40
41 void d30v_frame_find_saved_regs (struct frame_info *fi,
42 struct frame_saved_regs *fsr);
43 void d30v_frame_find_saved_regs_offsets (struct frame_info *fi,
44 struct frame_saved_regs *fsr);
45 static void d30v_pop_dummy_frame (struct frame_info *fi);
46 static void d30v_print_flags (void);
47 static void print_flags_command (char *, int);
48
49 /* the following defines assume:
50 fp is r61, lr is r62, sp is r63, and ?? is r22
51 if that changes, they will need to be updated */
52
53 #define OP_MASK_ALL_BUT_RA 0x0ffc0fff /* throw away Ra, keep the rest */
54
55 #define OP_STW_SPM 0x054c0fc0 /* stw Ra, @(sp-) */
56 #define OP_STW_SP_R0 0x05400fc0 /* stw Ra, @(sp,r0) */
57 #define OP_STW_SP_IMM0 0x05480fc0 /* st Ra, @(sp, 0x0) */
58 #define OP_STW_R22P_R0 0x05440580 /* stw Ra, @(r22+,r0) */
59
60 #define OP_ST2W_SPM 0x056c0fc0 /* st2w Ra, @(sp-) */
61 #define OP_ST2W_SP_R0 0x05600fc0 /* st2w Ra, @(sp, r0) */
62 #define OP_ST2W_SP_IMM0 0x05680fc0 /* st2w Ra, @(sp, 0x0) */
63 #define OP_ST2W_R22P_R0 0x05640580 /* st2w Ra, @(r22+, r0) */
64
65 #define OP_MASK_OPCODE 0x0ffc0000 /* just the opcode, ign operands */
66 #define OP_NOP 0x00f00000 /* nop */
67
68 #define OP_MASK_ALL_BUT_IMM 0x0fffffc0 /* throw away imm, keep the rest */
69 #define OP_SUB_SP_IMM 0x082bffc0 /* sub sp,sp,imm */
70 #define OP_ADD_SP_IMM 0x080bffc0 /* add sp,sp,imm */
71 #define OP_ADD_R22_SP_IMM 0x08096fc0 /* add r22,sp,imm */
72 #define OP_STW_FP_SP_IMM 0x054bdfc0 /* stw fp,@(sp,imm) */
73 #define OP_OR_SP_R0_IMM 0x03abf000 /* or sp,r0,imm */
74
75 /* no mask */
76 #define OP_OR_FP_R0_SP 0x03a3d03f /* or fp,r0,sp */
77 #define OP_OR_FP_SP_R0 0x03a3dfc0 /* or fp,sp,r0 */
78 #define OP_OR_FP_IMM0_SP 0x03abd03f /* or fp,0x0,sp */
79 #define OP_STW_FP_R22P_R0 0x0547d580 /* stw fp,@(r22+,r0) */
80 #define OP_STW_LR_R22P_R0 0x0547e580 /* stw lr,@(r22+,r0) */
81
82 #define OP_MASK_OP_AND_RB 0x0ff80fc0 /* keep op and rb,throw away rest */
83 #define OP_STW_SP_IMM 0x05480fc0 /* stw Ra,@(sp,imm) */
84 #define OP_ST2W_SP_IMM 0x05680fc0 /* st2w Ra,@(sp,imm) */
85 #define OP_STW_FP_IMM 0x05480f40 /* stw Ra,@(fp,imm) */
86 #define OP_STW_FP_R0 0x05400f40 /* stw Ra,@(fp,r0) */
87
88 #define OP_MASK_FM_BIT 0x80000000
89 #define OP_MASK_CC_BITS 0x70000000
90 #define OP_MASK_SUB_INST 0x0fffffff
91
92 #define EXTRACT_RA(op) (((op) >> 12) & 0x3f)
93 #define EXTRACT_RB(op) (((op) >> 6) & 0x3f)
94 #define EXTRACT_RC(op) (((op) & 0x3f)
95 #define EXTRACT_UIMM6(op) ((op) & 0x3f)
96 #define EXTRACT_IMM6(op) ((((int)EXTRACT_UIMM6(op)) << 26) >> 26)
97 #define EXTRACT_IMM26(op) ((((op)&0x0ff00000) >> 2) | ((op)&0x0003ffff))
98 #define EXTRACT_IMM32(opl, opr) ((EXTRACT_UIMM6(opl) << 26)|EXTRACT_IMM26(opr))
99
100
101 int
102 d30v_frame_chain_valid (CORE_ADDR chain, struct frame_info *fi)
103 {
104 #if 0
105 return ((chain) != 0 && (fi) != 0 && (fi)->return_pc != 0);
106 #else
107 return ((chain) != 0 && (fi) != 0 && (fi)->frame <= chain);
108 #endif
109 }
110
111 /* Discard from the stack the innermost frame, restoring all saved
112 registers. */
113
114 void
115 d30v_pop_frame (void)
116 {
117 struct frame_info *frame = get_current_frame ();
118 CORE_ADDR fp;
119 int regnum;
120 struct frame_saved_regs fsr;
121 char raw_buffer[8];
122
123 fp = FRAME_FP (frame);
124 if (frame->dummy)
125 {
126 d30v_pop_dummy_frame (frame);
127 return;
128 }
129
130 /* fill out fsr with the address of where each */
131 /* register was stored in the frame */
132 get_frame_saved_regs (frame, &fsr);
133
134 /* now update the current registers with the old values */
135 for (regnum = A0_REGNUM; regnum < A0_REGNUM + 2; regnum++)
136 {
137 if (fsr.regs[regnum])
138 {
139 read_memory (fsr.regs[regnum], raw_buffer, 8);
140 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8);
141 }
142 }
143 for (regnum = 0; regnum < SP_REGNUM; regnum++)
144 {
145 if (fsr.regs[regnum])
146 {
147 write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 4));
148 }
149 }
150 if (fsr.regs[PSW_REGNUM])
151 {
152 write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 4));
153 }
154
155 write_register (PC_REGNUM, read_register (LR_REGNUM));
156 write_register (SP_REGNUM, fp + frame->size);
157 target_store_registers (-1);
158 flush_cached_frames ();
159 }
160
161 static int
162 check_prologue (unsigned long op)
163 {
164 /* add sp,sp,imm -- observed */
165 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
166 return 1;
167
168 /* add r22,sp,imm -- observed */
169 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
170 return 1;
171
172 /* or fp,r0,sp -- observed */
173 if (op == OP_OR_FP_R0_SP)
174 return 1;
175
176 /* nop */
177 if ((op & OP_MASK_OPCODE) == OP_NOP)
178 return 1;
179
180 /* stw Ra,@(sp,r0) */
181 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0)
182 return 1;
183
184 /* stw Ra,@(sp,0x0) */
185 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0)
186 return 1;
187
188 /* st2w Ra,@(sp,r0) */
189 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0)
190 return 1;
191
192 /* st2w Ra,@(sp,0x0) */
193 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0)
194 return 1;
195
196 /* stw fp, @(r22+,r0) -- observed */
197 if (op == OP_STW_FP_R22P_R0)
198 return 1;
199
200 /* stw r62, @(r22+,r0) -- observed */
201 if (op == OP_STW_LR_R22P_R0)
202 return 1;
203
204 /* stw Ra, @(fp,r0) -- observed */
205 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
206 return 1; /* first arg */
207
208 /* stw Ra, @(fp,imm) -- observed */
209 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
210 return 1; /* second and subsequent args */
211
212 /* stw fp,@(sp,imm) -- observed */
213 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
214 return 1;
215
216 /* st2w Ra,@(r22+,r0) */
217 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
218 return 1;
219
220 /* stw Ra, @(sp-) */
221 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
222 return 1;
223
224 /* st2w Ra, @(sp-) */
225 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
226 return 1;
227
228 /* sub.? sp,sp,imm */
229 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
230 return 1;
231
232 return 0;
233 }
234
235 CORE_ADDR
236 d30v_skip_prologue (CORE_ADDR pc)
237 {
238 unsigned long op[2];
239 unsigned long opl, opr; /* left / right sub operations */
240 unsigned long fm0, fm1; /* left / right mode bits */
241 unsigned long cc0, cc1;
242 unsigned long op1, op2;
243 CORE_ADDR func_addr, func_end;
244 struct symtab_and_line sal;
245
246 /* If we have line debugging information, then the end of the */
247 /* prologue should the first assembly instruction of the first source line */
248 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
249 {
250 sal = find_pc_line (func_addr, 0);
251 if (sal.end && sal.end < func_end)
252 return sal.end;
253 }
254
255 if (target_read_memory (pc, (char *) &op[0], 8))
256 return pc; /* Can't access it -- assume no prologue. */
257
258 while (1)
259 {
260 opl = (unsigned long) read_memory_integer (pc, 4);
261 opr = (unsigned long) read_memory_integer (pc + 4, 4);
262
263 fm0 = (opl & OP_MASK_FM_BIT);
264 fm1 = (opr & OP_MASK_FM_BIT);
265
266 cc0 = (opl & OP_MASK_CC_BITS);
267 cc1 = (opr & OP_MASK_CC_BITS);
268
269 opl = (opl & OP_MASK_SUB_INST);
270 opr = (opr & OP_MASK_SUB_INST);
271
272 if (fm0 && fm1)
273 {
274 /* long instruction (opl contains the opcode) */
275 if (((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_SP_IMM) && /* add sp,sp,imm */
276 ((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_R22_SP_IMM) && /* add r22,sp,imm */
277 ((opl & OP_MASK_OP_AND_RB) != OP_STW_SP_IMM) && /* stw Ra, @(sp,imm) */
278 ((opl & OP_MASK_OP_AND_RB) != OP_ST2W_SP_IMM)) /* st2w Ra, @(sp,imm) */
279 break;
280 }
281 else
282 {
283 /* short instructions */
284 if (fm0 && !fm1)
285 {
286 op1 = opr;
287 op2 = opl;
288 }
289 else
290 {
291 op1 = opl;
292 op2 = opr;
293 }
294 if (check_prologue (op1))
295 {
296 if (!check_prologue (op2))
297 {
298 /* if the previous opcode was really part of the prologue */
299 /* and not just a NOP, then we want to break after both instructions */
300 if ((op1 & OP_MASK_OPCODE) != OP_NOP)
301 pc += 8;
302 break;
303 }
304 }
305 else
306 break;
307 }
308 pc += 8;
309 }
310 return pc;
311 }
312
313 static int end_of_stack;
314
315 /* Given a GDB frame, determine the address of the calling function's frame.
316 This will be used to create a new GDB frame struct, and then
317 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
318 */
319
320 CORE_ADDR
321 d30v_frame_chain (struct frame_info *frame)
322 {
323 struct frame_saved_regs fsr;
324
325 d30v_frame_find_saved_regs (frame, &fsr);
326
327 if (end_of_stack)
328 return (CORE_ADDR) 0;
329
330 if (frame->return_pc == IMEM_START)
331 return (CORE_ADDR) 0;
332
333 if (!fsr.regs[FP_REGNUM])
334 {
335 if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START)
336 return (CORE_ADDR) 0;
337
338 return fsr.regs[SP_REGNUM];
339 }
340
341 if (!read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4))
342 return (CORE_ADDR) 0;
343
344 return read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4);
345 }
346
347 static int next_addr, uses_frame;
348 static int frame_size;
349
350 static int
351 prologue_find_regs (unsigned long op, struct frame_saved_regs *fsr,
352 CORE_ADDR addr)
353 {
354 int n;
355 int offset;
356
357 /* add sp,sp,imm -- observed */
358 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
359 {
360 offset = EXTRACT_IMM6 (op);
361 /*next_addr += offset; */
362 frame_size += -offset;
363 return 1;
364 }
365
366 /* add r22,sp,imm -- observed */
367 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
368 {
369 offset = EXTRACT_IMM6 (op);
370 next_addr = (offset - frame_size);
371 return 1;
372 }
373
374 /* stw Ra, @(fp, offset) -- observed */
375 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
376 {
377 n = EXTRACT_RA (op);
378 offset = EXTRACT_IMM6 (op);
379 fsr->regs[n] = (offset - frame_size);
380 return 1;
381 }
382
383 /* stw Ra, @(fp, r0) -- observed */
384 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
385 {
386 n = EXTRACT_RA (op);
387 fsr->regs[n] = (-frame_size);
388 return 1;
389 }
390
391 /* or fp,0,sp -- observed */
392 if ((op == OP_OR_FP_R0_SP) ||
393 (op == OP_OR_FP_SP_R0) ||
394 (op == OP_OR_FP_IMM0_SP))
395 {
396 uses_frame = 1;
397 return 1;
398 }
399
400 /* nop */
401 if ((op & OP_MASK_OPCODE) == OP_NOP)
402 return 1;
403
404 /* stw Ra,@(r22+,r0) -- observed */
405 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_R22P_R0)
406 {
407 n = EXTRACT_RA (op);
408 fsr->regs[n] = next_addr;
409 next_addr += 4;
410 return 1;
411 }
412 #if 0 /* subsumed in pattern above */
413 /* stw fp,@(r22+,r0) -- observed */
414 if (op == OP_STW_FP_R22P_R0)
415 {
416 fsr->regs[FP_REGNUM] = next_addr; /* XXX */
417 next_addr += 4;
418 return 1;
419 }
420
421 /* stw r62,@(r22+,r0) -- observed */
422 if (op == OP_STW_LR_R22P_R0)
423 {
424 fsr->regs[LR_REGNUM] = next_addr;
425 next_addr += 4;
426 return 1;
427 }
428 #endif
429 /* st2w Ra,@(r22+,r0) -- observed */
430 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
431 {
432 n = EXTRACT_RA (op);
433 fsr->regs[n] = next_addr;
434 fsr->regs[n + 1] = next_addr + 4;
435 next_addr += 8;
436 return 1;
437 }
438
439 /* stw rn, @(sp-) */
440 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
441 {
442 n = EXTRACT_RA (op);
443 fsr->regs[n] = next_addr;
444 next_addr -= 4;
445 return 1;
446 }
447
448 /* st2w Ra, @(sp-) */
449 else if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
450 {
451 n = EXTRACT_RA (op);
452 fsr->regs[n] = next_addr;
453 fsr->regs[n + 1] = next_addr + 4;
454 next_addr -= 8;
455 return 1;
456 }
457
458 /* sub sp,sp,imm */
459 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
460 {
461 offset = EXTRACT_IMM6 (op);
462 frame_size += -offset;
463 return 1;
464 }
465
466 /* st rn, @(sp,0) -- observed */
467 if (((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) ||
468 ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0))
469 {
470 n = EXTRACT_RA (op);
471 fsr->regs[n] = (-frame_size);
472 return 1;
473 }
474
475 /* st2w rn, @(sp,0) */
476 if (((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) ||
477 ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0))
478 {
479 n = EXTRACT_RA (op);
480 fsr->regs[n] = (-frame_size);
481 fsr->regs[n + 1] = (-frame_size) + 4;
482 return 1;
483 }
484
485 /* stw fp,@(sp,imm) -- observed */
486 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
487 {
488 offset = EXTRACT_IMM6 (op);
489 fsr->regs[FP_REGNUM] = (offset - frame_size);
490 return 1;
491 }
492 return 0;
493 }
494
495 /* Put here the code to store, into a struct frame_saved_regs, the
496 addresses of the saved registers of frame described by FRAME_INFO.
497 This includes special registers such as pc and fp saved in special
498 ways in the stack frame. sp is even more special: the address we
499 return for it IS the sp for the next frame. */
500 void
501 d30v_frame_find_saved_regs (struct frame_info *fi, struct frame_saved_regs *fsr)
502 {
503 CORE_ADDR fp, pc;
504 unsigned long opl, opr;
505 unsigned long op1, op2;
506 unsigned long fm0, fm1;
507 int i;
508
509 fp = fi->frame;
510 memset (fsr, 0, sizeof (*fsr));
511 next_addr = 0;
512 frame_size = 0;
513 end_of_stack = 0;
514
515 uses_frame = 0;
516
517 d30v_frame_find_saved_regs_offsets (fi, fsr);
518
519 fi->size = frame_size;
520
521 if (!fp)
522 fp = read_register (SP_REGNUM);
523
524 for (i = 0; i < NUM_REGS - 1; i++)
525 if (fsr->regs[i])
526 {
527 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
528 }
529
530 if (fsr->regs[LR_REGNUM])
531 fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4);
532 else
533 fi->return_pc = read_register (LR_REGNUM);
534
535 /* the SP is not normally (ever?) saved, but check anyway */
536 if (!fsr->regs[SP_REGNUM])
537 {
538 /* if the FP was saved, that means the current FP is valid, */
539 /* otherwise, it isn't being used, so we use the SP instead */
540 if (uses_frame)
541 fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size;
542 else
543 {
544 fsr->regs[SP_REGNUM] = fp + fi->size;
545 fi->frameless = 1;
546 fsr->regs[FP_REGNUM] = 0;
547 }
548 }
549 }
550
551 void
552 d30v_frame_find_saved_regs_offsets (struct frame_info *fi,
553 struct frame_saved_regs *fsr)
554 {
555 CORE_ADDR fp, pc;
556 unsigned long opl, opr;
557 unsigned long op1, op2;
558 unsigned long fm0, fm1;
559 int i;
560
561 fp = fi->frame;
562 memset (fsr, 0, sizeof (*fsr));
563 next_addr = 0;
564 frame_size = 0;
565 end_of_stack = 0;
566
567 pc = get_pc_function_start (fi->pc);
568
569 uses_frame = 0;
570 while (pc < fi->pc)
571 {
572 opl = (unsigned long) read_memory_integer (pc, 4);
573 opr = (unsigned long) read_memory_integer (pc + 4, 4);
574
575 fm0 = (opl & OP_MASK_FM_BIT);
576 fm1 = (opr & OP_MASK_FM_BIT);
577
578 opl = (opl & OP_MASK_SUB_INST);
579 opr = (opr & OP_MASK_SUB_INST);
580
581 if (fm0 && fm1)
582 {
583 /* long instruction */
584 if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
585 {
586 /* add sp,sp,n */
587 long offset = EXTRACT_IMM32 (opl, opr);
588 frame_size += -offset;
589 }
590 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
591 {
592 /* add r22,sp,offset */
593 long offset = EXTRACT_IMM32 (opl, opr);
594 next_addr = (offset - frame_size);
595 }
596 else if ((opl & OP_MASK_OP_AND_RB) == OP_STW_SP_IMM)
597 {
598 /* st Ra, @(sp,imm) */
599 long offset = EXTRACT_IMM32 (opl, opr);
600 short n = EXTRACT_RA (opl);
601 fsr->regs[n] = (offset - frame_size);
602 }
603 else if ((opl & OP_MASK_OP_AND_RB) == OP_ST2W_SP_IMM)
604 {
605 /* st2w Ra, @(sp,offset) */
606 long offset = EXTRACT_IMM32 (opl, opr);
607 short n = EXTRACT_RA (opl);
608 fsr->regs[n] = (offset - frame_size);
609 fsr->regs[n + 1] = (offset - frame_size) + 4;
610 }
611 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_OR_SP_R0_IMM)
612 {
613 end_of_stack = 1;
614 }
615 else
616 break;
617 }
618 else
619 {
620 /* short instructions */
621 if (fm0 && !fm1)
622 {
623 op2 = opl;
624 op1 = opr;
625 }
626 else
627 {
628 op1 = opl;
629 op2 = opr;
630 }
631 if (!prologue_find_regs (op1, fsr, pc) || !prologue_find_regs (op2, fsr, pc))
632 break;
633 }
634 pc += 8;
635 }
636
637 #if 0
638 fi->size = frame_size;
639
640 if (!fp)
641 fp = read_register (SP_REGNUM);
642
643 for (i = 0; i < NUM_REGS - 1; i++)
644 if (fsr->regs[i])
645 {
646 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
647 }
648
649 if (fsr->regs[LR_REGNUM])
650 fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4);
651 else
652 fi->return_pc = read_register (LR_REGNUM);
653
654 /* the SP is not normally (ever?) saved, but check anyway */
655 if (!fsr->regs[SP_REGNUM])
656 {
657 /* if the FP was saved, that means the current FP is valid, */
658 /* otherwise, it isn't being used, so we use the SP instead */
659 if (uses_frame)
660 fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size;
661 else
662 {
663 fsr->regs[SP_REGNUM] = fp + fi->size;
664 fi->frameless = 1;
665 fsr->regs[FP_REGNUM] = 0;
666 }
667 }
668 #endif
669 }
670
671 void
672 d30v_init_extra_frame_info (int fromleaf, struct frame_info *fi)
673 {
674 struct frame_saved_regs dummy;
675
676 if (fi->next && (fi->pc == 0))
677 fi->pc = fi->next->return_pc;
678
679 d30v_frame_find_saved_regs_offsets (fi, &dummy);
680
681 if (uses_frame == 0)
682 fi->frameless = 1;
683 else
684 fi->frameless = 0;
685
686 if ((fi->next == 0) && (uses_frame == 0))
687 /* innermost frame and it's "frameless",
688 so the fi->frame field is wrong, fix it! */
689 fi->frame = read_sp ();
690
691 if (dummy.regs[LR_REGNUM])
692 {
693 /* it was saved, grab it! */
694 dummy.regs[LR_REGNUM] += (fi->frame + frame_size);
695 fi->return_pc = read_memory_unsigned_integer (dummy.regs[LR_REGNUM], 4);
696 }
697 else
698 fi->return_pc = read_register (LR_REGNUM);
699 }
700
701 void
702 d30v_init_frame_pc (int fromleaf, struct frame_info *prev)
703 {
704 /* default value, put here so we can breakpoint on it and
705 see if the default value is really the right thing to use */
706 prev->pc = (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \
707 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
708 }
709
710 static void d30v_print_register (int regnum, int tabular);
711
712 static void
713 d30v_print_register (int regnum, int tabular)
714 {
715 if (regnum < A0_REGNUM)
716 {
717 if (tabular)
718 printf_filtered ("%08lx", (long) read_register (regnum));
719 else
720 printf_filtered ("0x%lx %ld",
721 (long) read_register (regnum),
722 (long) read_register (regnum));
723 }
724 else
725 {
726 char regbuf[MAX_REGISTER_RAW_SIZE];
727
728 read_relative_register_raw_bytes (regnum, regbuf);
729
730 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0,
731 gdb_stdout, 'x', 1, 0, Val_pretty_default);
732
733 if (!tabular)
734 {
735 printf_filtered (" ");
736 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0,
737 gdb_stdout, 'd', 1, 0, Val_pretty_default);
738 }
739 }
740 }
741
742 static void
743 d30v_print_flags (void)
744 {
745 long psw = read_register (PSW_REGNUM);
746 printf_filtered ("flags #1");
747 printf_filtered (" (sm) %d", (psw & PSW_SM) != 0);
748 printf_filtered (" (ea) %d", (psw & PSW_EA) != 0);
749 printf_filtered (" (db) %d", (psw & PSW_DB) != 0);
750 printf_filtered (" (ds) %d", (psw & PSW_DS) != 0);
751 printf_filtered (" (ie) %d", (psw & PSW_IE) != 0);
752 printf_filtered (" (rp) %d", (psw & PSW_RP) != 0);
753 printf_filtered (" (md) %d\n", (psw & PSW_MD) != 0);
754
755 printf_filtered ("flags #2");
756 printf_filtered (" (f0) %d", (psw & PSW_F0) != 0);
757 printf_filtered (" (f1) %d", (psw & PSW_F1) != 0);
758 printf_filtered (" (f2) %d", (psw & PSW_F2) != 0);
759 printf_filtered (" (f3) %d", (psw & PSW_F3) != 0);
760 printf_filtered (" (s) %d", (psw & PSW_S) != 0);
761 printf_filtered (" (v) %d", (psw & PSW_V) != 0);
762 printf_filtered (" (va) %d", (psw & PSW_VA) != 0);
763 printf_filtered (" (c) %d\n", (psw & PSW_C) != 0);
764 }
765
766 static void
767 print_flags_command (char *args, int from_tty)
768 {
769 d30v_print_flags ();
770 }
771
772 void
773 d30v_do_registers_info (int regnum, int fpregs)
774 {
775 long long num1, num2;
776 long psw;
777
778 if (regnum != -1)
779 {
780 if (REGISTER_NAME (0) == NULL || REGISTER_NAME (0)[0] == '\000')
781 return;
782
783 printf_filtered ("%s ", REGISTER_NAME (regnum));
784 d30v_print_register (regnum, 0);
785
786 printf_filtered ("\n");
787 return;
788 }
789
790 /* Have to print all the registers. Format them nicely. */
791
792 printf_filtered ("PC=");
793 print_address (read_pc (), gdb_stdout);
794
795 printf_filtered (" PSW=");
796 d30v_print_register (PSW_REGNUM, 1);
797
798 printf_filtered (" BPC=");
799 print_address (read_register (BPC_REGNUM), gdb_stdout);
800
801 printf_filtered (" BPSW=");
802 d30v_print_register (BPSW_REGNUM, 1);
803 printf_filtered ("\n");
804
805 printf_filtered ("DPC=");
806 print_address (read_register (DPC_REGNUM), gdb_stdout);
807
808 printf_filtered (" DPSW=");
809 d30v_print_register (DPSW_REGNUM, 1);
810
811 printf_filtered (" IBA=");
812 print_address (read_register (IBA_REGNUM), gdb_stdout);
813 printf_filtered ("\n");
814
815 printf_filtered ("RPT_C=");
816 d30v_print_register (RPT_C_REGNUM, 1);
817
818 printf_filtered (" RPT_S=");
819 print_address (read_register (RPT_S_REGNUM), gdb_stdout);
820
821 printf_filtered (" RPT_E=");
822 print_address (read_register (RPT_E_REGNUM), gdb_stdout);
823 printf_filtered ("\n");
824
825 printf_filtered ("MOD_S=");
826 print_address (read_register (MOD_S_REGNUM), gdb_stdout);
827
828 printf_filtered (" MOD_E=");
829 print_address (read_register (MOD_E_REGNUM), gdb_stdout);
830 printf_filtered ("\n");
831
832 printf_filtered ("EIT_VB=");
833 print_address (read_register (EIT_VB_REGNUM), gdb_stdout);
834
835 printf_filtered (" INT_S=");
836 d30v_print_register (INT_S_REGNUM, 1);
837
838 printf_filtered (" INT_M=");
839 d30v_print_register (INT_M_REGNUM, 1);
840 printf_filtered ("\n");
841
842 d30v_print_flags ();
843 for (regnum = 0; regnum <= 63;)
844 {
845 int i;
846
847 printf_filtered ("R%d-R%d ", regnum, regnum + 7);
848 if (regnum < 10)
849 printf_filtered (" ");
850 if (regnum + 7 < 10)
851 printf_filtered (" ");
852
853 for (i = 0; i < 8; i++)
854 {
855 printf_filtered (" ");
856 d30v_print_register (regnum++, 1);
857 }
858
859 printf_filtered ("\n");
860 }
861
862 printf_filtered ("A0-A1 ");
863
864 d30v_print_register (A0_REGNUM, 1);
865 printf_filtered (" ");
866 d30v_print_register (A1_REGNUM, 1);
867 printf_filtered ("\n");
868 }
869
870 CORE_ADDR
871 d30v_fix_call_dummy (char *dummyname, CORE_ADDR start_sp, CORE_ADDR fun,
872 int nargs, struct value **args,
873 struct type *type, int gcc_p)
874 {
875 int regnum;
876 CORE_ADDR sp;
877 char buffer[MAX_REGISTER_RAW_SIZE];
878 struct frame_info *frame = get_current_frame ();
879 frame->dummy = start_sp;
880 /*start_sp |= DMEM_START; */
881
882 sp = start_sp;
883 for (regnum = 0; regnum < NUM_REGS; regnum++)
884 {
885 sp -= REGISTER_RAW_SIZE (regnum);
886 store_address (buffer, REGISTER_RAW_SIZE (regnum), read_register (regnum));
887 write_memory (sp, buffer, REGISTER_RAW_SIZE (regnum));
888 }
889 write_register (SP_REGNUM, (LONGEST) sp);
890 /* now we need to load LR with the return address */
891 write_register (LR_REGNUM, (LONGEST) d30v_call_dummy_address ());
892 return sp;
893 }
894
895 static void
896 d30v_pop_dummy_frame (struct frame_info *fi)
897 {
898 CORE_ADDR sp = fi->dummy;
899 int regnum;
900
901 for (regnum = 0; regnum < NUM_REGS; regnum++)
902 {
903 sp -= REGISTER_RAW_SIZE (regnum);
904 write_register (regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE (regnum)));
905 }
906 flush_cached_frames (); /* needed? */
907 }
908
909
910 CORE_ADDR
911 d30v_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
912 int struct_return, CORE_ADDR struct_addr)
913 {
914 int i, len, index = 0, regnum = 2;
915 char buffer[4], *contents;
916 LONGEST val;
917 CORE_ADDR ptrs[10];
918
919 #if 0
920 /* Pass 1. Put all large args on stack */
921 for (i = 0; i < nargs; i++)
922 {
923 struct value *arg = args[i];
924 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
925 len = TYPE_LENGTH (arg_type);
926 contents = VALUE_CONTENTS (arg);
927 val = extract_signed_integer (contents, len);
928 if (len > 4)
929 {
930 /* put on stack and pass pointers */
931 sp -= len;
932 write_memory (sp, contents, len);
933 ptrs[index++] = sp;
934 }
935 }
936 #endif
937 index = 0;
938
939 for (i = 0; i < nargs; i++)
940 {
941 struct value *arg = args[i];
942 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
943 len = TYPE_LENGTH (arg_type);
944 contents = VALUE_CONTENTS (arg);
945 if (len > 4)
946 {
947 /* we need multiple registers */
948 int ndx;
949
950 for (ndx = 0; len > 0; ndx += 8, len -= 8)
951 {
952 if (regnum & 1)
953 regnum++; /* all args > 4 bytes start in even register */
954
955 if (regnum < 18)
956 {
957 val = extract_signed_integer (&contents[ndx], 4);
958 write_register (regnum++, val);
959
960 if (len >= 8)
961 val = extract_signed_integer (&contents[ndx + 4], 4);
962 else
963 val = extract_signed_integer (&contents[ndx + 4], len - 4);
964 write_register (regnum++, val);
965 }
966 else
967 {
968 /* no more registers available. put it on the stack */
969
970 /* all args > 4 bytes are padded to a multiple of 8 bytes
971 and start on an 8 byte boundary */
972 if (sp & 7)
973 sp -= (sp & 7); /* align it */
974
975 sp -= ((len + 7) & ~7); /* allocate space */
976 write_memory (sp, &contents[ndx], len);
977 break;
978 }
979 }
980 }
981 else
982 {
983 if (regnum < 18)
984 {
985 val = extract_signed_integer (contents, len);
986 write_register (regnum++, val);
987 }
988 else
989 {
990 /* all args are padded to a multiple of 4 bytes (at least) */
991 sp -= ((len + 3) & ~3);
992 write_memory (sp, contents, len);
993 }
994 }
995 }
996 if (sp & 7)
997 /* stack pointer is not on an 8 byte boundary -- align it */
998 sp -= (sp & 7);
999 return sp;
1000 }
1001
1002
1003 /* pick an out-of-the-way place to set the return value */
1004 /* for an inferior function call. The link register is set to this */
1005 /* value and a momentary breakpoint is set there. When the breakpoint */
1006 /* is hit, the dummy frame is popped and the previous environment is */
1007 /* restored. */
1008
1009 CORE_ADDR
1010 d30v_call_dummy_address (void)
1011 {
1012 CORE_ADDR entry;
1013 struct minimal_symbol *sym;
1014
1015 entry = entry_point_address ();
1016
1017 if (entry != 0)
1018 return entry;
1019
1020 sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile);
1021
1022 if (!sym || MSYMBOL_TYPE (sym) != mst_text)
1023 return 0;
1024 else
1025 return SYMBOL_VALUE_ADDRESS (sym);
1026 }
1027
1028 /* Given a return value in `regbuf' with a type `valtype',
1029 extract and copy its value into `valbuf'. */
1030
1031 void
1032 d30v_extract_return_value (struct type *valtype, char regbuf[REGISTER_BYTES],
1033 char *valbuf)
1034 {
1035 memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype));
1036 }
1037
1038 /* The following code implements access to, and display of, the D30V's
1039 instruction trace buffer. The buffer consists of 64K or more
1040 4-byte words of data, of which each words includes an 8-bit count,
1041 an 8-bit segment number, and a 16-bit instruction address.
1042
1043 In theory, the trace buffer is continuously capturing instruction
1044 data that the CPU presents on its "debug bus", but in practice, the
1045 ROMified GDB stub only enables tracing when it continues or steps
1046 the program, and stops tracing when the program stops; so it
1047 actually works for GDB to read the buffer counter out of memory and
1048 then read each trace word. The counter records where the tracing
1049 stops, but there is no record of where it started, so we remember
1050 the PC when we resumed and then search backwards in the trace
1051 buffer for a word that includes that address. This is not perfect,
1052 because you will miss trace data if the resumption PC is the target
1053 of a branch. (The value of the buffer counter is semi-random, any
1054 trace data from a previous program stop is gone.) */
1055
1056 /* The address of the last word recorded in the trace buffer. */
1057
1058 #define DBBC_ADDR (0xd80000)
1059
1060 /* The base of the trace buffer, at least for the "Board_0". */
1061
1062 #define TRACE_BUFFER_BASE (0xf40000)
1063
1064 static void trace_command (char *, int);
1065
1066 static void untrace_command (char *, int);
1067
1068 static void trace_info (char *, int);
1069
1070 static void tdisassemble_command (char *, int);
1071
1072 static void display_trace (int, int);
1073
1074 /* True when instruction traces are being collected. */
1075
1076 static int tracing;
1077
1078 /* Remembered PC. */
1079
1080 static CORE_ADDR last_pc;
1081
1082 /* True when trace output should be displayed whenever program stops. */
1083
1084 static int trace_display;
1085
1086 /* True when trace listing should include source lines. */
1087
1088 static int default_trace_show_source = 1;
1089
1090 struct trace_buffer
1091 {
1092 int size;
1093 short *counts;
1094 CORE_ADDR *addrs;
1095 }
1096 trace_data;
1097
1098 static void
1099 trace_command (char *args, int from_tty)
1100 {
1101 /* Clear the host-side trace buffer, allocating space if needed. */
1102 trace_data.size = 0;
1103 if (trace_data.counts == NULL)
1104 trace_data.counts = (short *) xmalloc (65536 * sizeof (short));
1105 if (trace_data.addrs == NULL)
1106 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR));
1107
1108 tracing = 1;
1109
1110 printf_filtered ("Tracing is now on.\n");
1111 }
1112
1113 static void
1114 untrace_command (char *args, int from_tty)
1115 {
1116 tracing = 0;
1117
1118 printf_filtered ("Tracing is now off.\n");
1119 }
1120
1121 static void
1122 trace_info (char *args, int from_tty)
1123 {
1124 int i;
1125
1126 if (trace_data.size)
1127 {
1128 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1129
1130 for (i = 0; i < trace_data.size; ++i)
1131 {
1132 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1133 i, trace_data.counts[i],
1134 (trace_data.counts[i] == 1 ? "" : "s"),
1135 paddr_nz (trace_data.addrs[i]));
1136 }
1137 }
1138 else
1139 printf_filtered ("No entries in trace buffer.\n");
1140
1141 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1142 }
1143
1144 /* Print the instruction at address MEMADDR in debugged memory,
1145 on STREAM. Returns length of the instruction, in bytes. */
1146
1147 static int
1148 print_insn (CORE_ADDR memaddr, struct ui_file *stream)
1149 {
1150 /* If there's no disassembler, something is very wrong. */
1151 if (tm_print_insn == NULL)
1152 internal_error (__FILE__, __LINE__,
1153 "print_insn: no disassembler");
1154
1155 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1156 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1157 else
1158 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1159 return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1160 }
1161
1162 void
1163 d30v_eva_prepare_to_trace (void)
1164 {
1165 if (!tracing)
1166 return;
1167
1168 last_pc = read_register (PC_REGNUM);
1169 }
1170
1171 /* Collect trace data from the target board and format it into a form
1172 more useful for display. */
1173
1174 void
1175 d30v_eva_get_trace_data (void)
1176 {
1177 int count, i, j, oldsize;
1178 int trace_addr, trace_seg, trace_cnt, next_cnt;
1179 unsigned int last_trace, trace_word, next_word;
1180 unsigned int *tmpspace;
1181
1182 if (!tracing)
1183 return;
1184
1185 tmpspace = xmalloc (65536 * sizeof (unsigned int));
1186
1187 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1188
1189 /* Collect buffer contents from the target, stopping when we reach
1190 the word recorded when execution resumed. */
1191
1192 count = 0;
1193 while (last_trace > 0)
1194 {
1195 QUIT;
1196 trace_word =
1197 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1198 trace_addr = trace_word & 0xffff;
1199 last_trace -= 4;
1200 /* Ignore an apparently nonsensical entry. */
1201 if (trace_addr == 0xffd5)
1202 continue;
1203 tmpspace[count++] = trace_word;
1204 if (trace_addr == last_pc)
1205 break;
1206 if (count > 65535)
1207 break;
1208 }
1209
1210 /* Move the data to the host-side trace buffer, adjusting counts to
1211 include the last instruction executed and transforming the address
1212 into something that GDB likes. */
1213
1214 for (i = 0; i < count; ++i)
1215 {
1216 trace_word = tmpspace[i];
1217 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1218 trace_addr = trace_word & 0xffff;
1219 next_cnt = (next_word >> 24) & 0xff;
1220 j = trace_data.size + count - i - 1;
1221 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1222 trace_data.counts[j] = next_cnt + 1;
1223 }
1224
1225 oldsize = trace_data.size;
1226 trace_data.size += count;
1227
1228 xfree (tmpspace);
1229
1230 if (trace_display)
1231 display_trace (oldsize, trace_data.size);
1232 }
1233
1234 static void
1235 tdisassemble_command (char *arg, int from_tty)
1236 {
1237 int i, count;
1238 CORE_ADDR low, high;
1239 char *space_index;
1240
1241 if (!arg)
1242 {
1243 low = 0;
1244 high = trace_data.size;
1245 }
1246 else if (!(space_index = (char *) strchr (arg, ' ')))
1247 {
1248 low = parse_and_eval_address (arg);
1249 high = low + 5;
1250 }
1251 else
1252 {
1253 /* Two arguments. */
1254 *space_index = '\0';
1255 low = parse_and_eval_address (arg);
1256 high = parse_and_eval_address (space_index + 1);
1257 if (high < low)
1258 high = low;
1259 }
1260
1261 printf_filtered ("Dump of trace from %s to %s:\n",
1262 paddr_u (low),
1263 paddr_u (high));
1264
1265 display_trace (low, high);
1266
1267 printf_filtered ("End of trace dump.\n");
1268 gdb_flush (gdb_stdout);
1269 }
1270
1271 static void
1272 display_trace (int low, int high)
1273 {
1274 int i, count, trace_show_source, first, suppress;
1275 CORE_ADDR next_address;
1276
1277 trace_show_source = default_trace_show_source;
1278 if (!have_full_symbols () && !have_partial_symbols ())
1279 {
1280 trace_show_source = 0;
1281 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1282 printf_filtered ("Trace will not display any source.\n");
1283 }
1284
1285 first = 1;
1286 suppress = 0;
1287 for (i = low; i < high; ++i)
1288 {
1289 next_address = trace_data.addrs[i];
1290 count = trace_data.counts[i];
1291 while (count-- > 0)
1292 {
1293 QUIT;
1294 if (trace_show_source)
1295 {
1296 struct symtab_and_line sal, sal_prev;
1297
1298 sal_prev = find_pc_line (next_address - 4, 0);
1299 sal = find_pc_line (next_address, 0);
1300
1301 if (sal.symtab)
1302 {
1303 if (first || sal.line != sal_prev.line)
1304 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1305 suppress = 0;
1306 }
1307 else
1308 {
1309 if (!suppress)
1310 /* FIXME-32x64--assumes sal.pc fits in long. */
1311 printf_filtered ("No source file for address %s.\n",
1312 local_hex_string ((unsigned long) sal.pc));
1313 suppress = 1;
1314 }
1315 }
1316 first = 0;
1317 print_address (next_address, gdb_stdout);
1318 printf_filtered (":");
1319 printf_filtered ("\t");
1320 wrap_here (" ");
1321 next_address = next_address + print_insn (next_address, gdb_stdout);
1322 printf_filtered ("\n");
1323 gdb_flush (gdb_stdout);
1324 }
1325 }
1326 }
1327
1328 extern void (*target_resume_hook) (void);
1329 extern void (*target_wait_loop_hook) (void);
1330
1331 void
1332 _initialize_d30v_tdep (void)
1333 {
1334 tm_print_insn = print_insn_d30v;
1335
1336 target_resume_hook = d30v_eva_prepare_to_trace;
1337 target_wait_loop_hook = d30v_eva_get_trace_data;
1338
1339 add_info ("flags", print_flags_command, "Print d30v flags.");
1340
1341 add_com ("trace", class_support, trace_command,
1342 "Enable tracing of instruction execution.");
1343
1344 add_com ("untrace", class_support, untrace_command,
1345 "Disable tracing of instruction execution.");
1346
1347 add_com ("tdisassemble", class_vars, tdisassemble_command,
1348 "Disassemble the trace buffer.\n\
1349 Two optional arguments specify a range of trace buffer entries\n\
1350 as reported by info trace (NOT addresses!).");
1351
1352 add_info ("trace", trace_info,
1353 "Display info about the trace data buffer.");
1354
1355 add_show_from_set (add_set_cmd ("tracedisplay", no_class,
1356 var_integer, (char *) &trace_display,
1357 "Set automatic display of trace.\n", &setlist),
1358 &showlist);
1359 add_show_from_set (add_set_cmd ("tracesource", no_class,
1360 var_integer, (char *) &default_trace_show_source,
1361 "Set display of source code with trace.\n", &setlist),
1362 &showlist);
1363
1364 }
GDB Binutils - Deliverables
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