1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
2 Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 #include "gdb_string.h"
25 #include "arch-utils.h"
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
32 #include "gdb_assert.h"
33 #include "sim-regno.h"
34 #include "gdb/sim-frv.h"
35 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
37 extern void _initialize_frv_tdep (void);
39 static gdbarch_init_ftype frv_gdbarch_init
;
41 static gdbarch_register_name_ftype frv_register_name
;
42 static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc
;
43 static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address
;
44 static gdbarch_skip_prologue_ftype frv_skip_prologue
;
46 /* Register numbers. The order in which these appear define the
47 remote protocol, so take care in changing them. */
49 /* Register numbers 0 -- 63 are always reserved for general-purpose
50 registers. The chip at hand may have less. */
54 struct_return_regnum
= 3,
57 /* Register numbers 64 -- 127 are always reserved for floating-point
58 registers. The chip at hand may have less. */
59 first_fpr_regnum
= 64,
60 last_fpr_regnum
= 127,
62 /* The PC register. */
65 /* Register numbers 129 on up are always reserved for special-purpose
67 first_spr_regnum
= 129,
81 last_spr_regnum
= 148,
83 /* The total number of registers we know exist. */
84 frv_num_regs
= last_spr_regnum
+ 1,
86 /* Pseudo registers */
87 first_pseudo_regnum
= frv_num_regs
,
89 /* iacc0 - the 64-bit concatenation of iacc0h and iacc0l. */
90 iacc0_regnum
= first_pseudo_regnum
+ 0,
92 last_pseudo_regnum
= iacc0_regnum
,
93 frv_num_pseudo_regs
= last_pseudo_regnum
- first_pseudo_regnum
+ 1,
96 static LONGEST frv_call_dummy_words
[] =
100 struct frv_unwind_cache
/* was struct frame_extra_info */
102 /* The previous frame's inner-most stack address. Used as this
103 frame ID's stack_addr. */
106 /* The frame's base, optionally used by the high-level debug info. */
109 /* Table indicating the location of each and every register. */
110 struct trad_frame_saved_reg
*saved_regs
;
114 /* A structure describing a particular variant of the FRV.
115 We allocate and initialize one of these structures when we create
116 the gdbarch object for a variant.
118 At the moment, all the FR variants we support differ only in which
119 registers are present; the portable code of GDB knows that
120 registers whose names are the empty string don't exist, so the
121 `register_names' array captures all the per-variant information we
124 in the future, if we need to have per-variant maps for raw size,
125 virtual type, etc., we should replace register_names with an array
126 of structures, each of which gives all the necessary info for one
127 register. Don't stick parallel arrays in here --- that's so
131 /* How many general-purpose registers does this variant have? */
134 /* How many floating-point registers does this variant have? */
137 /* How many hardware watchpoints can it support? */
138 int num_hw_watchpoints
;
140 /* How many hardware breakpoints can it support? */
141 int num_hw_breakpoints
;
143 /* Register names. */
144 char **register_names
;
147 #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch))
150 /* Allocate a new variant structure, and set up default values for all
152 static struct gdbarch_tdep
*
155 struct gdbarch_tdep
*var
;
159 var
= xmalloc (sizeof (*var
));
160 memset (var
, 0, sizeof (*var
));
164 var
->num_hw_watchpoints
= 0;
165 var
->num_hw_breakpoints
= 0;
167 /* By default, don't supply any general-purpose or floating-point
170 = (char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
172 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
173 var
->register_names
[r
] = "";
175 /* Do, however, supply default names for the known special-purpose
178 var
->register_names
[pc_regnum
] = "pc";
179 var
->register_names
[lr_regnum
] = "lr";
180 var
->register_names
[lcr_regnum
] = "lcr";
182 var
->register_names
[psr_regnum
] = "psr";
183 var
->register_names
[ccr_regnum
] = "ccr";
184 var
->register_names
[cccr_regnum
] = "cccr";
185 var
->register_names
[tbr_regnum
] = "tbr";
187 /* Debug registers. */
188 var
->register_names
[brr_regnum
] = "brr";
189 var
->register_names
[dbar0_regnum
] = "dbar0";
190 var
->register_names
[dbar1_regnum
] = "dbar1";
191 var
->register_names
[dbar2_regnum
] = "dbar2";
192 var
->register_names
[dbar3_regnum
] = "dbar3";
194 /* iacc0 (Only found on MB93405.) */
195 var
->register_names
[iacc0h_regnum
] = "iacc0h";
196 var
->register_names
[iacc0l_regnum
] = "iacc0l";
197 var
->register_names
[iacc0_regnum
] = "iacc0";
203 /* Indicate that the variant VAR has NUM_GPRS general-purpose
204 registers, and fill in the names array appropriately. */
206 set_variant_num_gprs (struct gdbarch_tdep
*var
, int num_gprs
)
210 var
->num_gprs
= num_gprs
;
212 for (r
= 0; r
< num_gprs
; ++r
)
216 sprintf (buf
, "gr%d", r
);
217 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
222 /* Indicate that the variant VAR has NUM_FPRS floating-point
223 registers, and fill in the names array appropriately. */
225 set_variant_num_fprs (struct gdbarch_tdep
*var
, int num_fprs
)
229 var
->num_fprs
= num_fprs
;
231 for (r
= 0; r
< num_fprs
; ++r
)
235 sprintf (buf
, "fr%d", r
);
236 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
242 frv_register_name (int reg
)
246 if (reg
>= frv_num_regs
+ frv_num_pseudo_regs
)
249 return CURRENT_VARIANT
->register_names
[reg
];
254 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
256 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
257 return builtin_type_float
;
258 else if (reg
== iacc0_regnum
)
259 return builtin_type_int64
;
261 return builtin_type_int32
;
265 frv_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
266 int reg
, void *buffer
)
268 if (reg
== iacc0_regnum
)
270 regcache_raw_read (regcache
, iacc0h_regnum
, buffer
);
271 regcache_raw_read (regcache
, iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
276 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
277 int reg
, const void *buffer
)
279 if (reg
== iacc0_regnum
)
281 regcache_raw_write (regcache
, iacc0h_regnum
, buffer
);
282 regcache_raw_write (regcache
, iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
287 frv_register_sim_regno (int reg
)
289 static const int spr_map
[] =
291 H_SPR_PSR
, /* psr_regnum */
292 H_SPR_CCR
, /* ccr_regnum */
293 H_SPR_CCCR
, /* cccr_regnum */
297 H_SPR_TBR
, /* tbr_regnum */
298 H_SPR_BRR
, /* brr_regnum */
299 H_SPR_DBAR0
, /* dbar0_regnum */
300 H_SPR_DBAR1
, /* dbar1_regnum */
301 H_SPR_DBAR2
, /* dbar2_regnum */
302 H_SPR_DBAR3
, /* dbar3_regnum */
307 H_SPR_LR
, /* lr_regnum */
308 H_SPR_LCR
, /* lcr_regnum */
309 H_SPR_IACC0H
, /* iacc0h_regnum */
310 H_SPR_IACC0L
/* iacc0l_regnum */
313 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
315 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
316 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
317 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
318 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
319 else if (pc_regnum
== reg
)
320 return SIM_FRV_PC_REGNUM
;
321 else if (reg
>= first_spr_regnum
322 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
324 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
326 if (spr_reg_offset
< 0)
327 return SIM_REGNO_DOES_NOT_EXIST
;
329 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
332 internal_error (__FILE__
, __LINE__
, "Bad register number %d", reg
);
335 static const unsigned char *
336 frv_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenp
)
338 static unsigned char breakpoint
[] = {0xc0, 0x70, 0x00, 0x01};
339 *lenp
= sizeof (breakpoint
);
343 /* Define the maximum number of instructions which may be packed into a
344 bundle (VLIW instruction). */
345 static const int max_instrs_per_bundle
= 8;
347 /* Define the size (in bytes) of an FR-V instruction. */
348 static const int frv_instr_size
= 4;
350 /* Adjust a breakpoint's address to account for the FR-V architecture's
351 constraint that a break instruction must not appear as any but the
352 first instruction in the bundle. */
354 frv_gdbarch_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
356 int count
= max_instrs_per_bundle
;
357 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
358 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
360 /* Find the end of the previous packing sequence. This will be indicated
361 by either attempting to access some inaccessible memory or by finding
362 an instruction word whose packing bit is set to one. */
363 while (count
-- > 0 && addr
>= func_start
)
365 char instr
[frv_instr_size
];
368 status
= read_memory_nobpt (addr
, instr
, sizeof instr
);
373 /* This is a big endian architecture, so byte zero will have most
374 significant byte. The most significant bit of this byte is the
379 addr
-= frv_instr_size
;
383 bpaddr
= addr
+ frv_instr_size
;
389 /* Return true if REG is a caller-saves ("scratch") register,
392 is_caller_saves_reg (int reg
)
394 return ((4 <= reg
&& reg
<= 7)
395 || (14 <= reg
&& reg
<= 15)
396 || (32 <= reg
&& reg
<= 47));
400 /* Return true if REG is a callee-saves register, false otherwise. */
402 is_callee_saves_reg (int reg
)
404 return ((16 <= reg
&& reg
<= 31)
405 || (48 <= reg
&& reg
<= 63));
409 /* Return true if REG is an argument register, false otherwise. */
411 is_argument_reg (int reg
)
413 return (8 <= reg
&& reg
<= 13);
416 /* Given PC at the function's start address, attempt to find the
417 prologue end using SAL information. Return zero if the skip fails.
419 A non-optimized prologue traditionally has one SAL for the function
420 and a second for the function body. A single line function has
421 them both pointing at the same line.
423 An optimized prologue is similar but the prologue may contain
424 instructions (SALs) from the instruction body. Need to skip those
425 while not getting into the function body.
427 The functions end point and an increasing SAL line are used as
428 indicators of the prologue's endpoint.
430 This code is based on the function refine_prologue_limit (versions
431 found in both ia64 and ppc). */
434 skip_prologue_using_sal (CORE_ADDR func_addr
)
436 struct symtab_and_line prologue_sal
;
440 /* Get an initial range for the function. */
441 find_pc_partial_function (func_addr
, NULL
, &start_pc
, &end_pc
);
442 start_pc
+= FUNCTION_START_OFFSET
;
444 prologue_sal
= find_pc_line (start_pc
, 0);
445 if (prologue_sal
.line
!= 0)
447 while (prologue_sal
.end
< end_pc
)
449 struct symtab_and_line sal
;
451 sal
= find_pc_line (prologue_sal
.end
, 0);
454 /* Assume that a consecutive SAL for the same (or larger)
455 line mark the prologue -> body transition. */
456 if (sal
.line
>= prologue_sal
.line
)
458 /* The case in which compiler's optimizer/scheduler has
459 moved instructions into the prologue. We look ahead in
460 the function looking for address ranges whose
461 corresponding line number is less the first one that we
462 found for the function. This is more conservative then
463 refine_prologue_limit which scans a large number of SALs
464 looking for any in the prologue */
468 return prologue_sal
.end
;
472 /* Scan an FR-V prologue, starting at PC, until frame->PC.
473 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
474 We assume FRAME's saved_regs array has already been allocated and cleared.
475 Return the first PC value after the prologue.
477 Note that, for unoptimized code, we almost don't need this function
478 at all; all arguments and locals live on the stack, so we just need
479 the FP to find everything. The catch: structures passed by value
480 have their addresses living in registers; they're never spilled to
481 the stack. So if you ever want to be able to get to these
482 arguments in any frame but the top, you'll need to do this serious
483 prologue analysis. */
485 frv_analyze_prologue (CORE_ADDR pc
, struct frame_info
*next_frame
,
486 struct frv_unwind_cache
*info
)
488 /* When writing out instruction bitpatterns, we use the following
489 letters to label instruction fields:
490 P - The parallel bit. We don't use this.
491 J - The register number of GRj in the instruction description.
492 K - The register number of GRk in the instruction description.
493 I - The register number of GRi.
494 S - a signed imediate offset.
495 U - an unsigned immediate offset.
497 The dots below the numbers indicate where hex digit boundaries
498 fall, to make it easier to check the numbers. */
500 /* Non-zero iff we've seen the instruction that initializes the
501 frame pointer for this function's frame. */
504 /* If fp_set is non_zero, then this is the distance from
505 the stack pointer to frame pointer: fp = sp + fp_offset. */
508 /* Total size of frame prior to any alloca operations. */
511 /* Flag indicating if lr has been saved on the stack. */
512 int lr_saved_on_stack
= 0;
514 /* The number of the general-purpose register we saved the return
515 address ("link register") in, or -1 if we haven't moved it yet. */
516 int lr_save_reg
= -1;
518 /* Offset (from sp) at which lr has been saved on the stack. */
520 int lr_sp_offset
= 0;
522 /* If gr_saved[i] is non-zero, then we've noticed that general
523 register i has been saved at gr_sp_offset[i] from the stack
526 int gr_sp_offset
[64];
528 /* The address of the most recently scanned prologue instruction. */
529 CORE_ADDR last_prologue_pc
;
531 /* The address of the next instruction. */
534 /* The upper bound to of the pc values to scan. */
537 memset (gr_saved
, 0, sizeof (gr_saved
));
539 last_prologue_pc
= pc
;
541 /* Try to compute an upper limit (on how far to scan) based on the
543 lim_pc
= skip_prologue_using_sal (pc
);
544 /* If there's no line number info, lim_pc will be 0. In that case,
545 set the limit to be 100 instructions away from pc. Hopefully, this
546 will be far enough away to account for the entire prologue. Don't
547 worry about overshooting the end of the function. The scan loop
548 below contains some checks to avoid scanning unreasonably far. */
552 /* If we have a frame, we don't want to scan past the frame's pc. This
553 will catch those cases where the pc is in the prologue. */
556 CORE_ADDR frame_pc
= frame_pc_unwind (next_frame
);
557 if (frame_pc
< lim_pc
)
561 /* Scan the prologue. */
564 LONGEST op
= read_memory_integer (pc
, 4);
567 /* The tests in this chain of ifs should be in order of
568 decreasing selectivity, so that more particular patterns get
569 to fire before less particular patterns. */
571 /* Some sort of control transfer instruction: stop scanning prologue.
572 Integer Conditional Branch:
573 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
574 Floating-point / media Conditional Branch:
575 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
576 LCR Conditional Branch to LR
577 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
578 Integer conditional Branches to LR
579 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
580 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
581 Floating-point/Media Branches to LR
582 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
583 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
585 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
586 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
588 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
590 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
591 Integer Conditional Trap
592 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
593 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
594 Floating-point /media Conditional Trap
595 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
596 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
598 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
600 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
601 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
602 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
603 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
604 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
606 /* Stop scanning; not in prologue any longer. */
610 /* Loading something from memory into fp probably means that
611 we're in the epilogue. Stop scanning the prologue.
613 X 000010 0000010 XXXXXX 000100 XXXXXX
615 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
616 else if ((op
& 0x7ffc0fc0) == 0x04080100
617 || (op
& 0x7ffc0000) == 0x04c80000)
622 /* Setting the FP from the SP:
624 P 000010 0100010 000001 000000000000 = 0x04881000
625 0 111111 1111111 111111 111111111111 = 0x7fffffff
627 We treat this as part of the prologue. */
628 else if ((op
& 0x7fffffff) == 0x04881000)
632 last_prologue_pc
= next_pc
;
635 /* Move the link register to the scratch register grJ, before saving:
637 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
638 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
640 We treat this as part of the prologue. */
641 else if ((op
& 0x7fffffc0) == 0x080d01c0)
643 int gr_j
= op
& 0x3f;
645 /* If we're moving it to a scratch register, that's fine. */
646 if (is_caller_saves_reg (gr_j
))
649 last_prologue_pc
= next_pc
;
653 /* To save multiple callee-saves registers on the stack, at
657 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
658 0 000000 1111111 111111 111111 111111 = 0x01ffffff
661 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
662 0 000000 1111111 111111 111111 111111 = 0x01ffffff
664 We treat this as part of the prologue, and record the register's
665 saved address in the frame structure. */
666 else if ((op
& 0x01ffffff) == 0x000c10c0
667 || (op
& 0x01ffffff) == 0x000c1100)
669 int gr_k
= ((op
>> 25) & 0x3f);
670 int ope
= ((op
>> 6) & 0x3f);
674 /* Is it an std or an stq? */
680 /* Is it really a callee-saves register? */
681 if (is_callee_saves_reg (gr_k
))
683 for (i
= 0; i
< count
; i
++)
685 gr_saved
[gr_k
+ i
] = 1;
686 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
688 last_prologue_pc
= next_pc
;
692 /* Adjusting the stack pointer. (The stack pointer is GR1.)
694 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
695 0 111111 1111111 111111 000000000000 = 0x7ffff000
697 We treat this as part of the prologue. */
698 else if ((op
& 0x7ffff000) == 0x02401000)
702 /* Sign-extend the twelve-bit field.
703 (Isn't there a better way to do this?) */
704 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
707 last_prologue_pc
= pc
;
711 /* If the prologue is being adjusted again, we've
712 likely gone too far; i.e. we're probably in the
718 /* Setting the FP to a constant distance from the SP:
720 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
721 0 111111 1111111 111111 000000000000 = 0x7ffff000
723 We treat this as part of the prologue. */
724 else if ((op
& 0x7ffff000) == 0x04401000)
726 /* Sign-extend the twelve-bit field.
727 (Isn't there a better way to do this?) */
728 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
731 last_prologue_pc
= pc
;
734 /* To spill an argument register to a scratch register:
736 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
737 0 000000 1111111 000000 111111111111 = 0x01fc0fff
739 For the time being, we treat this as a prologue instruction,
740 assuming that GRi is an argument register. This one's kind
741 of suspicious, because it seems like it could be part of a
742 legitimate body instruction. But we only come here when the
743 source info wasn't helpful, so we have to do the best we can.
744 Hopefully once GCC and GDB agree on how to emit line number
745 info for prologues, then this code will never come into play. */
746 else if ((op
& 0x01fc0fff) == 0x00880000)
748 int gr_i
= ((op
>> 12) & 0x3f);
750 /* Make sure that the source is an arg register; if it is, we'll
751 treat it as a prologue instruction. */
752 if (is_argument_reg (gr_i
))
753 last_prologue_pc
= next_pc
;
756 /* To spill 16-bit values to the stack:
758 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
759 0 000000 1111111 111111 000000000000 = 0x01fff000
761 And for 8-bit values, we use STB instructions.
763 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
764 0 000000 1111111 111111 000000000000 = 0x01fff000
766 We check that GRk is really an argument register, and treat
767 all such as part of the prologue. */
768 else if ( (op
& 0x01fff000) == 0x01442000
769 || (op
& 0x01fff000) == 0x01402000)
771 int gr_k
= ((op
>> 25) & 0x3f);
773 /* Make sure that GRk is really an argument register; treat
774 it as a prologue instruction if so. */
775 if (is_argument_reg (gr_k
))
776 last_prologue_pc
= next_pc
;
779 /* To save multiple callee-saves register on the stack, at a
783 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
784 0 000000 1111111 111111 000000000000 = 0x01fff000
787 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
788 0 000000 1111111 111111 000000000000 = 0x01fff000
790 We treat this as part of the prologue, and record the register's
791 saved address in the frame structure. */
792 else if ((op
& 0x01fff000) == 0x014c1000
793 || (op
& 0x01fff000) == 0x01501000)
795 int gr_k
= ((op
>> 25) & 0x3f);
799 /* Is it a stdi or a stqi? */
800 if ((op
& 0x01fff000) == 0x014c1000)
805 /* Is it really a callee-saves register? */
806 if (is_callee_saves_reg (gr_k
))
808 /* Sign-extend the twelve-bit field.
809 (Isn't there a better way to do this?) */
810 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
812 for (i
= 0; i
< count
; i
++)
814 gr_saved
[gr_k
+ i
] = 1;
815 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
817 last_prologue_pc
= next_pc
;
821 /* Storing any kind of integer register at any constant offset
822 from any other register.
825 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
826 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
829 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
830 0 000000 1111111 000000 000000000000 = 0x01fc0000
832 These could be almost anything, but a lot of prologue
833 instructions fall into this pattern, so let's decode the
834 instruction once, and then work at a higher level. */
835 else if (((op
& 0x01fc0fff) == 0x000c0080)
836 || ((op
& 0x01fc0000) == 0x01480000))
838 int gr_k
= ((op
>> 25) & 0x3f);
839 int gr_i
= ((op
>> 12) & 0x3f);
842 /* Are we storing with gr0 as an offset, or using an
844 if ((op
& 0x01fc0fff) == 0x000c0080)
847 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
849 /* If the address isn't relative to the SP or FP, it's not a
850 prologue instruction. */
851 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
853 /* Do nothing; not a prologue instruction. */
856 /* Saving the old FP in the new frame (relative to the SP). */
857 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
859 gr_saved
[fp_regnum
] = 1;
860 gr_sp_offset
[fp_regnum
] = offset
;
861 last_prologue_pc
= next_pc
;
864 /* Saving callee-saves register(s) on the stack, relative to
866 else if (gr_i
== sp_regnum
867 && is_callee_saves_reg (gr_k
))
870 if (gr_i
== sp_regnum
)
871 gr_sp_offset
[gr_k
] = offset
;
873 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
874 last_prologue_pc
= next_pc
;
877 /* Saving the scratch register holding the return address. */
878 else if (lr_save_reg
!= -1
879 && gr_k
== lr_save_reg
)
881 lr_saved_on_stack
= 1;
882 if (gr_i
== sp_regnum
)
883 lr_sp_offset
= offset
;
885 lr_sp_offset
= offset
+ fp_offset
;
886 last_prologue_pc
= next_pc
;
889 /* Spilling int-sized arguments to the stack. */
890 else if (is_argument_reg (gr_k
))
891 last_prologue_pc
= next_pc
;
896 if (next_frame
&& info
)
901 /* If we know the relationship between the stack and frame
902 pointers, record the addresses of the registers we noticed.
903 Note that we have to do this as a separate step at the end,
904 because instructions may save relative to the SP, but we need
905 their addresses relative to the FP. */
907 frame_unwind_unsigned_register (next_frame
, fp_regnum
, &this_base
);
909 frame_unwind_unsigned_register (next_frame
, sp_regnum
, &this_base
);
911 for (i
= 0; i
< 64; i
++)
913 info
->saved_regs
[i
].addr
= this_base
- fp_offset
+ gr_sp_offset
[i
];
915 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
916 info
->base
= this_base
;
918 /* If LR was saved on the stack, record its location. */
919 if (lr_saved_on_stack
)
920 info
->saved_regs
[lr_regnum
].addr
= this_base
- fp_offset
+ lr_sp_offset
;
922 /* The call instruction moves the caller's PC in the callee's LR.
923 Since this is an unwind, do the reverse. Copy the location of LR
924 into PC (the address / regnum) so that a request for PC will be
925 converted into a request for the LR. */
926 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
928 /* Save the previous frame's computed SP value. */
929 trad_frame_set_value (info
->saved_regs
, sp_regnum
, info
->prev_sp
);
932 return last_prologue_pc
;
937 frv_skip_prologue (CORE_ADDR pc
)
939 CORE_ADDR func_addr
, func_end
, new_pc
;
943 /* If the line table has entry for a line *within* the function
944 (i.e., not in the prologue, and not past the end), then that's
946 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
948 struct symtab_and_line sal
;
950 sal
= find_pc_line (func_addr
, 0);
952 if (sal
.line
!= 0 && sal
.end
< func_end
)
958 /* The FR-V prologue is at least five instructions long (twenty bytes).
959 If we didn't find a real source location past that, then
960 do a full analysis of the prologue. */
961 if (new_pc
< pc
+ 20)
962 new_pc
= frv_analyze_prologue (pc
, 0, 0);
968 static struct frv_unwind_cache
*
969 frv_frame_unwind_cache (struct frame_info
*next_frame
,
970 void **this_prologue_cache
)
972 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
976 struct frv_unwind_cache
*info
;
978 if ((*this_prologue_cache
))
979 return (*this_prologue_cache
);
981 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
982 (*this_prologue_cache
) = info
;
983 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
985 /* Prologue analysis does the rest... */
986 frv_analyze_prologue (frame_func_unwind (next_frame
), next_frame
, info
);
992 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
995 int len
= TYPE_LENGTH (type
);
1000 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
1001 store_unsigned_integer (valbuf
, len
, gpr8_val
);
1006 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
1007 store_unsigned_integer (valbuf
, 4, regval
);
1008 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
1009 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, regval
);
1012 internal_error (__FILE__
, __LINE__
, "Illegal return value length: %d", len
);
1016 frv_extract_struct_value_address (struct regcache
*regcache
)
1019 regcache_cooked_read_unsigned (regcache
, struct_return_regnum
, &addr
);
1024 frv_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
1026 write_register (struct_return_regnum
, addr
);
1030 frv_frameless_function_invocation (struct frame_info
*frame
)
1032 return legacy_frameless_look_for_prologue (frame
);
1036 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1038 /* Require dword alignment. */
1039 return align_down (sp
, 8);
1043 frv_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1044 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1045 int nargs
, struct value
**args
, CORE_ADDR sp
,
1046 int struct_return
, CORE_ADDR struct_addr
)
1053 struct type
*arg_type
;
1055 enum type_code typecode
;
1061 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1062 nargs
, (int) sp
, struct_return
, struct_addr
);
1066 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1067 stack_space
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), 4);
1069 stack_space
-= (6 * 4);
1070 if (stack_space
> 0)
1073 /* Make sure stack is dword aligned. */
1074 sp
= align_down (sp
, 8);
1081 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1084 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1087 arg_type
= check_typedef (VALUE_TYPE (arg
));
1088 len
= TYPE_LENGTH (arg_type
);
1089 typecode
= TYPE_CODE (arg_type
);
1091 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1093 store_unsigned_integer (valbuf
, 4, VALUE_ADDRESS (arg
));
1094 typecode
= TYPE_CODE_PTR
;
1100 val
= (char *) VALUE_CONTENTS (arg
);
1105 int partial_len
= (len
< 4 ? len
: 4);
1109 regval
= extract_unsigned_integer (val
, partial_len
);
1111 printf(" Argnum %d data %x -> reg %d\n",
1112 argnum
, (int) regval
, argreg
);
1114 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1120 printf(" Argnum %d data %x -> offset %d (%x)\n",
1121 argnum
, *((int *)val
), stack_offset
, (int) (sp
+ stack_offset
));
1123 write_memory (sp
+ stack_offset
, val
, partial_len
);
1124 stack_offset
+= align_up (partial_len
, 4);
1131 /* Set the return address. For the frv, the return breakpoint is
1132 always at BP_ADDR. */
1133 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1135 /* Finally, update the SP register. */
1136 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1142 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1145 int len
= TYPE_LENGTH (type
);
1150 memset (val
, 0, sizeof (val
));
1151 memcpy (val
+ (4 - len
), valbuf
, len
);
1152 regcache_cooked_write (regcache
, 8, val
);
1156 regcache_cooked_write (regcache
, 8, valbuf
);
1157 regcache_cooked_write (regcache
, 9, (bfd_byte
*) valbuf
+ 4);
1160 internal_error (__FILE__
, __LINE__
,
1161 "Don't know how to return a %d-byte value.", len
);
1165 /* Hardware watchpoint / breakpoint support for the FR500
1169 frv_check_watch_resources (int type
, int cnt
, int ot
)
1171 struct gdbarch_tdep
*var
= CURRENT_VARIANT
;
1173 /* Watchpoints not supported on simulator. */
1174 if (strcmp (target_shortname
, "sim") == 0)
1177 if (type
== bp_hardware_breakpoint
)
1179 if (var
->num_hw_breakpoints
== 0)
1181 else if (cnt
<= var
->num_hw_breakpoints
)
1186 if (var
->num_hw_watchpoints
== 0)
1190 else if (cnt
<= var
->num_hw_watchpoints
)
1198 frv_stopped_data_address (void)
1200 CORE_ADDR brr
, dbar0
, dbar1
, dbar2
, dbar3
;
1202 brr
= read_register (brr_regnum
);
1203 dbar0
= read_register (dbar0_regnum
);
1204 dbar1
= read_register (dbar1_regnum
);
1205 dbar2
= read_register (dbar2_regnum
);
1206 dbar3
= read_register (dbar3_regnum
);
1210 else if (brr
& (1<<10))
1212 else if (brr
& (1<<9))
1214 else if (brr
& (1<<8))
1221 frv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1223 return frame_unwind_register_unsigned (next_frame
, pc_regnum
);
1226 /* Given a GDB frame, determine the address of the calling function's
1227 frame. This will be used to create a new GDB frame struct. */
1230 frv_frame_this_id (struct frame_info
*next_frame
,
1231 void **this_prologue_cache
, struct frame_id
*this_id
)
1233 struct frv_unwind_cache
*info
1234 = frv_frame_unwind_cache (next_frame
, this_prologue_cache
);
1237 struct minimal_symbol
*msym_stack
;
1240 /* The FUNC is easy. */
1241 func
= frame_func_unwind (next_frame
);
1243 /* Check if the stack is empty. */
1244 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1245 if (msym_stack
&& info
->base
== SYMBOL_VALUE_ADDRESS (msym_stack
))
1248 /* Hopefully the prologue analysis either correctly determined the
1249 frame's base (which is the SP from the previous frame), or set
1250 that base to "NULL". */
1251 base
= info
->prev_sp
;
1255 id
= frame_id_build (base
, func
);
1257 /* Check that we're not going round in circles with the same frame
1258 ID (but avoid applying the test to sentinel frames which do go
1259 round in circles). Can't use frame_id_eq() as that doesn't yet
1260 compare the frame's PC value. */
1261 if (frame_relative_level (next_frame
) >= 0
1262 && get_frame_type (next_frame
) != DUMMY_FRAME
1263 && frame_id_eq (get_frame_id (next_frame
), id
))
1270 frv_frame_prev_register (struct frame_info
*next_frame
,
1271 void **this_prologue_cache
,
1272 int regnum
, int *optimizedp
,
1273 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1274 int *realnump
, void *bufferp
)
1276 struct frv_unwind_cache
*info
1277 = frv_frame_unwind_cache (next_frame
, this_prologue_cache
);
1278 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
1279 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
1282 static const struct frame_unwind frv_frame_unwind
= {
1285 frv_frame_prev_register
1288 static const struct frame_unwind
*
1289 frv_frame_sniffer (struct frame_info
*next_frame
)
1291 return &frv_frame_unwind
;
1295 frv_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1297 struct frv_unwind_cache
*info
1298 = frv_frame_unwind_cache (next_frame
, this_cache
);
1302 static const struct frame_base frv_frame_base
= {
1304 frv_frame_base_address
,
1305 frv_frame_base_address
,
1306 frv_frame_base_address
1310 frv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1312 return frame_unwind_register_unsigned (next_frame
, sp_regnum
);
1316 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1317 dummy frame. The frame ID's base needs to match the TOS value
1318 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1321 static struct frame_id
1322 frv_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1324 return frame_id_build (frv_unwind_sp (gdbarch
, next_frame
),
1325 frame_pc_unwind (next_frame
));
1329 static struct gdbarch
*
1330 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1332 struct gdbarch
*gdbarch
;
1333 struct gdbarch_tdep
*var
;
1335 /* Check to see if we've already built an appropriate architecture
1336 object for this executable. */
1337 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1339 return arches
->gdbarch
;
1341 /* Select the right tdep structure for this variant. */
1342 var
= new_variant ();
1343 switch (info
.bfd_arch_info
->mach
)
1346 case bfd_mach_frvsimple
:
1347 case bfd_mach_fr500
:
1348 case bfd_mach_frvtomcat
:
1349 case bfd_mach_fr550
:
1350 set_variant_num_gprs (var
, 64);
1351 set_variant_num_fprs (var
, 64);
1354 case bfd_mach_fr400
:
1355 set_variant_num_gprs (var
, 32);
1356 set_variant_num_fprs (var
, 32);
1360 /* Never heard of this variant. */
1364 gdbarch
= gdbarch_alloc (&info
, var
);
1366 set_gdbarch_short_bit (gdbarch
, 16);
1367 set_gdbarch_int_bit (gdbarch
, 32);
1368 set_gdbarch_long_bit (gdbarch
, 32);
1369 set_gdbarch_long_long_bit (gdbarch
, 64);
1370 set_gdbarch_float_bit (gdbarch
, 32);
1371 set_gdbarch_double_bit (gdbarch
, 64);
1372 set_gdbarch_long_double_bit (gdbarch
, 64);
1373 set_gdbarch_ptr_bit (gdbarch
, 32);
1375 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1376 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1378 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1379 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1380 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1382 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1383 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1384 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1386 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1387 set_gdbarch_pseudo_register_write (gdbarch
, frv_pseudo_register_write
);
1389 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1390 set_gdbarch_breakpoint_from_pc (gdbarch
, frv_breakpoint_from_pc
);
1391 set_gdbarch_adjust_breakpoint_address (gdbarch
, frv_gdbarch_adjust_breakpoint_address
);
1393 set_gdbarch_deprecated_frameless_function_invocation (gdbarch
, frv_frameless_function_invocation
);
1395 set_gdbarch_use_struct_convention (gdbarch
, always_use_struct_convention
);
1396 set_gdbarch_extract_return_value (gdbarch
, frv_extract_return_value
);
1398 set_gdbarch_deprecated_store_struct_return (gdbarch
, frv_store_struct_return
);
1399 set_gdbarch_store_return_value (gdbarch
, frv_store_return_value
);
1400 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, frv_extract_struct_value_address
);
1403 set_gdbarch_unwind_pc (gdbarch
, frv_unwind_pc
);
1404 set_gdbarch_unwind_sp (gdbarch
, frv_unwind_sp
);
1405 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1406 frame_unwind_append_sniffer (gdbarch
, frv_frame_sniffer
);
1407 frame_base_set_default (gdbarch
, &frv_frame_base
);
1409 /* Settings for calling functions in the inferior. */
1410 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1411 set_gdbarch_unwind_dummy_id (gdbarch
, frv_unwind_dummy_id
);
1413 /* Settings that should be unnecessary. */
1414 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1416 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
1418 set_gdbarch_remote_translate_xfer_address
1419 (gdbarch
, generic_remote_translate_xfer_address
);
1421 /* Hardware watchpoint / breakpoint support. */
1422 switch (info
.bfd_arch_info
->mach
)
1425 case bfd_mach_frvsimple
:
1426 case bfd_mach_fr500
:
1427 case bfd_mach_frvtomcat
:
1428 /* fr500-style hardware debugging support. */
1429 var
->num_hw_watchpoints
= 4;
1430 var
->num_hw_breakpoints
= 4;
1433 case bfd_mach_fr400
:
1434 /* fr400-style hardware debugging support. */
1435 var
->num_hw_watchpoints
= 2;
1436 var
->num_hw_breakpoints
= 4;
1440 /* Otherwise, assume we don't have hardware debugging support. */
1441 var
->num_hw_watchpoints
= 0;
1442 var
->num_hw_breakpoints
= 0;
1446 set_gdbarch_print_insn (gdbarch
, print_insn_frv
);
1452 _initialize_frv_tdep (void)
1454 register_gdbarch_init (bfd_arch_frv
, frv_gdbarch_init
);