1 /* Debug register code for the i386.
3 Copyright (C) 2009-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "break-common.h"
25 /* Support for 8-byte wide hw watchpoints. */
26 #ifndef TARGET_HAS_DR_LEN_8
27 /* NOTE: sizeof (long) == 4 on win64. */
28 #define TARGET_HAS_DR_LEN_8 (sizeof (void *) == 8)
31 /* DR7 Debug Control register fields. */
33 /* How many bits to skip in DR7 to get to R/W and LEN fields. */
34 #define DR_CONTROL_SHIFT 16
35 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */
36 #define DR_CONTROL_SIZE 4
38 /* Watchpoint/breakpoint read/write fields in DR7. */
39 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */
40 #define DR_RW_WRITE (0x1) /* Break on data writes. */
41 #define DR_RW_READ (0x3) /* Break on data reads or writes. */
43 /* This is here for completeness. No platform supports this
44 functionality yet (as of March 2001). Note that the DE flag in the
45 CR4 register needs to be set to support this. */
47 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */
50 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift
51 is so we could OR this with the read/write field defined above. */
52 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */
53 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */
54 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */
55 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */
57 /* Local and Global Enable flags in DR7.
59 When the Local Enable flag is set, the breakpoint/watchpoint is
60 enabled only for the current task; the processor automatically
61 clears this flag on every task switch. When the Global Enable flag
62 is set, the breakpoint/watchpoint is enabled for all tasks; the
63 processor never clears this flag.
65 Currently, all watchpoint are locally enabled. If you need to
66 enable them globally, read the comment which pertains to this in
67 i386_insert_aligned_watchpoint below. */
68 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */
69 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */
70 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */
72 /* Local and global exact breakpoint enable flags (a.k.a. slowdown
73 flags). These are only required on i386, to allow detection of the
74 exact instruction which caused a watchpoint to break; i486 and
75 later processors do that automatically. We set these flags for
76 backwards compatibility. */
77 #define DR_LOCAL_SLOWDOWN (0x100)
78 #define DR_GLOBAL_SLOWDOWN (0x200)
80 /* Fields reserved by Intel. This includes the GD (General Detect
81 Enable) flag, which causes a debug exception to be generated when a
82 MOV instruction accesses one of the debug registers.
84 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */
85 #define DR_CONTROL_RESERVED (0xFC00)
87 /* Auxiliary helper macros. */
89 /* A value that masks all fields in DR7 that are reserved by Intel. */
90 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED)
92 /* The I'th debug register is vacant if its Local and Global Enable
93 bits are reset in the Debug Control register. */
94 #define I386_DR_VACANT(state, i) \
95 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0)
97 /* Locally enable the break/watchpoint in the I'th debug register. */
98 #define I386_DR_LOCAL_ENABLE(state, i) \
100 (state)->dr_control_mirror |= \
101 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
104 /* Globally enable the break/watchpoint in the I'th debug register. */
105 #define I386_DR_GLOBAL_ENABLE(state, i) \
107 (state)->dr_control_mirror |= \
108 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \
111 /* Disable the break/watchpoint in the I'th debug register. */
112 #define I386_DR_DISABLE(state, i) \
114 (state)->dr_control_mirror &= \
115 ~(3 << (DR_ENABLE_SIZE * (i))); \
118 /* Set in DR7 the RW and LEN fields for the I'th debug register. */
119 #define I386_DR_SET_RW_LEN(state, i,rwlen) \
121 (state)->dr_control_mirror &= \
122 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
123 (state)->dr_control_mirror |= \
124 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \
127 /* Get from DR7 the RW and LEN fields for the I'th debug register. */
128 #define I386_DR_GET_RW_LEN(dr7, i) \
130 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f)
132 /* Did the watchpoint whose address is in the I'th register break? */
133 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i)))
135 /* A macro to loop over all debug registers. */
136 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++)
138 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */
139 typedef enum { WP_INSERT
, WP_REMOVE
, WP_COUNT
} i386_wp_op_t
;
141 /* Implementation. */
143 /* Clear the reference counts and forget everything we knew about the
147 i386_low_init_dregs (struct i386_debug_reg_state
*state
)
151 ALL_DEBUG_REGISTERS (i
)
153 state
->dr_mirror
[i
] = 0;
154 state
->dr_ref_count
[i
] = 0;
156 state
->dr_control_mirror
= 0;
157 state
->dr_status_mirror
= 0;
160 /* Print the values of the mirrored debug registers. This is enabled via
161 the "set debug-hw-points 1" monitor command. */
164 i386_show_dr (struct i386_debug_reg_state
*state
,
165 const char *func
, CORE_ADDR addr
,
166 int len
, enum target_hw_bp_type type
)
170 fprintf (stderr
, "%s", func
);
172 fprintf (stderr
, " (addr=%lx, len=%d, type=%s)",
173 (unsigned long) addr
, len
,
174 type
== hw_write
? "data-write"
175 : (type
== hw_read
? "data-read"
176 : (type
== hw_access
? "data-read/write"
177 : (type
== hw_execute
? "instruction-execute"
178 /* FIXME: if/when I/O read/write
179 watchpoints are supported, add them
182 fprintf (stderr
, ":\n");
183 fprintf (stderr
, "\tCONTROL (DR7): %08x STATUS (DR6): %08x\n",
184 state
->dr_control_mirror
, state
->dr_status_mirror
);
185 ALL_DEBUG_REGISTERS (i
)
188 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n",
189 i
, paddress (state
->dr_mirror
[i
]),
190 state
->dr_ref_count
[i
],
191 i
+ 1, paddress (state
->dr_mirror
[i
+ 1]),
192 state
->dr_ref_count
[i
+ 1]);
197 /* Return the value of a 4-bit field for DR7 suitable for watching a
198 region of LEN bytes for accesses of type TYPE. LEN is assumed to
199 have the value of 1, 2, or 4. */
202 i386_length_and_rw_bits (int len
, enum target_hw_bp_type type
)
215 fatal ("The i386 doesn't support data-read watchpoints.\n");
220 /* Not yet supported. */
227 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n",
234 return (DR_LEN_1
| rw
);
236 return (DR_LEN_2
| rw
);
238 return (DR_LEN_4
| rw
);
240 if (TARGET_HAS_DR_LEN_8
)
241 return (DR_LEN_8
| rw
);
242 /* ELSE FALL THROUGH */
245 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n", len
);
249 /* Insert a watchpoint at address ADDR, which is assumed to be aligned
250 according to the length of the region to watch. LEN_RW_BITS is the
251 value of the bits from DR7 which describes the length and access
252 type of the region to be watched by this watchpoint. Return 0 on
253 success, -1 on failure. */
256 i386_insert_aligned_watchpoint (struct i386_debug_reg_state
*state
,
257 CORE_ADDR addr
, unsigned len_rw_bits
)
261 /* First, look for an occupied debug register with the same address
262 and the same RW and LEN definitions. If we find one, we can
263 reuse it for this watchpoint as well (and save a register). */
264 ALL_DEBUG_REGISTERS (i
)
266 if (!I386_DR_VACANT (state
, i
)
267 && state
->dr_mirror
[i
] == addr
268 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
270 state
->dr_ref_count
[i
]++;
275 /* Next, look for a vacant debug register. */
276 ALL_DEBUG_REGISTERS (i
)
278 if (I386_DR_VACANT (state
, i
))
282 /* No more debug registers! */
286 /* Now set up the register I to watch our region. */
288 /* Record the info in our local mirrored array. */
289 state
->dr_mirror
[i
] = addr
;
290 state
->dr_ref_count
[i
] = 1;
291 I386_DR_SET_RW_LEN (state
, i
, len_rw_bits
);
292 /* Note: we only enable the watchpoint locally, i.e. in the current
293 task. Currently, no i386 target allows or supports global
294 watchpoints; however, if any target would want that in the
295 future, GDB should probably provide a command to control whether
296 to enable watchpoints globally or locally, and the code below
297 should use global or local enable and slow-down flags as
299 I386_DR_LOCAL_ENABLE (state
, i
);
300 state
->dr_control_mirror
|= DR_LOCAL_SLOWDOWN
;
301 state
->dr_control_mirror
&= I386_DR_CONTROL_MASK
;
306 /* Remove a watchpoint at address ADDR, which is assumed to be aligned
307 according to the length of the region to watch. LEN_RW_BITS is the
308 value of the bits from DR7 which describes the length and access
309 type of the region watched by this watchpoint. Return 0 on
310 success, -1 on failure. */
313 i386_remove_aligned_watchpoint (struct i386_debug_reg_state
*state
,
314 CORE_ADDR addr
, unsigned len_rw_bits
)
318 ALL_DEBUG_REGISTERS (i
)
320 if (!I386_DR_VACANT (state
, i
)
321 && state
->dr_mirror
[i
] == addr
322 && I386_DR_GET_RW_LEN (state
->dr_control_mirror
, i
) == len_rw_bits
)
324 if (--state
->dr_ref_count
[i
] == 0) /* No longer in use? */
326 /* Reset our mirror. */
327 state
->dr_mirror
[i
] = 0;
328 I386_DR_DISABLE (state
, i
);
337 /* Insert or remove a (possibly non-aligned) watchpoint, or count the
338 number of debug registers required to watch a region at address
339 ADDR whose length is LEN for accesses of type TYPE. Return 0 on
340 successful insertion or removal, a positive number when queried
341 about the number of registers, or -1 on failure. If WHAT is not a
342 valid value, bombs through internal_error. */
345 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state
*state
,
346 i386_wp_op_t what
, CORE_ADDR addr
, int len
,
347 enum target_hw_bp_type type
)
350 int max_wp_len
= TARGET_HAS_DR_LEN_8
? 8 : 4;
352 static const int size_try_array
[8][8] =
354 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */
355 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */
356 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */
357 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */
358 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */
359 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */
360 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */
361 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */
366 int align
= addr
% max_wp_len
;
367 /* Four (eight on AMD64) is the maximum length a debug register
369 int try = (len
> max_wp_len
? (max_wp_len
- 1) : len
- 1);
370 int size
= size_try_array
[try][align
];
372 if (what
== WP_COUNT
)
374 /* size_try_array[] is defined such that each iteration
375 through the loop is guaranteed to produce an address and a
376 size that can be watched with a single debug register.
377 Thus, for counting the registers required to watch a
378 region, we simply need to increment the count on each
384 unsigned len_rw
= i386_length_and_rw_bits (size
, type
);
386 if (what
== WP_INSERT
)
387 retval
= i386_insert_aligned_watchpoint (state
, addr
, len_rw
);
388 else if (what
== WP_REMOVE
)
389 retval
= i386_remove_aligned_watchpoint (state
, addr
, len_rw
);
392 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n",
406 #define Z_PACKET_HW_BP '1'
407 #define Z_PACKET_WRITE_WP '2'
408 #define Z_PACKET_READ_WP '3'
409 #define Z_PACKET_ACCESS_WP '4'
411 /* Map the protocol watchpoint type TYPE to enum target_hw_bp_type. */
413 static enum target_hw_bp_type
414 Z_packet_to_hw_type (char type
)
420 case Z_PACKET_WRITE_WP
:
422 case Z_PACKET_READ_WP
:
424 case Z_PACKET_ACCESS_WP
:
427 fatal ("Z_packet_to_hw_type: bad watchpoint type %c", type
);
431 /* Update the inferior debug registers state, in INF_STATE, with the
432 new debug registers state, in NEW_STATE. */
435 i386_update_inferior_debug_regs (struct i386_debug_reg_state
*inf_state
,
436 struct i386_debug_reg_state
*new_state
)
440 ALL_DEBUG_REGISTERS (i
)
442 if (I386_DR_VACANT (new_state
, i
) != I386_DR_VACANT (inf_state
, i
))
443 i386_dr_low_set_addr (new_state
, i
);
445 gdb_assert (new_state
->dr_mirror
[i
] == inf_state
->dr_mirror
[i
]);
448 if (new_state
->dr_control_mirror
!= inf_state
->dr_control_mirror
)
449 i386_dr_low_set_control (new_state
);
451 *inf_state
= *new_state
;
454 /* Insert a watchpoint to watch a memory region which starts at
455 address ADDR and whose length is LEN bytes. Watch memory accesses
456 of the type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
459 i386_low_insert_watchpoint (struct i386_debug_reg_state
*state
,
460 char type_from_packet
, CORE_ADDR addr
, int len
)
463 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
464 /* Work on a local copy of the debug registers, and on success,
465 commit the change back to the inferior. */
466 struct i386_debug_reg_state local_state
= *state
;
469 return 1; /* unsupported */
471 if (((len
!= 1 && len
!= 2 && len
!= 4)
472 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
475 retval
= i386_handle_nonaligned_watchpoint (&local_state
, WP_INSERT
,
480 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
482 retval
= i386_insert_aligned_watchpoint (&local_state
, addr
, len_rw
);
486 i386_update_inferior_debug_regs (state
, &local_state
);
489 i386_show_dr (state
, "insert_watchpoint", addr
, len
, type
);
494 /* Remove a watchpoint that watched the memory region which starts at
495 address ADDR, whose length is LEN bytes, and for accesses of the
496 type TYPE_FROM_PACKET. Return 0 on success, -1 on failure. */
499 i386_low_remove_watchpoint (struct i386_debug_reg_state
*state
,
500 char type_from_packet
, CORE_ADDR addr
, int len
)
503 enum target_hw_bp_type type
= Z_packet_to_hw_type (type_from_packet
);
504 /* Work on a local copy of the debug registers, and on success,
505 commit the change back to the inferior. */
506 struct i386_debug_reg_state local_state
= *state
;
508 if (((len
!= 1 && len
!= 2 && len
!= 4)
509 && !(TARGET_HAS_DR_LEN_8
&& len
== 8))
512 retval
= i386_handle_nonaligned_watchpoint (&local_state
, WP_REMOVE
,
517 unsigned len_rw
= i386_length_and_rw_bits (len
, type
);
519 retval
= i386_remove_aligned_watchpoint (&local_state
, addr
, len_rw
);
523 i386_update_inferior_debug_regs (state
, &local_state
);
526 i386_show_dr (state
, "remove_watchpoint", addr
, len
, type
);
531 /* Return non-zero if we can watch a memory region that starts at
532 address ADDR and whose length is LEN bytes. */
535 i386_low_region_ok_for_watchpoint (struct i386_debug_reg_state
*state
,
536 CORE_ADDR addr
, int len
)
540 /* Compute how many aligned watchpoints we would need to cover this
542 nregs
= i386_handle_nonaligned_watchpoint (state
, WP_COUNT
,
543 addr
, len
, hw_write
);
544 return nregs
<= DR_NADDR
? 1 : 0;
547 /* If the inferior has some break/watchpoint that triggered, set the
548 address associated with that break/watchpoint and return true.
549 Otherwise, return false. */
552 i386_low_stopped_data_address (struct i386_debug_reg_state
*state
,
558 /* The current thread's DR_STATUS. We always need to read this to
559 check whether some watchpoint caused the trap. */
561 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a
562 data breakpoint trap. Only fetch it when necessary, to avoid an
563 unnecessary extra syscall when no watchpoint triggered. */
565 unsigned control
= 0;
567 /* In non-stop/async, threads can be running while we change the
568 global dr_mirror (and friends). Say, we set a watchpoint, and
569 let threads resume. Now, say you delete the watchpoint, or
570 add/remove watchpoints such that dr_mirror changes while threads
571 are running. On targets that support non-stop,
572 inserting/deleting watchpoints updates the global dr_mirror only.
573 It does not update the real thread's debug registers; that's only
574 done prior to resume. Instead, if threads are running when the
575 mirror changes, a temporary and transparent stop on all threads
576 is forced so they can get their copy of the debug registers
577 updated on re-resume. Now, say, a thread hit a watchpoint before
578 having been updated with the new dr_mirror contents, and we
579 haven't yet handled the corresponding SIGTRAP. If we trusted
580 dr_mirror below, we'd mistake the real trapped address (from the
581 last time we had updated debug registers in the thread) with
582 whatever was currently in dr_mirror. So to fix this, dr_mirror
583 always represents intention, what we _want_ threads to have in
584 debug registers. To get at the address and cause of the trap, we
585 need to read the state the thread still has in its debug
588 In sum, always get the current debug register values the current
589 thread has, instead of trusting the global mirror. If the thread
590 was running when we last changed watchpoints, the mirror no
591 longer represents what was set in this thread's debug
593 status
= i386_dr_low_get_status ();
595 ALL_DEBUG_REGISTERS (i
)
597 if (!I386_DR_WATCH_HIT (status
, i
))
602 control
= i386_dr_low_get_control ();
606 /* This second condition makes sure DRi is set up for a data
607 watchpoint, not a hardware breakpoint. The reason is that
608 GDB doesn't call the target_stopped_data_address method
609 except for data watchpoints. In other words, I'm being
611 if (I386_DR_GET_RW_LEN (control
, i
) != 0)
613 addr
= i386_dr_low_get_addr (i
);
616 i386_show_dr (state
, "watchpoint_hit", addr
, -1, hw_write
);
620 if (debug_hw_points
&& addr
== 0)
621 i386_show_dr (state
, "stopped_data_addr", 0, 0, hw_write
);
628 /* Return true if the inferior has some watchpoint that triggered.
629 Otherwise return false. */
632 i386_low_stopped_by_watchpoint (struct i386_debug_reg_state
*state
)
635 return i386_low_stopped_data_address (state
, &addr
);