1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
29 #include <asm/ptrace.h>
32 #include "gdb_proc_service.h"
34 /* Defined in auto-generated files. */
35 void init_registers_aarch64 (void);
36 extern const struct target_desc
*tdesc_aarch64
;
42 #define AARCH64_X_REGS_NUM 31
43 #define AARCH64_V_REGS_NUM 32
44 #define AARCH64_X0_REGNO 0
45 #define AARCH64_SP_REGNO 31
46 #define AARCH64_PC_REGNO 32
47 #define AARCH64_CPSR_REGNO 33
48 #define AARCH64_V0_REGNO 34
49 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
50 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
52 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
54 /* Here starts the macro definitions, data structures, and code for
55 the hardware breakpoint and hardware watchpoint support. The
56 following is the abbreviations that are used frequently in the code
63 /* Maximum number of hardware breakpoint and watchpoint registers.
64 Neither of these values may exceed the width of dr_changed_t
67 #define AARCH64_HBP_MAX_NUM 16
68 #define AARCH64_HWP_MAX_NUM 16
70 /* Alignment requirement in bytes of hardware breakpoint and
71 watchpoint address. This is the requirement for the addresses that
72 can be written to the hardware breakpoint/watchpoint value
73 registers. The kernel currently does not do any alignment on
74 addresses when receiving a writing request (via ptrace call) to
75 these debug registers, and it will reject any address that is
77 Some limited support has been provided in this gdbserver port for
78 unaligned watchpoints, so that from a gdb user point of view, an
79 unaligned watchpoint can still be set. This is achieved by
80 minimally enlarging the watched area to meet the alignment
81 requirement, and if necessary, splitting the watchpoint over
82 several hardware watchpoint registers. */
84 #define AARCH64_HBP_ALIGNMENT 4
85 #define AARCH64_HWP_ALIGNMENT 8
87 /* The maximum length of a memory region that can be watched by one
88 hardware watchpoint register. */
90 #define AARCH64_HWP_MAX_LEN_PER_REG 8
92 /* Each bit of a variable of this type is used to indicate whether a
93 hardware breakpoint or watchpoint setting has been changed since
94 the last updating. Bit N corresponds to the Nth hardware
95 breakpoint or watchpoint setting which is managed in
96 aarch64_debug_reg_state. Where N is valid between 0 and the total
97 number of the hardware breakpoint or watchpoint debug registers
98 minus 1. When the bit N is 1, it indicates the corresponding
99 breakpoint or watchpoint setting is changed, and thus the
100 corresponding hardware debug register needs to be updated via the
103 In the per-thread arch-specific data area, we define two such
104 variables for per-thread hardware breakpoint and watchpoint
105 settings respectively.
107 This type is part of the mechanism which helps reduce the number of
108 ptrace calls to the kernel, i.e. avoid asking the kernel to write
109 to the debug registers with unchanged values. */
111 typedef unsigned long long dr_changed_t
;
113 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
115 #define DR_MARK_ALL_CHANGED(x, m) \
118 gdb_assert (sizeof ((x)) * 8 >= (m)); \
119 (x) = (((dr_changed_t)1 << (m)) - 1); \
122 #define DR_MARK_N_CHANGED(x, n) \
125 (x) |= ((dr_changed_t)1 << (n)); \
128 #define DR_CLEAR_CHANGED(x) \
134 #define DR_HAS_CHANGED(x) ((x) != 0)
135 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
137 /* Structure for managing the hardware breakpoint/watchpoint resources.
138 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
139 content, and DR_REF_COUNT_* counts the numbers of references to the
140 corresponding bp/wp, by which way the limited hardware resources
141 are not wasted on duplicated bp/wp settings (though so far gdb has
142 done a good job by not sending duplicated bp/wp requests). */
144 struct aarch64_debug_reg_state
146 /* hardware breakpoint */
147 CORE_ADDR dr_addr_bp
[AARCH64_HBP_MAX_NUM
];
148 unsigned int dr_ctrl_bp
[AARCH64_HBP_MAX_NUM
];
149 unsigned int dr_ref_count_bp
[AARCH64_HBP_MAX_NUM
];
151 /* hardware watchpoint */
152 CORE_ADDR dr_addr_wp
[AARCH64_HWP_MAX_NUM
];
153 unsigned int dr_ctrl_wp
[AARCH64_HWP_MAX_NUM
];
154 unsigned int dr_ref_count_wp
[AARCH64_HWP_MAX_NUM
];
157 /* Per-process arch-specific data we want to keep. */
159 struct arch_process_info
161 /* Hardware breakpoint/watchpoint data.
162 The reason for them to be per-process rather than per-thread is
163 due to the lack of information in the gdbserver environment;
164 gdbserver is not told that whether a requested hardware
165 breakpoint/watchpoint is thread specific or not, so it has to set
166 each hw bp/wp for every thread in the current process. The
167 higher level bp/wp management in gdb will resume a thread if a hw
168 bp/wp trap is not expected for it. Since the hw bp/wp setting is
169 same for each thread, it is reasonable for the data to live here.
171 struct aarch64_debug_reg_state debug_reg_state
;
174 /* Per-thread arch-specific data we want to keep. */
178 /* When bit N is 1, it indicates the Nth hardware breakpoint or
179 watchpoint register pair needs to be updated when the thread is
180 resumed; see aarch64_linux_prepare_to_resume. */
181 dr_changed_t dr_changed_bp
;
182 dr_changed_t dr_changed_wp
;
185 /* Number of hardware breakpoints/watchpoints the target supports.
186 They are initialized with values obtained via the ptrace calls
187 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
189 static int aarch64_num_bp_regs
;
190 static int aarch64_num_wp_regs
;
193 aarch64_cannot_store_register (int regno
)
195 return regno
>= AARCH64_NUM_REGS
;
199 aarch64_cannot_fetch_register (int regno
)
201 return regno
>= AARCH64_NUM_REGS
;
205 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
207 struct user_pt_regs
*regset
= buf
;
210 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
211 collect_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
212 collect_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
213 collect_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
214 collect_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
218 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
220 const struct user_pt_regs
*regset
= buf
;
223 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
224 supply_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
225 supply_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
226 supply_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
227 supply_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
231 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
233 struct user_fpsimd_state
*regset
= buf
;
236 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
237 collect_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
238 collect_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
239 collect_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
243 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
245 const struct user_fpsimd_state
*regset
= buf
;
248 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
249 supply_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
250 supply_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
251 supply_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
254 /* Enable miscellaneous debugging output. The name is historical - it
255 was originally used to debug LinuxThreads support. */
256 extern int debug_threads
;
259 aarch64_get_pc (struct regcache
*regcache
)
263 collect_register_by_name (regcache
, "pc", &pc
);
265 debug_printf ("stop pc is %08lx\n", pc
);
270 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
272 unsigned long newpc
= pc
;
273 supply_register_by_name (regcache
, "pc", &newpc
);
276 #define aarch64_breakpoint_len 4
278 /* AArch64 BRK software debug mode instruction.
279 This instruction needs to match gdb/aarch64-tdep.c
280 (aarch64_default_breakpoint). */
281 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
284 aarch64_breakpoint_at (CORE_ADDR where
)
286 gdb_byte insn
[aarch64_breakpoint_len
];
288 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
289 aarch64_breakpoint_len
);
290 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
296 /* Print the values of the cached breakpoint/watchpoint registers.
297 This is enabled via the "set debug-hw-points" monitor command. */
300 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
301 const char *func
, CORE_ADDR addr
,
302 int len
, enum target_hw_bp_type type
)
306 fprintf (stderr
, "%s", func
);
308 fprintf (stderr
, " (addr=0x%08lx, len=%d, type=%s)",
309 (unsigned long) addr
, len
,
310 type
== hw_write
? "hw-write-watchpoint"
311 : (type
== hw_read
? "hw-read-watchpoint"
312 : (type
== hw_access
? "hw-access-watchpoint"
313 : (type
== hw_execute
? "hw-breakpoint"
315 fprintf (stderr
, ":\n");
317 fprintf (stderr
, "\tBREAKPOINTs:\n");
318 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
319 fprintf (stderr
, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
320 i
, paddress (state
->dr_addr_bp
[i
]),
321 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
323 fprintf (stderr
, "\tWATCHPOINTs:\n");
324 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
325 fprintf (stderr
, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
326 i
, paddress (state
->dr_addr_wp
[i
]),
327 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
331 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
335 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
337 state
->dr_addr_bp
[i
] = 0;
338 state
->dr_ctrl_bp
[i
] = 0;
339 state
->dr_ref_count_bp
[i
] = 0;
342 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
344 state
->dr_addr_wp
[i
] = 0;
345 state
->dr_ctrl_wp
[i
] = 0;
346 state
->dr_ref_count_wp
[i
] = 0;
350 /* ptrace expects control registers to be formatted as follows:
353 +--------------------------------+----------+------+------+----+
354 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
355 +--------------------------------+----------+------+------+----+
357 The TYPE field is ignored for breakpoints. */
359 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
360 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
362 /* Utility function that returns the length in bytes of a watchpoint
363 according to the content of a hardware debug control register CTRL.
364 Note that the kernel currently only supports the following Byte
365 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
366 that for a hardware watchpoint, its valid length can only be 1
367 byte, 2 bytes, 4 bytes or 8 bytes. */
369 static inline unsigned int
370 aarch64_watchpoint_length (unsigned int ctrl
)
372 switch (DR_CONTROL_LENGTH (ctrl
))
387 /* Given the hardware breakpoint or watchpoint type TYPE and its
388 length LEN, return the expected encoding for a hardware
389 breakpoint/watchpoint control register. */
392 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type
, int len
)
394 unsigned int ctrl
, ttype
;
412 perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
418 ctrl
|= ((1 << len
) - 1) << 5;
420 ctrl
|= (2 << 1) | 1;
425 /* Addresses to be written to the hardware breakpoint and watchpoint
426 value registers need to be aligned; the alignment is 4-byte and
427 8-type respectively. Linux kernel rejects any non-aligned address
428 it receives from the related ptrace call. Furthermore, the kernel
429 currently only supports the following Byte Address Select (BAS)
430 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
431 watchpoint to be accepted by the kernel (via ptrace call), its
432 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
433 Despite these limitations, the unaligned watchpoint is supported in
436 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
439 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
441 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
442 : AARCH64_HBP_ALIGNMENT
;
444 if (addr
& (alignment
- 1))
447 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
453 /* Given the (potentially unaligned) watchpoint address in ADDR and
454 length in LEN, return the aligned address and aligned length in
455 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
456 aligned address and length will be valid to be written to the
457 hardware watchpoint value and control registers. See the comment
458 above aarch64_point_is_aligned for the information about the
459 alignment requirement. The given watchpoint may get truncated if
460 more than one hardware register is needed to cover the watched
461 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
462 address and length of the remaining part of the watchpoint (which
463 can be processed by calling this routine again to generate another
464 aligned address and length pair.
466 Essentially, unaligned watchpoint is achieved by minimally
467 enlarging the watched area to meet the alignment requirement, and
468 if necessary, splitting the watchpoint over several hardware
469 watchpoint registers. The trade-off is that there will be
470 false-positive hits for the read-type or the access-type hardware
471 watchpoints; for the write type, which is more commonly used, there
472 will be no such issues, as the higher-level breakpoint management
473 in gdb always examines the exact watched region for any content
474 change, and transparently resumes a thread from a watchpoint trap
475 if there is no change to the watched region.
477 Another limitation is that because the watched region is enlarged,
478 the watchpoint fault address returned by
479 aarch64_stopped_data_address may be outside of the original watched
480 region, especially when the triggering instruction is accessing a
481 larger region. When the fault address is not within any known
482 range, watchpoints_triggered in gdb will get confused, as the
483 higher-level watchpoint management is only aware of original
484 watched regions, and will think that some unknown watchpoint has
485 been triggered. In such a case, gdb may stop without displaying
486 any detailed information.
488 Once the kernel provides the full support for Byte Address Select
489 (BAS) in the hardware watchpoint control register, these
490 limitations can be largely relaxed with some further work. */
493 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
494 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
499 CORE_ADDR aligned_addr
;
500 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
501 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
503 /* As assumed by the algorithm. */
504 gdb_assert (alignment
== max_wp_len
);
509 /* Address to be put into the hardware watchpoint value register
511 offset
= addr
& (alignment
- 1);
512 aligned_addr
= addr
- offset
;
514 gdb_assert (offset
>= 0 && offset
< alignment
);
515 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
516 gdb_assert ((offset
+ len
) > 0);
518 if (offset
+ len
>= max_wp_len
)
520 /* Need more than one watchpoint registers; truncate it at the
521 alignment boundary. */
522 aligned_len
= max_wp_len
;
523 len
-= (max_wp_len
- offset
);
524 addr
+= (max_wp_len
- offset
);
525 gdb_assert ((addr
& (alignment
- 1)) == 0);
529 /* Find the smallest valid length that is large enough to
530 accommodate this watchpoint. */
531 static const unsigned char
532 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
533 { 1, 2, 4, 4, 8, 8, 8, 8 };
535 aligned_len
= aligned_len_array
[offset
+ len
- 1];
540 if (aligned_addr_p
!= NULL
)
541 *aligned_addr_p
= aligned_addr
;
542 if (aligned_len_p
!= NULL
)
543 *aligned_len_p
= aligned_len
;
544 if (next_addr_p
!= NULL
)
546 if (next_len_p
!= NULL
)
550 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
551 registers with data from *STATE. */
554 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
555 int tid
, int watchpoint
)
559 struct user_hwdebug_state regs
;
560 const CORE_ADDR
*addr
;
561 const unsigned int *ctrl
;
563 memset (®s
, 0, sizeof (regs
));
564 iov
.iov_base
= ®s
;
565 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
566 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
567 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
570 iov
.iov_len
= (offsetof (struct user_hwdebug_state
, dbg_regs
[count
- 1])
571 + sizeof (regs
.dbg_regs
[count
- 1]));
573 for (i
= 0; i
< count
; i
++)
575 regs
.dbg_regs
[i
].addr
= addr
[i
];
576 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
579 if (ptrace (PTRACE_SETREGSET
, tid
,
580 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
582 error (_("Unexpected error setting hardware debug registers"));
585 struct aarch64_dr_update_callback_param
592 /* Callback function which records the information about the change of
593 one hardware breakpoint/watchpoint setting for the thread ENTRY.
594 The information is passed in via PTR.
595 N.B. The actual updating of hardware debug registers is not
596 carried out until the moment the thread is resumed. */
599 debug_reg_change_callback (struct inferior_list_entry
*entry
, void *ptr
)
601 struct thread_info
*thread
= (struct thread_info
*) entry
;
602 struct lwp_info
*lwp
= get_thread_lwp (thread
);
603 struct aarch64_dr_update_callback_param
*param_p
604 = (struct aarch64_dr_update_callback_param
*) ptr
;
605 int pid
= param_p
->pid
;
606 int idx
= param_p
->idx
;
607 int is_watchpoint
= param_p
->is_watchpoint
;
608 struct arch_lwp_info
*info
= lwp
->arch_private
;
609 dr_changed_t
*dr_changed_ptr
;
610 dr_changed_t dr_changed
;
614 fprintf (stderr
, "debug_reg_change_callback: \n\tOn entry:\n");
615 fprintf (stderr
, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
616 "dr_changed_wp=0x%llx\n",
617 pid
, lwpid_of (thread
), info
->dr_changed_bp
,
618 info
->dr_changed_wp
);
621 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
622 : &info
->dr_changed_bp
;
623 dr_changed
= *dr_changed_ptr
;
625 /* Only update the threads of this process. */
626 if (pid_of (thread
) == pid
)
629 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
630 : aarch64_num_bp_regs
)));
632 /* The following assertion is not right, as there can be changes
633 that have not been made to the hardware debug registers
634 before new changes overwrite the old ones. This can happen,
635 for instance, when the breakpoint/watchpoint hit one of the
636 threads and the user enters continue; then what happens is:
637 1) all breakpoints/watchpoints are removed for all threads;
638 2) a single step is carried out for the thread that was hit;
639 3) all of the points are inserted again for all threads;
640 4) all threads are resumed.
641 The 2nd step will only affect the one thread in which the
642 bp/wp was hit, which means only that one thread is resumed;
643 remember that the actual updating only happen in
644 aarch64_linux_prepare_to_resume, so other threads remain
645 stopped during the removal and insertion of bp/wp. Therefore
646 for those threads, the change of insertion of the bp/wp
647 overwrites that of the earlier removals. (The situation may
648 be different when bp/wp is steppable, or in the non-stop
650 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
652 /* The actual update is done later just before resuming the lwp,
653 we just mark that one register pair needs updating. */
654 DR_MARK_N_CHANGED (dr_changed
, idx
);
655 *dr_changed_ptr
= dr_changed
;
657 /* If the lwp isn't stopped, force it to momentarily pause, so
658 we can update its debug registers. */
660 linux_stop_lwp (lwp
);
665 fprintf (stderr
, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
666 "dr_changed_wp=0x%llx\n",
667 pid
, lwpid_of (thread
), info
->dr_changed_bp
,
668 info
->dr_changed_wp
);
674 /* Notify each thread that their IDXth breakpoint/watchpoint register
675 pair needs to be updated. The message will be recorded in each
676 thread's arch-specific data area, the actual updating will be done
677 when the thread is resumed. */
680 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
681 int is_watchpoint
, unsigned int idx
)
683 struct aarch64_dr_update_callback_param param
;
685 /* Only update the threads of this process. */
686 param
.pid
= pid_of (current_thread
);
688 param
.is_watchpoint
= is_watchpoint
;
691 find_inferior (&all_threads
, debug_reg_change_callback
, (void *) ¶m
);
695 /* Return the pointer to the debug register state structure in the
696 current process' arch-specific data area. */
698 static struct aarch64_debug_reg_state
*
699 aarch64_get_debug_reg_state ()
701 struct process_info
*proc
;
703 proc
= current_process ();
704 return &proc
->priv
->arch_private
->debug_reg_state
;
707 /* Record the insertion of one breakpoint/watchpoint, as represented
708 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
711 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
712 enum target_hw_bp_type type
,
713 CORE_ADDR addr
, int len
)
715 int i
, idx
, num_regs
, is_watchpoint
;
716 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
717 CORE_ADDR
*dr_addr_p
;
719 /* Set up state pointers. */
720 is_watchpoint
= (type
!= hw_execute
);
721 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
724 num_regs
= aarch64_num_wp_regs
;
725 dr_addr_p
= state
->dr_addr_wp
;
726 dr_ctrl_p
= state
->dr_ctrl_wp
;
727 dr_ref_count
= state
->dr_ref_count_wp
;
731 num_regs
= aarch64_num_bp_regs
;
732 dr_addr_p
= state
->dr_addr_bp
;
733 dr_ctrl_p
= state
->dr_ctrl_bp
;
734 dr_ref_count
= state
->dr_ref_count_bp
;
737 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
739 /* Find an existing or free register in our cache. */
741 for (i
= 0; i
< num_regs
; ++i
)
743 if ((dr_ctrl_p
[i
] & 1) == 0)
745 gdb_assert (dr_ref_count
[i
] == 0);
747 /* no break; continue hunting for an exising one. */
749 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
751 gdb_assert (dr_ref_count
[i
] != 0);
761 /* Update our cache. */
762 if ((dr_ctrl_p
[idx
] & 1) == 0)
765 dr_addr_p
[idx
] = addr
;
766 dr_ctrl_p
[idx
] = ctrl
;
767 dr_ref_count
[idx
] = 1;
768 /* Notify the change. */
769 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
780 /* Record the removal of one breakpoint/watchpoint, as represented by
781 ADDR and CTRL, in the process' arch-specific data area *STATE. */
784 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
785 enum target_hw_bp_type type
,
786 CORE_ADDR addr
, int len
)
788 int i
, num_regs
, is_watchpoint
;
789 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
790 CORE_ADDR
*dr_addr_p
;
792 /* Set up state pointers. */
793 is_watchpoint
= (type
!= hw_execute
);
794 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
797 num_regs
= aarch64_num_wp_regs
;
798 dr_addr_p
= state
->dr_addr_wp
;
799 dr_ctrl_p
= state
->dr_ctrl_wp
;
800 dr_ref_count
= state
->dr_ref_count_wp
;
804 num_regs
= aarch64_num_bp_regs
;
805 dr_addr_p
= state
->dr_addr_bp
;
806 dr_ctrl_p
= state
->dr_ctrl_bp
;
807 dr_ref_count
= state
->dr_ref_count_bp
;
810 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
812 /* Find the entry that matches the ADDR and CTRL. */
813 for (i
= 0; i
< num_regs
; ++i
)
814 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
816 gdb_assert (dr_ref_count
[i
] != 0);
824 /* Clear our cache. */
825 if (--dr_ref_count
[i
] == 0)
827 /* Clear the enable bit. */
831 /* Notify the change. */
832 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
839 aarch64_handle_breakpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
840 int len
, int is_insert
)
842 struct aarch64_debug_reg_state
*state
;
844 /* The hardware breakpoint on AArch64 should always be 4-byte
846 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
849 state
= aarch64_get_debug_reg_state ();
852 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
854 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
857 /* This is essentially the same as aarch64_handle_breakpoint, apart
858 from that it is an aligned watchpoint to be handled. */
861 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type
,
862 CORE_ADDR addr
, int len
, int is_insert
)
864 struct aarch64_debug_reg_state
*state
;
866 state
= aarch64_get_debug_reg_state ();
869 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
871 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
874 /* Insert/remove unaligned watchpoint by calling
875 aarch64_align_watchpoint repeatedly until the whole watched region,
876 as represented by ADDR and LEN, has been properly aligned and ready
877 to be written to one or more hardware watchpoint registers.
878 IS_INSERT indicates whether this is an insertion or a deletion.
879 Return 0 if succeed. */
882 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type
,
883 CORE_ADDR addr
, int len
, int is_insert
)
885 struct aarch64_debug_reg_state
*state
886 = aarch64_get_debug_reg_state ();
890 CORE_ADDR aligned_addr
;
891 int aligned_len
, ret
;
893 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
897 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
900 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
905 "handle_unaligned_watchpoint: is_insert: %d\n"
906 " aligned_addr: 0x%s, aligned_len: %d\n"
907 " next_addr: 0x%s, next_len: %d\n",
908 is_insert
, paddress (aligned_addr
), aligned_len
,
909 paddress (addr
), len
);
919 aarch64_handle_watchpoint (enum target_hw_bp_type type
, CORE_ADDR addr
,
920 int len
, int is_insert
)
922 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
923 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
);
925 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
);
929 aarch64_supports_z_point_type (char z_type
)
935 case Z_PACKET_WRITE_WP
:
936 case Z_PACKET_READ_WP
:
937 case Z_PACKET_ACCESS_WP
:
944 /* Insert a hardware breakpoint/watchpoint.
945 It actually only records the info of the to-be-inserted bp/wp;
946 the actual insertion will happen when threads are resumed.
949 Return 1 if TYPE is unsupported type;
950 Return -1 if an error occurs. */
953 aarch64_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
954 int len
, struct raw_breakpoint
*bp
)
957 enum target_hw_bp_type targ_type
;
960 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
961 (unsigned long) addr
, len
);
963 /* Determine the type from the raw breakpoint type. */
964 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
966 if (targ_type
!= hw_execute
)
968 aarch64_handle_watchpoint (targ_type
, addr
, len
, 1 /* is_insert */);
971 aarch64_handle_breakpoint (targ_type
, addr
, len
, 1 /* is_insert */);
974 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
975 "insert_point", addr
, len
, targ_type
);
980 /* Remove a hardware breakpoint/watchpoint.
981 It actually only records the info of the to-be-removed bp/wp,
982 the actual removal will be done when threads are resumed.
985 Return 1 if TYPE is an unsupported type;
986 Return -1 if an error occurs. */
989 aarch64_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
990 int len
, struct raw_breakpoint
*bp
)
993 enum target_hw_bp_type targ_type
;
996 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
997 (unsigned long) addr
, len
);
999 /* Determine the type from the raw breakpoint type. */
1000 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
1002 /* Set up state pointers. */
1003 if (targ_type
!= hw_execute
)
1005 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */);
1008 aarch64_handle_breakpoint (targ_type
, addr
, len
, 0 /* is_insert */);
1010 if (show_debug_regs
)
1011 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1012 "remove_point", addr
, len
, targ_type
);
1017 /* Returns the address associated with the watchpoint that hit, if
1018 any; returns 0 otherwise. */
1021 aarch64_stopped_data_address (void)
1025 struct aarch64_debug_reg_state
*state
;
1027 pid
= lwpid_of (current_thread
);
1029 /* Get the siginfo. */
1030 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
1031 return (CORE_ADDR
) 0;
1033 /* Need to be a hardware breakpoint/watchpoint trap. */
1034 if (siginfo
.si_signo
!= SIGTRAP
1035 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1036 return (CORE_ADDR
) 0;
1038 /* Check if the address matches any watched address. */
1039 state
= aarch64_get_debug_reg_state ();
1040 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
1042 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
1043 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
1044 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
1045 if (state
->dr_ref_count_wp
[i
]
1046 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
1047 && addr_trap
>= addr_watch
1048 && addr_trap
< addr_watch
+ len
)
1052 return (CORE_ADDR
) 0;
1055 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1059 aarch64_stopped_by_watchpoint (void)
1061 if (aarch64_stopped_data_address () != 0)
1067 /* Fetch the thread-local storage pointer for libthread_db. */
1070 ps_get_thread_area (const struct ps_prochandle
*ph
,
1071 lwpid_t lwpid
, int idx
, void **base
)
1076 iovec
.iov_base
= ®
;
1077 iovec
.iov_len
= sizeof (reg
);
1079 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
1082 /* IDX is the bias from the thread pointer to the beginning of the
1083 thread descriptor. It has to be subtracted due to implementation
1084 quirks in libthread_db. */
1085 *base
= (void *) (reg
- idx
);
1090 /* Called when a new process is created. */
1092 static struct arch_process_info
*
1093 aarch64_linux_new_process (void)
1095 struct arch_process_info
*info
= xcalloc (1, sizeof (*info
));
1097 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
1102 /* Called when a new thread is detected. */
1105 aarch64_linux_new_thread (struct lwp_info
*lwp
)
1107 struct arch_lwp_info
*info
= xcalloc (1, sizeof (*info
));
1109 /* Mark that all the hardware breakpoint/watchpoint register pairs
1110 for this thread need to be initialized (with data from
1111 aarch_process_info.debug_reg_state). */
1112 DR_MARK_ALL_CHANGED (info
->dr_changed_bp
, aarch64_num_bp_regs
);
1113 DR_MARK_ALL_CHANGED (info
->dr_changed_wp
, aarch64_num_wp_regs
);
1115 lwp
->arch_private
= info
;
1119 aarch64_linux_new_fork (struct process_info
*parent
,
1120 struct process_info
*child
)
1122 /* These are allocated by linux_add_process. */
1123 gdb_assert (parent
->priv
!= NULL
1124 && parent
->priv
->arch_private
!= NULL
);
1125 gdb_assert (child
->priv
!= NULL
1126 && child
->priv
->arch_private
!= NULL
);
1128 /* Linux kernel before 2.6.33 commit
1129 72f674d203cd230426437cdcf7dd6f681dad8b0d
1130 will inherit hardware debug registers from parent
1131 on fork/vfork/clone. Newer Linux kernels create such tasks with
1132 zeroed debug registers.
1134 GDB core assumes the child inherits the watchpoints/hw
1135 breakpoints of the parent, and will remove them all from the
1136 forked off process. Copy the debug registers mirrors into the
1137 new process so that all breakpoints and watchpoints can be
1138 removed together. The debug registers mirror will become zeroed
1139 in the end before detaching the forked off process, thus making
1140 this compatible with older Linux kernels too. */
1142 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
1145 /* Called when resuming a thread.
1146 If the debug regs have changed, update the thread's copies. */
1149 aarch64_linux_prepare_to_resume (struct lwp_info
*lwp
)
1151 struct thread_info
*thread
= get_lwp_thread (lwp
);
1152 ptid_t ptid
= ptid_of (thread
);
1153 struct arch_lwp_info
*info
= lwp
->arch_private
;
1155 if (DR_HAS_CHANGED (info
->dr_changed_bp
)
1156 || DR_HAS_CHANGED (info
->dr_changed_wp
))
1158 int tid
= ptid_get_lwp (ptid
);
1159 struct process_info
*proc
= find_process_pid (ptid_get_pid (ptid
));
1160 struct aarch64_debug_reg_state
*state
1161 = &proc
->priv
->arch_private
->debug_reg_state
;
1163 if (show_debug_regs
)
1164 fprintf (stderr
, "prepare_to_resume thread %ld\n", lwpid_of (thread
));
1167 if (DR_HAS_CHANGED (info
->dr_changed_wp
))
1169 aarch64_linux_set_debug_regs (state
, tid
, 1);
1170 DR_CLEAR_CHANGED (info
->dr_changed_wp
);
1174 if (DR_HAS_CHANGED (info
->dr_changed_bp
))
1176 aarch64_linux_set_debug_regs (state
, tid
, 0);
1177 DR_CLEAR_CHANGED (info
->dr_changed_bp
);
1182 /* ptrace hardware breakpoint resource info is formatted as follows:
1185 +---------------+--------------+---------------+---------------+
1186 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1187 +---------------+--------------+---------------+---------------+ */
1189 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1190 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1191 #define AARCH64_DEBUG_ARCH_V8 0x6
1194 aarch64_arch_setup (void)
1198 struct user_hwdebug_state dreg_state
;
1200 current_process ()->tdesc
= tdesc_aarch64
;
1202 pid
= lwpid_of (current_thread
);
1203 iov
.iov_base
= &dreg_state
;
1204 iov
.iov_len
= sizeof (dreg_state
);
1206 /* Get hardware watchpoint register info. */
1207 if (ptrace (PTRACE_GETREGSET
, pid
, NT_ARM_HW_WATCH
, &iov
) == 0
1208 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
1210 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
1211 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
1213 warning ("Unexpected number of hardware watchpoint registers reported"
1214 " by ptrace, got %d, expected %d.",
1215 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
1216 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
1221 warning ("Unable to determine the number of hardware watchpoints"
1223 aarch64_num_wp_regs
= 0;
1226 /* Get hardware breakpoint register info. */
1227 if (ptrace (PTRACE_GETREGSET
, pid
, NT_ARM_HW_BREAK
, &iov
) == 0
1228 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
1230 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
1231 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
1233 warning ("Unexpected number of hardware breakpoint registers reported"
1234 " by ptrace, got %d, expected %d.",
1235 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
1236 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
1241 warning ("Unable to determine the number of hardware breakpoints"
1243 aarch64_num_bp_regs
= 0;
1247 static struct regset_info aarch64_regsets
[] =
1249 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
1250 sizeof (struct user_pt_regs
), GENERAL_REGS
,
1251 aarch64_fill_gregset
, aarch64_store_gregset
},
1252 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
1253 sizeof (struct user_fpsimd_state
), FP_REGS
,
1254 aarch64_fill_fpregset
, aarch64_store_fpregset
1256 { 0, 0, 0, -1, -1, NULL
, NULL
}
1259 static struct regsets_info aarch64_regsets_info
=
1261 aarch64_regsets
, /* regsets */
1262 0, /* num_regsets */
1263 NULL
, /* disabled_regsets */
1266 static struct regs_info regs_info
=
1268 NULL
, /* regset_bitmap */
1270 &aarch64_regsets_info
,
1273 static const struct regs_info
*
1274 aarch64_regs_info (void)
1279 /* Implementation of linux_target_ops method "supports_tracepoints". */
1282 aarch64_supports_tracepoints (void)
1287 struct linux_target_ops the_low_target
=
1291 aarch64_cannot_fetch_register
,
1292 aarch64_cannot_store_register
,
1296 (const unsigned char *) &aarch64_breakpoint
,
1297 aarch64_breakpoint_len
,
1300 aarch64_breakpoint_at
,
1301 aarch64_supports_z_point_type
,
1302 aarch64_insert_point
,
1303 aarch64_remove_point
,
1304 aarch64_stopped_by_watchpoint
,
1305 aarch64_stopped_data_address
,
1309 aarch64_linux_new_process
,
1310 aarch64_linux_new_thread
,
1311 aarch64_linux_new_fork
,
1312 aarch64_linux_prepare_to_resume
,
1314 aarch64_supports_tracepoints
,
1318 initialize_low_arch (void)
1320 init_registers_aarch64 ();
1322 initialize_regsets_info (&aarch64_regsets_info
);