1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2013 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "elf/common.h"
28 #include <sys/ptrace.h>
31 #include "gdb_proc_service.h"
33 /* Defined in auto-generated files. */
34 void init_registers_aarch64 (void);
36 /* Defined in auto-generated files. */
37 void init_registers_aarch64_without_fpu (void);
43 #define AARCH64_X_REGS_NUM 31
44 #define AARCH64_V_REGS_NUM 32
45 #define AARCH64_X0_REGNO 0
46 #define AARCH64_SP_REGNO 31
47 #define AARCH64_PC_REGNO 32
48 #define AARCH64_CPSR_REGNO 33
49 #define AARCH64_V0_REGNO 34
51 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
56 /* These offsets correspond to GET/SETREGSET */
58 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
59 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8,
60 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8,
61 24*8, 25*8, 26*8, 27*8, 28*8,
66 33*8, /* cpsr 4 bytes!*/
68 /* FP register offsets correspond to GET/SETFPREGSET */
69 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
70 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
71 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
72 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
75 /* Here starts the macro definitions, data structures, and code for
76 the hardware breakpoint and hardware watchpoint support. The
77 following is the abbreviations that are used frequently in the code
84 /* Maximum number of hardware breakpoint and watchpoint registers.
85 Neither of these values may exceed the width of dr_changed_t
88 #define AARCH64_HBP_MAX_NUM 16
89 #define AARCH64_HWP_MAX_NUM 16
91 /* Alignment requirement in bytes of hardware breakpoint and
92 watchpoint address. This is the requirement for the addresses that
93 can be written to the hardware breakpoint/watchpoint value
94 registers. The kernel currently does not do any alignment on
95 addresses when receiving a writing request (via ptrace call) to
96 these debug registers, and it will reject any address that is
98 Some limited support has been provided in this gdbserver port for
99 unaligned watchpoints, so that from a gdb user point of view, an
100 unaligned watchpoint can still be set. This is achieved by
101 minimally enlarging the watched area to meet the alignment
102 requirement, and if necessary, splitting the watchpoint over
103 several hardware watchpoint registers. */
105 #define AARCH64_HBP_ALIGNMENT 4
106 #define AARCH64_HWP_ALIGNMENT 8
108 /* The maximum length of a memory region that can be watched by one
109 hardware watchpoint register. */
111 #define AARCH64_HWP_MAX_LEN_PER_REG 8
113 /* Each bit of a variable of this type is used to indicate whether a
114 hardware breakpoint or watchpoint setting has been changed since
115 the last updating. Bit N corresponds to the Nth hardware
116 breakpoint or watchpoint setting which is managed in
117 aarch64_debug_reg_state. Where N is valid between 0 and the total
118 number of the hardware breakpoint or watchpoint debug registers
119 minus 1. When the bit N is 1, it indicates the corresponding
120 breakpoint or watchpoint setting is changed, and thus the
121 corresponding hardware debug register needs to be updated via the
124 In the per-thread arch-specific data area, we define two such
125 variables for per-thread hardware breakpoint and watchpoint
126 settings respectively.
128 This type is part of the mechanism which helps reduce the number of
129 ptrace calls to the kernel, i.e. avoid asking the kernel to write
130 to the debug registers with unchanged values. */
132 typedef unsigned long long dr_changed_t
;
134 /* Set each of the lower M bits of X to 1; assert X is wide enough. */
136 #define DR_MARK_ALL_CHANGED(x, m) \
139 gdb_assert (sizeof ((x)) * 8 >= (m)); \
140 (x) = (((dr_changed_t)1 << (m)) - 1); \
143 #define DR_MARK_N_CHANGED(x, n) \
146 (x) |= ((dr_changed_t)1 << (n)); \
149 #define DR_CLEAR_CHANGED(x) \
155 #define DR_HAS_CHANGED(x) ((x) != 0)
156 #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
158 /* Structure for managing the hardware breakpoint/watchpoint resources.
159 DR_ADDR_* stores the address, DR_CTRL_* stores the control register
160 content, and DR_REF_COUNT_* counts the numbers of references to the
161 corresponding bp/wp, by which way the limited hardware resources
162 are not wasted on duplicated bp/wp settings (though so far gdb has
163 done a good job by not sending duplicated bp/wp requests). */
165 struct aarch64_debug_reg_state
167 /* hardware breakpoint */
168 CORE_ADDR dr_addr_bp
[AARCH64_HBP_MAX_NUM
];
169 unsigned int dr_ctrl_bp
[AARCH64_HBP_MAX_NUM
];
170 unsigned int dr_ref_count_bp
[AARCH64_HBP_MAX_NUM
];
172 /* hardware watchpoint */
173 CORE_ADDR dr_addr_wp
[AARCH64_HWP_MAX_NUM
];
174 unsigned int dr_ctrl_wp
[AARCH64_HWP_MAX_NUM
];
175 unsigned int dr_ref_count_wp
[AARCH64_HWP_MAX_NUM
];
178 /* Per-process arch-specific data we want to keep. */
180 struct arch_process_info
182 /* Hardware breakpoint/watchpoint data.
183 The reason for them to be per-process rather than per-thread is
184 due to the lack of information in the gdbserver environment;
185 gdbserver is not told that whether a requested hardware
186 breakpoint/watchpoint is thread specific or not, so it has to set
187 each hw bp/wp for every thread in the current process. The
188 higher level bp/wp management in gdb will resume a thread if a hw
189 bp/wp trap is not expected for it. Since the hw bp/wp setting is
190 same for each thread, it is reasonable for the data to live here.
192 struct aarch64_debug_reg_state debug_reg_state
;
195 /* Per-thread arch-specific data we want to keep. */
199 /* When bit N is 1, it indicates the Nth hardware breakpoint or
200 watchpoint register pair needs to be updated when the thread is
201 resumed; see aarch64_linux_prepare_to_resume. */
202 dr_changed_t dr_changed_bp
;
203 dr_changed_t dr_changed_wp
;
206 /* Number of hardware breakpoints/watchpoints the target supports.
207 They are initialized with values obtained via the ptrace calls
208 with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
210 static int aarch64_num_bp_regs
;
211 static int aarch64_num_wp_regs
;
213 /* Hardware breakpoint/watchpoint types.
214 The values map to their encodings in the bit 4 and bit 3 of the
215 hardware breakpoint/watchpoint control registers. */
217 enum target_point_type
219 hw_execute
= 0, /* Execute HW breakpoint */
220 hw_read
= 1, /* Read HW watchpoint */
221 hw_write
= 2, /* Common HW watchpoint */
222 hw_access
= 3, /* Access HW watchpoint */
223 point_type_unsupported
226 #define Z_PACKET_SW_BP '0'
227 #define Z_PACKET_HW_BP '1'
228 #define Z_PACKET_WRITE_WP '2'
229 #define Z_PACKET_READ_WP '3'
230 #define Z_PACKET_ACCESS_WP '4'
232 /* Map the protocol breakpoint/watchpoint type TYPE to
233 enum target_point_type. */
235 static enum target_point_type
236 Z_packet_to_point_type (char type
)
241 /* Leave the handling of the sw breakpoint with the gdb client. */
242 return point_type_unsupported
;
245 case Z_PACKET_WRITE_WP
:
247 case Z_PACKET_READ_WP
:
249 case Z_PACKET_ACCESS_WP
:
252 return point_type_unsupported
;
257 aarch64_cannot_store_register (int regno
)
259 return regno
>= AARCH64_NUM_REGS
;
263 aarch64_cannot_fetch_register (int regno
)
265 return regno
>= AARCH64_NUM_REGS
;
269 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
271 struct user_pt_regs
*regset
= buf
;
274 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
275 collect_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
276 collect_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
277 collect_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
278 collect_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
282 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
284 const struct user_pt_regs
*regset
= buf
;
287 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
288 supply_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
289 supply_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
290 supply_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
291 supply_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
295 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
297 struct user_fpsimd_state
*regset
= buf
;
300 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
301 collect_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
305 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
307 const struct user_fpsimd_state
*regset
= buf
;
310 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
311 supply_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
314 /* Debugging of hardware breakpoint/watchpoint support. */
315 extern int debug_hw_points
;
317 /* Enable miscellaneous debugging output. The name is historical - it
318 was originally used to debug LinuxThreads support. */
319 extern int debug_threads
;
322 aarch64_get_pc (struct regcache
*regcache
)
326 collect_register_by_name (regcache
, "pc", &pc
);
328 fprintf (stderr
, "stop pc is %08lx\n", pc
);
333 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
335 unsigned long newpc
= pc
;
336 supply_register_by_name (regcache
, "pc", &newpc
);
339 /* Correct in either endianness. */
341 #define aarch64_breakpoint_len 4
343 static const unsigned long aarch64_breakpoint
= 0x00800011;
346 aarch64_breakpoint_at (CORE_ADDR where
)
350 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
351 if (insn
== aarch64_breakpoint
)
357 /* Print the values of the cached breakpoint/watchpoint registers.
358 This is enabled via the "set debug-hw-points" monitor command. */
361 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state
*state
,
362 const char *func
, CORE_ADDR addr
,
363 int len
, enum target_point_type type
)
367 fprintf (stderr
, "%s", func
);
369 fprintf (stderr
, " (addr=0x%08lx, len=%d, type=%s)",
370 (unsigned long) addr
, len
,
371 type
== hw_write
? "hw-write-watchpoint"
372 : (type
== hw_read
? "hw-read-watchpoint"
373 : (type
== hw_access
? "hw-access-watchpoint"
374 : (type
== hw_execute
? "hw-breakpoint"
376 fprintf (stderr
, ":\n");
378 fprintf (stderr
, "\tBREAKPOINTs:\n");
379 for (i
= 0; i
< aarch64_num_bp_regs
; i
++)
380 fprintf (stderr
, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
381 i
, paddress (state
->dr_addr_bp
[i
]),
382 state
->dr_ctrl_bp
[i
], state
->dr_ref_count_bp
[i
]);
384 fprintf (stderr
, "\tWATCHPOINTs:\n");
385 for (i
= 0; i
< aarch64_num_wp_regs
; i
++)
386 fprintf (stderr
, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
387 i
, paddress (state
->dr_addr_wp
[i
]),
388 state
->dr_ctrl_wp
[i
], state
->dr_ref_count_wp
[i
]);
392 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
396 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
398 state
->dr_addr_bp
[i
] = 0;
399 state
->dr_ctrl_bp
[i
] = 0;
400 state
->dr_ref_count_bp
[i
] = 0;
403 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
405 state
->dr_addr_wp
[i
] = 0;
406 state
->dr_ctrl_wp
[i
] = 0;
407 state
->dr_ref_count_wp
[i
] = 0;
411 /* ptrace expects control registers to be formatted as follows:
414 +--------------------------------+----------+------+------+----+
415 | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
416 +--------------------------------+----------+------+------+----+
418 The TYPE field is ignored for breakpoints. */
420 #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
421 #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
423 /* Utility function that returns the length in bytes of a watchpoint
424 according to the content of a hardware debug control register CTRL.
425 Note that the kernel currently only supports the following Byte
426 Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
427 that for a hardware watchpoint, its valid length can only be 1
428 byte, 2 bytes, 4 bytes or 8 bytes. */
430 static inline unsigned int
431 aarch64_watchpoint_length (unsigned int ctrl
)
433 switch (DR_CONTROL_LENGTH (ctrl
))
448 /* Given the hardware breakpoint or watchpoint type TYPE and its
449 length LEN, return the expected encoding for a hardware
450 breakpoint/watchpoint control register. */
453 aarch64_point_encode_ctrl_reg (enum target_point_type type
, int len
)
460 ctrl
|= ((1 << len
) - 1) << 5;
462 ctrl
|= (2 << 1) | 1;
467 /* Addresses to be written to the hardware breakpoint and watchpoint
468 value registers need to be aligned; the alignment is 4-byte and
469 8-type respectively. Linux kernel rejects any non-aligned address
470 it receives from the related ptrace call. Furthermore, the kernel
471 currently only supports the following Byte Address Select (BAS)
472 values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
473 watchpoint to be accepted by the kernel (via ptrace call), its
474 valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
475 Despite these limitations, the unaligned watchpoint is supported in
478 Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
481 aarch64_point_is_aligned (int is_watchpoint
, CORE_ADDR addr
, int len
)
483 unsigned int alignment
= is_watchpoint
? AARCH64_HWP_ALIGNMENT
484 : AARCH64_HBP_ALIGNMENT
;
486 if (addr
& (alignment
- 1))
489 if (len
!= 8 && len
!= 4 && len
!= 2 && len
!= 1)
495 /* Given the (potentially unaligned) watchpoint address in ADDR and
496 length in LEN, return the aligned address and aligned length in
497 *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
498 aligned address and length will be valid to be written to the
499 hardware watchpoint value and control registers. See the comment
500 above aarch64_point_is_aligned for the information about the
501 alignment requirement. The given watchpoint may get truncated if
502 more than one hardware register is needed to cover the watched
503 region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
504 address and length of the remaining part of the watchpoint (which
505 can be processed by calling this routine again to generate another
506 aligned address and length pair.
508 Essentially, unaligned watchpoint is achieved by minimally
509 enlarging the watched area to meet the alignment requirement, and
510 if necessary, splitting the watchpoint over several hardware
511 watchpoint registers. The trade-off is that there will be
512 false-positive hits for the read-type or the access-type hardware
513 watchpoints; for the write type, which is more commonly used, there
514 will be no such issues, as the higher-level breakpoint management
515 in gdb always examines the exact watched region for any content
516 change, and transparently resumes a thread from a watchpoint trap
517 if there is no change to the watched region.
519 Another limitation is that because the watched region is enlarged,
520 the watchpoint fault address returned by
521 aarch64_stopped_data_address may be outside of the original watched
522 region, especially when the triggering instruction is accessing a
523 larger region. When the fault address is not within any known
524 range, watchpoints_triggered in gdb will get confused, as the
525 higher-level watchpoint management is only aware of original
526 watched regions, and will think that some unknown watchpoint has
527 been triggered. In such a case, gdb may stop without displaying
528 any detailed information.
530 Once the kernel provides the full support for Byte Address Select
531 (BAS) in the hardware watchpoint control register, these
532 limitations can be largely relaxed with some further work. */
535 aarch64_align_watchpoint (CORE_ADDR addr
, int len
, CORE_ADDR
*aligned_addr_p
,
536 int *aligned_len_p
, CORE_ADDR
*next_addr_p
,
541 CORE_ADDR aligned_addr
;
542 const unsigned int alignment
= AARCH64_HWP_ALIGNMENT
;
543 const unsigned int max_wp_len
= AARCH64_HWP_MAX_LEN_PER_REG
;
545 /* As assumed by the algorithm. */
546 gdb_assert (alignment
== max_wp_len
);
551 /* Address to be put into the hardware watchpoint value register
553 offset
= addr
& (alignment
- 1);
554 aligned_addr
= addr
- offset
;
556 gdb_assert (offset
>= 0 && offset
< alignment
);
557 gdb_assert (aligned_addr
>= 0 && aligned_addr
<= addr
);
558 gdb_assert ((offset
+ len
) > 0);
560 if (offset
+ len
>= max_wp_len
)
562 /* Need more than one watchpoint registers; truncate it at the
563 alignment boundary. */
564 aligned_len
= max_wp_len
;
565 len
-= (max_wp_len
- offset
);
566 addr
+= (max_wp_len
- offset
);
567 gdb_assert ((addr
& (alignment
- 1)) == 0);
571 /* Find the smallest valid length that is large enough to
572 accommodate this watchpoint. */
573 static const unsigned char
574 aligned_len_array
[AARCH64_HWP_MAX_LEN_PER_REG
] =
575 { 1, 2, 4, 4, 8, 8, 8, 8 };
577 aligned_len
= aligned_len_array
[offset
+ len
- 1];
582 if (aligned_addr_p
!= NULL
)
583 *aligned_addr_p
= aligned_addr
;
584 if (aligned_len_p
!= NULL
)
585 *aligned_len_p
= aligned_len
;
586 if (next_addr_p
!= NULL
)
588 if (next_len_p
!= NULL
)
592 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
593 registers with data from *STATE. */
596 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state
*state
,
597 int tid
, int watchpoint
)
601 struct user_hwdebug_state regs
;
602 const CORE_ADDR
*addr
;
603 const unsigned int *ctrl
;
605 iov
.iov_base
= ®s
;
606 iov
.iov_len
= sizeof (regs
);
607 count
= watchpoint
? aarch64_num_wp_regs
: aarch64_num_bp_regs
;
608 addr
= watchpoint
? state
->dr_addr_wp
: state
->dr_addr_bp
;
609 ctrl
= watchpoint
? state
->dr_ctrl_wp
: state
->dr_ctrl_bp
;
611 for (i
= 0; i
< count
; i
++)
613 regs
.dbg_regs
[i
].addr
= addr
[i
];
614 regs
.dbg_regs
[i
].ctrl
= ctrl
[i
];
617 if (ptrace (PTRACE_SETREGSET
, tid
,
618 watchpoint
? NT_ARM_HW_WATCH
: NT_ARM_HW_BREAK
,
620 error (_("Unexpected error setting hardware debug registers"));
623 struct aarch64_dr_update_callback_param
630 /* Callback function which records the information about the change of
631 one hardware breakpoint/watchpoint setting for the thread ENTRY.
632 The information is passed in via PTR.
633 N.B. The actual updating of hardware debug registers is not
634 carried out until the moment the thread is resumed. */
637 debug_reg_change_callback (struct inferior_list_entry
*entry
, void *ptr
)
639 struct lwp_info
*lwp
= (struct lwp_info
*) entry
;
640 struct aarch64_dr_update_callback_param
*param_p
641 = (struct aarch64_dr_update_callback_param
*) ptr
;
642 int pid
= param_p
->pid
;
643 int idx
= param_p
->idx
;
644 int is_watchpoint
= param_p
->is_watchpoint
;
645 struct arch_lwp_info
*info
= lwp
->arch_private
;
646 dr_changed_t
*dr_changed_ptr
;
647 dr_changed_t dr_changed
;
651 fprintf (stderr
, "debug_reg_change_callback: \n\tOn entry:\n");
652 fprintf (stderr
, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
653 "dr_changed_wp=0x%llx\n",
654 pid
, lwpid_of (lwp
), info
->dr_changed_bp
,
655 info
->dr_changed_wp
);
658 dr_changed_ptr
= is_watchpoint
? &info
->dr_changed_wp
659 : &info
->dr_changed_bp
;
660 dr_changed
= *dr_changed_ptr
;
662 /* Only update the threads of this process. */
663 if (pid_of (lwp
) == pid
)
666 && (idx
<= (is_watchpoint
? aarch64_num_wp_regs
667 : aarch64_num_bp_regs
)));
669 /* The following assertion is not right, as there can be changes
670 that have not been made to the hardware debug registers
671 before new changes overwrite the old ones. This can happen,
672 for instance, when the breakpoint/watchpoint hit one of the
673 threads and the user enters continue; then what happens is:
674 1) all breakpoints/watchpoints are removed for all threads;
675 2) a single step is carried out for the thread that was hit;
676 3) all of the points are inserted again for all threads;
677 4) all threads are resumed.
678 The 2nd step will only affect the one thread in which the
679 bp/wp was hit, which means only that one thread is resumed;
680 remember that the actual updating only happen in
681 aarch64_linux_prepare_to_resume, so other threads remain
682 stopped during the removal and insertion of bp/wp. Therefore
683 for those threads, the change of insertion of the bp/wp
684 overwrites that of the earlier removals. (The situation may
685 be different when bp/wp is steppable, or in the non-stop
687 /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */
689 /* The actual update is done later just before resuming the lwp,
690 we just mark that one register pair needs updating. */
691 DR_MARK_N_CHANGED (dr_changed
, idx
);
692 *dr_changed_ptr
= dr_changed
;
694 /* If the lwp isn't stopped, force it to momentarily pause, so
695 we can update its debug registers. */
697 linux_stop_lwp (lwp
);
702 fprintf (stderr
, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, "
703 "dr_changed_wp=0x%llx\n",
704 pid
, lwpid_of (lwp
), info
->dr_changed_bp
, info
->dr_changed_wp
);
710 /* Notify each thread that their IDXth breakpoint/watchpoint register
711 pair needs to be updated. The message will be recorded in each
712 thread's arch-specific data area, the actual updating will be done
713 when the thread is resumed. */
716 aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state
*state
,
717 int is_watchpoint
, unsigned int idx
)
719 struct aarch64_dr_update_callback_param param
;
721 /* Only update the threads of this process. */
722 param
.pid
= pid_of (get_thread_lwp (current_inferior
));
724 param
.is_watchpoint
= is_watchpoint
;
727 find_inferior (&all_lwps
, debug_reg_change_callback
, (void *) ¶m
);
731 /* Return the pointer to the debug register state structure in the
732 current process' arch-specific data area. */
734 static struct aarch64_debug_reg_state
*
735 aarch64_get_debug_reg_state ()
737 struct process_info
*proc
;
739 proc
= current_process ();
740 return &proc
->private->arch_private
->debug_reg_state
;
743 /* Record the insertion of one breakpoint/watchpoint, as represented
744 by ADDR and CTRL, in the process' arch-specific data area *STATE. */
747 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state
*state
,
748 enum target_point_type type
,
749 CORE_ADDR addr
, int len
)
751 int i
, idx
, num_regs
, is_watchpoint
;
752 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
753 CORE_ADDR
*dr_addr_p
;
755 /* Set up state pointers. */
756 is_watchpoint
= (type
!= hw_execute
);
757 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
760 num_regs
= aarch64_num_wp_regs
;
761 dr_addr_p
= state
->dr_addr_wp
;
762 dr_ctrl_p
= state
->dr_ctrl_wp
;
763 dr_ref_count
= state
->dr_ref_count_wp
;
767 num_regs
= aarch64_num_bp_regs
;
768 dr_addr_p
= state
->dr_addr_bp
;
769 dr_ctrl_p
= state
->dr_ctrl_bp
;
770 dr_ref_count
= state
->dr_ref_count_bp
;
773 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
775 /* Find an existing or free register in our cache. */
777 for (i
= 0; i
< num_regs
; ++i
)
779 if ((dr_ctrl_p
[i
] & 1) == 0)
781 gdb_assert (dr_ref_count
[i
] == 0);
783 /* no break; continue hunting for an exising one. */
785 else if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
787 gdb_assert (dr_ref_count
[i
] != 0);
797 /* Update our cache. */
798 if ((dr_ctrl_p
[idx
] & 1) == 0)
801 dr_addr_p
[idx
] = addr
;
802 dr_ctrl_p
[idx
] = ctrl
;
803 dr_ref_count
[idx
] = 1;
804 /* Notify the change. */
805 aarch64_notify_debug_reg_change (state
, is_watchpoint
, idx
);
816 /* Record the removal of one breakpoint/watchpoint, as represented by
817 ADDR and CTRL, in the process' arch-specific data area *STATE. */
820 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state
*state
,
821 enum target_point_type type
,
822 CORE_ADDR addr
, int len
)
824 int i
, num_regs
, is_watchpoint
;
825 unsigned int ctrl
, *dr_ctrl_p
, *dr_ref_count
;
826 CORE_ADDR
*dr_addr_p
;
828 /* Set up state pointers. */
829 is_watchpoint
= (type
!= hw_execute
);
830 gdb_assert (aarch64_point_is_aligned (is_watchpoint
, addr
, len
));
833 num_regs
= aarch64_num_wp_regs
;
834 dr_addr_p
= state
->dr_addr_wp
;
835 dr_ctrl_p
= state
->dr_ctrl_wp
;
836 dr_ref_count
= state
->dr_ref_count_wp
;
840 num_regs
= aarch64_num_bp_regs
;
841 dr_addr_p
= state
->dr_addr_bp
;
842 dr_ctrl_p
= state
->dr_ctrl_bp
;
843 dr_ref_count
= state
->dr_ref_count_bp
;
846 ctrl
= aarch64_point_encode_ctrl_reg (type
, len
);
848 /* Find the entry that matches the ADDR and CTRL. */
849 for (i
= 0; i
< num_regs
; ++i
)
850 if (dr_addr_p
[i
] == addr
&& dr_ctrl_p
[i
] == ctrl
)
852 gdb_assert (dr_ref_count
[i
] != 0);
860 /* Clear our cache. */
861 if (--dr_ref_count
[i
] == 0)
863 /* Clear the enable bit. */
867 /* Notify the change. */
868 aarch64_notify_debug_reg_change (state
, is_watchpoint
, i
);
875 aarch64_handle_breakpoint (enum target_point_type type
, CORE_ADDR addr
,
876 int len
, int is_insert
)
878 struct aarch64_debug_reg_state
*state
;
880 /* The hardware breakpoint on AArch64 should always be 4-byte
882 if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr
, len
))
885 state
= aarch64_get_debug_reg_state ();
888 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
890 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
893 /* This is essentially the same as aarch64_handle_breakpoint, apart
894 from that it is an aligned watchpoint to be handled. */
897 aarch64_handle_aligned_watchpoint (enum target_point_type type
,
898 CORE_ADDR addr
, int len
, int is_insert
)
900 struct aarch64_debug_reg_state
*state
;
902 state
= aarch64_get_debug_reg_state ();
905 return aarch64_dr_state_insert_one_point (state
, type
, addr
, len
);
907 return aarch64_dr_state_remove_one_point (state
, type
, addr
, len
);
910 /* Insert/remove unaligned watchpoint by calling
911 aarch64_align_watchpoint repeatedly until the whole watched region,
912 as represented by ADDR and LEN, has been properly aligned and ready
913 to be written to one or more hardware watchpoint registers.
914 IS_INSERT indicates whether this is an insertion or a deletion.
915 Return 0 if succeed. */
918 aarch64_handle_unaligned_watchpoint (enum target_point_type type
,
919 CORE_ADDR addr
, int len
, int is_insert
)
921 struct aarch64_debug_reg_state
*state
922 = aarch64_get_debug_reg_state ();
926 CORE_ADDR aligned_addr
;
927 int aligned_len
, ret
;
929 aarch64_align_watchpoint (addr
, len
, &aligned_addr
, &aligned_len
,
933 ret
= aarch64_dr_state_insert_one_point (state
, type
, aligned_addr
,
936 ret
= aarch64_dr_state_remove_one_point (state
, type
, aligned_addr
,
941 "handle_unaligned_watchpoint: is_insert: %d\n"
942 " aligned_addr: 0x%s, aligned_len: %d\n"
943 " next_addr: 0x%s, next_len: %d\n",
944 is_insert
, paddress (aligned_addr
), aligned_len
,
945 paddress (addr
), len
);
955 aarch64_handle_watchpoint (enum target_point_type type
, CORE_ADDR addr
,
956 int len
, int is_insert
)
958 if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr
, len
))
959 return aarch64_handle_aligned_watchpoint (type
, addr
, len
, is_insert
);
961 return aarch64_handle_unaligned_watchpoint (type
, addr
, len
, is_insert
);
964 /* Insert a hardware breakpoint/watchpoint.
965 It actually only records the info of the to-be-inserted bp/wp;
966 the actual insertion will happen when threads are resumed.
969 Return 1 if TYPE is unsupported type;
970 Return -1 if an error occurs. */
973 aarch64_insert_point (char type
, CORE_ADDR addr
, int len
)
976 enum target_point_type targ_type
;
979 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
980 (unsigned long) addr
, len
);
982 /* Determine the type from the packet. */
983 targ_type
= Z_packet_to_point_type (type
);
984 if (targ_type
== point_type_unsupported
)
987 if (targ_type
!= hw_execute
)
989 aarch64_handle_watchpoint (targ_type
, addr
, len
, 1 /* is_insert */);
992 aarch64_handle_breakpoint (targ_type
, addr
, len
, 1 /* is_insert */);
994 if (debug_hw_points
> 1)
995 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
996 "insert_point", addr
, len
, targ_type
);
1001 /* Remove a hardware breakpoint/watchpoint.
1002 It actually only records the info of the to-be-removed bp/wp,
1003 the actual removal will be done when threads are resumed.
1005 Return 0 if succeed;
1006 Return 1 if TYPE is an unsupported type;
1007 Return -1 if an error occurs. */
1010 aarch64_remove_point (char type
, CORE_ADDR addr
, int len
)
1013 enum target_point_type targ_type
;
1015 if (debug_hw_points
)
1016 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
1017 (unsigned long) addr
, len
);
1019 /* Determine the type from the packet. */
1020 targ_type
= Z_packet_to_point_type (type
);
1021 if (targ_type
== point_type_unsupported
)
1024 /* Set up state pointers. */
1025 if (targ_type
!= hw_execute
)
1027 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */);
1030 aarch64_handle_breakpoint (targ_type
, addr
, len
, 0 /* is_insert */);
1032 if (debug_hw_points
> 1)
1033 aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (),
1034 "remove_point", addr
, len
, targ_type
);
1039 /* Returns the address associated with the watchpoint that hit, if
1040 any; returns 0 otherwise. */
1043 aarch64_stopped_data_address (void)
1047 struct aarch64_debug_reg_state
*state
;
1049 pid
= lwpid_of (get_thread_lwp (current_inferior
));
1051 /* Get the siginfo. */
1052 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
1053 return (CORE_ADDR
) 0;
1055 /* Need to be a hardware breakpoint/watchpoint trap. */
1056 if (siginfo
.si_signo
!= SIGTRAP
1057 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
1058 return (CORE_ADDR
) 0;
1060 /* Check if the address matches any watched address. */
1061 state
= aarch64_get_debug_reg_state ();
1062 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
1064 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
1065 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
1066 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
1067 if (state
->dr_ref_count_wp
[i
]
1068 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
1069 && addr_trap
>= addr_watch
1070 && addr_trap
< addr_watch
+ len
)
1074 return (CORE_ADDR
) 0;
1077 /* Returns 1 if target was stopped due to a watchpoint hit, 0
1081 aarch64_stopped_by_watchpoint (void)
1083 if (aarch64_stopped_data_address () != 0)
1089 /* Fetch the thread-local storage pointer for libthread_db. */
1092 ps_get_thread_area (const struct ps_prochandle
*ph
,
1093 lwpid_t lwpid
, int idx
, void **base
)
1098 iovec
.iov_base
= ®
;
1099 iovec
.iov_len
= sizeof (reg
);
1101 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
1104 /* IDX is the bias from the thread pointer to the beginning of the
1105 thread descriptor. It has to be subtracted due to implementation
1106 quirks in libthread_db. */
1107 *base
= (void *) (reg
- idx
);
1112 /* Called when a new process is created. */
1114 static struct arch_process_info
*
1115 aarch64_linux_new_process (void)
1117 struct arch_process_info
*info
= xcalloc (1, sizeof (*info
));
1119 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
1124 /* Called when a new thread is detected. */
1126 static struct arch_lwp_info
*
1127 aarch64_linux_new_thread (void)
1129 struct arch_lwp_info
*info
= xcalloc (1, sizeof (*info
));
1131 /* Mark that all the hardware breakpoint/watchpoint register pairs
1132 for this thread need to be initialized (with data from
1133 aarch_process_info.debug_reg_state). */
1134 DR_MARK_ALL_CHANGED (info
->dr_changed_bp
, aarch64_num_bp_regs
);
1135 DR_MARK_ALL_CHANGED (info
->dr_changed_wp
, aarch64_num_wp_regs
);
1140 /* Called when resuming a thread.
1141 If the debug regs have changed, update the thread's copies. */
1144 aarch64_linux_prepare_to_resume (struct lwp_info
*lwp
)
1146 ptid_t ptid
= ptid_of (lwp
);
1147 struct arch_lwp_info
*info
= lwp
->arch_private
;
1149 if (DR_HAS_CHANGED (info
->dr_changed_bp
)
1150 || DR_HAS_CHANGED (info
->dr_changed_wp
))
1152 int tid
= ptid_get_lwp (ptid
);
1153 struct process_info
*proc
= find_process_pid (ptid_get_pid (ptid
));
1154 struct aarch64_debug_reg_state
*state
1155 = &proc
->private->arch_private
->debug_reg_state
;
1157 if (debug_hw_points
)
1158 fprintf (stderr
, "prepare_to_resume thread %ld\n", lwpid_of (lwp
));
1161 if (DR_HAS_CHANGED (info
->dr_changed_wp
))
1163 aarch64_linux_set_debug_regs (state
, tid
, 1);
1164 DR_CLEAR_CHANGED (info
->dr_changed_wp
);
1168 if (DR_HAS_CHANGED (info
->dr_changed_bp
))
1170 aarch64_linux_set_debug_regs (state
, tid
, 0);
1171 DR_CLEAR_CHANGED (info
->dr_changed_bp
);
1176 /* ptrace hardware breakpoint resource info is formatted as follows:
1179 +---------------+--------------+---------------+---------------+
1180 | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
1181 +---------------+--------------+---------------+---------------+ */
1183 #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
1184 #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
1185 #define AARCH64_DEBUG_ARCH_V8 0x6
1188 aarch64_arch_setup (void)
1192 struct user_hwdebug_state dreg_state
;
1194 init_registers_aarch64 ();
1196 pid
= lwpid_of (get_thread_lwp (current_inferior
));
1197 iov
.iov_base
= &dreg_state
;
1198 iov
.iov_len
= sizeof (dreg_state
);
1200 /* Get hardware watchpoint register info. */
1201 if (ptrace (PTRACE_GETREGSET
, pid
, NT_ARM_HW_WATCH
, &iov
) == 0
1202 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
1204 aarch64_num_wp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
1205 if (aarch64_num_wp_regs
> AARCH64_HWP_MAX_NUM
)
1207 warning ("Unexpected number of hardware watchpoint registers reported"
1208 " by ptrace, got %d, expected %d.",
1209 aarch64_num_wp_regs
, AARCH64_HWP_MAX_NUM
);
1210 aarch64_num_wp_regs
= AARCH64_HWP_MAX_NUM
;
1215 warning ("Unable to determine the number of hardware watchpoints"
1217 aarch64_num_wp_regs
= 0;
1220 /* Get hardware breakpoint register info. */
1221 if (ptrace (PTRACE_GETREGSET
, pid
, NT_ARM_HW_BREAK
, &iov
) == 0
1222 && AARCH64_DEBUG_ARCH (dreg_state
.dbg_info
) == AARCH64_DEBUG_ARCH_V8
)
1224 aarch64_num_bp_regs
= AARCH64_DEBUG_NUM_SLOTS (dreg_state
.dbg_info
);
1225 if (aarch64_num_bp_regs
> AARCH64_HBP_MAX_NUM
)
1227 warning ("Unexpected number of hardware breakpoint registers reported"
1228 " by ptrace, got %d, expected %d.",
1229 aarch64_num_bp_regs
, AARCH64_HBP_MAX_NUM
);
1230 aarch64_num_bp_regs
= AARCH64_HBP_MAX_NUM
;
1235 warning ("Unable to determine the number of hardware breakpoints"
1237 aarch64_num_bp_regs
= 0;
1241 struct regset_info target_regsets
[] =
1243 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
1244 sizeof (struct user_pt_regs
), GENERAL_REGS
,
1245 aarch64_fill_gregset
, aarch64_store_gregset
},
1246 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
1247 sizeof (struct user_fpsimd_state
), FP_REGS
,
1248 aarch64_fill_fpregset
, aarch64_store_fpregset
1250 { 0, 0, 0, -1, -1, NULL
, NULL
}
1253 struct linux_target_ops the_low_target
=
1259 aarch64_cannot_fetch_register
,
1260 aarch64_cannot_store_register
,
1264 (const unsigned char *) &aarch64_breakpoint
,
1265 aarch64_breakpoint_len
,
1268 aarch64_breakpoint_at
,
1269 aarch64_insert_point
,
1270 aarch64_remove_point
,
1271 aarch64_stopped_by_watchpoint
,
1272 aarch64_stopped_data_address
,
1276 aarch64_linux_new_process
,
1277 aarch64_linux_new_thread
,
1278 aarch64_linux_prepare_to_resume
,