1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
42 /* Defined in auto-generated files. */
43 void init_registers_aarch64 (void);
44 extern const struct target_desc
*tdesc_aarch64
;
50 #define AARCH64_X_REGS_NUM 31
51 #define AARCH64_V_REGS_NUM 32
52 #define AARCH64_X0_REGNO 0
53 #define AARCH64_SP_REGNO 31
54 #define AARCH64_PC_REGNO 32
55 #define AARCH64_CPSR_REGNO 33
56 #define AARCH64_V0_REGNO 34
57 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
58 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
60 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
62 /* Per-process arch-specific data we want to keep. */
64 struct arch_process_info
66 /* Hardware breakpoint/watchpoint data.
67 The reason for them to be per-process rather than per-thread is
68 due to the lack of information in the gdbserver environment;
69 gdbserver is not told that whether a requested hardware
70 breakpoint/watchpoint is thread specific or not, so it has to set
71 each hw bp/wp for every thread in the current process. The
72 higher level bp/wp management in gdb will resume a thread if a hw
73 bp/wp trap is not expected for it. Since the hw bp/wp setting is
74 same for each thread, it is reasonable for the data to live here.
76 struct aarch64_debug_reg_state debug_reg_state
;
79 /* Return true if the size of register 0 is 8 byte. */
84 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
86 return register_size (regcache
->tdesc
, 0) == 8;
89 /* Implementation of linux_target_ops method "cannot_store_register". */
92 aarch64_cannot_store_register (int regno
)
94 return regno
>= AARCH64_NUM_REGS
;
97 /* Implementation of linux_target_ops method "cannot_fetch_register". */
100 aarch64_cannot_fetch_register (int regno
)
102 return regno
>= AARCH64_NUM_REGS
;
106 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
108 struct user_pt_regs
*regset
= buf
;
111 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
112 collect_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
113 collect_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
114 collect_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
115 collect_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
119 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
121 const struct user_pt_regs
*regset
= buf
;
124 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
125 supply_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
126 supply_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
127 supply_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
128 supply_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
132 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
134 struct user_fpsimd_state
*regset
= buf
;
137 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
138 collect_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
139 collect_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
140 collect_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
144 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
146 const struct user_fpsimd_state
*regset
= buf
;
149 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
150 supply_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
151 supply_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
152 supply_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
155 /* Enable miscellaneous debugging output. The name is historical - it
156 was originally used to debug LinuxThreads support. */
157 extern int debug_threads
;
159 /* Implementation of linux_target_ops method "get_pc". */
162 aarch64_get_pc (struct regcache
*regcache
)
164 if (register_size (regcache
->tdesc
, 0) == 8)
168 collect_register_by_name (regcache
, "pc", &pc
);
170 debug_printf ("stop pc is %08lx\n", pc
);
177 collect_register_by_name (regcache
, "pc", &pc
);
179 debug_printf ("stop pc is %04x\n", pc
);
184 /* Implementation of linux_target_ops method "set_pc". */
187 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
189 if (register_size (regcache
->tdesc
, 0) == 8)
191 unsigned long newpc
= pc
;
192 supply_register_by_name (regcache
, "pc", &newpc
);
196 unsigned int newpc
= pc
;
197 supply_register_by_name (regcache
, "pc", &newpc
);
201 #define aarch64_breakpoint_len 4
203 /* AArch64 BRK software debug mode instruction.
204 This instruction needs to match gdb/aarch64-tdep.c
205 (aarch64_default_breakpoint). */
206 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
208 /* Implementation of linux_target_ops method "breakpoint_at". */
211 aarch64_breakpoint_at (CORE_ADDR where
)
213 gdb_byte insn
[aarch64_breakpoint_len
];
215 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
216 aarch64_breakpoint_len
);
217 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
224 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
228 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
230 state
->dr_addr_bp
[i
] = 0;
231 state
->dr_ctrl_bp
[i
] = 0;
232 state
->dr_ref_count_bp
[i
] = 0;
235 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
237 state
->dr_addr_wp
[i
] = 0;
238 state
->dr_ctrl_wp
[i
] = 0;
239 state
->dr_ref_count_wp
[i
] = 0;
243 /* Return the pointer to the debug register state structure in the
244 current process' arch-specific data area. */
246 struct aarch64_debug_reg_state
*
247 aarch64_get_debug_reg_state (pid_t pid
)
249 struct process_info
*proc
= find_process_pid (pid
);
251 return &proc
->priv
->arch_private
->debug_reg_state
;
254 /* Implementation of linux_target_ops method "supports_z_point_type". */
257 aarch64_supports_z_point_type (char z_type
)
263 if (!extended_protocol
&& is_64bit_tdesc ())
265 /* Only enable Z0 packet in non-multi-arch debugging. If
266 extended protocol is used, don't enable Z0 packet because
267 GDBserver may attach to 32-bit process. */
272 /* Disable Z0 packet so that GDBserver doesn't have to handle
273 different breakpoint instructions (aarch64, arm, thumb etc)
274 in multi-arch debugging. */
279 case Z_PACKET_WRITE_WP
:
280 case Z_PACKET_READ_WP
:
281 case Z_PACKET_ACCESS_WP
:
288 /* Implementation of linux_target_ops method "insert_point".
290 It actually only records the info of the to-be-inserted bp/wp;
291 the actual insertion will happen when threads are resumed. */
294 aarch64_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
295 int len
, struct raw_breakpoint
*bp
)
298 enum target_hw_bp_type targ_type
;
299 struct aarch64_debug_reg_state
*state
300 = aarch64_get_debug_reg_state (pid_of (current_thread
));
303 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
304 (unsigned long) addr
, len
);
306 /* Determine the type from the raw breakpoint type. */
307 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
309 if (targ_type
!= hw_execute
)
311 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
312 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
313 1 /* is_insert */, state
);
319 aarch64_handle_breakpoint (targ_type
, addr
, len
, 1 /* is_insert */,
323 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
329 /* Implementation of linux_target_ops method "remove_point".
331 It actually only records the info of the to-be-removed bp/wp,
332 the actual removal will be done when threads are resumed. */
335 aarch64_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
336 int len
, struct raw_breakpoint
*bp
)
339 enum target_hw_bp_type targ_type
;
340 struct aarch64_debug_reg_state
*state
341 = aarch64_get_debug_reg_state (pid_of (current_thread
));
344 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
345 (unsigned long) addr
, len
);
347 /* Determine the type from the raw breakpoint type. */
348 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
350 /* Set up state pointers. */
351 if (targ_type
!= hw_execute
)
353 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
357 aarch64_handle_breakpoint (targ_type
, addr
, len
, 0 /* is_insert */,
361 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
367 /* Implementation of linux_target_ops method "stopped_data_address". */
370 aarch64_stopped_data_address (void)
374 struct aarch64_debug_reg_state
*state
;
376 pid
= lwpid_of (current_thread
);
378 /* Get the siginfo. */
379 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
380 return (CORE_ADDR
) 0;
382 /* Need to be a hardware breakpoint/watchpoint trap. */
383 if (siginfo
.si_signo
!= SIGTRAP
384 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
385 return (CORE_ADDR
) 0;
387 /* Check if the address matches any watched address. */
388 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
389 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
391 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
392 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
393 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
394 if (state
->dr_ref_count_wp
[i
]
395 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
396 && addr_trap
>= addr_watch
397 && addr_trap
< addr_watch
+ len
)
401 return (CORE_ADDR
) 0;
404 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
407 aarch64_stopped_by_watchpoint (void)
409 if (aarch64_stopped_data_address () != 0)
415 /* Fetch the thread-local storage pointer for libthread_db. */
418 ps_get_thread_area (const struct ps_prochandle
*ph
,
419 lwpid_t lwpid
, int idx
, void **base
)
421 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
425 /* Implementation of linux_target_ops method "siginfo_fixup". */
428 aarch64_linux_siginfo_fixup (siginfo_t
*native
, void *inf
, int direction
)
430 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
431 if (!is_64bit_tdesc ())
434 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
437 aarch64_siginfo_from_compat_siginfo (native
,
438 (struct compat_siginfo
*) inf
);
446 /* Implementation of linux_target_ops method "linux_new_process". */
448 static struct arch_process_info
*
449 aarch64_linux_new_process (void)
451 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
453 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
458 /* Implementation of linux_target_ops method "linux_new_fork". */
461 aarch64_linux_new_fork (struct process_info
*parent
,
462 struct process_info
*child
)
464 /* These are allocated by linux_add_process. */
465 gdb_assert (parent
->priv
!= NULL
466 && parent
->priv
->arch_private
!= NULL
);
467 gdb_assert (child
->priv
!= NULL
468 && child
->priv
->arch_private
!= NULL
);
470 /* Linux kernel before 2.6.33 commit
471 72f674d203cd230426437cdcf7dd6f681dad8b0d
472 will inherit hardware debug registers from parent
473 on fork/vfork/clone. Newer Linux kernels create such tasks with
474 zeroed debug registers.
476 GDB core assumes the child inherits the watchpoints/hw
477 breakpoints of the parent, and will remove them all from the
478 forked off process. Copy the debug registers mirrors into the
479 new process so that all breakpoints and watchpoints can be
480 removed together. The debug registers mirror will become zeroed
481 in the end before detaching the forked off process, thus making
482 this compatible with older Linux kernels too. */
484 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
487 /* Return the right target description according to the ELF file of
490 static const struct target_desc
*
491 aarch64_linux_read_description (void)
493 unsigned int machine
;
497 tid
= lwpid_of (current_thread
);
499 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
502 return tdesc_aarch64
;
504 return tdesc_arm_with_neon
;
507 /* Implementation of linux_target_ops method "arch_setup". */
510 aarch64_arch_setup (void)
512 current_process ()->tdesc
= aarch64_linux_read_description ();
514 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
517 static struct regset_info aarch64_regsets
[] =
519 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
520 sizeof (struct user_pt_regs
), GENERAL_REGS
,
521 aarch64_fill_gregset
, aarch64_store_gregset
},
522 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
523 sizeof (struct user_fpsimd_state
), FP_REGS
,
524 aarch64_fill_fpregset
, aarch64_store_fpregset
526 { 0, 0, 0, -1, -1, NULL
, NULL
}
529 static struct regsets_info aarch64_regsets_info
=
531 aarch64_regsets
, /* regsets */
533 NULL
, /* disabled_regsets */
536 static struct regs_info regs_info_aarch64
=
538 NULL
, /* regset_bitmap */
540 &aarch64_regsets_info
,
543 /* Implementation of linux_target_ops method "regs_info". */
545 static const struct regs_info
*
546 aarch64_regs_info (void)
548 if (is_64bit_tdesc ())
549 return ®s_info_aarch64
;
551 return ®s_info_aarch32
;
554 /* Implementation of linux_target_ops method "supports_tracepoints". */
557 aarch64_supports_tracepoints (void)
559 if (current_thread
== NULL
)
563 /* We don't support tracepoints on aarch32 now. */
564 return is_64bit_tdesc ();
568 /* Implementation of linux_target_ops method "get_thread_area". */
571 aarch64_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
576 iovec
.iov_base
= ®
;
577 iovec
.iov_len
= sizeof (reg
);
579 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
587 /* List of condition codes that we need. */
589 enum aarch64_condition_codes
600 /* Representation of an operand. At this time, it only supports register
601 and immediate types. */
603 struct aarch64_operand
605 /* Type of the operand. */
611 /* Value of the operand according to the type. */
615 struct aarch64_register reg
;
619 /* List of registers that we are currently using, we can add more here as
620 we need to use them. */
622 /* General purpose scratch registers (64 bit). */
623 static const struct aarch64_register x0
= { 0, 1 };
624 static const struct aarch64_register x1
= { 1, 1 };
625 static const struct aarch64_register x2
= { 2, 1 };
626 static const struct aarch64_register x3
= { 3, 1 };
627 static const struct aarch64_register x4
= { 4, 1 };
629 /* General purpose scratch registers (32 bit). */
630 static const struct aarch64_register w0
= { 0, 0 };
631 static const struct aarch64_register w2
= { 2, 0 };
633 /* Intra-procedure scratch registers. */
634 static const struct aarch64_register ip0
= { 16, 1 };
636 /* Special purpose registers. */
637 static const struct aarch64_register fp
= { 29, 1 };
638 static const struct aarch64_register lr
= { 30, 1 };
639 static const struct aarch64_register sp
= { 31, 1 };
640 static const struct aarch64_register xzr
= { 31, 1 };
642 /* Dynamically allocate a new register. If we know the register
643 statically, we should make it a global as above instead of using this
646 static struct aarch64_register
647 aarch64_register (unsigned num
, int is64
)
649 return (struct aarch64_register
) { num
, is64
};
652 /* Helper function to create a register operand, for instructions with
653 different types of operands.
656 p += emit_mov (p, x0, register_operand (x1)); */
658 static struct aarch64_operand
659 register_operand (struct aarch64_register reg
)
661 struct aarch64_operand operand
;
663 operand
.type
= OPERAND_REGISTER
;
669 /* Helper function to create an immediate operand, for instructions with
670 different types of operands.
673 p += emit_mov (p, x0, immediate_operand (12)); */
675 static struct aarch64_operand
676 immediate_operand (uint32_t imm
)
678 struct aarch64_operand operand
;
680 operand
.type
= OPERAND_IMMEDIATE
;
686 /* Helper function to create an offset memory operand.
689 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
691 static struct aarch64_memory_operand
692 offset_memory_operand (int32_t offset
)
694 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
697 /* Helper function to create a pre-index memory operand.
700 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
702 static struct aarch64_memory_operand
703 preindex_memory_operand (int32_t index
)
705 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
708 /* Helper function to create a post-index memory operand.
711 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
713 static struct aarch64_memory_operand
714 postindex_memory_operand (int32_t index
)
716 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
719 /* System control registers. These special registers can be written and
720 read with the MRS and MSR instructions.
722 - NZCV: Condition flags. GDB refers to this register under the CPSR
724 - FPSR: Floating-point status register.
725 - FPCR: Floating-point control registers.
726 - TPIDR_EL0: Software thread ID register. */
728 enum aarch64_system_control_registers
730 /* op0 op1 crn crm op2 */
731 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
732 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
733 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
734 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
737 /* Write a BLR instruction into *BUF.
741 RN is the register to branch to. */
744 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
746 return emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
749 /* Write a RET instruction into *BUF.
753 RN is the register to branch to. */
756 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
758 return emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
762 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
763 struct aarch64_register rt
,
764 struct aarch64_register rt2
,
765 struct aarch64_register rn
,
766 struct aarch64_memory_operand operand
)
773 opc
= ENCODE (2, 2, 30);
775 opc
= ENCODE (0, 2, 30);
777 switch (operand
.type
)
779 case MEMORY_OPERAND_OFFSET
:
781 pre_index
= ENCODE (1, 1, 24);
782 write_back
= ENCODE (0, 1, 23);
785 case MEMORY_OPERAND_POSTINDEX
:
787 pre_index
= ENCODE (0, 1, 24);
788 write_back
= ENCODE (1, 1, 23);
791 case MEMORY_OPERAND_PREINDEX
:
793 pre_index
= ENCODE (1, 1, 24);
794 write_back
= ENCODE (1, 1, 23);
801 return emit_insn (buf
, opcode
| opc
| pre_index
| write_back
802 | ENCODE (operand
.index
>> 3, 7, 15)
803 | ENCODE (rt2
.num
, 5, 10)
804 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
807 /* Write a STP instruction into *BUF.
809 STP rt, rt2, [rn, #offset]
810 STP rt, rt2, [rn, #index]!
811 STP rt, rt2, [rn], #index
813 RT and RT2 are the registers to store.
814 RN is the base address register.
815 OFFSET is the immediate to add to the base address. It is limited to a
816 -512 .. 504 range (7 bits << 3). */
819 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
820 struct aarch64_register rt2
, struct aarch64_register rn
,
821 struct aarch64_memory_operand operand
)
823 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
826 /* Write a LDP instruction into *BUF.
828 LDP rt, rt2, [rn, #offset]
829 LDP rt, rt2, [rn, #index]!
830 LDP rt, rt2, [rn], #index
832 RT and RT2 are the registers to store.
833 RN is the base address register.
834 OFFSET is the immediate to add to the base address. It is limited to a
835 -512 .. 504 range (7 bits << 3). */
838 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
839 struct aarch64_register rt2
, struct aarch64_register rn
,
840 struct aarch64_memory_operand operand
)
842 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
845 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
847 LDP qt, qt2, [rn, #offset]
849 RT and RT2 are the Q registers to store.
850 RN is the base address register.
851 OFFSET is the immediate to add to the base address. It is limited to
852 -1024 .. 1008 range (7 bits << 4). */
855 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
856 struct aarch64_register rn
, int32_t offset
)
858 uint32_t opc
= ENCODE (2, 2, 30);
859 uint32_t pre_index
= ENCODE (1, 1, 24);
861 return emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
862 | ENCODE (offset
>> 4, 7, 15) | ENCODE (rt2
, 5, 10)
863 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
866 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
868 STP qt, qt2, [rn, #offset]
870 RT and RT2 are the Q registers to store.
871 RN is the base address register.
872 OFFSET is the immediate to add to the base address. It is limited to
873 -1024 .. 1008 range (7 bits << 4). */
876 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
877 struct aarch64_register rn
, int32_t offset
)
879 uint32_t opc
= ENCODE (2, 2, 30);
880 uint32_t pre_index
= ENCODE (1, 1, 24);
882 return emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
883 | ENCODE (offset
>> 4, 7, 15)
884 | ENCODE (rt2
, 5, 10)
885 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
888 /* Write a LDRH instruction into *BUF.
890 LDRH wt, [xn, #offset]
891 LDRH wt, [xn, #index]!
892 LDRH wt, [xn], #index
894 RT is the register to store.
895 RN is the base address register.
896 OFFSET is the immediate to add to the base address. It is limited to
897 0 .. 32760 range (12 bits << 3). */
900 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
901 struct aarch64_register rn
,
902 struct aarch64_memory_operand operand
)
904 return emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
907 /* Write a LDRB instruction into *BUF.
909 LDRB wt, [xn, #offset]
910 LDRB wt, [xn, #index]!
911 LDRB wt, [xn], #index
913 RT is the register to store.
914 RN is the base address register.
915 OFFSET is the immediate to add to the base address. It is limited to
916 0 .. 32760 range (12 bits << 3). */
919 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
920 struct aarch64_register rn
,
921 struct aarch64_memory_operand operand
)
923 return emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
928 /* Write a STR instruction into *BUF.
930 STR rt, [rn, #offset]
931 STR rt, [rn, #index]!
934 RT is the register to store.
935 RN is the base address register.
936 OFFSET is the immediate to add to the base address. It is limited to
937 0 .. 32760 range (12 bits << 3). */
940 emit_str (uint32_t *buf
, struct aarch64_register rt
,
941 struct aarch64_register rn
,
942 struct aarch64_memory_operand operand
)
944 return emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
947 /* Helper function emitting an exclusive load or store instruction. */
950 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
951 enum aarch64_opcodes opcode
,
952 struct aarch64_register rs
,
953 struct aarch64_register rt
,
954 struct aarch64_register rt2
,
955 struct aarch64_register rn
)
957 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
958 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
959 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
962 /* Write a LAXR instruction into *BUF.
966 RT is the destination register.
967 RN is the base address register. */
970 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
971 struct aarch64_register rn
)
973 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
977 /* Write a STXR instruction into *BUF.
981 RS is the result register, it indicates if the store succeeded or not.
982 RT is the destination register.
983 RN is the base address register. */
986 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
987 struct aarch64_register rt
, struct aarch64_register rn
)
989 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
993 /* Write a STLR instruction into *BUF.
997 RT is the register to store.
998 RN is the base address register. */
1001 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1002 struct aarch64_register rn
)
1004 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1008 /* Helper function for data processing instructions with register sources. */
1011 emit_data_processing_reg (uint32_t *buf
, enum aarch64_opcodes opcode
,
1012 struct aarch64_register rd
,
1013 struct aarch64_register rn
,
1014 struct aarch64_register rm
)
1016 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1018 return emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1019 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1022 /* Helper function for data processing instructions taking either a register
1026 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1027 struct aarch64_register rd
,
1028 struct aarch64_register rn
,
1029 struct aarch64_operand operand
)
1031 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1032 /* The opcode is different for register and immediate source operands. */
1033 uint32_t operand_opcode
;
1035 if (operand
.type
== OPERAND_IMMEDIATE
)
1037 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1038 operand_opcode
= ENCODE (8, 4, 25);
1040 return emit_insn (buf
, opcode
| operand_opcode
| size
1041 | ENCODE (operand
.imm
, 12, 10)
1042 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1046 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1047 operand_opcode
= ENCODE (5, 4, 25);
1049 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1054 /* Write an ADD instruction into *BUF.
1059 This function handles both an immediate and register add.
1061 RD is the destination register.
1062 RN is the input register.
1063 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1064 OPERAND_REGISTER. */
1067 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1068 struct aarch64_register rn
, struct aarch64_operand operand
)
1070 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1073 /* Write a SUB instruction into *BUF.
1078 This function handles both an immediate and register sub.
1080 RD is the destination register.
1081 RN is the input register.
1082 IMM is the immediate to substract to RN. */
1085 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1086 struct aarch64_register rn
, struct aarch64_operand operand
)
1088 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1091 /* Write a MOV instruction into *BUF.
1096 This function handles both a wide immediate move and a register move,
1097 with the condition that the source register is not xzr. xzr and the
1098 stack pointer share the same encoding and this function only supports
1101 RD is the destination register.
1102 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1103 OPERAND_REGISTER. */
1106 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1107 struct aarch64_operand operand
)
1109 if (operand
.type
== OPERAND_IMMEDIATE
)
1111 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1112 /* Do not shift the immediate. */
1113 uint32_t shift
= ENCODE (0, 2, 21);
1115 return emit_insn (buf
, MOV
| size
| shift
1116 | ENCODE (operand
.imm
, 16, 5)
1117 | ENCODE (rd
.num
, 5, 0));
1120 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1123 /* Write a MOVK instruction into *BUF.
1125 MOVK rd, #imm, lsl #shift
1127 RD is the destination register.
1128 IMM is the immediate.
1129 SHIFT is the logical shift left to apply to IMM. */
1132 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1135 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1137 return emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1138 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1141 /* Write instructions into *BUF in order to move ADDR into a register.
1142 ADDR can be a 64-bit value.
1144 This function will emit a series of MOV and MOVK instructions, such as:
1147 MOVK xd, #(addr >> 16), lsl #16
1148 MOVK xd, #(addr >> 32), lsl #32
1149 MOVK xd, #(addr >> 48), lsl #48 */
1152 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1156 /* The MOV (wide immediate) instruction clears to top bits of the
1158 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1160 if ((addr
>> 16) != 0)
1161 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1165 if ((addr
>> 32) != 0)
1166 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1170 if ((addr
>> 48) != 0)
1171 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1176 /* Write a SUBS instruction into *BUF.
1180 This instruction update the condition flags.
1182 RD is the destination register.
1183 RN and RM are the source registers. */
1186 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1187 struct aarch64_register rn
, struct aarch64_operand operand
)
1189 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1192 /* Write a CMP instruction into *BUF.
1196 This instruction is an alias of SUBS xzr, rn, rm.
1198 RN and RM are the registers to compare. */
1201 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1202 struct aarch64_operand operand
)
1204 return emit_subs (buf
, xzr
, rn
, operand
);
1207 /* Write a AND instruction into *BUF.
1211 RD is the destination register.
1212 RN and RM are the source registers. */
1215 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1216 struct aarch64_register rn
, struct aarch64_register rm
)
1218 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1221 /* Write a ORR instruction into *BUF.
1225 RD is the destination register.
1226 RN and RM are the source registers. */
1229 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1230 struct aarch64_register rn
, struct aarch64_register rm
)
1232 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1235 /* Write a ORN instruction into *BUF.
1239 RD is the destination register.
1240 RN and RM are the source registers. */
1243 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1244 struct aarch64_register rn
, struct aarch64_register rm
)
1246 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1249 /* Write a EOR instruction into *BUF.
1253 RD is the destination register.
1254 RN and RM are the source registers. */
1257 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1258 struct aarch64_register rn
, struct aarch64_register rm
)
1260 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1263 /* Write a MVN instruction into *BUF.
1267 This is an alias for ORN rd, xzr, rm.
1269 RD is the destination register.
1270 RM is the source register. */
1273 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1274 struct aarch64_register rm
)
1276 return emit_orn (buf
, rd
, xzr
, rm
);
1279 /* Write a LSLV instruction into *BUF.
1283 RD is the destination register.
1284 RN and RM are the source registers. */
1287 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1288 struct aarch64_register rn
, struct aarch64_register rm
)
1290 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1293 /* Write a LSRV instruction into *BUF.
1297 RD is the destination register.
1298 RN and RM are the source registers. */
1301 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1302 struct aarch64_register rn
, struct aarch64_register rm
)
1304 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1307 /* Write a ASRV instruction into *BUF.
1311 RD is the destination register.
1312 RN and RM are the source registers. */
1315 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1316 struct aarch64_register rn
, struct aarch64_register rm
)
1318 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1321 /* Write a MUL instruction into *BUF.
1325 RD is the destination register.
1326 RN and RM are the source registers. */
1329 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1330 struct aarch64_register rn
, struct aarch64_register rm
)
1332 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1335 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1339 RT is the destination register.
1340 SYSTEM_REG is special purpose register to read. */
1343 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1344 enum aarch64_system_control_registers system_reg
)
1346 return emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1347 | ENCODE (rt
.num
, 5, 0));
1350 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1354 SYSTEM_REG is special purpose register to write.
1355 RT is the input register. */
1358 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1359 struct aarch64_register rt
)
1361 return emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1362 | ENCODE (rt
.num
, 5, 0));
1365 /* Write a SEVL instruction into *BUF.
1367 This is a hint instruction telling the hardware to trigger an event. */
1370 emit_sevl (uint32_t *buf
)
1372 return emit_insn (buf
, SEVL
);
1375 /* Write a WFE instruction into *BUF.
1377 This is a hint instruction telling the hardware to wait for an event. */
1380 emit_wfe (uint32_t *buf
)
1382 return emit_insn (buf
, WFE
);
1385 /* Write a SBFM instruction into *BUF.
1387 SBFM rd, rn, #immr, #imms
1389 This instruction moves the bits from #immr to #imms into the
1390 destination, sign extending the result.
1392 RD is the destination register.
1393 RN is the source register.
1394 IMMR is the bit number to start at (least significant bit).
1395 IMMS is the bit number to stop at (most significant bit). */
1398 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1399 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1401 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1402 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1404 return emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1405 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1406 | ENCODE (rd
.num
, 5, 0));
1409 /* Write a SBFX instruction into *BUF.
1411 SBFX rd, rn, #lsb, #width
1413 This instruction moves #width bits from #lsb into the destination, sign
1414 extending the result. This is an alias for:
1416 SBFM rd, rn, #lsb, #(lsb + width - 1)
1418 RD is the destination register.
1419 RN is the source register.
1420 LSB is the bit number to start at (least significant bit).
1421 WIDTH is the number of bits to move. */
1424 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1425 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1427 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1430 /* Write a UBFM instruction into *BUF.
1432 UBFM rd, rn, #immr, #imms
1434 This instruction moves the bits from #immr to #imms into the
1435 destination, extending the result with zeros.
1437 RD is the destination register.
1438 RN is the source register.
1439 IMMR is the bit number to start at (least significant bit).
1440 IMMS is the bit number to stop at (most significant bit). */
1443 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1444 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1446 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1447 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1449 return emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1450 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1451 | ENCODE (rd
.num
, 5, 0));
1454 /* Write a UBFX instruction into *BUF.
1456 UBFX rd, rn, #lsb, #width
1458 This instruction moves #width bits from #lsb into the destination,
1459 extending the result with zeros. This is an alias for:
1461 UBFM rd, rn, #lsb, #(lsb + width - 1)
1463 RD is the destination register.
1464 RN is the source register.
1465 LSB is the bit number to start at (least significant bit).
1466 WIDTH is the number of bits to move. */
1469 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1470 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1472 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1475 /* Write a CSINC instruction into *BUF.
1477 CSINC rd, rn, rm, cond
1479 This instruction conditionally increments rn or rm and places the result
1480 in rd. rn is chosen is the condition is true.
1482 RD is the destination register.
1483 RN and RM are the source registers.
1484 COND is the encoded condition. */
1487 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1488 struct aarch64_register rn
, struct aarch64_register rm
,
1491 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1493 return emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1494 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1495 | ENCODE (rd
.num
, 5, 0));
1498 /* Write a CSET instruction into *BUF.
1502 This instruction conditionally write 1 or 0 in the destination register.
1503 1 is written if the condition is true. This is an alias for:
1505 CSINC rd, xzr, xzr, !cond
1507 Note that the condition needs to be inverted.
1509 RD is the destination register.
1510 RN and RM are the source registers.
1511 COND is the encoded condition. */
1514 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1516 /* The least significant bit of the condition needs toggling in order to
1518 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1521 /* Write LEN instructions from BUF into the inferior memory at *TO.
1523 Note instructions are always little endian on AArch64, unlike data. */
1526 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1528 size_t byte_len
= len
* sizeof (uint32_t);
1529 #if (__BYTE_ORDER == __BIG_ENDIAN)
1530 uint32_t *le_buf
= xmalloc (byte_len
);
1533 for (i
= 0; i
< len
; i
++)
1534 le_buf
[i
] = htole32 (buf
[i
]);
1536 write_inferior_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1540 write_inferior_memory (*to
, (const unsigned char *) buf
, byte_len
);
1546 /* Sub-class of struct aarch64_insn_data, store information of
1547 instruction relocation for fast tracepoint. Visitor can
1548 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1549 the relocated instructions in buffer pointed by INSN_PTR. */
1551 struct aarch64_insn_relocation_data
1553 struct aarch64_insn_data base
;
1555 /* The new address the instruction is relocated to. */
1557 /* Pointer to the buffer of relocated instruction(s). */
1561 /* Implementation of aarch64_insn_visitor method "b". */
1564 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1565 struct aarch64_insn_data
*data
)
1567 struct aarch64_insn_relocation_data
*insn_reloc
1568 = (struct aarch64_insn_relocation_data
*) data
;
1570 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1572 if (can_encode_int32 (new_offset
, 28))
1573 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1576 /* Implementation of aarch64_insn_visitor method "b_cond". */
1579 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1580 struct aarch64_insn_data
*data
)
1582 struct aarch64_insn_relocation_data
*insn_reloc
1583 = (struct aarch64_insn_relocation_data
*) data
;
1585 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1587 if (can_encode_int32 (new_offset
, 21))
1589 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1592 else if (can_encode_int32 (new_offset
, 28))
1594 /* The offset is out of range for a conditional branch
1595 instruction but not for a unconditional branch. We can use
1596 the following instructions instead:
1598 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1599 B NOT_TAKEN ; Else jump over TAKEN and continue.
1606 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1607 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1608 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1612 /* Implementation of aarch64_insn_visitor method "cb". */
1615 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1616 const unsigned rn
, int is64
,
1617 struct aarch64_insn_data
*data
)
1619 struct aarch64_insn_relocation_data
*insn_reloc
1620 = (struct aarch64_insn_relocation_data
*) data
;
1622 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1624 if (can_encode_int32 (new_offset
, 21))
1626 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1627 aarch64_register (rn
, is64
), new_offset
);
1629 else if (can_encode_int32 (new_offset
, 28))
1631 /* The offset is out of range for a compare and branch
1632 instruction but not for a unconditional branch. We can use
1633 the following instructions instead:
1635 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1636 B NOT_TAKEN ; Else jump over TAKEN and continue.
1642 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1643 aarch64_register (rn
, is64
), 8);
1644 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1645 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1649 /* Implementation of aarch64_insn_visitor method "tb". */
1652 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1653 const unsigned rt
, unsigned bit
,
1654 struct aarch64_insn_data
*data
)
1656 struct aarch64_insn_relocation_data
*insn_reloc
1657 = (struct aarch64_insn_relocation_data
*) data
;
1659 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1661 if (can_encode_int32 (new_offset
, 16))
1663 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1664 aarch64_register (rt
, 1), new_offset
);
1666 else if (can_encode_int32 (new_offset
, 28))
1668 /* The offset is out of range for a test bit and branch
1669 instruction but not for a unconditional branch. We can use
1670 the following instructions instead:
1672 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1673 B NOT_TAKEN ; Else jump over TAKEN and continue.
1679 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1680 aarch64_register (rt
, 1), 8);
1681 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1682 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
1687 /* Implementation of aarch64_insn_visitor method "adr". */
1690 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
1692 struct aarch64_insn_data
*data
)
1694 struct aarch64_insn_relocation_data
*insn_reloc
1695 = (struct aarch64_insn_relocation_data
*) data
;
1696 /* We know exactly the address the ADR{P,} instruction will compute.
1697 We can just write it to the destination register. */
1698 CORE_ADDR address
= data
->insn_addr
+ offset
;
1702 /* Clear the lower 12 bits of the offset to get the 4K page. */
1703 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1704 aarch64_register (rd
, 1),
1708 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1709 aarch64_register (rd
, 1), address
);
1712 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
1715 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
1716 const unsigned rt
, const int is64
,
1717 struct aarch64_insn_data
*data
)
1719 struct aarch64_insn_relocation_data
*insn_reloc
1720 = (struct aarch64_insn_relocation_data
*) data
;
1721 CORE_ADDR address
= data
->insn_addr
+ offset
;
1723 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1724 aarch64_register (rt
, 1), address
);
1726 /* We know exactly what address to load from, and what register we
1729 MOV xd, #(oldloc + offset)
1730 MOVK xd, #((oldloc + offset) >> 16), lsl #16
1733 LDR xd, [xd] ; or LDRSW xd, [xd]
1738 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
1739 aarch64_register (rt
, 1),
1740 aarch64_register (rt
, 1),
1741 offset_memory_operand (0));
1743 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
1744 aarch64_register (rt
, is64
),
1745 aarch64_register (rt
, 1),
1746 offset_memory_operand (0));
1749 /* Implementation of aarch64_insn_visitor method "others". */
1752 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
1753 struct aarch64_insn_data
*data
)
1755 struct aarch64_insn_relocation_data
*insn_reloc
1756 = (struct aarch64_insn_relocation_data
*) data
;
1758 /* The instruction is not PC relative. Just re-emit it at the new
1760 insn_reloc
->insn_ptr
+= emit_insn (insn_reloc
->insn_ptr
, insn
);
1763 static const struct aarch64_insn_visitor visitor
=
1765 aarch64_ftrace_insn_reloc_b
,
1766 aarch64_ftrace_insn_reloc_b_cond
,
1767 aarch64_ftrace_insn_reloc_cb
,
1768 aarch64_ftrace_insn_reloc_tb
,
1769 aarch64_ftrace_insn_reloc_adr
,
1770 aarch64_ftrace_insn_reloc_ldr_literal
,
1771 aarch64_ftrace_insn_reloc_others
,
1774 /* Implementation of linux_target_ops method
1775 "install_fast_tracepoint_jump_pad". */
1778 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1780 CORE_ADDR collector
,
1783 CORE_ADDR
*jump_entry
,
1784 CORE_ADDR
*trampoline
,
1785 ULONGEST
*trampoline_size
,
1786 unsigned char *jjump_pad_insn
,
1787 ULONGEST
*jjump_pad_insn_size
,
1788 CORE_ADDR
*adjusted_insn_addr
,
1789 CORE_ADDR
*adjusted_insn_addr_end
,
1797 CORE_ADDR buildaddr
= *jump_entry
;
1798 struct aarch64_insn_relocation_data insn_data
;
1800 /* We need to save the current state on the stack both to restore it
1801 later and to collect register values when the tracepoint is hit.
1803 The saved registers are pushed in a layout that needs to be in sync
1804 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
1805 the supply_fast_tracepoint_registers function will fill in the
1806 register cache from a pointer to saved registers on the stack we build
1809 For simplicity, we set the size of each cell on the stack to 16 bytes.
1810 This way one cell can hold any register type, from system registers
1811 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
1812 has to be 16 bytes aligned anyway.
1814 Note that the CPSR register does not exist on AArch64. Instead we
1815 can access system bits describing the process state with the
1816 MRS/MSR instructions, namely the condition flags. We save them as
1817 if they are part of a CPSR register because that's how GDB
1818 interprets these system bits. At the moment, only the condition
1819 flags are saved in CPSR (NZCV).
1821 Stack layout, each cell is 16 bytes (descending):
1823 High *-------- SIMD&FP registers from 31 down to 0. --------*
1829 *---- General purpose registers from 30 down to 0. ----*
1835 *------------- Special purpose registers. -------------*
1838 | CPSR (NZCV) | 5 cells
1841 *------------- collecting_t object --------------------*
1842 | TPIDR_EL0 | struct tracepoint * |
1843 Low *------------------------------------------------------*
1845 After this stack is set up, we issue a call to the collector, passing
1846 it the saved registers at (SP + 16). */
1848 /* Push SIMD&FP registers on the stack:
1850 SUB sp, sp, #(32 * 16)
1852 STP q30, q31, [sp, #(30 * 16)]
1857 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
1858 for (i
= 30; i
>= 0; i
-= 2)
1859 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
1861 /* Push general puspose registers on the stack. Note that we do not need
1862 to push x31 as it represents the xzr register and not the stack
1863 pointer in a STR instruction.
1865 SUB sp, sp, #(31 * 16)
1867 STR x30, [sp, #(30 * 16)]
1872 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
1873 for (i
= 30; i
>= 0; i
-= 1)
1874 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
1875 offset_memory_operand (i
* 16));
1877 /* Make space for 5 more cells.
1879 SUB sp, sp, #(5 * 16)
1882 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
1887 ADD x4, sp, #((32 + 31 + 5) * 16)
1888 STR x4, [sp, #(4 * 16)]
1891 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
1892 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
1894 /* Save PC (tracepoint address):
1899 STR x3, [sp, #(3 * 16)]
1903 p
+= emit_mov_addr (p
, x3
, tpaddr
);
1904 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
1906 /* Save CPSR (NZCV), FPSR and FPCR:
1912 STR x2, [sp, #(2 * 16)]
1913 STR x1, [sp, #(1 * 16)]
1914 STR x0, [sp, #(0 * 16)]
1917 p
+= emit_mrs (p
, x2
, NZCV
);
1918 p
+= emit_mrs (p
, x1
, FPSR
);
1919 p
+= emit_mrs (p
, x0
, FPCR
);
1920 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
1921 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
1922 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
1924 /* Push the collecting_t object. It consist of the address of the
1925 tracepoint and an ID for the current thread. We get the latter by
1926 reading the tpidr_el0 system register. It corresponds to the
1927 NT_ARM_TLS register accessible with ptrace.
1934 STP x0, x1, [sp, #-16]!
1938 p
+= emit_mov_addr (p
, x0
, tpoint
);
1939 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
1940 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
1944 The shared memory for the lock is at lockaddr. It will hold zero
1945 if no-one is holding the lock, otherwise it contains the address of
1946 the collecting_t object on the stack of the thread which acquired it.
1948 At this stage, the stack pointer points to this thread's collecting_t
1951 We use the following registers:
1952 - x0: Address of the lock.
1953 - x1: Pointer to collecting_t object.
1954 - x2: Scratch register.
1960 ; Trigger an event local to this core. So the following WFE
1961 ; instruction is ignored.
1964 ; Wait for an event. The event is triggered by either the SEVL
1965 ; or STLR instructions (store release).
1968 ; Atomically read at lockaddr. This marks the memory location as
1969 ; exclusive. This instruction also has memory constraints which
1970 ; make sure all previous data reads and writes are done before
1974 ; Try again if another thread holds the lock.
1977 ; We can lock it! Write the address of the collecting_t object.
1978 ; This instruction will fail if the memory location is not marked
1979 ; as exclusive anymore. If it succeeds, it will remove the
1980 ; exclusive mark on the memory location. This way, if another
1981 ; thread executes this instruction before us, we will fail and try
1988 p
+= emit_mov_addr (p
, x0
, lockaddr
);
1989 p
+= emit_mov (p
, x1
, register_operand (sp
));
1993 p
+= emit_ldaxr (p
, x2
, x0
);
1994 p
+= emit_cb (p
, 1, w2
, -2 * 4);
1995 p
+= emit_stxr (p
, w2
, x1
, x0
);
1996 p
+= emit_cb (p
, 1, x2
, -4 * 4);
1998 /* Call collector (struct tracepoint *, unsigned char *):
2003 ; Saved registers start after the collecting_t object.
2006 ; We use an intra-procedure-call scratch register.
2007 MOV ip0, #(collector)
2010 ; And call back to C!
2015 p
+= emit_mov_addr (p
, x0
, tpoint
);
2016 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2018 p
+= emit_mov_addr (p
, ip0
, collector
);
2019 p
+= emit_blr (p
, ip0
);
2021 /* Release the lock.
2026 ; This instruction is a normal store with memory ordering
2027 ; constraints. Thanks to this we do not have to put a data
2028 ; barrier instruction to make sure all data read and writes are done
2029 ; before this instruction is executed. Furthermore, this instrucion
2030 ; will trigger an event, letting other threads know they can grab
2035 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2036 p
+= emit_stlr (p
, xzr
, x0
);
2038 /* Free collecting_t object:
2043 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2045 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2046 registers from the stack.
2048 LDR x2, [sp, #(2 * 16)]
2049 LDR x1, [sp, #(1 * 16)]
2050 LDR x0, [sp, #(0 * 16)]
2056 ADD sp, sp #(5 * 16)
2059 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2060 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2061 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2062 p
+= emit_msr (p
, NZCV
, x2
);
2063 p
+= emit_msr (p
, FPSR
, x1
);
2064 p
+= emit_msr (p
, FPCR
, x0
);
2066 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2068 /* Pop general purpose registers:
2072 LDR x30, [sp, #(30 * 16)]
2074 ADD sp, sp, #(31 * 16)
2077 for (i
= 0; i
<= 30; i
+= 1)
2078 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2079 offset_memory_operand (i
* 16));
2080 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2082 /* Pop SIMD&FP registers:
2086 LDP q30, q31, [sp, #(30 * 16)]
2088 ADD sp, sp, #(32 * 16)
2091 for (i
= 0; i
<= 30; i
+= 2)
2092 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2093 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2095 /* Write the code into the inferior memory. */
2096 append_insns (&buildaddr
, p
- buf
, buf
);
2098 /* Now emit the relocated instruction. */
2099 *adjusted_insn_addr
= buildaddr
;
2100 target_read_uint32 (tpaddr
, &insn
);
2102 insn_data
.base
.insn_addr
= tpaddr
;
2103 insn_data
.new_addr
= buildaddr
;
2104 insn_data
.insn_ptr
= buf
;
2106 aarch64_relocate_instruction (insn
, &visitor
,
2107 (struct aarch64_insn_data
*) &insn_data
);
2109 /* We may not have been able to relocate the instruction. */
2110 if (insn_data
.insn_ptr
== buf
)
2113 "E.Could not relocate instruction from %s to %s.",
2114 core_addr_to_string_nz (tpaddr
),
2115 core_addr_to_string_nz (buildaddr
));
2119 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2120 *adjusted_insn_addr_end
= buildaddr
;
2122 /* Go back to the start of the buffer. */
2125 /* Emit a branch back from the jump pad. */
2126 offset
= (tpaddr
+ orig_size
- buildaddr
);
2127 if (!can_encode_int32 (offset
, 28))
2130 "E.Jump back from jump pad too far from tracepoint "
2131 "(offset 0x%" PRIx32
" cannot be encoded in 28 bits).",
2136 p
+= emit_b (p
, 0, offset
);
2137 append_insns (&buildaddr
, p
- buf
, buf
);
2139 /* Give the caller a branch instruction into the jump pad. */
2140 offset
= (*jump_entry
- tpaddr
);
2141 if (!can_encode_int32 (offset
, 28))
2144 "E.Jump pad too far from tracepoint "
2145 "(offset 0x%" PRIx32
" cannot be encoded in 28 bits).",
2150 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2151 *jjump_pad_insn_size
= 4;
2153 /* Return the end address of our pad. */
2154 *jump_entry
= buildaddr
;
2159 /* Helper function writing LEN instructions from START into
2160 current_insn_ptr. */
2163 emit_ops_insns (const uint32_t *start
, int len
)
2165 CORE_ADDR buildaddr
= current_insn_ptr
;
2168 debug_printf ("Adding %d instrucions at %s\n",
2169 len
, paddress (buildaddr
));
2171 append_insns (&buildaddr
, len
, start
);
2172 current_insn_ptr
= buildaddr
;
2175 /* Pop a register from the stack. */
2178 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2180 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2183 /* Push a register on the stack. */
2186 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2188 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2191 /* Implementation of emit_ops method "emit_prologue". */
2194 aarch64_emit_prologue (void)
2199 /* This function emit a prologue for the following function prototype:
2201 enum eval_result_type f (unsigned char *regs,
2204 The first argument is a buffer of raw registers. The second
2205 argument is the result of
2206 evaluating the expression, which will be set to whatever is on top of
2207 the stack at the end.
2209 The stack set up by the prologue is as such:
2211 High *------------------------------------------------------*
2214 | x1 (ULONGEST *value) |
2215 | x0 (unsigned char *regs) |
2216 Low *------------------------------------------------------*
2218 As we are implementing a stack machine, each opcode can expand the
2219 stack so we never know how far we are from the data saved by this
2220 prologue. In order to be able refer to value and regs later, we save
2221 the current stack pointer in the frame pointer. This way, it is not
2222 clobbered when calling C functions.
2224 Finally, throughtout every operation, we are using register x0 as the
2225 top of the stack, and x1 as a scratch register. */
2227 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2228 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2229 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2231 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2234 emit_ops_insns (buf
, p
- buf
);
2237 /* Implementation of emit_ops method "emit_epilogue". */
2240 aarch64_emit_epilogue (void)
2245 /* Store the result of the expression (x0) in *value. */
2246 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2247 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2248 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2250 /* Restore the previous state. */
2251 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2252 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2254 /* Return expr_eval_no_error. */
2255 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2256 p
+= emit_ret (p
, lr
);
2258 emit_ops_insns (buf
, p
- buf
);
2261 /* Implementation of emit_ops method "emit_add". */
2264 aarch64_emit_add (void)
2269 p
+= emit_pop (p
, x1
);
2270 p
+= emit_add (p
, x0
, x0
, register_operand (x1
));
2272 emit_ops_insns (buf
, p
- buf
);
2275 /* Implementation of emit_ops method "emit_sub". */
2278 aarch64_emit_sub (void)
2283 p
+= emit_pop (p
, x1
);
2284 p
+= emit_sub (p
, x0
, x0
, register_operand (x1
));
2286 emit_ops_insns (buf
, p
- buf
);
2289 /* Implementation of emit_ops method "emit_mul". */
2292 aarch64_emit_mul (void)
2297 p
+= emit_pop (p
, x1
);
2298 p
+= emit_mul (p
, x0
, x1
, x0
);
2300 emit_ops_insns (buf
, p
- buf
);
2303 /* Implementation of emit_ops method "emit_lsh". */
2306 aarch64_emit_lsh (void)
2311 p
+= emit_pop (p
, x1
);
2312 p
+= emit_lslv (p
, x0
, x1
, x0
);
2314 emit_ops_insns (buf
, p
- buf
);
2317 /* Implementation of emit_ops method "emit_rsh_signed". */
2320 aarch64_emit_rsh_signed (void)
2325 p
+= emit_pop (p
, x1
);
2326 p
+= emit_asrv (p
, x0
, x1
, x0
);
2328 emit_ops_insns (buf
, p
- buf
);
2331 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2334 aarch64_emit_rsh_unsigned (void)
2339 p
+= emit_pop (p
, x1
);
2340 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2342 emit_ops_insns (buf
, p
- buf
);
2345 /* Implementation of emit_ops method "emit_ext". */
2348 aarch64_emit_ext (int arg
)
2353 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2355 emit_ops_insns (buf
, p
- buf
);
2358 /* Implementation of emit_ops method "emit_log_not". */
2361 aarch64_emit_log_not (void)
2366 /* If the top of the stack is 0, replace it with 1. Else replace it with
2369 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2370 p
+= emit_cset (p
, x0
, EQ
);
2372 emit_ops_insns (buf
, p
- buf
);
2375 /* Implementation of emit_ops method "emit_bit_and". */
2378 aarch64_emit_bit_and (void)
2383 p
+= emit_pop (p
, x1
);
2384 p
+= emit_and (p
, x0
, x0
, x1
);
2386 emit_ops_insns (buf
, p
- buf
);
2389 /* Implementation of emit_ops method "emit_bit_or". */
2392 aarch64_emit_bit_or (void)
2397 p
+= emit_pop (p
, x1
);
2398 p
+= emit_orr (p
, x0
, x0
, x1
);
2400 emit_ops_insns (buf
, p
- buf
);
2403 /* Implementation of emit_ops method "emit_bit_xor". */
2406 aarch64_emit_bit_xor (void)
2411 p
+= emit_pop (p
, x1
);
2412 p
+= emit_eor (p
, x0
, x0
, x1
);
2414 emit_ops_insns (buf
, p
- buf
);
2417 /* Implementation of emit_ops method "emit_bit_not". */
2420 aarch64_emit_bit_not (void)
2425 p
+= emit_mvn (p
, x0
, x0
);
2427 emit_ops_insns (buf
, p
- buf
);
2430 /* Implementation of emit_ops method "emit_equal". */
2433 aarch64_emit_equal (void)
2438 p
+= emit_pop (p
, x1
);
2439 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2440 p
+= emit_cset (p
, x0
, EQ
);
2442 emit_ops_insns (buf
, p
- buf
);
2445 /* Implementation of emit_ops method "emit_less_signed". */
2448 aarch64_emit_less_signed (void)
2453 p
+= emit_pop (p
, x1
);
2454 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2455 p
+= emit_cset (p
, x0
, LT
);
2457 emit_ops_insns (buf
, p
- buf
);
2460 /* Implementation of emit_ops method "emit_less_unsigned". */
2463 aarch64_emit_less_unsigned (void)
2468 p
+= emit_pop (p
, x1
);
2469 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2470 p
+= emit_cset (p
, x0
, LO
);
2472 emit_ops_insns (buf
, p
- buf
);
2475 /* Implementation of emit_ops method "emit_ref". */
2478 aarch64_emit_ref (int size
)
2486 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2489 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2492 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2495 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2498 /* Unknown size, bail on compilation. */
2503 emit_ops_insns (buf
, p
- buf
);
2506 /* Implementation of emit_ops method "emit_if_goto". */
2509 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2514 /* The Z flag is set or cleared here. */
2515 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2516 /* This instruction must not change the Z flag. */
2517 p
+= emit_pop (p
, x0
);
2518 /* Branch over the next instruction if x0 == 0. */
2519 p
+= emit_bcond (p
, EQ
, 8);
2521 /* The NOP instruction will be patched with an unconditional branch. */
2523 *offset_p
= (p
- buf
) * 4;
2528 emit_ops_insns (buf
, p
- buf
);
2531 /* Implementation of emit_ops method "emit_goto". */
2534 aarch64_emit_goto (int *offset_p
, int *size_p
)
2539 /* The NOP instruction will be patched with an unconditional branch. */
2546 emit_ops_insns (buf
, p
- buf
);
2549 /* Implementation of emit_ops method "write_goto_address". */
2552 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2556 emit_b (&insn
, 0, to
- from
);
2557 append_insns (&from
, 1, &insn
);
2560 /* Implementation of emit_ops method "emit_const". */
2563 aarch64_emit_const (LONGEST num
)
2568 p
+= emit_mov_addr (p
, x0
, num
);
2570 emit_ops_insns (buf
, p
- buf
);
2573 /* Implementation of emit_ops method "emit_call". */
2576 aarch64_emit_call (CORE_ADDR fn
)
2581 p
+= emit_mov_addr (p
, ip0
, fn
);
2582 p
+= emit_blr (p
, ip0
);
2584 emit_ops_insns (buf
, p
- buf
);
2587 /* Implementation of emit_ops method "emit_reg". */
2590 aarch64_emit_reg (int reg
)
2595 /* Set x0 to unsigned char *regs. */
2596 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2597 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2598 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2600 emit_ops_insns (buf
, p
- buf
);
2602 aarch64_emit_call (get_raw_reg_func_addr ());
2605 /* Implementation of emit_ops method "emit_pop". */
2608 aarch64_emit_pop (void)
2613 p
+= emit_pop (p
, x0
);
2615 emit_ops_insns (buf
, p
- buf
);
2618 /* Implementation of emit_ops method "emit_stack_flush". */
2621 aarch64_emit_stack_flush (void)
2626 p
+= emit_push (p
, x0
);
2628 emit_ops_insns (buf
, p
- buf
);
2631 /* Implementation of emit_ops method "emit_zero_ext". */
2634 aarch64_emit_zero_ext (int arg
)
2639 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2641 emit_ops_insns (buf
, p
- buf
);
2644 /* Implementation of emit_ops method "emit_swap". */
2647 aarch64_emit_swap (void)
2652 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2653 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2654 p
+= emit_mov (p
, x0
, register_operand (x1
));
2656 emit_ops_insns (buf
, p
- buf
);
2659 /* Implementation of emit_ops method "emit_stack_adjust". */
2662 aarch64_emit_stack_adjust (int n
)
2664 /* This is not needed with our design. */
2668 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2670 emit_ops_insns (buf
, p
- buf
);
2673 /* Implementation of emit_ops method "emit_int_call_1". */
2676 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2681 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2683 emit_ops_insns (buf
, p
- buf
);
2685 aarch64_emit_call (fn
);
2688 /* Implementation of emit_ops method "emit_void_call_2". */
2691 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2696 /* Push x0 on the stack. */
2697 aarch64_emit_stack_flush ();
2699 /* Setup arguments for the function call:
2702 x1: top of the stack
2707 p
+= emit_mov (p
, x1
, register_operand (x0
));
2708 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2710 emit_ops_insns (buf
, p
- buf
);
2712 aarch64_emit_call (fn
);
2715 aarch64_emit_pop ();
2718 /* Implementation of emit_ops method "emit_eq_goto". */
2721 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
2726 p
+= emit_pop (p
, x1
);
2727 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2728 /* Branch over the next instruction if x0 != x1. */
2729 p
+= emit_bcond (p
, NE
, 8);
2730 /* The NOP instruction will be patched with an unconditional branch. */
2732 *offset_p
= (p
- buf
) * 4;
2737 emit_ops_insns (buf
, p
- buf
);
2740 /* Implementation of emit_ops method "emit_ne_goto". */
2743 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
2748 p
+= emit_pop (p
, x1
);
2749 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2750 /* Branch over the next instruction if x0 == x1. */
2751 p
+= emit_bcond (p
, EQ
, 8);
2752 /* The NOP instruction will be patched with an unconditional branch. */
2754 *offset_p
= (p
- buf
) * 4;
2759 emit_ops_insns (buf
, p
- buf
);
2762 /* Implementation of emit_ops method "emit_lt_goto". */
2765 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
2770 p
+= emit_pop (p
, x1
);
2771 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2772 /* Branch over the next instruction if x0 >= x1. */
2773 p
+= emit_bcond (p
, GE
, 8);
2774 /* The NOP instruction will be patched with an unconditional branch. */
2776 *offset_p
= (p
- buf
) * 4;
2781 emit_ops_insns (buf
, p
- buf
);
2784 /* Implementation of emit_ops method "emit_le_goto". */
2787 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
2792 p
+= emit_pop (p
, x1
);
2793 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2794 /* Branch over the next instruction if x0 > x1. */
2795 p
+= emit_bcond (p
, GT
, 8);
2796 /* The NOP instruction will be patched with an unconditional branch. */
2798 *offset_p
= (p
- buf
) * 4;
2803 emit_ops_insns (buf
, p
- buf
);
2806 /* Implementation of emit_ops method "emit_gt_goto". */
2809 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
2814 p
+= emit_pop (p
, x1
);
2815 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2816 /* Branch over the next instruction if x0 <= x1. */
2817 p
+= emit_bcond (p
, LE
, 8);
2818 /* The NOP instruction will be patched with an unconditional branch. */
2820 *offset_p
= (p
- buf
) * 4;
2825 emit_ops_insns (buf
, p
- buf
);
2828 /* Implementation of emit_ops method "emit_ge_got". */
2831 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
2836 p
+= emit_pop (p
, x1
);
2837 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2838 /* Branch over the next instruction if x0 <= x1. */
2839 p
+= emit_bcond (p
, LT
, 8);
2840 /* The NOP instruction will be patched with an unconditional branch. */
2842 *offset_p
= (p
- buf
) * 4;
2847 emit_ops_insns (buf
, p
- buf
);
2850 static struct emit_ops aarch64_emit_ops_impl
=
2852 aarch64_emit_prologue
,
2853 aarch64_emit_epilogue
,
2858 aarch64_emit_rsh_signed
,
2859 aarch64_emit_rsh_unsigned
,
2861 aarch64_emit_log_not
,
2862 aarch64_emit_bit_and
,
2863 aarch64_emit_bit_or
,
2864 aarch64_emit_bit_xor
,
2865 aarch64_emit_bit_not
,
2867 aarch64_emit_less_signed
,
2868 aarch64_emit_less_unsigned
,
2870 aarch64_emit_if_goto
,
2872 aarch64_write_goto_address
,
2877 aarch64_emit_stack_flush
,
2878 aarch64_emit_zero_ext
,
2880 aarch64_emit_stack_adjust
,
2881 aarch64_emit_int_call_1
,
2882 aarch64_emit_void_call_2
,
2883 aarch64_emit_eq_goto
,
2884 aarch64_emit_ne_goto
,
2885 aarch64_emit_lt_goto
,
2886 aarch64_emit_le_goto
,
2887 aarch64_emit_gt_goto
,
2888 aarch64_emit_ge_got
,
2891 /* Implementation of linux_target_ops method "emit_ops". */
2893 static struct emit_ops
*
2894 aarch64_emit_ops (void)
2896 return &aarch64_emit_ops_impl
;
2899 /* Implementation of linux_target_ops method
2900 "get_min_fast_tracepoint_insn_len". */
2903 aarch64_get_min_fast_tracepoint_insn_len (void)
2908 /* Implementation of linux_target_ops method "supports_range_stepping". */
2911 aarch64_supports_range_stepping (void)
2916 struct linux_target_ops the_low_target
=
2920 aarch64_cannot_fetch_register
,
2921 aarch64_cannot_store_register
,
2922 NULL
, /* fetch_register */
2925 (const unsigned char *) &aarch64_breakpoint
,
2926 aarch64_breakpoint_len
,
2927 NULL
, /* breakpoint_reinsert_addr */
2928 0, /* decr_pc_after_break */
2929 aarch64_breakpoint_at
,
2930 aarch64_supports_z_point_type
,
2931 aarch64_insert_point
,
2932 aarch64_remove_point
,
2933 aarch64_stopped_by_watchpoint
,
2934 aarch64_stopped_data_address
,
2935 NULL
, /* collect_ptrace_register */
2936 NULL
, /* supply_ptrace_register */
2937 aarch64_linux_siginfo_fixup
,
2938 aarch64_linux_new_process
,
2939 aarch64_linux_new_thread
,
2940 aarch64_linux_new_fork
,
2941 aarch64_linux_prepare_to_resume
,
2942 NULL
, /* process_qsupported */
2943 aarch64_supports_tracepoints
,
2944 aarch64_get_thread_area
,
2945 aarch64_install_fast_tracepoint_jump_pad
,
2947 aarch64_get_min_fast_tracepoint_insn_len
,
2948 aarch64_supports_range_stepping
,
2952 initialize_low_arch (void)
2954 init_registers_aarch64 ();
2956 initialize_low_arch_aarch32 ();
2958 initialize_regsets_info (&aarch64_regsets_info
);