1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
2 Copyright (C) 1995-2014 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "linux-low.h"
21 #include <sys/ptrace.h>
23 /* Defined in auto-generated file reg-crisv32.c. */
24 void init_registers_crisv32 (void);
25 extern const struct target_desc
*tdesc_crisv32
;
28 #define cris_num_regs 49
30 #ifndef PTRACE_GET_THREAD_AREA
31 #define PTRACE_GET_THREAD_AREA 25
34 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
35 without any significant gain). */
37 /* Locations need to match <include/asm/arch/ptrace.h>. */
38 static int cris_regmap
[] = {
41 9*4, 10*4, 11*4, 12*4,
42 13*4, 14*4, 24*4, 15*4,
52 30*4, 31*4, 32*4, 33*4,
53 34*4, 35*4, 36*4, 37*4,
58 extern int debug_threads
;
61 cris_get_pc (struct regcache
*regcache
)
64 collect_register_by_name (regcache
, "pc", &pc
);
66 debug_printf ("stop pc is %08lx\n", pc
);
71 cris_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
73 unsigned long newpc
= pc
;
74 supply_register_by_name (regcache
, "pc", &newpc
);
77 static const unsigned short cris_breakpoint
= 0xe938;
78 #define cris_breakpoint_len 2
81 cris_breakpoint_at (CORE_ADDR where
)
85 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
87 if (insn
== cris_breakpoint
)
90 /* If necessary, recognize more trap instructions here. GDB only uses the
95 /* We only place breakpoints in empty marker functions, and thread locking
96 is outside of the function. So rather than importing software single-step,
97 we can just run until exit. */
99 /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
100 for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event
101 will fail when debugging multi-threaded applications. */
104 cris_reinsert_addr (void)
106 struct regcache
*regcache
= get_thread_regcache (current_inferior
, 1);
108 collect_register_by_name (regcache
, "srp", &pc
);
113 cris_write_data_breakpoint (struct regcache
*regcache
,
114 int bp
, unsigned long start
, unsigned long end
)
119 supply_register_by_name (regcache
, "s3", &start
);
120 supply_register_by_name (regcache
, "s4", &end
);
123 supply_register_by_name (regcache
, "s5", &start
);
124 supply_register_by_name (regcache
, "s6", &end
);
127 supply_register_by_name (regcache
, "s7", &start
);
128 supply_register_by_name (regcache
, "s8", &end
);
131 supply_register_by_name (regcache
, "s9", &start
);
132 supply_register_by_name (regcache
, "s10", &end
);
135 supply_register_by_name (regcache
, "s11", &start
);
136 supply_register_by_name (regcache
, "s12", &end
);
139 supply_register_by_name (regcache
, "s13", &start
);
140 supply_register_by_name (regcache
, "s14", &end
);
146 cris_insert_point (char type
, CORE_ADDR addr
, int len
)
149 unsigned long bp_ctrl
;
150 unsigned long start
, end
;
152 struct regcache
*regcache
;
154 /* Breakpoint/watchpoint types (GDB terminology):
155 0 = memory breakpoint for instructions
156 (not supported; done via memory write instead)
157 1 = hardware breakpoint for instructions (not supported)
158 2 = write watchpoint (supported)
159 3 = read watchpoint (supported)
160 4 = access watchpoint (supported). */
162 if (type
< '2' || type
> '4')
168 regcache
= get_thread_regcache (current_inferior
, 1);
170 /* Read watchpoints are set as access watchpoints, because of GDB's
171 inability to deal with pure read watchpoints. */
175 /* Get the configuration register. */
176 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
178 /* The watchpoint allocation scheme is the simplest possible.
179 For example, if a region is watched for read and
180 a write watch is requested, a new watchpoint will
181 be used. Also, if a watch for a region that is already
182 covered by one or more existing watchpoints, a new
183 watchpoint will be used. */
185 /* First, find a free data watchpoint. */
186 for (bp
= 0; bp
< 6; bp
++)
188 /* Each data watchpoint's control registers occupy 2 bits
189 (hence the 3), starting at bit 2 for D0 (hence the 2)
190 with 4 bits between for each watchpoint (yes, the 4). */
191 if (!(bp_ctrl
& (0x3 << (2 + (bp
* 4)))))
197 /* We're out of watchpoints. */
201 /* Configure the control register first. */
202 if (type
== '3' || type
== '4')
204 /* Trigger on read. */
205 bp_ctrl
|= (1 << (2 + bp
* 4));
207 if (type
== '2' || type
== '4')
209 /* Trigger on write. */
210 bp_ctrl
|= (2 << (2 + bp
* 4));
213 /* Setup the configuration register. */
214 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
216 /* Setup the range. */
218 end
= addr
+ len
- 1;
220 /* Configure the watchpoint register. */
221 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
223 collect_register_by_name (regcache
, "ccs", &ccs
);
224 /* Set the S1 flag to enable watchpoints. */
226 supply_register_by_name (regcache
, "ccs", &ccs
);
232 cris_remove_point (char type
, CORE_ADDR addr
, int len
)
235 unsigned long bp_ctrl
;
236 unsigned long start
, end
;
237 struct regcache
*regcache
;
238 unsigned long bp_d_regs
[12];
240 /* Breakpoint/watchpoint types:
241 0 = memory breakpoint for instructions
242 (not supported; done via memory write instead)
243 1 = hardware breakpoint for instructions (not supported)
244 2 = write watchpoint (supported)
245 3 = read watchpoint (supported)
246 4 = access watchpoint (supported). */
247 if (type
< '2' || type
> '4')
250 regcache
= get_thread_regcache (current_inferior
, 1);
252 /* Read watchpoints are set as access watchpoints, because of GDB's
253 inability to deal with pure read watchpoints. */
257 /* Get the configuration register. */
258 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
260 /* Try to find a watchpoint that is configured for the
261 specified range, then check that read/write also matches. */
263 /* Ugly pointer arithmetic, since I cannot rely on a
264 single switch (addr) as there may be several watchpoints with
265 the same start address for example. */
267 /* Get all range registers to simplify search. */
268 collect_register_by_name (regcache
, "s3", &bp_d_regs
[0]);
269 collect_register_by_name (regcache
, "s4", &bp_d_regs
[1]);
270 collect_register_by_name (regcache
, "s5", &bp_d_regs
[2]);
271 collect_register_by_name (regcache
, "s6", &bp_d_regs
[3]);
272 collect_register_by_name (regcache
, "s7", &bp_d_regs
[4]);
273 collect_register_by_name (regcache
, "s8", &bp_d_regs
[5]);
274 collect_register_by_name (regcache
, "s9", &bp_d_regs
[6]);
275 collect_register_by_name (regcache
, "s10", &bp_d_regs
[7]);
276 collect_register_by_name (regcache
, "s11", &bp_d_regs
[8]);
277 collect_register_by_name (regcache
, "s12", &bp_d_regs
[9]);
278 collect_register_by_name (regcache
, "s13", &bp_d_regs
[10]);
279 collect_register_by_name (regcache
, "s14", &bp_d_regs
[11]);
281 for (bp
= 0; bp
< 6; bp
++)
283 if (bp_d_regs
[bp
* 2] == addr
284 && bp_d_regs
[bp
* 2 + 1] == (addr
+ len
- 1)) {
285 /* Matching range. */
286 int bitpos
= 2 + bp
* 4;
289 /* Read/write bits for this BP. */
290 rw_bits
= (bp_ctrl
& (0x3 << bitpos
)) >> bitpos
;
292 if ((type
== '3' && rw_bits
== 0x1)
293 || (type
== '2' && rw_bits
== 0x2)
294 || (type
== '4' && rw_bits
== 0x3))
296 /* Read/write matched. */
304 /* No watchpoint matched. */
308 /* Found a matching watchpoint. Now, deconfigure it by
309 both disabling read/write in bp_ctrl and zeroing its
310 start/end addresses. */
311 bp_ctrl
&= ~(3 << (2 + (bp
* 4)));
312 /* Setup the configuration register. */
313 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
316 /* Configure the watchpoint register. */
317 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
319 /* Note that we don't clear the S1 flag here. It's done when continuing. */
324 cris_stopped_by_watchpoint (void)
327 struct regcache
*regcache
= get_thread_regcache (current_inferior
, 1);
329 collect_register_by_name (regcache
, "exs", &exs
);
331 return (((exs
& 0xff00) >> 8) == 0xc);
335 cris_stopped_data_address (void)
338 struct regcache
*regcache
= get_thread_regcache (current_inferior
, 1);
340 collect_register_by_name (regcache
, "eda", &eda
);
342 /* FIXME: Possibly adjust to match watched range. */
347 ps_get_thread_area (const struct ps_prochandle
*ph
,
348 lwpid_t lwpid
, int idx
, void **base
)
350 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
, NULL
, base
) != 0)
353 /* IDX is the bias from the thread pointer to the beginning of the
354 thread descriptor. It has to be subtracted due to implementation
355 quirks in libthread_db. */
356 *base
= (void *) ((char *) *base
- idx
);
361 cris_fill_gregset (struct regcache
*regcache
, void *buf
)
365 for (i
= 0; i
< cris_num_regs
; i
++)
367 if (cris_regmap
[i
] != -1)
368 collect_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
373 cris_store_gregset (struct regcache
*regcache
, const void *buf
)
377 for (i
= 0; i
< cris_num_regs
; i
++)
379 if (cris_regmap
[i
] != -1)
380 supply_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
385 cris_arch_setup (void)
387 current_process ()->tdesc
= tdesc_crisv32
;
390 static struct regset_info cris_regsets
[] = {
391 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, cris_num_regs
* 4,
392 GENERAL_REGS
, cris_fill_gregset
, cris_store_gregset
},
393 { 0, 0, 0, -1, -1, NULL
, NULL
}
397 static struct regsets_info cris_regsets_info
=
399 cris_regsets
, /* regsets */
401 NULL
, /* disabled_regsets */
404 static struct usrregs_info cris_usrregs_info
=
410 static struct regs_info regs_info
=
412 NULL
, /* regset_bitmap */
417 static const struct regs_info
*
418 cris_regs_info (void)
423 struct linux_target_ops the_low_target
= {
428 NULL
, /* fetch_register */
431 (const unsigned char *) &cris_breakpoint
,
438 cris_stopped_by_watchpoint
,
439 cris_stopped_data_address
,
443 initialize_low_arch (void)
445 init_registers_crisv32 ();
447 initialize_regsets_info (&cris_regsets_info
);