1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
2 Copyright (C) 1995-2013 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "linux-low.h"
21 #include <sys/ptrace.h>
23 /* Defined in auto-generated file reg-crisv32.c. */
24 void init_registers_crisv32 (void);
25 extern const struct target_desc
*tdesc_crisv32
;
28 #define cris_num_regs 49
30 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
31 without any significant gain). */
33 /* Locations need to match <include/asm/arch/ptrace.h>. */
34 static int cris_regmap
[] = {
37 9*4, 10*4, 11*4, 12*4,
38 13*4, 14*4, 24*4, 15*4,
48 30*4, 31*4, 32*4, 33*4,
49 34*4, 35*4, 36*4, 37*4,
54 extern int debug_threads
;
57 cris_get_pc (struct regcache
*regcache
)
60 collect_register_by_name (regcache
, "pc", &pc
);
62 fprintf (stderr
, "stop pc is %08lx\n", pc
);
67 cris_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
69 unsigned long newpc
= pc
;
70 supply_register_by_name (regcache
, "pc", &newpc
);
73 static const unsigned short cris_breakpoint
= 0xe938;
74 #define cris_breakpoint_len 2
77 cris_breakpoint_at (CORE_ADDR where
)
81 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
83 if (insn
== cris_breakpoint
)
86 /* If necessary, recognize more trap instructions here. GDB only uses the
91 /* We only place breakpoints in empty marker functions, and thread locking
92 is outside of the function. So rather than importing software single-step,
93 we can just run until exit. */
95 /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
96 for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event
97 will fail when debugging multi-threaded applications. */
100 cris_reinsert_addr (void)
102 struct regcache
*regcache
= get_thread_regcache (current_inferior
, 1);
104 collect_register_by_name (regcache
, "srp", &pc
);
109 cris_write_data_breakpoint (struct regcache
*regcache
,
110 int bp
, unsigned long start
, unsigned long end
)
115 supply_register_by_name (regcache
, "s3", &start
);
116 supply_register_by_name (regcache
, "s4", &end
);
119 supply_register_by_name (regcache
, "s5", &start
);
120 supply_register_by_name (regcache
, "s6", &end
);
123 supply_register_by_name (regcache
, "s7", &start
);
124 supply_register_by_name (regcache
, "s8", &end
);
127 supply_register_by_name (regcache
, "s9", &start
);
128 supply_register_by_name (regcache
, "s10", &end
);
131 supply_register_by_name (regcache
, "s11", &start
);
132 supply_register_by_name (regcache
, "s12", &end
);
135 supply_register_by_name (regcache
, "s13", &start
);
136 supply_register_by_name (regcache
, "s14", &end
);
142 cris_insert_point (char type
, CORE_ADDR addr
, int len
)
145 unsigned long bp_ctrl
;
146 unsigned long start
, end
;
148 struct regcache
*regcache
;
150 /* Breakpoint/watchpoint types (GDB terminology):
151 0 = memory breakpoint for instructions
152 (not supported; done via memory write instead)
153 1 = hardware breakpoint for instructions (not supported)
154 2 = write watchpoint (supported)
155 3 = read watchpoint (supported)
156 4 = access watchpoint (supported). */
158 if (type
< '2' || type
> '4')
164 regcache
= get_thread_regcache (current_inferior
, 1);
166 /* Read watchpoints are set as access watchpoints, because of GDB's
167 inability to deal with pure read watchpoints. */
171 /* Get the configuration register. */
172 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
174 /* The watchpoint allocation scheme is the simplest possible.
175 For example, if a region is watched for read and
176 a write watch is requested, a new watchpoint will
177 be used. Also, if a watch for a region that is already
178 covered by one or more existing watchpoints, a new
179 watchpoint will be used. */
181 /* First, find a free data watchpoint. */
182 for (bp
= 0; bp
< 6; bp
++)
184 /* Each data watchpoint's control registers occupy 2 bits
185 (hence the 3), starting at bit 2 for D0 (hence the 2)
186 with 4 bits between for each watchpoint (yes, the 4). */
187 if (!(bp_ctrl
& (0x3 << (2 + (bp
* 4)))))
193 /* We're out of watchpoints. */
197 /* Configure the control register first. */
198 if (type
== '3' || type
== '4')
200 /* Trigger on read. */
201 bp_ctrl
|= (1 << (2 + bp
* 4));
203 if (type
== '2' || type
== '4')
205 /* Trigger on write. */
206 bp_ctrl
|= (2 << (2 + bp
* 4));
209 /* Setup the configuration register. */
210 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
212 /* Setup the range. */
214 end
= addr
+ len
- 1;
216 /* Configure the watchpoint register. */
217 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
219 collect_register_by_name (regcache
, "ccs", &ccs
);
220 /* Set the S1 flag to enable watchpoints. */
222 supply_register_by_name (regcache
, "ccs", &ccs
);
228 cris_remove_point (char type
, CORE_ADDR addr
, int len
)
231 unsigned long bp_ctrl
;
232 unsigned long start
, end
;
233 struct regcache
*regcache
;
234 unsigned long bp_d_regs
[12];
236 /* Breakpoint/watchpoint types:
237 0 = memory breakpoint for instructions
238 (not supported; done via memory write instead)
239 1 = hardware breakpoint for instructions (not supported)
240 2 = write watchpoint (supported)
241 3 = read watchpoint (supported)
242 4 = access watchpoint (supported). */
243 if (type
< '2' || type
> '4')
246 regcache
= get_thread_regcache (current_inferior
, 1);
248 /* Read watchpoints are set as access watchpoints, because of GDB's
249 inability to deal with pure read watchpoints. */
253 /* Get the configuration register. */
254 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
256 /* Try to find a watchpoint that is configured for the
257 specified range, then check that read/write also matches. */
259 /* Ugly pointer arithmetic, since I cannot rely on a
260 single switch (addr) as there may be several watchpoints with
261 the same start address for example. */
263 /* Get all range registers to simplify search. */
264 collect_register_by_name (regcache
, "s3", &bp_d_regs
[0]);
265 collect_register_by_name (regcache
, "s4", &bp_d_regs
[1]);
266 collect_register_by_name (regcache
, "s5", &bp_d_regs
[2]);
267 collect_register_by_name (regcache
, "s6", &bp_d_regs
[3]);
268 collect_register_by_name (regcache
, "s7", &bp_d_regs
[4]);
269 collect_register_by_name (regcache
, "s8", &bp_d_regs
[5]);
270 collect_register_by_name (regcache
, "s9", &bp_d_regs
[6]);
271 collect_register_by_name (regcache
, "s10", &bp_d_regs
[7]);
272 collect_register_by_name (regcache
, "s11", &bp_d_regs
[8]);
273 collect_register_by_name (regcache
, "s12", &bp_d_regs
[9]);
274 collect_register_by_name (regcache
, "s13", &bp_d_regs
[10]);
275 collect_register_by_name (regcache
, "s14", &bp_d_regs
[11]);
277 for (bp
= 0; bp
< 6; bp
++)
279 if (bp_d_regs
[bp
* 2] == addr
280 && bp_d_regs
[bp
* 2 + 1] == (addr
+ len
- 1)) {
281 /* Matching range. */
282 int bitpos
= 2 + bp
* 4;
285 /* Read/write bits for this BP. */
286 rw_bits
= (bp_ctrl
& (0x3 << bitpos
)) >> bitpos
;
288 if ((type
== '3' && rw_bits
== 0x1)
289 || (type
== '2' && rw_bits
== 0x2)
290 || (type
== '4' && rw_bits
== 0x3))
292 /* Read/write matched. */
300 /* No watchpoint matched. */
304 /* Found a matching watchpoint. Now, deconfigure it by
305 both disabling read/write in bp_ctrl and zeroing its
306 start/end addresses. */
307 bp_ctrl
&= ~(3 << (2 + (bp
* 4)));
308 /* Setup the configuration register. */
309 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
312 /* Configure the watchpoint register. */
313 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
315 /* Note that we don't clear the S1 flag here. It's done when continuing. */
320 cris_stopped_by_watchpoint (void)
323 struct regcache
*regcache
= get_thread_regcache (current_inferior
, 1);
325 collect_register_by_name (regcache
, "exs", &exs
);
327 return (((exs
& 0xff00) >> 8) == 0xc);
331 cris_stopped_data_address (void)
334 struct regcache
*regcache
= get_thread_regcache (current_inferior
, 1);
336 collect_register_by_name (regcache
, "eda", &eda
);
338 /* FIXME: Possibly adjust to match watched range. */
343 cris_fill_gregset (struct regcache
*regcache
, void *buf
)
347 for (i
= 0; i
< cris_num_regs
; i
++)
349 if (cris_regmap
[i
] != -1)
350 collect_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
355 cris_store_gregset (struct regcache
*regcache
, const void *buf
)
359 for (i
= 0; i
< cris_num_regs
; i
++)
361 if (cris_regmap
[i
] != -1)
362 supply_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
367 cris_arch_setup (void)
369 current_process ()->tdesc
= tdesc_crisv32
;
372 typedef unsigned long elf_gregset_t
[cris_num_regs
];
374 static struct regset_info cris_regsets
[] = {
375 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, cris_num_regs
* 4,
376 GENERAL_REGS
, cris_fill_gregset
, cris_store_gregset
},
377 { 0, 0, 0, -1, -1, NULL
, NULL
}
381 static struct regsets_info cris_regsets_info
=
383 cris_regsets
, /* regsets */
385 NULL
, /* disabled_regsets */
388 static struct usrregs_info cris_usrregs_info
=
394 static struct regs_info regs_info
=
396 NULL
, /* regset_bitmap */
401 static const struct regs_info
*
402 cris_regs_info (void)
407 struct linux_target_ops the_low_target
= {
412 NULL
, /* fetch_register */
415 (const unsigned char *) &cris_breakpoint
,
422 cris_stopped_by_watchpoint
,
423 cris_stopped_data_address
,
427 initialize_low_arch (void)
429 init_register_crisv32 ();
431 initialize_regsets_info (&cris_regsets_info
);