gdb/gdbserver/linux-mips-low.c

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2015 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Defined in auto-generated file mips-linux.c.  */
  29 void init_registers_mips_linux (void);
  30 extern const struct target_desc *tdesc_mips_linux;
  31
  32 /* Defined in auto-generated file mips-dsp-linux.c.  */
  33 void init_registers_mips_dsp_linux (void);
  34 extern const struct target_desc *tdesc_mips_dsp_linux;
  35
  36 /* Defined in auto-generated file mips64-linux.c.  */
  37 void init_registers_mips64_linux (void);
  38 extern const struct target_desc *tdesc_mips64_linux;
  39
  40 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  41 void init_registers_mips64_dsp_linux (void);
  42 extern const struct target_desc *tdesc_mips64_dsp_linux;
  43
  44 #ifdef __mips64
  45 #define tdesc_mips_linux tdesc_mips64_linux
  46 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  47 #endif
  48
  49 #ifndef PTRACE_GET_THREAD_AREA
  50 #define PTRACE_GET_THREAD_AREA 25
  51 #endif
  52
  53 #ifdef HAVE_SYS_REG_H
  54 #include <sys/reg.h>
  55 #endif
  56
  57 #define mips_num_regs 73
  58 #define mips_dsp_num_regs 80
  59
  60 #include <asm/ptrace.h>
  61
  62 #ifndef DSP_BASE
  63 #define DSP_BASE 71
  64 #define DSP_CONTROL 77
  65 #endif
  66
  67 union mips_register
  68 {
  69   unsigned char buf[8];
  70
  71   /* Deliberately signed, for proper sign extension.  */
  72   int reg32;
  73   long long reg64;
  74 };
  75
  76 /* Return the ptrace ``address'' of register REGNO. */
  77
  78 #define mips_base_regs                                                  \
  79   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
  80   8,  9,  10, 11, 12, 13, 14, 15,                                       \
  81   16, 17, 18, 19, 20, 21, 22, 23,                                       \
  82   24, 25, 26, 27, 28, 29, 30, 31,                                       \
  83                                                                         \
  84   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
  85                                                                         \
  86   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
  87   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
  88   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
  89   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
  90   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
  91   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
  92   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
  93   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
  94   FPC_CSR, FPC_EIR
  95
  96 #define mips_dsp_regs                                                   \
  97   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
  98   DSP_BASE + 4,  DSP_BASE + 5,                                          \
  99   DSP_CONTROL
 100
 101 static int mips_regmap[mips_num_regs] = {
 102   mips_base_regs,
 103   0
 104 };
 105
 106 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 107   mips_base_regs,
 108   mips_dsp_regs,
 109   0
 110 };
 111
 112 /* DSP registers are not in any regset and can only be accessed
 113    individually.  */
 114
 115 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 116   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 117 };
 118
 119 static int have_dsp = -1;
 120
 121 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 122    user register set accordingly.  */
 123
 124 static const struct target_desc *
 125 mips_read_description (void)
 126 {
 127   if (have_dsp < 0)
 128     {
 129       int pid = lwpid_of (current_thread);
 130
 131       errno = 0;
 132       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 133       switch (errno)
 134         {
 135         case 0:
 136           have_dsp = 1;
 137           break;
 138         case EIO:
 139           have_dsp = 0;
 140           break;
 141         default:
 142           perror_with_name ("ptrace");
 143           break;
 144         }
 145     }
 146
 147   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 148 }
 149
 150 static void
 151 mips_arch_setup (void)
 152 {
 153   current_process ()->tdesc = mips_read_description ();
 154 }
 155
 156 static struct usrregs_info *
 157 get_usrregs_info (void)
 158 {
 159   const struct regs_info *regs_info = the_low_target.regs_info ();
 160
 161   return regs_info->usrregs;
 162 }
 163
 164 /* Per-process arch-specific data we want to keep.  */
 165
 166 struct arch_process_info
 167 {
 168   /* -1 if the kernel and/or CPU do not support watch registers.
 169       1 if watch_readback is valid and we can read style, num_valid
 170         and the masks.
 171       0 if we need to read the watch_readback.  */
 172
 173   int watch_readback_valid;
 174
 175   /* Cached watch register read values.  */
 176
 177   struct pt_watch_regs watch_readback;
 178
 179   /* Current watchpoint requests for this process.  */
 180
 181   struct mips_watchpoint *current_watches;
 182
 183   /* The current set of watch register values for writing the
 184      registers.  */
 185
 186   struct pt_watch_regs watch_mirror;
 187 };
 188
 189 /* Per-thread arch-specific data we want to keep.  */
 190
 191 struct arch_lwp_info
 192 {
 193   /* Non-zero if our copy differs from what's recorded in the thread.  */
 194   int watch_registers_changed;
 195 };
 196
 197 /* From mips-linux-nat.c.  */
 198
 199 /* Pseudo registers can not be read.  ptrace does not provide a way to
 200    read (or set) PS_REGNUM, and there's no point in reading or setting
 201    ZERO_REGNUM.  We also can not set BADVADDR, CAUSE, or FCRIR via
 202    ptrace().  */
 203
 204 static int
 205 mips_cannot_fetch_register (int regno)
 206 {
 207   const struct target_desc *tdesc;
 208
 209   if (get_usrregs_info ()->regmap[regno] == -1)
 210     return 1;
 211
 212   tdesc = current_process ()->tdesc;
 213
 214   if (find_regno (tdesc, "r0") == regno)
 215     return 1;
 216
 217   return 0;
 218 }
 219
 220 static int
 221 mips_cannot_store_register (int regno)
 222 {
 223   const struct target_desc *tdesc;
 224
 225   if (get_usrregs_info ()->regmap[regno] == -1)
 226     return 1;
 227
 228   tdesc = current_process ()->tdesc;
 229
 230   if (find_regno (tdesc, "r0") == regno)
 231     return 1;
 232
 233   if (find_regno (tdesc, "cause") == regno)
 234     return 1;
 235
 236   if (find_regno (tdesc, "badvaddr") == regno)
 237     return 1;
 238
 239   if (find_regno (tdesc, "fir") == regno)
 240     return 1;
 241
 242   return 0;
 243 }
 244
 245 static CORE_ADDR
 246 mips_get_pc (struct regcache *regcache)
 247 {
 248   union mips_register pc;
 249   collect_register_by_name (regcache, "pc", pc.buf);
 250   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 251 }
 252
 253 static void
 254 mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
 255 {
 256   union mips_register newpc;
 257   if (register_size (regcache->tdesc, 0) == 4)
 258     newpc.reg32 = pc;
 259   else
 260     newpc.reg64 = pc;
 261
 262   supply_register_by_name (regcache, "pc", newpc.buf);
 263 }
 264
 265 /* Correct in either endianness.  */
 266 static const unsigned int mips_breakpoint = 0x0005000d;
 267 #define mips_breakpoint_len 4
 268
 269 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
 270
 271 static const gdb_byte *
 272 mips_sw_breakpoint_from_kind (int kind, int *size)
 273 {
 274   *size = mips_breakpoint_len;
 275   return (const gdb_byte *) &mips_breakpoint;
 276 }
 277
 278 /* We only place breakpoints in empty marker functions, and thread locking
 279    is outside of the function.  So rather than importing software single-step,
 280    we can just run until exit.  */
 281 static CORE_ADDR
 282 mips_reinsert_addr (void)
 283 {
 284   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 285   union mips_register ra;
 286   collect_register_by_name (regcache, "r31", ra.buf);
 287   return register_size (regcache->tdesc, 0) == 4 ? ra.reg32 : ra.reg64;
 288 }
 289
 290 static int
 291 mips_breakpoint_at (CORE_ADDR where)
 292 {
 293   unsigned int insn;
 294
 295   (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
 296   if (insn == mips_breakpoint)
 297     return 1;
 298
 299   /* If necessary, recognize more trap instructions here.  GDB only uses the
 300      one.  */
 301   return 0;
 302 }
 303
 304 /* Mark the watch registers of lwp, represented by ENTRY, as changed,
 305    if the lwp's process id is *PID_P.  */
 306
 307 static int
 308 update_watch_registers_callback (struct inferior_list_entry *entry,
 309                                  void *pid_p)
 310 {
 311   struct thread_info *thread = (struct thread_info *) entry;
 312   struct lwp_info *lwp = get_thread_lwp (thread);
 313   int pid = *(int *) pid_p;
 314
 315   /* Only update the threads of this process.  */
 316   if (pid_of (thread) == pid)
 317     {
 318       /* The actual update is done later just before resuming the lwp,
 319          we just mark that the registers need updating.  */
 320       lwp->arch_private->watch_registers_changed = 1;
 321
 322       /* If the lwp isn't stopped, force it to momentarily pause, so
 323          we can update its watch registers.  */
 324       if (!lwp->stopped)
 325         linux_stop_lwp (lwp);
 326     }
 327
 328   return 0;
 329 }
 330
 331 /* This is the implementation of linux_target_ops method
 332    new_process.  */
 333
 334 static struct arch_process_info *
 335 mips_linux_new_process (void)
 336 {
 337   struct arch_process_info *info = XCNEW (struct arch_process_info);
 338
 339   return info;
 340 }
 341
 342 /* This is the implementation of linux_target_ops method new_thread.
 343    Mark the watch registers as changed, so the threads' copies will
 344    be updated.  */
 345
 346 static void
 347 mips_linux_new_thread (struct lwp_info *lwp)
 348 {
 349   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 350
 351   info->watch_registers_changed = 1;
 352
 353   lwp->arch_private = info;
 354 }
 355
 356 /* Create a new mips_watchpoint and add it to the list.  */
 357
 358 static void
 359 mips_add_watchpoint (struct arch_process_info *private, CORE_ADDR addr,
 360                      int len, int watch_type)
 361 {
 362   struct mips_watchpoint *new_watch;
 363   struct mips_watchpoint **pw;
 364
 365   new_watch = XNEW (struct mips_watchpoint);
 366   new_watch->addr = addr;
 367   new_watch->len = len;
 368   new_watch->type = watch_type;
 369   new_watch->next = NULL;
 370
 371   pw = &private->current_watches;
 372   while (*pw != NULL)
 373     pw = &(*pw)->next;
 374   *pw = new_watch;
 375 }
 376
 377 /* Hook to call when a new fork is attached.  */
 378
 379 static void
 380 mips_linux_new_fork (struct process_info *parent,
 381                         struct process_info *child)
 382 {
 383   struct arch_process_info *parent_private;
 384   struct arch_process_info *child_private;
 385   struct mips_watchpoint *wp;
 386
 387   /* These are allocated by linux_add_process.  */
 388   gdb_assert (parent->priv != NULL
 389               && parent->priv->arch_private != NULL);
 390   gdb_assert (child->priv != NULL
 391               && child->priv->arch_private != NULL);
 392
 393   /* Linux kernel before 2.6.33 commit
 394      72f674d203cd230426437cdcf7dd6f681dad8b0d
 395      will inherit hardware debug registers from parent
 396      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 397      zeroed debug registers.
 398
 399      GDB core assumes the child inherits the watchpoints/hw
 400      breakpoints of the parent, and will remove them all from the
 401      forked off process.  Copy the debug registers mirrors into the
 402      new process so that all breakpoints and watchpoints can be
 403      removed together.  The debug registers mirror will become zeroed
 404      in the end before detaching the forked off process, thus making
 405      this compatible with older Linux kernels too.  */
 406
 407   parent_private = parent->priv->arch_private;
 408   child_private = child->priv->arch_private;
 409
 410   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 411   child_private->watch_readback = parent_private->watch_readback;
 412
 413   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 414     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 415
 416   child_private->watch_mirror = parent_private->watch_mirror;
 417 }
 418 /* This is the implementation of linux_target_ops method
 419    prepare_to_resume.  If the watch regs have changed, update the
 420    thread's copies.  */
 421
 422 static void
 423 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 424 {
 425   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 426   struct process_info *proc = find_process_pid (ptid_get_pid (ptid));
 427   struct arch_process_info *priv = proc->priv->arch_private;
 428
 429   if (lwp->arch_private->watch_registers_changed)
 430     {
 431       /* Only update the watch registers if we have set or unset a
 432          watchpoint already.  */
 433       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 434         {
 435           /* Write the mirrored watch register values.  */
 436           int tid = ptid_get_lwp (ptid);
 437
 438           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 439                             &priv->watch_mirror, NULL))
 440             perror_with_name ("Couldn't write watch register");
 441         }
 442
 443       lwp->arch_private->watch_registers_changed = 0;
 444     }
 445 }
 446
 447 static int
 448 mips_supports_z_point_type (char z_type)
 449 {
 450   switch (z_type)
 451     {
 452     case Z_PACKET_WRITE_WP:
 453     case Z_PACKET_READ_WP:
 454     case Z_PACKET_ACCESS_WP:
 455       return 1;
 456     default:
 457       return 0;
 458     }
 459 }
 460
 461 /* This is the implementation of linux_target_ops method
 462    insert_point.  */
 463
 464 static int
 465 mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 466                    int len, struct raw_breakpoint *bp)
 467 {
 468   struct process_info *proc = current_process ();
 469   struct arch_process_info *priv = proc->priv->arch_private;
 470   struct pt_watch_regs regs;
 471   int pid;
 472   long lwpid;
 473   enum target_hw_bp_type watch_type;
 474   uint32_t irw;
 475
 476   lwpid = lwpid_of (current_thread);
 477   if (!mips_linux_read_watch_registers (lwpid,
 478                                         &priv->watch_readback,
 479                                         &priv->watch_readback_valid,
 480                                         0))
 481     return -1;
 482
 483   if (len <= 0)
 484     return -1;
 485
 486   regs = priv->watch_readback;
 487   /* Add the current watches.  */
 488   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 489
 490   /* Now try to add the new watch.  */
 491   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 492   irw = mips_linux_watch_type_to_irw (watch_type);
 493   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 494     return -1;
 495
 496   /* It fit.  Stick it on the end of the list.  */
 497   mips_add_watchpoint (priv, addr, len, watch_type);
 498
 499   priv->watch_mirror = regs;
 500
 501   /* Only update the threads of this process.  */
 502   pid = pid_of (proc);
 503   find_inferior (&all_threads, update_watch_registers_callback, &pid);
 504
 505   return 0;
 506 }
 507
 508 /* This is the implementation of linux_target_ops method
 509    remove_point.  */
 510
 511 static int
 512 mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
 513                    int len, struct raw_breakpoint *bp)
 514 {
 515   struct process_info *proc = current_process ();
 516   struct arch_process_info *priv = proc->priv->arch_private;
 517
 518   int deleted_one;
 519   int pid;
 520   enum target_hw_bp_type watch_type;
 521
 522   struct mips_watchpoint **pw;
 523   struct mips_watchpoint *w;
 524
 525   /* Search for a known watch that matches.  Then unlink and free it.  */
 526   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 527   deleted_one = 0;
 528   pw = &priv->current_watches;
 529   while ((w = *pw))
 530     {
 531       if (w->addr == addr && w->len == len && w->type == watch_type)
 532         {
 533           *pw = w->next;
 534           free (w);
 535           deleted_one = 1;
 536           break;
 537         }
 538       pw = &(w->next);
 539     }
 540
 541   if (!deleted_one)
 542     return -1;  /* We don't know about it, fail doing nothing.  */
 543
 544   /* At this point watch_readback is known to be valid because we
 545      could not have added the watch without reading it.  */
 546   gdb_assert (priv->watch_readback_valid == 1);
 547
 548   priv->watch_mirror = priv->watch_readback;
 549   mips_linux_watch_populate_regs (priv->current_watches,
 550                                   &priv->watch_mirror);
 551
 552   /* Only update the threads of this process.  */
 553   pid = pid_of (proc);
 554   find_inferior (&all_threads, update_watch_registers_callback, &pid);
 555   return 0;
 556 }
 557
 558 /* This is the implementation of linux_target_ops method
 559    stopped_by_watchpoint.  The watchhi R and W bits indicate
 560    the watch register triggered. */
 561
 562 static int
 563 mips_stopped_by_watchpoint (void)
 564 {
 565   struct process_info *proc = current_process ();
 566   struct arch_process_info *priv = proc->priv->arch_private;
 567   int n;
 568   int num_valid;
 569   long lwpid = lwpid_of (current_thread);
 570
 571   if (!mips_linux_read_watch_registers (lwpid,
 572                                         &priv->watch_readback,
 573                                         &priv->watch_readback_valid,
 574                                         1))
 575     return 0;
 576
 577   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 578
 579   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 580     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 581         & (R_MASK | W_MASK))
 582       return 1;
 583
 584   return 0;
 585 }
 586
 587 /* This is the implementation of linux_target_ops method
 588    stopped_data_address.  */
 589
 590 static CORE_ADDR
 591 mips_stopped_data_address (void)
 592 {
 593   struct process_info *proc = current_process ();
 594   struct arch_process_info *priv = proc->priv->arch_private;
 595   int n;
 596   int num_valid;
 597   long lwpid = lwpid_of (current_thread);
 598
 599   /* On MIPS we don't know the low order 3 bits of the data address.
 600      GDB does not support remote targets that can't report the
 601      watchpoint address.  So, make our best guess; return the starting
 602      address of a watchpoint request which overlaps the one that
 603      triggered.  */
 604
 605   if (!mips_linux_read_watch_registers (lwpid,
 606                                         &priv->watch_readback,
 607                                         &priv->watch_readback_valid,
 608                                         0))
 609     return 0;
 610
 611   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 612
 613   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 614     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 615         & (R_MASK | W_MASK))
 616       {
 617         CORE_ADDR t_low, t_hi;
 618         int t_irw;
 619         struct mips_watchpoint *watch;
 620
 621         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 622         t_irw = t_low & IRW_MASK;
 623         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 624                 | IRW_MASK);
 625         t_low &= ~(CORE_ADDR)t_hi;
 626
 627         for (watch = priv->current_watches;
 628              watch != NULL;
 629              watch = watch->next)
 630           {
 631             CORE_ADDR addr = watch->addr;
 632             CORE_ADDR last_byte = addr + watch->len - 1;
 633
 634             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 635               {
 636                 /* Different type.  */
 637                 continue;
 638               }
 639             /* Check for overlap of even a single byte.  */
 640             if (last_byte >= t_low && addr <= t_low + t_hi)
 641               return addr;
 642           }
 643       }
 644
 645   /* Shouldn't happen.  */
 646   return 0;
 647 }
 648
 649 /* Fetch the thread-local storage pointer for libthread_db.  */
 650
 651 ps_err_e
 652 ps_get_thread_area (const struct ps_prochandle *ph,
 653                     lwpid_t lwpid, int idx, void **base)
 654 {
 655   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 656     return PS_ERR;
 657
 658   /* IDX is the bias from the thread pointer to the beginning of the
 659      thread descriptor.  It has to be subtracted due to implementation
 660      quirks in libthread_db.  */
 661   *base = (void *) ((char *)*base - idx);
 662
 663   return PS_OK;
 664 }
 665
 666 #ifdef HAVE_PTRACE_GETREGS
 667
 668 static void
 669 mips_collect_register (struct regcache *regcache,
 670                        int use_64bit, int regno, union mips_register *reg)
 671 {
 672   union mips_register tmp_reg;
 673
 674   if (use_64bit)
 675     {
 676       collect_register (regcache, regno, &tmp_reg.reg64);
 677       *reg = tmp_reg;
 678     }
 679   else
 680     {
 681       collect_register (regcache, regno, &tmp_reg.reg32);
 682       reg->reg64 = tmp_reg.reg32;
 683     }
 684 }
 685
 686 static void
 687 mips_supply_register (struct regcache *regcache,
 688                       int use_64bit, int regno, const union mips_register *reg)
 689 {
 690   int offset = 0;
 691
 692   /* For big-endian 32-bit targets, ignore the high four bytes of each
 693      eight-byte slot.  */
 694   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 695     offset = 4;
 696
 697   supply_register (regcache, regno, reg->buf + offset);
 698 }
 699
 700 static void
 701 mips_collect_register_32bit (struct regcache *regcache,
 702                              int use_64bit, int regno, unsigned char *buf)
 703 {
 704   union mips_register tmp_reg;
 705   int reg32;
 706
 707   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 708   reg32 = tmp_reg.reg64;
 709   memcpy (buf, &reg32, 4);
 710 }
 711
 712 static void
 713 mips_supply_register_32bit (struct regcache *regcache,
 714                             int use_64bit, int regno, const unsigned char *buf)
 715 {
 716   union mips_register tmp_reg;
 717   int reg32;
 718
 719   memcpy (&reg32, buf, 4);
 720   tmp_reg.reg64 = reg32;
 721   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 722 }
 723
 724 static void
 725 mips_fill_gregset (struct regcache *regcache, void *buf)
 726 {
 727   union mips_register *regset = buf;
 728   int i, use_64bit;
 729   const struct target_desc *tdesc = regcache->tdesc;
 730
 731   use_64bit = (register_size (tdesc, 0) == 8);
 732
 733   for (i = 1; i < 32; i++)
 734     mips_collect_register (regcache, use_64bit, i, regset + i);
 735
 736   mips_collect_register (regcache, use_64bit,
 737                          find_regno (tdesc, "lo"), regset + 32);
 738   mips_collect_register (regcache, use_64bit,
 739                          find_regno (tdesc, "hi"), regset + 33);
 740   mips_collect_register (regcache, use_64bit,
 741                          find_regno (tdesc, "pc"), regset + 34);
 742   mips_collect_register (regcache, use_64bit,
 743                          find_regno (tdesc, "badvaddr"), regset + 35);
 744   mips_collect_register (regcache, use_64bit,
 745                          find_regno (tdesc, "status"), regset + 36);
 746   mips_collect_register (regcache, use_64bit,
 747                          find_regno (tdesc, "cause"), regset + 37);
 748
 749   mips_collect_register (regcache, use_64bit,
 750                          find_regno (tdesc, "restart"), regset + 0);
 751 }
 752
 753 static void
 754 mips_store_gregset (struct regcache *regcache, const void *buf)
 755 {
 756   const union mips_register *regset = buf;
 757   int i, use_64bit;
 758
 759   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 760
 761   for (i = 0; i < 32; i++)
 762     mips_supply_register (regcache, use_64bit, i, regset + i);
 763
 764   mips_supply_register (regcache, use_64bit,
 765                         find_regno (regcache->tdesc, "lo"), regset + 32);
 766   mips_supply_register (regcache, use_64bit,
 767                         find_regno (regcache->tdesc, "hi"), regset + 33);
 768   mips_supply_register (regcache, use_64bit,
 769                         find_regno (regcache->tdesc, "pc"), regset + 34);
 770   mips_supply_register (regcache, use_64bit,
 771                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 772   mips_supply_register (regcache, use_64bit,
 773                         find_regno (regcache->tdesc, "status"), regset + 36);
 774   mips_supply_register (regcache, use_64bit,
 775                         find_regno (regcache->tdesc, "cause"), regset + 37);
 776
 777   mips_supply_register (regcache, use_64bit,
 778                         find_regno (regcache->tdesc, "restart"), regset + 0);
 779 }
 780
 781 static void
 782 mips_fill_fpregset (struct regcache *regcache, void *buf)
 783 {
 784   union mips_register *regset = buf;
 785   int i, use_64bit, first_fp, big_endian;
 786
 787   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 788   first_fp = find_regno (regcache->tdesc, "f0");
 789   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 790
 791   /* See GDB for a discussion of this peculiar layout.  */
 792   for (i = 0; i < 32; i++)
 793     if (use_64bit)
 794       collect_register (regcache, first_fp + i, regset[i].buf);
 795     else
 796       collect_register (regcache, first_fp + i,
 797                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 798
 799   mips_collect_register_32bit (regcache, use_64bit,
 800                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 801   mips_collect_register_32bit (regcache, use_64bit,
 802                                find_regno (regcache->tdesc, "fir"),
 803                                regset[32].buf + 4);
 804 }
 805
 806 static void
 807 mips_store_fpregset (struct regcache *regcache, const void *buf)
 808 {
 809   const union mips_register *regset = buf;
 810   int i, use_64bit, first_fp, big_endian;
 811
 812   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 813   first_fp = find_regno (regcache->tdesc, "f0");
 814   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 815
 816   /* See GDB for a discussion of this peculiar layout.  */
 817   for (i = 0; i < 32; i++)
 818     if (use_64bit)
 819       supply_register (regcache, first_fp + i, regset[i].buf);
 820     else
 821       supply_register (regcache, first_fp + i,
 822                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 823
 824   mips_supply_register_32bit (regcache, use_64bit,
 825                               find_regno (regcache->tdesc, "fcsr"),
 826                               regset[32].buf);
 827   mips_supply_register_32bit (regcache, use_64bit,
 828                               find_regno (regcache->tdesc, "fir"),
 829                               regset[32].buf + 4);
 830 }
 831 #endif /* HAVE_PTRACE_GETREGS */
 832
 833 static struct regset_info mips_regsets[] = {
 834 #ifdef HAVE_PTRACE_GETREGS
 835   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 836     mips_fill_gregset, mips_store_gregset },
 837   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 838     mips_fill_fpregset, mips_store_fpregset },
 839 #endif /* HAVE_PTRACE_GETREGS */
 840   { 0, 0, 0, -1, -1, NULL, NULL }
 841 };
 842
 843 static struct regsets_info mips_regsets_info =
 844   {
 845     mips_regsets, /* regsets */
 846     0, /* num_regsets */
 847     NULL, /* disabled_regsets */
 848   };
 849
 850 static struct usrregs_info mips_dsp_usrregs_info =
 851   {
 852     mips_dsp_num_regs,
 853     mips_dsp_regmap,
 854   };
 855
 856 static struct usrregs_info mips_usrregs_info =
 857   {
 858     mips_num_regs,
 859     mips_regmap,
 860   };
 861
 862 static struct regs_info dsp_regs_info =
 863   {
 864     mips_dsp_regset_bitmap,
 865     &mips_dsp_usrregs_info,
 866     &mips_regsets_info
 867   };
 868
 869 static struct regs_info regs_info =
 870   {
 871     NULL, /* regset_bitmap */
 872     &mips_usrregs_info,
 873     &mips_regsets_info
 874   };
 875
 876 static const struct regs_info *
 877 mips_regs_info (void)
 878 {
 879   if (have_dsp)
 880     return &dsp_regs_info;
 881   else
 882     return &regs_info;
 883 }
 884
 885 struct linux_target_ops the_low_target = {
 886   mips_arch_setup,
 887   mips_regs_info,
 888   mips_cannot_fetch_register,
 889   mips_cannot_store_register,
 890   NULL, /* fetch_register */
 891   mips_get_pc,
 892   mips_set_pc,
 893   NULL, /* breakpoint_kind_from_pc */
 894   mips_sw_breakpoint_from_kind,
 895   mips_reinsert_addr,
 896   0,
 897   mips_breakpoint_at,
 898   mips_supports_z_point_type,
 899   mips_insert_point,
 900   mips_remove_point,
 901   mips_stopped_by_watchpoint,
 902   mips_stopped_data_address,
 903   NULL,
 904   NULL,
 905   NULL, /* siginfo_fixup */
 906   mips_linux_new_process,
 907   mips_linux_new_thread,
 908   mips_linux_new_fork,
 909   mips_linux_prepare_to_resume
 910 };
 911
 912 void
 913 initialize_low_arch (void)
 914 {
 915   /* Initialize the Linux target descriptions.  */
 916   init_registers_mips_linux ();
 917   init_registers_mips_dsp_linux ();
 918   init_registers_mips64_linux ();
 919   init_registers_mips64_dsp_linux ();
 920
 921   initialize_regsets_info (&mips_regsets_info);
 922 }