1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Holds the AT_HWCAP auxv entry. */
49 static unsigned long ppc_hwcap
;
51 /* Holds the AT_HWCAP2 auxv entry. */
53 static unsigned long ppc_hwcap2
;
56 #define ppc_num_regs 73
59 /* We use a constant for FPSCR instead of PT_FPSCR, because
60 many shipped PPC64 kernels had the wrong value in ptrace.h. */
61 static int ppc_regmap
[] =
62 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
63 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
64 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
65 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
66 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
67 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
68 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
69 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
70 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
71 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
72 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
73 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
74 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
75 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
76 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
77 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
78 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
79 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
80 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
82 /* Currently, don't check/send MQ. */
83 static int ppc_regmap
[] =
84 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
85 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
86 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
87 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
88 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
89 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
90 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
91 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
92 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
93 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
94 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
95 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
96 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
97 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
98 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
99 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
100 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
101 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
102 PT_ORIG_R3
* 4, PT_TRAP
* 4
105 static int ppc_regmap_e500
[] =
106 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
107 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
108 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
109 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
110 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
111 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
112 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
113 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
122 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
123 PT_CTR
* 4, PT_XER
* 4, -1,
124 PT_ORIG_R3
* 4, PT_TRAP
* 4
128 /* Check whether the kernel provides a register set with number
129 REGSET_ID of size REGSETSIZE for process/thread TID. */
132 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
134 void *buf
= alloca (regsetsize
);
138 iov
.iov_len
= regsetsize
;
140 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
147 ppc_cannot_store_register (int regno
)
149 const struct target_desc
*tdesc
= current_process ()->tdesc
;
151 #ifndef __powerpc64__
152 /* Some kernels do not allow us to store fpscr. */
153 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
154 && regno
== find_regno (tdesc
, "fpscr"))
158 /* Some kernels do not allow us to store orig_r3 or trap. */
159 if (regno
== find_regno (tdesc
, "orig_r3")
160 || regno
== find_regno (tdesc
, "trap"))
167 ppc_cannot_fetch_register (int regno
)
173 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
175 memset (buf
, 0, sizeof (long));
177 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
179 /* Little-endian values always sit at the left end of the buffer. */
180 collect_register (regcache
, regno
, buf
);
182 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
184 /* Big-endian values sit at the right end of the buffer. In case of
185 registers whose sizes are smaller than sizeof (long), we must use a
186 padding to access them correctly. */
187 int size
= register_size (regcache
->tdesc
, regno
);
189 if (size
< sizeof (long))
190 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
192 collect_register (regcache
, regno
, buf
);
195 perror_with_name ("Unexpected byte order");
199 ppc_supply_ptrace_register (struct regcache
*regcache
,
200 int regno
, const char *buf
)
202 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
204 /* Little-endian values always sit at the left end of the buffer. */
205 supply_register (regcache
, regno
, buf
);
207 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
209 /* Big-endian values sit at the right end of the buffer. In case of
210 registers whose sizes are smaller than sizeof (long), we must use a
211 padding to access them correctly. */
212 int size
= register_size (regcache
->tdesc
, regno
);
214 if (size
< sizeof (long))
215 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
217 supply_register (regcache
, regno
, buf
);
220 perror_with_name ("Unexpected byte order");
224 #define INSTR_SC 0x44000002
225 #define NR_spu_run 0x0116
227 /* If the PPU thread is currently stopped on a spu_run system call,
228 return to FD and ADDR the file handle and NPC parameter address
229 used with the system call. Return non-zero if successful. */
231 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
237 if (register_size (regcache
->tdesc
, 0) == 4)
239 unsigned int pc
, r0
, r3
, r4
;
240 collect_register_by_name (regcache
, "pc", &pc
);
241 collect_register_by_name (regcache
, "r0", &r0
);
242 collect_register_by_name (regcache
, "orig_r3", &r3
);
243 collect_register_by_name (regcache
, "r4", &r4
);
244 curr_pc
= (CORE_ADDR
) pc
;
247 *addr
= (CORE_ADDR
) r4
;
251 unsigned long pc
, r0
, r3
, r4
;
252 collect_register_by_name (regcache
, "pc", &pc
);
253 collect_register_by_name (regcache
, "r0", &r0
);
254 collect_register_by_name (regcache
, "orig_r3", &r3
);
255 collect_register_by_name (regcache
, "r4", &r4
);
256 curr_pc
= (CORE_ADDR
) pc
;
259 *addr
= (CORE_ADDR
) r4
;
262 /* Fetch instruction preceding current NIP. */
263 if ((*the_target
->read_memory
) (curr_pc
- 4,
264 (unsigned char *) &curr_insn
, 4) != 0)
266 /* It should be a "sc" instruction. */
267 if (curr_insn
!= INSTR_SC
)
269 /* System call number should be NR_spu_run. */
270 if (curr_r0
!= NR_spu_run
)
277 ppc_get_pc (struct regcache
*regcache
)
282 if (parse_spufs_run (regcache
, &fd
, &addr
))
285 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
286 return ((CORE_ADDR
)1 << 63)
287 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
289 else if (register_size (regcache
->tdesc
, 0) == 4)
292 collect_register_by_name (regcache
, "pc", &pc
);
293 return (CORE_ADDR
) pc
;
298 collect_register_by_name (regcache
, "pc", &pc
);
299 return (CORE_ADDR
) pc
;
304 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
309 if (parse_spufs_run (regcache
, &fd
, &addr
))
311 unsigned int newpc
= pc
;
312 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
314 else if (register_size (regcache
->tdesc
, 0) == 4)
316 unsigned int newpc
= pc
;
317 supply_register_by_name (regcache
, "pc", &newpc
);
321 unsigned long newpc
= pc
;
322 supply_register_by_name (regcache
, "pc", &newpc
);
328 ppc_get_auxv (unsigned long type
, unsigned long *valp
)
330 const struct target_desc
*tdesc
= current_process ()->tdesc
;
331 int wordsize
= register_size (tdesc
, 0);
332 unsigned char *data
= (unsigned char *) alloca (2 * wordsize
);
335 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
339 unsigned int *data_p
= (unsigned int *)data
;
340 if (data_p
[0] == type
)
348 unsigned long *data_p
= (unsigned long *)data
;
349 if (data_p
[0] == type
)
356 offset
+= 2 * wordsize
;
363 #ifndef __powerpc64__
364 static int ppc_regmap_adjusted
;
368 /* Correct in either endianness.
369 This instruction is "twge r2, r2", which GDB uses as a software
371 static const unsigned int ppc_breakpoint
= 0x7d821008;
372 #define ppc_breakpoint_len 4
374 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
376 static const gdb_byte
*
377 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
379 *size
= ppc_breakpoint_len
;
380 return (const gdb_byte
*) &ppc_breakpoint
;
384 ppc_breakpoint_at (CORE_ADDR where
)
388 if (where
& ((CORE_ADDR
)1 << 63))
391 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
392 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
393 NULL
, where
& 0xffffffff, 4);
399 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
400 if (insn
== ppc_breakpoint
)
402 /* If necessary, recognize more trap instructions here. GDB only uses
409 /* Implement supports_z_point_type target-ops.
410 Returns true if type Z_TYPE breakpoint is supported.
412 Handling software breakpoint at server side, so tracepoints
413 and breakpoints can be inserted at the same location. */
416 ppc_supports_z_point_type (char z_type
)
423 case Z_PACKET_WRITE_WP
:
424 case Z_PACKET_ACCESS_WP
:
430 /* Implement insert_point target-ops.
431 Returns 0 on success, -1 on failure and 1 on unsupported. */
434 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
435 int size
, struct raw_breakpoint
*bp
)
439 case raw_bkpt_type_sw
:
440 return insert_memory_breakpoint (bp
);
442 case raw_bkpt_type_hw
:
443 case raw_bkpt_type_write_wp
:
444 case raw_bkpt_type_access_wp
:
451 /* Implement remove_point target-ops.
452 Returns 0 on success, -1 on failure and 1 on unsupported. */
455 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
456 int size
, struct raw_breakpoint
*bp
)
460 case raw_bkpt_type_sw
:
461 return remove_memory_breakpoint (bp
);
463 case raw_bkpt_type_hw
:
464 case raw_bkpt_type_write_wp
:
465 case raw_bkpt_type_access_wp
:
472 /* Provide only a fill function for the general register set. ps_lgetregs
473 will use this for NPTL support. */
475 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
479 for (i
= 0; i
< 32; i
++)
480 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
482 for (i
= 64; i
< 70; i
++)
483 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
485 for (i
= 71; i
< 73; i
++)
486 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
489 /* Program Priority Register regset fill function. */
492 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
494 char *ppr
= (char *) buf
;
496 collect_register_by_name (regcache
, "ppr", ppr
);
499 /* Program Priority Register regset store function. */
502 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
504 const char *ppr
= (const char *) buf
;
506 supply_register_by_name (regcache
, "ppr", ppr
);
509 /* Data Stream Control Register regset fill function. */
512 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
514 char *dscr
= (char *) buf
;
516 collect_register_by_name (regcache
, "dscr", dscr
);
519 /* Data Stream Control Register regset store function. */
522 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
524 const char *dscr
= (const char *) buf
;
526 supply_register_by_name (regcache
, "dscr", dscr
);
529 /* Target Address Register regset fill function. */
532 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
534 char *tar
= (char *) buf
;
536 collect_register_by_name (regcache
, "tar", tar
);
539 /* Target Address Register regset store function. */
542 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
544 const char *tar
= (const char *) buf
;
546 supply_register_by_name (regcache
, "tar", tar
);
549 /* Event-Based Branching regset store function. Unless the inferior
550 has a perf event open, ptrace can return in error when reading and
551 writing to the regset, with ENODATA. For reading, the registers
552 will correctly show as unavailable. For writing, gdbserver
553 currently only caches any register writes from P and G packets and
554 the stub always tries to write all the regsets when resuming the
555 inferior, which would result in frequent warnings. For this
556 reason, we don't define a fill function. This also means that the
557 client-side regcache will be dirty if the user tries to write to
558 the EBB registers. G packets that the client sends to write to
559 unrelated registers will also include data for EBB registers, even
560 if they are unavailable. */
563 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
565 const char *regset
= (const char *) buf
;
567 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
568 .dat file is BESCR, EBBHR, EBBRR. */
569 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
570 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
571 supply_register_by_name (regcache
, "bescr", ®set
[16]);
574 /* Performance Monitoring Unit regset fill function. */
577 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
579 char *regset
= (char *) buf
;
581 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
582 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
583 collect_register_by_name (regcache
, "siar", ®set
[0]);
584 collect_register_by_name (regcache
, "sdar", ®set
[8]);
585 collect_register_by_name (regcache
, "sier", ®set
[16]);
586 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
587 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
590 /* Performance Monitoring Unit regset store function. */
593 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
595 const char *regset
= (const char *) buf
;
597 supply_register_by_name (regcache
, "siar", ®set
[0]);
598 supply_register_by_name (regcache
, "sdar", ®set
[8]);
599 supply_register_by_name (regcache
, "sier", ®set
[16]);
600 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
601 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
604 /* Hardware Transactional Memory special-purpose register regset fill
608 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
611 char *regset
= (char *) buf
;
613 base
= find_regno (regcache
->tdesc
, "tfhar");
614 for (i
= 0; i
< 3; i
++)
615 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
618 /* Hardware Transactional Memory special-purpose register regset store
622 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
625 const char *regset
= (const char *) buf
;
627 base
= find_regno (regcache
->tdesc
, "tfhar");
628 for (i
= 0; i
< 3; i
++)
629 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
632 /* For the same reasons as the EBB regset, none of the HTM
633 checkpointed regsets have a fill function. These registers are
634 only available if the inferior is in a transaction. */
636 /* Hardware Transactional Memory checkpointed general-purpose regset
640 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
642 int i
, base
, size
, endian_offset
;
643 const char *regset
= (const char *) buf
;
645 base
= find_regno (regcache
->tdesc
, "cr0");
646 size
= register_size (regcache
->tdesc
, base
);
648 gdb_assert (size
== 4 || size
== 8);
650 for (i
= 0; i
< 32; i
++)
651 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
655 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
658 supply_register_by_name (regcache
, "ccr",
659 ®set
[PT_CCR
* size
+ endian_offset
]);
661 supply_register_by_name (regcache
, "cxer",
662 ®set
[PT_XER
* size
+ endian_offset
]);
664 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
665 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
668 /* Hardware Transactional Memory checkpointed floating-point regset
672 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
675 const char *regset
= (const char *) buf
;
677 base
= find_regno (regcache
->tdesc
, "cf0");
679 for (i
= 0; i
< 32; i
++)
680 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
682 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
685 /* Hardware Transactional Memory checkpointed vector regset store
689 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
692 const char *regset
= (const char *) buf
;
695 base
= find_regno (regcache
->tdesc
, "cvr0");
697 for (i
= 0; i
< 32; i
++)
698 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
700 if (__BYTE_ORDER
== __BIG_ENDIAN
)
703 supply_register_by_name (regcache
, "cvscr",
704 ®set
[32 * 16 + vscr_offset
]);
706 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
709 /* Hardware Transactional Memory checkpointed vector-scalar regset
713 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
716 const char *regset
= (const char *) buf
;
718 base
= find_regno (regcache
->tdesc
, "cvs0h");
719 for (i
= 0; i
< 32; i
++)
720 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
723 /* Hardware Transactional Memory checkpointed Program Priority
724 Register regset store function. */
727 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
729 const char *cppr
= (const char *) buf
;
731 supply_register_by_name (regcache
, "cppr", cppr
);
734 /* Hardware Transactional Memory checkpointed Data Stream Control
735 Register regset store function. */
738 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
740 const char *cdscr
= (const char *) buf
;
742 supply_register_by_name (regcache
, "cdscr", cdscr
);
745 /* Hardware Transactional Memory checkpointed Target Address Register
746 regset store function. */
749 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
751 const char *ctar
= (const char *) buf
;
753 supply_register_by_name (regcache
, "ctar", ctar
);
757 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
760 char *regset
= (char *) buf
;
762 base
= find_regno (regcache
->tdesc
, "vs0h");
763 for (i
= 0; i
< 32; i
++)
764 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
768 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
771 const char *regset
= (const char *) buf
;
773 base
= find_regno (regcache
->tdesc
, "vs0h");
774 for (i
= 0; i
< 32; i
++)
775 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
779 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
782 char *regset
= (char *) buf
;
785 base
= find_regno (regcache
->tdesc
, "vr0");
786 for (i
= 0; i
< 32; i
++)
787 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
789 if (__BYTE_ORDER
== __BIG_ENDIAN
)
792 collect_register_by_name (regcache
, "vscr",
793 ®set
[32 * 16 + vscr_offset
]);
795 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
799 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
802 const char *regset
= (const char *) buf
;
805 base
= find_regno (regcache
->tdesc
, "vr0");
806 for (i
= 0; i
< 32; i
++)
807 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
809 if (__BYTE_ORDER
== __BIG_ENDIAN
)
812 supply_register_by_name (regcache
, "vscr",
813 ®set
[32 * 16 + vscr_offset
]);
814 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
817 struct gdb_evrregset_t
819 unsigned long evr
[32];
820 unsigned long long acc
;
821 unsigned long spefscr
;
825 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
828 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
830 ev0
= find_regno (regcache
->tdesc
, "ev0h");
831 for (i
= 0; i
< 32; i
++)
832 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
834 collect_register_by_name (regcache
, "acc", ®set
->acc
);
835 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
839 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
842 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
844 ev0
= find_regno (regcache
->tdesc
, "ev0h");
845 for (i
= 0; i
< 32; i
++)
846 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
848 supply_register_by_name (regcache
, "acc", ®set
->acc
);
849 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
852 /* Support for hardware single step. */
855 ppc_supports_hardware_single_step (void)
860 static struct regset_info ppc_regsets
[] = {
861 /* List the extra register sets before GENERAL_REGS. That way we will
862 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
863 general registers. Some kernels support these, but not the newer
864 PPC_PTRACE_GETREGS. */
865 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
866 NULL
, ppc_store_tm_ctarregset
},
867 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
868 NULL
, ppc_store_tm_cdscrregset
},
869 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
870 NULL
, ppc_store_tm_cpprregset
},
871 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
872 NULL
, ppc_store_tm_cvsxregset
},
873 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
874 NULL
, ppc_store_tm_cvrregset
},
875 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
876 NULL
, ppc_store_tm_cfprregset
},
877 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
878 NULL
, ppc_store_tm_cgprregset
},
879 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
880 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
881 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
882 NULL
, ppc_store_ebbregset
},
883 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
884 ppc_fill_pmuregset
, ppc_store_pmuregset
},
885 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
886 ppc_fill_tarregset
, ppc_store_tarregset
},
887 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
888 ppc_fill_pprregset
, ppc_store_pprregset
},
889 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
890 ppc_fill_dscrregset
, ppc_store_dscrregset
},
891 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
892 ppc_fill_vsxregset
, ppc_store_vsxregset
},
893 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
894 ppc_fill_vrregset
, ppc_store_vrregset
},
895 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
896 ppc_fill_evrregset
, ppc_store_evrregset
},
897 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
901 static struct usrregs_info ppc_usrregs_info
=
907 static struct regsets_info ppc_regsets_info
=
909 ppc_regsets
, /* regsets */
911 NULL
, /* disabled_regsets */
914 static struct regs_info regs_info
=
916 NULL
, /* regset_bitmap */
921 static const struct regs_info
*
928 ppc_arch_setup (void)
930 const struct target_desc
*tdesc
;
931 struct regset_info
*regset
;
932 struct ppc_linux_features features
= ppc_linux_no_features
;
934 int tid
= lwpid_of (current_thread
);
936 features
.wordsize
= ppc_linux_target_wordsize (tid
);
938 if (features
.wordsize
== 4)
939 tdesc
= tdesc_powerpc_32l
;
941 tdesc
= tdesc_powerpc_64l
;
943 current_process ()->tdesc
= tdesc
;
945 /* The value of current_process ()->tdesc needs to be set for this
947 ppc_get_auxv (AT_HWCAP
, &ppc_hwcap
);
948 ppc_get_auxv (AT_HWCAP2
, &ppc_hwcap2
);
950 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
952 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
955 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
956 features
.altivec
= true;
958 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
959 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
960 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
962 features
.ppr_dscr
= true;
963 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
964 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
965 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
966 && ppc_check_regset (tid
, NT_PPC_TAR
,
967 PPC_LINUX_SIZEOF_TARREGSET
)
968 && ppc_check_regset (tid
, NT_PPC_EBB
,
969 PPC_LINUX_SIZEOF_EBBREGSET
)
970 && ppc_check_regset (tid
, NT_PPC_PMU
,
971 PPC_LINUX_SIZEOF_PMUREGSET
))
973 features
.isa207
= true;
974 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
975 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
976 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
981 if (ppc_hwcap
& PPC_FEATURE_CELL
)
982 features
.cell
= true;
984 tdesc
= ppc_linux_match_description (features
);
986 /* On 32-bit machines, check for SPE registers.
987 Set the low target's regmap field as appropriately. */
988 #ifndef __powerpc64__
989 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
990 tdesc
= tdesc_powerpc_e500l
;
992 if (!ppc_regmap_adjusted
)
994 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
995 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
997 /* If the FPSCR is 64-bit wide, we need to fetch the whole
998 64-bit slot and not just its second word. The PT_FPSCR
999 supplied in a 32-bit GDB compilation doesn't reflect
1001 if (register_size (tdesc
, 70) == 8)
1002 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
1004 ppc_regmap_adjusted
= 1;
1008 current_process ()->tdesc
= tdesc
;
1010 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
1011 switch (regset
->get_request
)
1013 case PTRACE_GETVRREGS
:
1014 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
1016 case PTRACE_GETVSXREGS
:
1017 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
1019 case PTRACE_GETEVRREGS
:
1020 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
1021 regset
->size
= 32 * 4 + 8 + 4;
1025 case PTRACE_GETREGSET
:
1026 switch (regset
->nt_type
)
1029 regset
->size
= (features
.ppr_dscr
?
1030 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
1033 regset
->size
= (features
.ppr_dscr
?
1034 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
1037 regset
->size
= (features
.isa207
?
1038 PPC_LINUX_SIZEOF_TARREGSET
: 0);
1041 regset
->size
= (features
.isa207
?
1042 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
1045 regset
->size
= (features
.isa207
?
1046 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
1049 regset
->size
= (features
.htm
?
1050 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
1052 case NT_PPC_TM_CGPR
:
1053 if (features
.wordsize
== 4)
1054 regset
->size
= (features
.htm
?
1055 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
1057 regset
->size
= (features
.htm
?
1058 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
1060 case NT_PPC_TM_CFPR
:
1061 regset
->size
= (features
.htm
?
1062 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
1064 case NT_PPC_TM_CVMX
:
1065 regset
->size
= (features
.htm
?
1066 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
1068 case NT_PPC_TM_CVSX
:
1069 regset
->size
= (features
.htm
?
1070 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
1072 case NT_PPC_TM_CPPR
:
1073 regset
->size
= (features
.htm
?
1074 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
1076 case NT_PPC_TM_CDSCR
:
1077 regset
->size
= (features
.htm
?
1078 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
1080 case NT_PPC_TM_CTAR
:
1081 regset
->size
= (features
.htm
?
1082 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1093 /* Implementation of linux_target_ops method "supports_tracepoints". */
1096 ppc_supports_tracepoints (void)
1101 /* Get the thread area address. This is used to recognize which
1102 thread is which when tracing with the in-process agent library. We
1103 don't read anything from the address, and treat it as opaque; it's
1104 the address itself that we assume is unique per-thread. */
1107 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1109 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1110 struct thread_info
*thr
= get_lwp_thread (lwp
);
1111 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1114 #ifdef __powerpc64__
1115 if (register_size (regcache
->tdesc
, 0) == 8)
1116 collect_register_by_name (regcache
, "r13", &tp
);
1119 collect_register_by_name (regcache
, "r2", &tp
);
1126 #ifdef __powerpc64__
1128 /* Older glibc doesn't provide this. */
1130 #ifndef EF_PPC64_ABI
1131 #define EF_PPC64_ABI 3
1134 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1138 is_elfv2_inferior (void)
1140 /* To be used as fallback if we're unable to determine the right result -
1141 assume inferior uses the same ABI as gdbserver. */
1143 const int def_res
= 1;
1145 const int def_res
= 0;
1150 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
1153 /* Assume ELF header is at the beginning of the page where program headers
1154 are located. If it doesn't look like one, bail. */
1156 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1157 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1160 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1165 /* Generate a ds-form instruction in BUF and return the number of bytes written
1168 | OPCD | RST | RA | DS |XO| */
1170 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1172 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1176 gdb_assert ((opcd
& ~0x3f) == 0);
1177 gdb_assert ((rst
& ~0x1f) == 0);
1178 gdb_assert ((ra
& ~0x1f) == 0);
1179 gdb_assert ((xo
& ~0x3) == 0);
1181 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1182 *buf
= (opcd
<< 26) | insn
;
1186 /* Followings are frequently used ds-form instructions. */
1188 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1189 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1190 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1191 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1193 /* Generate a d-form instruction in BUF.
1196 | OPCD | RST | RA | D | */
1199 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1203 gdb_assert ((opcd
& ~0x3f) == 0);
1204 gdb_assert ((rst
& ~0x1f) == 0);
1205 gdb_assert ((ra
& ~0x1f) == 0);
1207 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1208 *buf
= (opcd
<< 26) | insn
;
1212 /* Followings are frequently used d-form instructions. */
1214 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1215 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1216 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1217 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1218 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1219 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1220 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1221 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1222 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1224 /* Generate a xfx-form instruction in BUF and return the number of bytes
1228 | OPCD | RST | RI | XO |/| */
1231 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1234 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1236 gdb_assert ((opcd
& ~0x3f) == 0);
1237 gdb_assert ((rst
& ~0x1f) == 0);
1238 gdb_assert ((xo
& ~0x3ff) == 0);
1240 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1241 *buf
= (opcd
<< 26) | insn
;
1245 /* Followings are frequently used xfx-form instructions. */
1247 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1248 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1249 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1250 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1251 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1253 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1256 /* Generate a x-form instruction in BUF and return the number of bytes written.
1259 | OPCD | RST | RA | RB | XO |RC| */
1262 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1266 gdb_assert ((opcd
& ~0x3f) == 0);
1267 gdb_assert ((rst
& ~0x1f) == 0);
1268 gdb_assert ((ra
& ~0x1f) == 0);
1269 gdb_assert ((rb
& ~0x1f) == 0);
1270 gdb_assert ((xo
& ~0x3ff) == 0);
1271 gdb_assert ((rc
& ~1) == 0);
1273 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1274 *buf
= (opcd
<< 26) | insn
;
1278 /* Followings are frequently used x-form instructions. */
1280 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1281 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1282 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1283 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1284 /* Assume bf = cr7. */
1285 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1288 /* Generate a md-form instruction in BUF and return the number of bytes written.
1290 0 6 11 16 21 27 30 31 32
1291 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1294 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1298 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1299 unsigned int sh0_4
= sh
& 0x1f;
1300 unsigned int sh5
= (sh
>> 5) & 1;
1302 gdb_assert ((opcd
& ~0x3f) == 0);
1303 gdb_assert ((rs
& ~0x1f) == 0);
1304 gdb_assert ((ra
& ~0x1f) == 0);
1305 gdb_assert ((sh
& ~0x3f) == 0);
1306 gdb_assert ((mb
& ~0x3f) == 0);
1307 gdb_assert ((xo
& ~0x7) == 0);
1308 gdb_assert ((rc
& ~0x1) == 0);
1310 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1311 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1312 *buf
= (opcd
<< 26) | insn
;
1316 /* The following are frequently used md-form instructions. */
1318 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1319 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1320 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1321 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1323 /* Generate a i-form instruction in BUF and return the number of bytes written.
1326 | OPCD | LI |AA|LK| */
1329 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1333 gdb_assert ((opcd
& ~0x3f) == 0);
1335 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1336 *buf
= (opcd
<< 26) | insn
;
1340 /* The following are frequently used i-form instructions. */
1342 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1343 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1345 /* Generate a b-form instruction in BUF and return the number of bytes written.
1348 | OPCD | BO | BI | BD |AA|LK| */
1351 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1356 gdb_assert ((opcd
& ~0x3f) == 0);
1357 gdb_assert ((bo
& ~0x1f) == 0);
1358 gdb_assert ((bi
& ~0x1f) == 0);
1360 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1361 *buf
= (opcd
<< 26) | insn
;
1365 /* The following are frequently used b-form instructions. */
1366 /* Assume bi = cr7. */
1367 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1369 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1370 respectively. They are primary used for save/restore GPRs in jump-pad,
1371 not used for bytecode compiling. */
1373 #ifdef __powerpc64__
1374 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1375 GEN_LD (buf, rt, ra, si) : \
1376 GEN_LWZ (buf, rt, ra, si))
1377 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1378 GEN_STD (buf, rt, ra, si) : \
1379 GEN_STW (buf, rt, ra, si))
1381 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1382 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1385 /* Generate a sequence of instructions to load IMM in the register REG.
1386 Write the instructions in BUF and return the number of bytes written. */
1389 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1393 if ((imm
+ 32768) < 65536)
1395 /* li reg, imm[15:0] */
1396 p
+= GEN_LI (p
, reg
, imm
);
1398 else if ((imm
>> 32) == 0)
1400 /* lis reg, imm[31:16]
1401 ori reg, reg, imm[15:0]
1402 rldicl reg, reg, 0, 32 */
1403 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1404 if ((imm
& 0xffff) != 0)
1405 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1406 /* Clear upper 32-bit if sign-bit is set. */
1407 if (imm
& (1u << 31) && is_64
)
1408 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1413 /* lis reg, <imm[63:48]>
1414 ori reg, reg, <imm[48:32]>
1415 rldicr reg, reg, 32, 31
1416 oris reg, reg, <imm[31:16]>
1417 ori reg, reg, <imm[15:0]> */
1418 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1419 if (((imm
>> 32) & 0xffff) != 0)
1420 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1421 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1422 if (((imm
>> 16) & 0xffff) != 0)
1423 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1424 if ((imm
& 0xffff) != 0)
1425 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1431 /* Generate a sequence for atomically exchange at location LOCK.
1432 This code sequence clobbers r6, r7, r8. LOCK is the location for
1433 the atomic-xchg, OLD_VALUE is expected old value stored in the
1434 location, and R_NEW is a register for the new value. */
1437 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1440 const int r_lock
= 6;
1441 const int r_old
= 7;
1442 const int r_tmp
= 8;
1446 1: lwarx TMP, 0, LOCK
1452 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1453 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1455 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1456 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1457 p
+= GEN_BNE (p
, -8);
1458 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1459 p
+= GEN_BNE (p
, -16);
1464 /* Generate a sequence of instructions for calling a function
1465 at address of FN. Return the number of bytes are written in BUF. */
1468 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1472 /* Must be called by r12 for caller to calculate TOC address. */
1473 p
+= gen_limm (p
, 12, fn
, is_64
);
1476 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1477 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1478 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1480 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1481 *p
++ = 0x4e800421; /* bctrl */
1486 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1487 of instruction. This function is used to adjust pc-relative instructions
1491 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1496 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1497 op6
= PPC_OP6 (insn
);
1499 if (op6
== 18 && (insn
& 2) == 0)
1501 /* branch && AA = 0 */
1502 rel
= PPC_LI (insn
);
1503 newrel
= (oldloc
- *to
) + rel
;
1505 /* Out of range. Cannot relocate instruction. */
1506 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1509 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1511 else if (op6
== 16 && (insn
& 2) == 0)
1513 /* conditional branch && AA = 0 */
1515 /* If the new relocation is too big for even a 26-bit unconditional
1516 branch, there is nothing we can do. Just abort.
1518 Otherwise, if it can be fit in 16-bit conditional branch, just
1519 copy the instruction and relocate the address.
1521 If the it's big for conditional-branch (16-bit), try to invert the
1522 condition and jump with 26-bit branch. For example,
1533 After this transform, we are actually jump from *TO+4 instead of *TO,
1534 so check the relocation again because it will be 1-insn farther then
1535 before if *TO is after OLDLOC.
1538 For BDNZT (or so) is transformed from
1550 See also "BO field encodings". */
1552 rel
= PPC_BD (insn
);
1553 newrel
= (oldloc
- *to
) + rel
;
1555 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1556 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1557 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1561 /* Out of range. Cannot relocate instruction. */
1562 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1565 if ((PPC_BO (insn
) & 0x14) == 0x4)
1567 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1570 /* Jump over the unconditional branch. */
1571 insn
= (insn
& ~0xfffc) | 0x8;
1572 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1575 /* Build a unconditional branch and copy LK bit. */
1576 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1577 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1582 else if ((PPC_BO (insn
) & 0x14) == 0)
1584 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1585 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1589 /* Out of range. Cannot relocate instruction. */
1590 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1593 /* Copy BI field. */
1594 bf_insn
|= (insn
& 0x1f0000);
1596 /* Invert condition. */
1597 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1598 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1600 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1602 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1605 /* Build a unconditional branch and copy LK bit. */
1606 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1607 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1612 else /* (BO & 0x14) == 0x14, branch always. */
1614 /* Out of range. Cannot relocate instruction. */
1615 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1618 /* Build a unconditional branch and copy LK bit. */
1619 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1620 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1627 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1631 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1632 See target.h for details. */
1635 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1636 CORE_ADDR collector
,
1639 CORE_ADDR
*jump_entry
,
1640 CORE_ADDR
*trampoline
,
1641 ULONGEST
*trampoline_size
,
1642 unsigned char *jjump_pad_insn
,
1643 ULONGEST
*jjump_pad_insn_size
,
1644 CORE_ADDR
*adjusted_insn_addr
,
1645 CORE_ADDR
*adjusted_insn_addr_end
,
1651 CORE_ADDR buildaddr
= *jump_entry
;
1652 const CORE_ADDR entryaddr
= *jump_entry
;
1653 int rsz
, min_frame
, frame_size
, tp_reg
;
1654 #ifdef __powerpc64__
1655 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1656 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1657 int is_opd
= is_64
&& !is_elfv2_inferior ();
1659 int is_64
= 0, is_opd
= 0;
1662 #ifdef __powerpc64__
1665 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1668 frame_size
= (40 * rsz
) + min_frame
;
1676 frame_size
= (40 * rsz
) + min_frame
;
1678 #ifdef __powerpc64__
1682 /* Stack frame layout for this jump pad,
1684 High thread_area (r13/r2) |
1685 tpoint - collecting_t obj
1695 R0 - collected registers
1701 The code flow of this jump pad,
1706 4. Call gdb_collector
1707 5. Restore GPR and SPR
1709 7. Build a jump for back to the program
1710 8. Copy/relocate original instruction
1711 9. Build a jump for replacing orignal instruction. */
1713 /* Adjust stack pointer. */
1715 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1717 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1719 /* Store GPRs. Save R1 later, because it had just been modified, but
1720 we want the original value. */
1721 for (j
= 2; j
< 32; j
++)
1722 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1723 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1724 /* Set r0 to the original value of r1 before adjusting stack frame,
1725 and then save it. */
1726 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1727 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1729 /* Save CR, XER, LR, and CTR. */
1730 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1731 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1732 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1733 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1734 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1735 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1736 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1737 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1739 /* Save PC<tpaddr> */
1740 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1741 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1744 /* Setup arguments to collector. */
1745 /* Set r4 to collected registers. */
1746 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1747 /* Set r3 to TPOINT. */
1748 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1750 /* Prepare collecting_t object for lock. */
1751 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1752 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1753 /* Set R5 to collecting object. */
1754 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1756 p
+= GEN_LWSYNC (p
);
1757 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1758 p
+= GEN_LWSYNC (p
);
1760 /* Call to collector. */
1761 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1763 /* Simply write 0 to release the lock. */
1764 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1765 p
+= gen_limm (p
, 4, 0, is_64
);
1766 p
+= GEN_LWSYNC (p
);
1767 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1769 /* Restore stack and registers. */
1770 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1771 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1772 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1773 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1774 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1775 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1776 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1777 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1780 for (j
= 2; j
< 32; j
++)
1781 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1782 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1784 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1786 /* Flush instructions to inferior memory. */
1787 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1789 /* Now, insert the original instruction to execute in the jump pad. */
1790 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1791 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1792 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1794 /* Verify the relocation size. If should be 4 for normal copy,
1795 8 or 12 for some conditional branch. */
1796 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1797 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1799 sprintf (err
, "E.Unexpected instruction length = %d"
1800 "when relocate instruction.",
1801 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1805 buildaddr
= *adjusted_insn_addr_end
;
1807 /* Finally, write a jump back to the program. */
1808 offset
= (tpaddr
+ 4) - buildaddr
;
1809 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1811 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1812 "(offset 0x%x > 26-bit).", offset
);
1816 p
+= GEN_B (p
, offset
);
1817 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1818 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1820 /* The jump pad is now built. Wire in a jump to our jump pad. This
1821 is always done last (by our caller actually), so that we can
1822 install fast tracepoints with threads running. This relies on
1823 the agent's atomic write support. */
1824 offset
= entryaddr
- tpaddr
;
1825 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1827 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1828 "(offset 0x%x > 26-bit).", offset
);
1832 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1833 *jjump_pad_insn_size
= 4;
1838 /* Returns the minimum instruction length for installing a tracepoint. */
1841 ppc_get_min_fast_tracepoint_insn_len (void)
1846 /* Emits a given buffer into the target at current_insn_ptr. Length
1847 is in units of 32-bit words. */
1850 emit_insns (uint32_t *buf
, int n
)
1852 n
= n
* sizeof (uint32_t);
1853 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1854 current_insn_ptr
+= n
;
1857 #define __EMIT_ASM(NAME, INSNS) \
1860 extern uint32_t start_bcax_ ## NAME []; \
1861 extern uint32_t end_bcax_ ## NAME []; \
1862 emit_insns (start_bcax_ ## NAME, \
1863 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1864 __asm__ (".section .text.__ppcbcax\n\t" \
1865 "start_bcax_" #NAME ":\n\t" \
1867 "end_bcax_" #NAME ":\n\t" \
1871 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1872 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1876 Bytecode execution stack frame - 32-bit
1878 | LR save area (SP + 4)
1879 SP' -> +- Back chain (SP + 0)
1880 | Save r31 for access saved arguments
1881 | Save r30 for bytecode stack pointer
1882 | Save r4 for incoming argument *value
1883 | Save r3 for incoming argument regs
1884 r30 -> +- Bytecode execution stack
1886 | 64-byte (8 doublewords) at initial.
1887 | Expand stack as needed.
1890 | Some padding for minimum stack frame and 16-byte alignment.
1892 SP +- Back-chain (SP')
1898 r30 is the stack-pointer for bytecode machine.
1899 It should point to next-empty, so we can use LDU for pop.
1900 r3 is used for cache of the high part of TOP value.
1901 It was the first argument, pointer to regs.
1902 r4 is used for cache of the low part of TOP value.
1903 It was the second argument, pointer to the result.
1904 We should set *result = TOP after leaving this function.
1907 * To restore stack at epilogue
1909 * To check stack is big enough for bytecode execution.
1911 * To return execution result.
1916 /* Regardless of endian, register 3 is always high part, 4 is low part.
1917 These defines are used when the register pair is stored/loaded.
1918 Likewise, to simplify code, have a similiar define for 5:6. */
1920 #if __BYTE_ORDER == __LITTLE_ENDIAN
1921 #define TOP_FIRST "4"
1922 #define TOP_SECOND "3"
1923 #define TMP_FIRST "6"
1924 #define TMP_SECOND "5"
1926 #define TOP_FIRST "3"
1927 #define TOP_SECOND "4"
1928 #define TMP_FIRST "5"
1929 #define TMP_SECOND "6"
1932 /* Emit prologue in inferior memory. See above comments. */
1935 ppc_emit_prologue (void)
1937 EMIT_ASM (/* Save return address. */
1940 /* Adjust SP. 96 is the initial frame size. */
1942 /* Save r30 and incoming arguments. */
1943 "stw 31, 96-4(1) \n"
1944 "stw 30, 96-8(1) \n"
1945 "stw 4, 96-12(1) \n"
1946 "stw 3, 96-16(1) \n"
1947 /* Point r31 to original r1 for access arguments. */
1949 /* Set r30 to pointing stack-top. */
1951 /* Initial r3/TOP to 0. */
1956 /* Emit epilogue in inferior memory. See above comments. */
1959 ppc_emit_epilogue (void)
1961 EMIT_ASM (/* *result = TOP */
1963 "stw " TOP_FIRST
", 0(5) \n"
1964 "stw " TOP_SECOND
", 4(5) \n"
1965 /* Restore registers. */
1972 /* Return 0 for no-error. */
1978 /* TOP = stack[--sp] + TOP */
1983 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1984 "lwz " TMP_SECOND
", 4(30)\n"
1989 /* TOP = stack[--sp] - TOP */
1994 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1995 "lwz " TMP_SECOND
", 4(30) \n"
1997 "subfe 3, 3, 5 \n");
2000 /* TOP = stack[--sp] * TOP */
2005 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2006 "lwz " TMP_SECOND
", 4(30) \n"
2015 /* TOP = stack[--sp] << TOP */
2020 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2021 "lwz " TMP_SECOND
", 4(30) \n"
2022 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2023 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2024 "slw 5, 5, 4\n" /* Shift high part left */
2025 "slw 4, 6, 4\n" /* Shift low part left */
2026 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
2027 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
2029 "or 3, 7, 3\n"); /* Assemble high part */
2032 /* Top = stack[--sp] >> TOP
2033 (Arithmetic shift right) */
2036 ppc_emit_rsh_signed (void)
2038 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2039 "lwz " TMP_SECOND
", 4(30) \n"
2040 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2041 "sraw 3, 5, 4\n" /* Shift high part right */
2043 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
2044 "sraw 4, 5, 7\n" /* Shift high to low */
2047 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
2048 "srw 4, 6, 4\n" /* Shift low part right */
2049 "slw 5, 5, 7\n" /* Shift high to low */
2050 "or 4, 4, 5\n" /* Assemble low part */
2054 /* Top = stack[--sp] >> TOP
2055 (Logical shift right) */
2058 ppc_emit_rsh_unsigned (void)
2060 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2061 "lwz " TMP_SECOND
", 4(30) \n"
2062 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2063 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2064 "srw 6, 6, 4\n" /* Shift low part right */
2065 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2066 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2068 "srw 3, 5, 4\n" /* Shift high part right */
2069 "or 4, 6, 7\n"); /* Assemble low part */
2072 /* Emit code for signed-extension specified by ARG. */
2075 ppc_emit_ext (int arg
)
2080 EMIT_ASM ("extsb 4, 4\n"
2084 EMIT_ASM ("extsh 4, 4\n"
2088 EMIT_ASM ("srawi 3, 4, 31");
2095 /* Emit code for zero-extension specified by ARG. */
2098 ppc_emit_zero_ext (int arg
)
2103 EMIT_ASM ("clrlwi 4,4,24\n"
2107 EMIT_ASM ("clrlwi 4,4,16\n"
2111 EMIT_ASM ("li 3, 0");
2119 i.e., TOP = (TOP == 0) ? 1 : 0; */
2122 ppc_emit_log_not (void)
2124 EMIT_ASM ("or 4, 3, 4 \n"
2130 /* TOP = stack[--sp] & TOP */
2133 ppc_emit_bit_and (void)
2135 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2136 "lwz " TMP_SECOND
", 4(30) \n"
2141 /* TOP = stack[--sp] | TOP */
2144 ppc_emit_bit_or (void)
2146 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2147 "lwz " TMP_SECOND
", 4(30) \n"
2152 /* TOP = stack[--sp] ^ TOP */
2155 ppc_emit_bit_xor (void)
2157 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2158 "lwz " TMP_SECOND
", 4(30) \n"
2164 i.e., TOP = ~(TOP | TOP) */
2167 ppc_emit_bit_not (void)
2169 EMIT_ASM ("nor 3, 3, 3 \n"
2173 /* TOP = stack[--sp] == TOP */
2176 ppc_emit_equal (void)
2178 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2179 "lwz " TMP_SECOND
", 4(30) \n"
2188 /* TOP = stack[--sp] < TOP
2189 (Signed comparison) */
2192 ppc_emit_less_signed (void)
2194 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2195 "lwz " TMP_SECOND
", 4(30) \n"
2198 /* CR6 bit 0 = low less and high equal */
2199 "crand 6*4+0, 6*4+0, 7*4+2\n"
2200 /* CR7 bit 0 = (low less and high equal) or high less */
2201 "cror 7*4+0, 7*4+0, 6*4+0\n"
2203 "rlwinm 4, 4, 29, 31, 31 \n"
2207 /* TOP = stack[--sp] < TOP
2208 (Unsigned comparison) */
2211 ppc_emit_less_unsigned (void)
2213 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2214 "lwz " TMP_SECOND
", 4(30) \n"
2217 /* CR6 bit 0 = low less and high equal */
2218 "crand 6*4+0, 6*4+0, 7*4+2\n"
2219 /* CR7 bit 0 = (low less and high equal) or high less */
2220 "cror 7*4+0, 7*4+0, 6*4+0\n"
2222 "rlwinm 4, 4, 29, 31, 31 \n"
2226 /* Access the memory address in TOP in size of SIZE.
2227 Zero-extend the read value. */
2230 ppc_emit_ref (int size
)
2235 EMIT_ASM ("lbz 4, 0(4)\n"
2239 EMIT_ASM ("lhz 4, 0(4)\n"
2243 EMIT_ASM ("lwz 4, 0(4)\n"
2247 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2248 EMIT_ASM ("lwz 3, 4(4)\n"
2251 EMIT_ASM ("lwz 3, 0(4)\n"
2260 ppc_emit_const (LONGEST num
)
2265 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2266 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2268 emit_insns (buf
, p
- buf
);
2269 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2272 /* Set TOP to the value of register REG by calling get_raw_reg function
2273 with two argument, collected buffer and register number. */
2276 ppc_emit_reg (int reg
)
2281 /* fctx->regs is passed in r3 and then saved in -16(31). */
2282 p
+= GEN_LWZ (p
, 3, 31, -16);
2283 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2284 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2286 emit_insns (buf
, p
- buf
);
2287 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2289 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2291 EMIT_ASM ("mr 5, 4\n"
2297 /* TOP = stack[--sp] */
2302 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2303 "lwz " TOP_SECOND
", 4(30) \n");
2306 /* stack[sp++] = TOP
2308 Because we may use up bytecode stack, expand 8 doublewords more
2312 ppc_emit_stack_flush (void)
2314 /* Make sure bytecode stack is big enough before push.
2315 Otherwise, expand 64-byte more. */
2317 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2318 " stw " TOP_SECOND
", 4(30)\n"
2319 " addi 5, 30, -(8 + 8) \n"
2322 " stwu 31, -64(1) \n"
2323 "1:addi 30, 30, -8 \n");
2326 /* Swap TOP and stack[sp-1] */
2329 ppc_emit_swap (void)
2331 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2332 "lwz " TMP_SECOND
", 12(30) \n"
2333 "stw " TOP_FIRST
", 8(30) \n"
2334 "stw " TOP_SECOND
", 12(30) \n"
2339 /* Discard N elements in the stack. Also used for ppc64. */
2342 ppc_emit_stack_adjust (int n
)
2354 p
+= GEN_ADDI (p
, 30, 30, n
);
2356 emit_insns (buf
, p
- buf
);
2357 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2360 /* Call function FN. */
2363 ppc_emit_call (CORE_ADDR fn
)
2368 p
+= gen_call (p
, fn
, 0, 0);
2370 emit_insns (buf
, p
- buf
);
2371 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2374 /* FN's prototype is `LONGEST(*fn)(int)'.
2379 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2384 /* Setup argument. arg1 is a 16-bit value. */
2385 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2386 p
+= gen_call (p
, fn
, 0, 0);
2388 emit_insns (buf
, p
- buf
);
2389 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2391 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2393 EMIT_ASM ("mr 5, 4\n"
2399 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2402 TOP should be preserved/restored before/after the call. */
2405 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2410 /* Save TOP. 0(30) is next-empty. */
2411 p
+= GEN_STW (p
, 3, 30, 0);
2412 p
+= GEN_STW (p
, 4, 30, 4);
2414 /* Setup argument. arg1 is a 16-bit value. */
2415 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2417 p
+= GEN_MR (p
, 5, 4);
2418 p
+= GEN_MR (p
, 6, 3);
2422 p
+= GEN_MR (p
, 5, 3);
2423 p
+= GEN_MR (p
, 6, 4);
2425 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2426 p
+= gen_call (p
, fn
, 0, 0);
2429 p
+= GEN_LWZ (p
, 3, 30, 0);
2430 p
+= GEN_LWZ (p
, 4, 30, 4);
2432 emit_insns (buf
, p
- buf
);
2433 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2436 /* Note in the following goto ops:
2438 When emitting goto, the target address is later relocated by
2439 write_goto_address. OFFSET_P is the offset of the branch instruction
2440 in the code sequence, and SIZE_P is how to relocate the instruction,
2441 recognized by ppc_write_goto_address. In current implementation,
2442 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2445 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2448 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2450 EMIT_ASM ("or. 3, 3, 4 \n"
2451 "lwzu " TOP_FIRST
", 8(30) \n"
2452 "lwz " TOP_SECOND
", 4(30) \n"
2461 /* Unconditional goto. Also used for ppc64. */
2464 ppc_emit_goto (int *offset_p
, int *size_p
)
2466 EMIT_ASM ("1:b 1b");
2474 /* Goto if stack[--sp] == TOP */
2477 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2479 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2480 "lwz " TMP_SECOND
", 4(30) \n"
2484 "lwzu " TOP_FIRST
", 8(30) \n"
2485 "lwz " TOP_SECOND
", 4(30) \n"
2494 /* Goto if stack[--sp] != TOP */
2497 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2499 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2500 "lwz " TMP_SECOND
", 4(30) \n"
2504 "lwzu " TOP_FIRST
", 8(30) \n"
2505 "lwz " TOP_SECOND
", 4(30) \n"
2514 /* Goto if stack[--sp] < TOP */
2517 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2519 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2520 "lwz " TMP_SECOND
", 4(30) \n"
2523 /* CR6 bit 0 = low less and high equal */
2524 "crand 6*4+0, 6*4+0, 7*4+2\n"
2525 /* CR7 bit 0 = (low less and high equal) or high less */
2526 "cror 7*4+0, 7*4+0, 6*4+0\n"
2527 "lwzu " TOP_FIRST
", 8(30) \n"
2528 "lwz " TOP_SECOND
", 4(30)\n"
2537 /* Goto if stack[--sp] <= TOP */
2540 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2542 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2543 "lwz " TMP_SECOND
", 4(30) \n"
2546 /* CR6 bit 0 = low less/equal and high equal */
2547 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2548 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2549 "cror 7*4+0, 7*4+0, 6*4+0\n"
2550 "lwzu " TOP_FIRST
", 8(30) \n"
2551 "lwz " TOP_SECOND
", 4(30)\n"
2560 /* Goto if stack[--sp] > TOP */
2563 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2565 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2566 "lwz " TMP_SECOND
", 4(30) \n"
2569 /* CR6 bit 0 = low greater and high equal */
2570 "crand 6*4+0, 6*4+1, 7*4+2\n"
2571 /* CR7 bit 0 = (low greater and high equal) or high greater */
2572 "cror 7*4+0, 7*4+1, 6*4+0\n"
2573 "lwzu " TOP_FIRST
", 8(30) \n"
2574 "lwz " TOP_SECOND
", 4(30)\n"
2583 /* Goto if stack[--sp] >= TOP */
2586 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2588 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2589 "lwz " TMP_SECOND
", 4(30) \n"
2592 /* CR6 bit 0 = low ge and high equal */
2593 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2594 /* CR7 bit 0 = (low ge and high equal) or high greater */
2595 "cror 7*4+0, 7*4+1, 6*4+0\n"
2596 "lwzu " TOP_FIRST
", 8(30)\n"
2597 "lwz " TOP_SECOND
", 4(30)\n"
2606 /* Relocate previous emitted branch instruction. FROM is the address
2607 of the branch instruction, TO is the goto target address, and SIZE
2608 if the value we set by *SIZE_P before. Currently, it is either
2609 24 or 14 of branch and conditional-branch instruction.
2610 Also used for ppc64. */
2613 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2615 long rel
= to
- from
;
2619 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2620 opcd
= (insn
>> 26) & 0x3f;
2626 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2628 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2632 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2634 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2641 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2644 /* Table of emit ops for 32-bit. */
2646 static struct emit_ops ppc_emit_ops_impl
=
2654 ppc_emit_rsh_signed
,
2655 ppc_emit_rsh_unsigned
,
2663 ppc_emit_less_signed
,
2664 ppc_emit_less_unsigned
,
2668 ppc_write_goto_address
,
2673 ppc_emit_stack_flush
,
2676 ppc_emit_stack_adjust
,
2677 ppc_emit_int_call_1
,
2678 ppc_emit_void_call_2
,
2687 #ifdef __powerpc64__
2691 Bytecode execution stack frame - 64-bit
2693 | LR save area (SP + 16)
2694 | CR save area (SP + 8)
2695 SP' -> +- Back chain (SP + 0)
2696 | Save r31 for access saved arguments
2697 | Save r30 for bytecode stack pointer
2698 | Save r4 for incoming argument *value
2699 | Save r3 for incoming argument regs
2700 r30 -> +- Bytecode execution stack
2702 | 64-byte (8 doublewords) at initial.
2703 | Expand stack as needed.
2706 | Some padding for minimum stack frame.
2708 SP +- Back-chain (SP')
2711 = 112 + (4 * 8) + 64
2714 r30 is the stack-pointer for bytecode machine.
2715 It should point to next-empty, so we can use LDU for pop.
2716 r3 is used for cache of TOP value.
2717 It was the first argument, pointer to regs.
2718 r4 is the second argument, pointer to the result.
2719 We should set *result = TOP after leaving this function.
2722 * To restore stack at epilogue
2724 * To check stack is big enough for bytecode execution.
2725 => r30 - 8 > SP + 112
2726 * To return execution result.
2731 /* Emit prologue in inferior memory. See above comments. */
2734 ppc64v1_emit_prologue (void)
2736 /* On ELFv1, function pointers really point to function descriptor,
2737 so emit one here. We don't care about contents of words 1 and 2,
2738 so let them just overlap out code. */
2739 uint64_t opd
= current_insn_ptr
+ 8;
2742 /* Mind the strict aliasing rules. */
2743 memcpy (buf
, &opd
, sizeof buf
);
2745 EMIT_ASM (/* Save return address. */
2748 /* Save r30 and incoming arguments. */
2753 /* Point r31 to current r1 for access arguments. */
2755 /* Adjust SP. 208 is the initial frame size. */
2756 "stdu 1, -208(1) \n"
2757 /* Set r30 to pointing stack-top. */
2758 "addi 30, 1, 168 \n"
2759 /* Initial r3/TOP to 0. */
2763 /* Emit prologue in inferior memory. See above comments. */
2766 ppc64v2_emit_prologue (void)
2768 EMIT_ASM (/* Save return address. */
2771 /* Save r30 and incoming arguments. */
2776 /* Point r31 to current r1 for access arguments. */
2778 /* Adjust SP. 208 is the initial frame size. */
2779 "stdu 1, -208(1) \n"
2780 /* Set r30 to pointing stack-top. */
2781 "addi 30, 1, 168 \n"
2782 /* Initial r3/TOP to 0. */
2786 /* Emit epilogue in inferior memory. See above comments. */
2789 ppc64_emit_epilogue (void)
2791 EMIT_ASM (/* Restore SP. */
2796 /* Restore registers. */
2801 /* Return 0 for no-error. */
2807 /* TOP = stack[--sp] + TOP */
2810 ppc64_emit_add (void)
2812 EMIT_ASM ("ldu 4, 8(30) \n"
2816 /* TOP = stack[--sp] - TOP */
2819 ppc64_emit_sub (void)
2821 EMIT_ASM ("ldu 4, 8(30) \n"
2825 /* TOP = stack[--sp] * TOP */
2828 ppc64_emit_mul (void)
2830 EMIT_ASM ("ldu 4, 8(30) \n"
2831 "mulld 3, 4, 3 \n");
2834 /* TOP = stack[--sp] << TOP */
2837 ppc64_emit_lsh (void)
2839 EMIT_ASM ("ldu 4, 8(30) \n"
2843 /* Top = stack[--sp] >> TOP
2844 (Arithmetic shift right) */
2847 ppc64_emit_rsh_signed (void)
2849 EMIT_ASM ("ldu 4, 8(30) \n"
2853 /* Top = stack[--sp] >> TOP
2854 (Logical shift right) */
2857 ppc64_emit_rsh_unsigned (void)
2859 EMIT_ASM ("ldu 4, 8(30) \n"
2863 /* Emit code for signed-extension specified by ARG. */
2866 ppc64_emit_ext (int arg
)
2871 EMIT_ASM ("extsb 3, 3");
2874 EMIT_ASM ("extsh 3, 3");
2877 EMIT_ASM ("extsw 3, 3");
2884 /* Emit code for zero-extension specified by ARG. */
2887 ppc64_emit_zero_ext (int arg
)
2892 EMIT_ASM ("rldicl 3,3,0,56");
2895 EMIT_ASM ("rldicl 3,3,0,48");
2898 EMIT_ASM ("rldicl 3,3,0,32");
2906 i.e., TOP = (TOP == 0) ? 1 : 0; */
2909 ppc64_emit_log_not (void)
2911 EMIT_ASM ("cntlzd 3, 3 \n"
2915 /* TOP = stack[--sp] & TOP */
2918 ppc64_emit_bit_and (void)
2920 EMIT_ASM ("ldu 4, 8(30) \n"
2924 /* TOP = stack[--sp] | TOP */
2927 ppc64_emit_bit_or (void)
2929 EMIT_ASM ("ldu 4, 8(30) \n"
2933 /* TOP = stack[--sp] ^ TOP */
2936 ppc64_emit_bit_xor (void)
2938 EMIT_ASM ("ldu 4, 8(30) \n"
2943 i.e., TOP = ~(TOP | TOP) */
2946 ppc64_emit_bit_not (void)
2948 EMIT_ASM ("nor 3, 3, 3 \n");
2951 /* TOP = stack[--sp] == TOP */
2954 ppc64_emit_equal (void)
2956 EMIT_ASM ("ldu 4, 8(30) \n"
2962 /* TOP = stack[--sp] < TOP
2963 (Signed comparison) */
2966 ppc64_emit_less_signed (void)
2968 EMIT_ASM ("ldu 4, 8(30) \n"
2971 "rlwinm 3, 3, 29, 31, 31 \n");
2974 /* TOP = stack[--sp] < TOP
2975 (Unsigned comparison) */
2978 ppc64_emit_less_unsigned (void)
2980 EMIT_ASM ("ldu 4, 8(30) \n"
2983 "rlwinm 3, 3, 29, 31, 31 \n");
2986 /* Access the memory address in TOP in size of SIZE.
2987 Zero-extend the read value. */
2990 ppc64_emit_ref (int size
)
2995 EMIT_ASM ("lbz 3, 0(3)");
2998 EMIT_ASM ("lhz 3, 0(3)");
3001 EMIT_ASM ("lwz 3, 0(3)");
3004 EMIT_ASM ("ld 3, 0(3)");
3012 ppc64_emit_const (LONGEST num
)
3017 p
+= gen_limm (p
, 3, num
, 1);
3019 emit_insns (buf
, p
- buf
);
3020 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3023 /* Set TOP to the value of register REG by calling get_raw_reg function
3024 with two argument, collected buffer and register number. */
3027 ppc64v1_emit_reg (int reg
)
3032 /* fctx->regs is passed in r3 and then saved in 176(1). */
3033 p
+= GEN_LD (p
, 3, 31, -32);
3034 p
+= GEN_LI (p
, 4, reg
);
3035 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3036 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
3037 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3039 emit_insns (buf
, p
- buf
);
3040 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3043 /* Likewise, for ELFv2. */
3046 ppc64v2_emit_reg (int reg
)
3051 /* fctx->regs is passed in r3 and then saved in 176(1). */
3052 p
+= GEN_LD (p
, 3, 31, -32);
3053 p
+= GEN_LI (p
, 4, reg
);
3054 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3055 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
3056 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3058 emit_insns (buf
, p
- buf
);
3059 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3062 /* TOP = stack[--sp] */
3065 ppc64_emit_pop (void)
3067 EMIT_ASM ("ldu 3, 8(30)");
3070 /* stack[sp++] = TOP
3072 Because we may use up bytecode stack, expand 8 doublewords more
3076 ppc64_emit_stack_flush (void)
3078 /* Make sure bytecode stack is big enough before push.
3079 Otherwise, expand 64-byte more. */
3081 EMIT_ASM (" std 3, 0(30) \n"
3082 " addi 4, 30, -(112 + 8) \n"
3085 " stdu 31, -64(1) \n"
3086 "1:addi 30, 30, -8 \n");
3089 /* Swap TOP and stack[sp-1] */
3092 ppc64_emit_swap (void)
3094 EMIT_ASM ("ld 4, 8(30) \n"
3099 /* Call function FN - ELFv1. */
3102 ppc64v1_emit_call (CORE_ADDR fn
)
3107 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3108 p
+= gen_call (p
, fn
, 1, 1);
3109 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3111 emit_insns (buf
, p
- buf
);
3112 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3115 /* Call function FN - ELFv2. */
3118 ppc64v2_emit_call (CORE_ADDR fn
)
3123 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3124 p
+= gen_call (p
, fn
, 1, 0);
3125 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3127 emit_insns (buf
, p
- buf
);
3128 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3131 /* FN's prototype is `LONGEST(*fn)(int)'.
3136 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3141 /* Setup argument. arg1 is a 16-bit value. */
3142 p
+= gen_limm (p
, 3, arg1
, 1);
3143 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3144 p
+= gen_call (p
, fn
, 1, 1);
3145 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3147 emit_insns (buf
, p
- buf
);
3148 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3151 /* Likewise for ELFv2. */
3154 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3159 /* Setup argument. arg1 is a 16-bit value. */
3160 p
+= gen_limm (p
, 3, arg1
, 1);
3161 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3162 p
+= gen_call (p
, fn
, 1, 0);
3163 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3165 emit_insns (buf
, p
- buf
);
3166 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3169 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3172 TOP should be preserved/restored before/after the call. */
3175 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3180 /* Save TOP. 0(30) is next-empty. */
3181 p
+= GEN_STD (p
, 3, 30, 0);
3183 /* Setup argument. arg1 is a 16-bit value. */
3184 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3185 p
+= gen_limm (p
, 3, arg1
, 1);
3186 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3187 p
+= gen_call (p
, fn
, 1, 1);
3188 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3191 p
+= GEN_LD (p
, 3, 30, 0);
3193 emit_insns (buf
, p
- buf
);
3194 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3197 /* Likewise for ELFv2. */
3200 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3205 /* Save TOP. 0(30) is next-empty. */
3206 p
+= GEN_STD (p
, 3, 30, 0);
3208 /* Setup argument. arg1 is a 16-bit value. */
3209 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3210 p
+= gen_limm (p
, 3, arg1
, 1);
3211 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3212 p
+= gen_call (p
, fn
, 1, 0);
3213 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3216 p
+= GEN_LD (p
, 3, 30, 0);
3218 emit_insns (buf
, p
- buf
);
3219 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3222 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3225 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3227 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3237 /* Goto if stack[--sp] == TOP */
3240 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3242 EMIT_ASM ("ldu 4, 8(30) \n"
3253 /* Goto if stack[--sp] != TOP */
3256 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3258 EMIT_ASM ("ldu 4, 8(30) \n"
3269 /* Goto if stack[--sp] < TOP */
3272 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3274 EMIT_ASM ("ldu 4, 8(30) \n"
3285 /* Goto if stack[--sp] <= TOP */
3288 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3290 EMIT_ASM ("ldu 4, 8(30) \n"
3301 /* Goto if stack[--sp] > TOP */
3304 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3306 EMIT_ASM ("ldu 4, 8(30) \n"
3317 /* Goto if stack[--sp] >= TOP */
3320 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3322 EMIT_ASM ("ldu 4, 8(30) \n"
3333 /* Table of emit ops for 64-bit ELFv1. */
3335 static struct emit_ops ppc64v1_emit_ops_impl
=
3337 ppc64v1_emit_prologue
,
3338 ppc64_emit_epilogue
,
3343 ppc64_emit_rsh_signed
,
3344 ppc64_emit_rsh_unsigned
,
3352 ppc64_emit_less_signed
,
3353 ppc64_emit_less_unsigned
,
3357 ppc_write_goto_address
,
3362 ppc64_emit_stack_flush
,
3363 ppc64_emit_zero_ext
,
3365 ppc_emit_stack_adjust
,
3366 ppc64v1_emit_int_call_1
,
3367 ppc64v1_emit_void_call_2
,
3376 /* Table of emit ops for 64-bit ELFv2. */
3378 static struct emit_ops ppc64v2_emit_ops_impl
=
3380 ppc64v2_emit_prologue
,
3381 ppc64_emit_epilogue
,
3386 ppc64_emit_rsh_signed
,
3387 ppc64_emit_rsh_unsigned
,
3395 ppc64_emit_less_signed
,
3396 ppc64_emit_less_unsigned
,
3400 ppc_write_goto_address
,
3405 ppc64_emit_stack_flush
,
3406 ppc64_emit_zero_ext
,
3408 ppc_emit_stack_adjust
,
3409 ppc64v2_emit_int_call_1
,
3410 ppc64v2_emit_void_call_2
,
3421 /* Implementation of linux_target_ops method "emit_ops". */
3423 static struct emit_ops
*
3426 #ifdef __powerpc64__
3427 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3429 if (register_size (regcache
->tdesc
, 0) == 8)
3431 if (is_elfv2_inferior ())
3432 return &ppc64v2_emit_ops_impl
;
3434 return &ppc64v1_emit_ops_impl
;
3437 return &ppc_emit_ops_impl
;
3440 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3443 ppc_get_ipa_tdesc_idx (void)
3445 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3446 const struct target_desc
*tdesc
= regcache
->tdesc
;
3448 #ifdef __powerpc64__
3449 if (tdesc
== tdesc_powerpc_64l
)
3450 return PPC_TDESC_BASE
;
3451 if (tdesc
== tdesc_powerpc_altivec64l
)
3452 return PPC_TDESC_ALTIVEC
;
3453 if (tdesc
== tdesc_powerpc_cell64l
)
3454 return PPC_TDESC_CELL
;
3455 if (tdesc
== tdesc_powerpc_vsx64l
)
3456 return PPC_TDESC_VSX
;
3457 if (tdesc
== tdesc_powerpc_isa205_64l
)
3458 return PPC_TDESC_ISA205
;
3459 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3460 return PPC_TDESC_ISA205_ALTIVEC
;
3461 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3462 return PPC_TDESC_ISA205_VSX
;
3463 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3464 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3465 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3466 return PPC_TDESC_ISA207_VSX
;
3467 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3468 return PPC_TDESC_ISA207_HTM_VSX
;
3471 if (tdesc
== tdesc_powerpc_32l
)
3472 return PPC_TDESC_BASE
;
3473 if (tdesc
== tdesc_powerpc_altivec32l
)
3474 return PPC_TDESC_ALTIVEC
;
3475 if (tdesc
== tdesc_powerpc_cell32l
)
3476 return PPC_TDESC_CELL
;
3477 if (tdesc
== tdesc_powerpc_vsx32l
)
3478 return PPC_TDESC_VSX
;
3479 if (tdesc
== tdesc_powerpc_isa205_32l
)
3480 return PPC_TDESC_ISA205
;
3481 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3482 return PPC_TDESC_ISA205_ALTIVEC
;
3483 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3484 return PPC_TDESC_ISA205_VSX
;
3485 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3486 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3487 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3488 return PPC_TDESC_ISA207_VSX
;
3489 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3490 return PPC_TDESC_ISA207_HTM_VSX
;
3491 if (tdesc
== tdesc_powerpc_e500l
)
3492 return PPC_TDESC_E500
;
3497 struct linux_target_ops the_low_target
= {
3500 ppc_cannot_fetch_register
,
3501 ppc_cannot_store_register
,
3502 NULL
, /* fetch_register */
3505 NULL
, /* breakpoint_kind_from_pc */
3506 ppc_sw_breakpoint_from_kind
,
3510 ppc_supports_z_point_type
,
3515 ppc_collect_ptrace_register
,
3516 ppc_supply_ptrace_register
,
3517 NULL
, /* siginfo_fixup */
3518 NULL
, /* new_process */
3519 NULL
, /* delete_process */
3520 NULL
, /* new_thread */
3521 NULL
, /* delete_thread */
3522 NULL
, /* new_fork */
3523 NULL
, /* prepare_to_resume */
3524 NULL
, /* process_qsupported */
3525 ppc_supports_tracepoints
,
3526 ppc_get_thread_area
,
3527 ppc_install_fast_tracepoint_jump_pad
,
3529 ppc_get_min_fast_tracepoint_insn_len
,
3530 NULL
, /* supports_range_stepping */
3531 NULL
, /* breakpoint_kind_from_current_state */
3532 ppc_supports_hardware_single_step
,
3533 NULL
, /* get_syscall_trapinfo */
3534 ppc_get_ipa_tdesc_idx
,
3538 initialize_low_arch (void)
3540 /* Initialize the Linux target descriptions. */
3542 init_registers_powerpc_32l ();
3543 init_registers_powerpc_altivec32l ();
3544 init_registers_powerpc_cell32l ();
3545 init_registers_powerpc_vsx32l ();
3546 init_registers_powerpc_isa205_32l ();
3547 init_registers_powerpc_isa205_altivec32l ();
3548 init_registers_powerpc_isa205_vsx32l ();
3549 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3550 init_registers_powerpc_isa207_vsx32l ();
3551 init_registers_powerpc_isa207_htm_vsx32l ();
3552 init_registers_powerpc_e500l ();
3554 init_registers_powerpc_64l ();
3555 init_registers_powerpc_altivec64l ();
3556 init_registers_powerpc_cell64l ();
3557 init_registers_powerpc_vsx64l ();
3558 init_registers_powerpc_isa205_64l ();
3559 init_registers_powerpc_isa205_altivec64l ();
3560 init_registers_powerpc_isa205_vsx64l ();
3561 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3562 init_registers_powerpc_isa207_vsx64l ();
3563 init_registers_powerpc_isa207_htm_vsx64l ();
3566 initialize_regsets_info (&ppc_regsets_info
);