1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
24 #include <asm/ptrace.h>
26 /* These are in <asm/cputable.h> in current kernels. */
27 #define PPC_FEATURE_HAS_VSX 0x00000080
28 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
29 #define PPC_FEATURE_HAS_SPE 0x00800000
30 #define PPC_FEATURE_CELL 0x00010000
31 #define PPC_FEATURE_HAS_DFP 0x00000400
33 static unsigned long ppc_hwcap
;
36 /* Defined in auto-generated file powerpc-32l.c. */
37 void init_registers_powerpc_32l (void);
38 /* Defined in auto-generated file powerpc-altivec32l.c. */
39 void init_registers_powerpc_altivec32l (void);
40 /* Defined in auto-generated file powerpc-cell32l.c. */
41 void init_registers_powerpc_cell32l (void);
42 /* Defined in auto-generated file powerpc-vsx32l.c. */
43 void init_registers_powerpc_vsx32l (void);
44 /* Defined in auto-generated file powerpc-isa205-32l.c. */
45 void init_registers_powerpc_isa205_32l (void);
46 /* Defined in auto-generated file powerpc-isa205-altivec32l.c. */
47 void init_registers_powerpc_isa205_altivec32l (void);
48 /* Defined in auto-generated file powerpc-isa205-vsx32l.c. */
49 void init_registers_powerpc_isa205_vsx32l (void);
50 /* Defined in auto-generated file powerpc-e500l.c. */
51 void init_registers_powerpc_e500l (void);
52 /* Defined in auto-generated file powerpc-64l.c. */
53 void init_registers_powerpc_64l (void);
54 /* Defined in auto-generated file powerpc-altivec64l.c. */
55 void init_registers_powerpc_altivec64l (void);
56 /* Defined in auto-generated file powerpc-cell64l.c. */
57 void init_registers_powerpc_cell64l (void);
58 /* Defined in auto-generated file powerpc-vsx64l.c. */
59 void init_registers_powerpc_vsx64l (void);
60 /* Defined in auto-generated file powerpc-isa205-64l.c. */
61 void init_registers_powerpc_isa205_64l (void);
62 /* Defined in auto-generated file powerpc-isa205-altivec64l.c. */
63 void init_registers_powerpc_isa205_altivec64l (void);
64 /* Defined in auto-generated file powerpc-isa205-vsx64l.c. */
65 void init_registers_powerpc_isa205_vsx64l (void);
67 #define ppc_num_regs 73
69 /* This sometimes isn't defined. */
78 /* We use a constant for FPSCR instead of PT_FPSCR, because
79 many shipped PPC64 kernels had the wrong value in ptrace.h. */
80 static int ppc_regmap
[] =
81 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
82 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
83 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
84 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
85 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
86 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
87 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
88 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
89 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
90 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
91 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
92 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
93 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
94 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
95 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
96 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
97 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
98 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
99 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
101 /* Currently, don't check/send MQ. */
102 static int ppc_regmap
[] =
103 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
104 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
105 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
106 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
107 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
108 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
109 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
110 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
111 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
112 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
113 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
114 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
115 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
116 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
117 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
118 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
119 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
120 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
121 PT_ORIG_R3
* 4, PT_TRAP
* 4
124 static int ppc_regmap_e500
[] =
125 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
126 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
127 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
128 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
129 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
130 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
131 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
132 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
141 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
142 PT_CTR
* 4, PT_XER
* 4, -1,
143 PT_ORIG_R3
* 4, PT_TRAP
* 4
148 ppc_cannot_store_register (int regno
)
150 #ifndef __powerpc64__
151 /* Some kernels do not allow us to store fpscr. */
152 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
) && regno
== find_regno ("fpscr"))
156 /* Some kernels do not allow us to store orig_r3 or trap. */
157 if (regno
== find_regno ("orig_r3")
158 || regno
== find_regno ("trap"))
165 ppc_cannot_fetch_register (int regno
)
171 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
173 int size
= register_size (regno
);
175 memset (buf
, 0, sizeof (long));
177 if (size
< sizeof (long))
178 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
180 collect_register (regcache
, regno
, buf
);
184 ppc_supply_ptrace_register (struct regcache
*regcache
,
185 int regno
, const char *buf
)
187 int size
= register_size (regno
);
188 if (size
< sizeof (long))
189 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
191 supply_register (regcache
, regno
, buf
);
195 #define INSTR_SC 0x44000002
196 #define NR_spu_run 0x0116
198 /* If the PPU thread is currently stopped on a spu_run system call,
199 return to FD and ADDR the file handle and NPC parameter address
200 used with the system call. Return non-zero if successful. */
202 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
208 if (register_size (0) == 4)
210 unsigned int pc
, r0
, r3
, r4
;
211 collect_register_by_name (regcache
, "pc", &pc
);
212 collect_register_by_name (regcache
, "r0", &r0
);
213 collect_register_by_name (regcache
, "orig_r3", &r3
);
214 collect_register_by_name (regcache
, "r4", &r4
);
215 curr_pc
= (CORE_ADDR
) pc
;
218 *addr
= (CORE_ADDR
) r4
;
222 unsigned long pc
, r0
, r3
, r4
;
223 collect_register_by_name (regcache
, "pc", &pc
);
224 collect_register_by_name (regcache
, "r0", &r0
);
225 collect_register_by_name (regcache
, "orig_r3", &r3
);
226 collect_register_by_name (regcache
, "r4", &r4
);
227 curr_pc
= (CORE_ADDR
) pc
;
230 *addr
= (CORE_ADDR
) r4
;
233 /* Fetch instruction preceding current NIP. */
234 if ((*the_target
->read_memory
) (curr_pc
- 4,
235 (unsigned char *) &curr_insn
, 4) != 0)
237 /* It should be a "sc" instruction. */
238 if (curr_insn
!= INSTR_SC
)
240 /* System call number should be NR_spu_run. */
241 if (curr_r0
!= NR_spu_run
)
248 ppc_get_pc (struct regcache
*regcache
)
253 if (parse_spufs_run (regcache
, &fd
, &addr
))
256 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
257 return ((CORE_ADDR
)1 << 63)
258 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
260 else if (register_size (0) == 4)
263 collect_register_by_name (regcache
, "pc", &pc
);
264 return (CORE_ADDR
) pc
;
269 collect_register_by_name (regcache
, "pc", &pc
);
270 return (CORE_ADDR
) pc
;
275 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
280 if (parse_spufs_run (regcache
, &fd
, &addr
))
282 unsigned int newpc
= pc
;
283 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
285 else if (register_size (0) == 4)
287 unsigned int newpc
= pc
;
288 supply_register_by_name (regcache
, "pc", &newpc
);
292 unsigned long newpc
= pc
;
293 supply_register_by_name (regcache
, "pc", &newpc
);
299 ppc_get_hwcap (unsigned long *valp
)
301 int wordsize
= register_size (0);
302 unsigned char *data
= alloca (2 * wordsize
);
305 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
309 unsigned int *data_p
= (unsigned int *)data
;
310 if (data_p
[0] == AT_HWCAP
)
318 unsigned long *data_p
= (unsigned long *)data
;
319 if (data_p
[0] == AT_HWCAP
)
326 offset
+= 2 * wordsize
;
334 ppc_arch_setup (void)
338 struct regcache
*regcache
;
340 /* On a 64-bit host, assume 64-bit inferior process with no
341 AltiVec registers. Reset ppc_hwcap to ensure that the
342 collect_register call below does not fail. */
343 init_registers_powerpc_64l ();
346 /* Only if the high bit of the MSR is set, we actually have
347 a 64-bit inferior. */
348 regcache
= new_register_cache ();
349 fetch_inferior_registers (regcache
, find_regno ("msr"));
350 collect_register_by_name (regcache
, "msr", &msr
);
351 free_register_cache (regcache
);
354 ppc_get_hwcap (&ppc_hwcap
);
355 if (ppc_hwcap
& PPC_FEATURE_CELL
)
356 init_registers_powerpc_cell64l ();
357 else if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
359 /* Power ISA 2.05 (implemented by Power 6 and newer processors)
360 increases the FPSCR from 32 bits to 64 bits. Even though Power 7
361 supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05
362 set, only PPC_FEATURE_ARCH_2_06. Since for now the only bits
363 used in the higher half of the register are for Decimal Floating
364 Point, we check if that feature is available to decide the size
366 if (ppc_hwcap
& PPC_FEATURE_HAS_DFP
)
367 init_registers_powerpc_isa205_vsx64l ();
369 init_registers_powerpc_vsx64l ();
371 else if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
373 if (ppc_hwcap
& PPC_FEATURE_HAS_DFP
)
374 init_registers_powerpc_isa205_altivec64l ();
376 init_registers_powerpc_altivec64l ();
383 /* OK, we have a 32-bit inferior. */
384 init_registers_powerpc_32l ();
386 ppc_get_hwcap (&ppc_hwcap
);
387 if (ppc_hwcap
& PPC_FEATURE_CELL
)
388 init_registers_powerpc_cell32l ();
389 else if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
391 if (ppc_hwcap
& PPC_FEATURE_HAS_DFP
)
392 init_registers_powerpc_isa205_vsx32l ();
394 init_registers_powerpc_vsx32l ();
396 else if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
398 if (ppc_hwcap
& PPC_FEATURE_HAS_DFP
)
399 init_registers_powerpc_isa205_altivec32l ();
401 init_registers_powerpc_altivec32l ();
404 /* On 32-bit machines, check for SPE registers.
405 Set the low target's regmap field as appropriately. */
406 #ifndef __powerpc64__
407 the_low_target
.regmap
= ppc_regmap
;
408 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
410 init_registers_powerpc_e500l ();
411 the_low_target
.regmap
= ppc_regmap_e500
;
414 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
415 slot and not just its second word. The PT_FPSCR supplied in a
416 32-bit GDB compilation doesn't reflect this. */
417 if (register_size (70) == 8)
418 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
422 /* Correct in either endianness.
423 This instruction is "twge r2, r2", which GDB uses as a software
425 static const unsigned int ppc_breakpoint
= 0x7d821008;
426 #define ppc_breakpoint_len 4
429 ppc_breakpoint_at (CORE_ADDR where
)
433 if (where
& ((CORE_ADDR
)1 << 63))
436 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
437 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
438 NULL
, where
& 0xffffffff, 4);
444 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
445 if (insn
== ppc_breakpoint
)
447 /* If necessary, recognize more trap instructions here. GDB only uses
454 /* Provide only a fill function for the general register set. ps_lgetregs
455 will use this for NPTL support. */
457 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
461 for (i
= 0; i
< 32; i
++)
462 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
464 for (i
= 64; i
< 70; i
++)
465 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
467 for (i
= 71; i
< 73; i
++)
468 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
471 #ifndef PTRACE_GETVSXREGS
472 #define PTRACE_GETVSXREGS 27
473 #define PTRACE_SETVSXREGS 28
476 #define SIZEOF_VSXREGS 32*8
479 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
484 if (!(ppc_hwcap
& PPC_FEATURE_HAS_VSX
))
487 base
= find_regno ("vs0h");
488 for (i
= 0; i
< 32; i
++)
489 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
493 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
496 const char *regset
= buf
;
498 if (!(ppc_hwcap
& PPC_FEATURE_HAS_VSX
))
501 base
= find_regno ("vs0h");
502 for (i
= 0; i
< 32; i
++)
503 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
506 #ifndef PTRACE_GETVRREGS
507 #define PTRACE_GETVRREGS 18
508 #define PTRACE_SETVRREGS 19
511 #define SIZEOF_VRREGS 33*16+4
514 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
519 if (!(ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
))
522 base
= find_regno ("vr0");
523 for (i
= 0; i
< 32; i
++)
524 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
526 collect_register_by_name (regcache
, "vscr", ®set
[32 * 16 + 12]);
527 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
531 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
534 const char *regset
= buf
;
536 if (!(ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
))
539 base
= find_regno ("vr0");
540 for (i
= 0; i
< 32; i
++)
541 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
543 supply_register_by_name (regcache
, "vscr", ®set
[32 * 16 + 12]);
544 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
547 #ifndef PTRACE_GETEVRREGS
548 #define PTRACE_GETEVRREGS 20
549 #define PTRACE_SETEVRREGS 21
552 struct gdb_evrregset_t
554 unsigned long evr
[32];
555 unsigned long long acc
;
556 unsigned long spefscr
;
560 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
563 struct gdb_evrregset_t
*regset
= buf
;
565 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
))
568 ev0
= find_regno ("ev0h");
569 for (i
= 0; i
< 32; i
++)
570 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
572 collect_register_by_name (regcache
, "acc", ®set
->acc
);
573 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
577 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
580 const struct gdb_evrregset_t
*regset
= buf
;
582 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
))
585 ev0
= find_regno ("ev0h");
586 for (i
= 0; i
< 32; i
++)
587 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
589 supply_register_by_name (regcache
, "acc", ®set
->acc
);
590 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
593 struct regset_info target_regsets
[] = {
594 /* List the extra register sets before GENERAL_REGS. That way we will
595 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
596 general registers. Some kernels support these, but not the newer
597 PPC_PTRACE_GETREGS. */
598 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, SIZEOF_VSXREGS
, EXTENDED_REGS
,
599 ppc_fill_vsxregset
, ppc_store_vsxregset
},
600 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, SIZEOF_VRREGS
, EXTENDED_REGS
,
601 ppc_fill_vrregset
, ppc_store_vrregset
},
602 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 32 * 4 + 8 + 4, EXTENDED_REGS
,
603 ppc_fill_evrregset
, ppc_store_evrregset
},
604 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
605 { 0, 0, 0, -1, -1, NULL
, NULL
}
608 struct linux_target_ops the_low_target
= {
613 ppc_cannot_fetch_register
,
614 ppc_cannot_store_register
,
615 NULL
, /* fetch_register */
618 (const unsigned char *) &ppc_breakpoint
,
627 ppc_collect_ptrace_register
,
628 ppc_supply_ptrace_register
,