1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
24 #include <asm/ptrace.h>
26 #include "arch/ppc-linux-common.h"
27 #include "arch/ppc-linux-tdesc.h"
28 #include "nat/ppc-linux.h"
29 #include "linux-ppc-tdesc-init.h"
31 #include "tracepoint.h"
33 #define PPC_FIELD(value, from, len) \
34 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
35 #define PPC_SEXT(v, bs) \
36 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
37 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
38 - ((CORE_ADDR) 1 << ((bs) - 1)))
39 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
40 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
41 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
42 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
44 static unsigned long ppc_hwcap
;
47 #define ppc_num_regs 73
50 /* We use a constant for FPSCR instead of PT_FPSCR, because
51 many shipped PPC64 kernels had the wrong value in ptrace.h. */
52 static int ppc_regmap
[] =
53 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
54 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
55 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
56 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
57 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
58 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
59 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
60 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
61 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
62 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
63 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
64 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
65 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
66 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
67 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
68 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
69 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
70 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
71 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
73 /* Currently, don't check/send MQ. */
74 static int ppc_regmap
[] =
75 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
76 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
77 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
78 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
79 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
80 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
81 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
82 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
83 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
84 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
85 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
86 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
87 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
88 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
89 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
90 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
91 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
92 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
93 PT_ORIG_R3
* 4, PT_TRAP
* 4
96 static int ppc_regmap_e500
[] =
97 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
98 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
99 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
100 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
101 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
102 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
103 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
104 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
113 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
114 PT_CTR
* 4, PT_XER
* 4, -1,
115 PT_ORIG_R3
* 4, PT_TRAP
* 4
120 ppc_cannot_store_register (int regno
)
122 const struct target_desc
*tdesc
= current_process ()->tdesc
;
124 #ifndef __powerpc64__
125 /* Some kernels do not allow us to store fpscr. */
126 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
127 && regno
== find_regno (tdesc
, "fpscr"))
131 /* Some kernels do not allow us to store orig_r3 or trap. */
132 if (regno
== find_regno (tdesc
, "orig_r3")
133 || regno
== find_regno (tdesc
, "trap"))
140 ppc_cannot_fetch_register (int regno
)
146 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
148 memset (buf
, 0, sizeof (long));
150 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
152 /* Little-endian values always sit at the left end of the buffer. */
153 collect_register (regcache
, regno
, buf
);
155 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
157 /* Big-endian values sit at the right end of the buffer. In case of
158 registers whose sizes are smaller than sizeof (long), we must use a
159 padding to access them correctly. */
160 int size
= register_size (regcache
->tdesc
, regno
);
162 if (size
< sizeof (long))
163 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
165 collect_register (regcache
, regno
, buf
);
168 perror_with_name ("Unexpected byte order");
172 ppc_supply_ptrace_register (struct regcache
*regcache
,
173 int regno
, const char *buf
)
175 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
177 /* Little-endian values always sit at the left end of the buffer. */
178 supply_register (regcache
, regno
, buf
);
180 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
182 /* Big-endian values sit at the right end of the buffer. In case of
183 registers whose sizes are smaller than sizeof (long), we must use a
184 padding to access them correctly. */
185 int size
= register_size (regcache
->tdesc
, regno
);
187 if (size
< sizeof (long))
188 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
190 supply_register (regcache
, regno
, buf
);
193 perror_with_name ("Unexpected byte order");
197 #define INSTR_SC 0x44000002
198 #define NR_spu_run 0x0116
200 /* If the PPU thread is currently stopped on a spu_run system call,
201 return to FD and ADDR the file handle and NPC parameter address
202 used with the system call. Return non-zero if successful. */
204 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
210 if (register_size (regcache
->tdesc
, 0) == 4)
212 unsigned int pc
, r0
, r3
, r4
;
213 collect_register_by_name (regcache
, "pc", &pc
);
214 collect_register_by_name (regcache
, "r0", &r0
);
215 collect_register_by_name (regcache
, "orig_r3", &r3
);
216 collect_register_by_name (regcache
, "r4", &r4
);
217 curr_pc
= (CORE_ADDR
) pc
;
220 *addr
= (CORE_ADDR
) r4
;
224 unsigned long pc
, r0
, r3
, r4
;
225 collect_register_by_name (regcache
, "pc", &pc
);
226 collect_register_by_name (regcache
, "r0", &r0
);
227 collect_register_by_name (regcache
, "orig_r3", &r3
);
228 collect_register_by_name (regcache
, "r4", &r4
);
229 curr_pc
= (CORE_ADDR
) pc
;
232 *addr
= (CORE_ADDR
) r4
;
235 /* Fetch instruction preceding current NIP. */
236 if ((*the_target
->read_memory
) (curr_pc
- 4,
237 (unsigned char *) &curr_insn
, 4) != 0)
239 /* It should be a "sc" instruction. */
240 if (curr_insn
!= INSTR_SC
)
242 /* System call number should be NR_spu_run. */
243 if (curr_r0
!= NR_spu_run
)
250 ppc_get_pc (struct regcache
*regcache
)
255 if (parse_spufs_run (regcache
, &fd
, &addr
))
258 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
259 return ((CORE_ADDR
)1 << 63)
260 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
262 else if (register_size (regcache
->tdesc
, 0) == 4)
265 collect_register_by_name (regcache
, "pc", &pc
);
266 return (CORE_ADDR
) pc
;
271 collect_register_by_name (regcache
, "pc", &pc
);
272 return (CORE_ADDR
) pc
;
277 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
282 if (parse_spufs_run (regcache
, &fd
, &addr
))
284 unsigned int newpc
= pc
;
285 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
287 else if (register_size (regcache
->tdesc
, 0) == 4)
289 unsigned int newpc
= pc
;
290 supply_register_by_name (regcache
, "pc", &newpc
);
294 unsigned long newpc
= pc
;
295 supply_register_by_name (regcache
, "pc", &newpc
);
301 ppc_get_auxv (unsigned long type
, unsigned long *valp
)
303 const struct target_desc
*tdesc
= current_process ()->tdesc
;
304 int wordsize
= register_size (tdesc
, 0);
305 unsigned char *data
= (unsigned char *) alloca (2 * wordsize
);
308 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
312 unsigned int *data_p
= (unsigned int *)data
;
313 if (data_p
[0] == type
)
321 unsigned long *data_p
= (unsigned long *)data
;
322 if (data_p
[0] == type
)
329 offset
+= 2 * wordsize
;
336 #ifndef __powerpc64__
337 static int ppc_regmap_adjusted
;
341 /* Correct in either endianness.
342 This instruction is "twge r2, r2", which GDB uses as a software
344 static const unsigned int ppc_breakpoint
= 0x7d821008;
345 #define ppc_breakpoint_len 4
347 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
349 static const gdb_byte
*
350 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
352 *size
= ppc_breakpoint_len
;
353 return (const gdb_byte
*) &ppc_breakpoint
;
357 ppc_breakpoint_at (CORE_ADDR where
)
361 if (where
& ((CORE_ADDR
)1 << 63))
364 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
365 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
366 NULL
, where
& 0xffffffff, 4);
372 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
373 if (insn
== ppc_breakpoint
)
375 /* If necessary, recognize more trap instructions here. GDB only uses
382 /* Implement supports_z_point_type target-ops.
383 Returns true if type Z_TYPE breakpoint is supported.
385 Handling software breakpoint at server side, so tracepoints
386 and breakpoints can be inserted at the same location. */
389 ppc_supports_z_point_type (char z_type
)
396 case Z_PACKET_WRITE_WP
:
397 case Z_PACKET_ACCESS_WP
:
403 /* Implement insert_point target-ops.
404 Returns 0 on success, -1 on failure and 1 on unsupported. */
407 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
408 int size
, struct raw_breakpoint
*bp
)
412 case raw_bkpt_type_sw
:
413 return insert_memory_breakpoint (bp
);
415 case raw_bkpt_type_hw
:
416 case raw_bkpt_type_write_wp
:
417 case raw_bkpt_type_access_wp
:
424 /* Implement remove_point target-ops.
425 Returns 0 on success, -1 on failure and 1 on unsupported. */
428 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
429 int size
, struct raw_breakpoint
*bp
)
433 case raw_bkpt_type_sw
:
434 return remove_memory_breakpoint (bp
);
436 case raw_bkpt_type_hw
:
437 case raw_bkpt_type_write_wp
:
438 case raw_bkpt_type_access_wp
:
445 /* Provide only a fill function for the general register set. ps_lgetregs
446 will use this for NPTL support. */
448 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
452 for (i
= 0; i
< 32; i
++)
453 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
455 for (i
= 64; i
< 70; i
++)
456 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
458 for (i
= 71; i
< 73; i
++)
459 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
463 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
466 char *regset
= (char *) buf
;
468 base
= find_regno (regcache
->tdesc
, "vs0h");
469 for (i
= 0; i
< 32; i
++)
470 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
474 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
477 const char *regset
= (const char *) buf
;
479 base
= find_regno (regcache
->tdesc
, "vs0h");
480 for (i
= 0; i
< 32; i
++)
481 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
485 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
488 char *regset
= (char *) buf
;
491 base
= find_regno (regcache
->tdesc
, "vr0");
492 for (i
= 0; i
< 32; i
++)
493 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
495 if (__BYTE_ORDER
== __BIG_ENDIAN
)
498 /* Zero-pad the unused bytes in the fields for vscr and vrsave in
499 case they get displayed somewhere. */
500 memset (®set
[32 * 16], 0, 16);
501 collect_register_by_name (regcache
, "vscr",
502 ®set
[32 * 16 + vscr_offset
]);
504 memset (®set
[33 * 16], 0, 16);
505 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
509 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
512 const char *regset
= (const char *) buf
;
515 base
= find_regno (regcache
->tdesc
, "vr0");
516 for (i
= 0; i
< 32; i
++)
517 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
519 if (__BYTE_ORDER
== __BIG_ENDIAN
)
522 supply_register_by_name (regcache
, "vscr",
523 ®set
[32 * 16 + vscr_offset
]);
524 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
527 struct gdb_evrregset_t
529 unsigned long evr
[32];
530 unsigned long long acc
;
531 unsigned long spefscr
;
535 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
538 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
540 ev0
= find_regno (regcache
->tdesc
, "ev0h");
541 for (i
= 0; i
< 32; i
++)
542 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
544 collect_register_by_name (regcache
, "acc", ®set
->acc
);
545 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
549 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
552 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
554 ev0
= find_regno (regcache
->tdesc
, "ev0h");
555 for (i
= 0; i
< 32; i
++)
556 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
558 supply_register_by_name (regcache
, "acc", ®set
->acc
);
559 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
562 /* Support for hardware single step. */
565 ppc_supports_hardware_single_step (void)
570 static struct regset_info ppc_regsets
[] = {
571 /* List the extra register sets before GENERAL_REGS. That way we will
572 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
573 general registers. Some kernels support these, but not the newer
574 PPC_PTRACE_GETREGS. */
575 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
576 ppc_fill_vsxregset
, ppc_store_vsxregset
},
577 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
578 ppc_fill_vrregset
, ppc_store_vrregset
},
579 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
580 ppc_fill_evrregset
, ppc_store_evrregset
},
581 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
585 static struct usrregs_info ppc_usrregs_info
=
591 static struct regsets_info ppc_regsets_info
=
593 ppc_regsets
, /* regsets */
595 NULL
, /* disabled_regsets */
598 static struct regs_info regs_info
=
600 NULL
, /* regset_bitmap */
605 static const struct regs_info
*
612 ppc_arch_setup (void)
614 const struct target_desc
*tdesc
;
615 struct regset_info
*regset
;
616 struct ppc_linux_features features
= ppc_linux_no_features
;
618 int tid
= lwpid_of (current_thread
);
620 features
.wordsize
= ppc_linux_target_wordsize (tid
);
622 if (features
.wordsize
== 4)
623 tdesc
= tdesc_powerpc_32l
;
625 tdesc
= tdesc_powerpc_64l
;
627 current_process ()->tdesc
= tdesc
;
629 /* The value of current_process ()->tdesc needs to be set for this
631 ppc_get_auxv (AT_HWCAP
, &ppc_hwcap
);
633 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
635 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
638 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
639 features
.altivec
= true;
641 if (ppc_hwcap
& PPC_FEATURE_CELL
)
642 features
.cell
= true;
644 tdesc
= ppc_linux_match_description (features
);
646 /* On 32-bit machines, check for SPE registers.
647 Set the low target's regmap field as appropriately. */
648 #ifndef __powerpc64__
649 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
650 tdesc
= tdesc_powerpc_e500l
;
652 if (!ppc_regmap_adjusted
)
654 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
655 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
657 /* If the FPSCR is 64-bit wide, we need to fetch the whole
658 64-bit slot and not just its second word. The PT_FPSCR
659 supplied in a 32-bit GDB compilation doesn't reflect
661 if (register_size (tdesc
, 70) == 8)
662 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
664 ppc_regmap_adjusted
= 1;
668 current_process ()->tdesc
= tdesc
;
670 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
671 switch (regset
->get_request
)
673 case PTRACE_GETVRREGS
:
674 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
676 case PTRACE_GETVSXREGS
:
677 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
679 case PTRACE_GETEVRREGS
:
680 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
681 regset
->size
= 32 * 4 + 8 + 4;
690 /* Implementation of linux_target_ops method "supports_tracepoints". */
693 ppc_supports_tracepoints (void)
698 /* Get the thread area address. This is used to recognize which
699 thread is which when tracing with the in-process agent library. We
700 don't read anything from the address, and treat it as opaque; it's
701 the address itself that we assume is unique per-thread. */
704 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
706 struct lwp_info
*lwp
= find_lwp_pid (pid_to_ptid (lwpid
));
707 struct thread_info
*thr
= get_lwp_thread (lwp
);
708 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
712 if (register_size (regcache
->tdesc
, 0) == 8)
713 collect_register_by_name (regcache
, "r13", &tp
);
716 collect_register_by_name (regcache
, "r2", &tp
);
725 /* Older glibc doesn't provide this. */
728 #define EF_PPC64_ABI 3
731 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
735 is_elfv2_inferior (void)
737 /* To be used as fallback if we're unable to determine the right result -
738 assume inferior uses the same ABI as gdbserver. */
740 const int def_res
= 1;
742 const int def_res
= 0;
747 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
750 /* Assume ELF header is at the beginning of the page where program headers
751 are located. If it doesn't look like one, bail. */
753 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
754 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
757 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
762 /* Generate a ds-form instruction in BUF and return the number of bytes written
765 | OPCD | RST | RA | DS |XO| */
767 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
769 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
773 gdb_assert ((opcd
& ~0x3f) == 0);
774 gdb_assert ((rst
& ~0x1f) == 0);
775 gdb_assert ((ra
& ~0x1f) == 0);
776 gdb_assert ((xo
& ~0x3) == 0);
778 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
779 *buf
= (opcd
<< 26) | insn
;
783 /* Followings are frequently used ds-form instructions. */
785 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
786 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
787 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
788 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
790 /* Generate a d-form instruction in BUF.
793 | OPCD | RST | RA | D | */
796 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
800 gdb_assert ((opcd
& ~0x3f) == 0);
801 gdb_assert ((rst
& ~0x1f) == 0);
802 gdb_assert ((ra
& ~0x1f) == 0);
804 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
805 *buf
= (opcd
<< 26) | insn
;
809 /* Followings are frequently used d-form instructions. */
811 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
812 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
813 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
814 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
815 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
816 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
817 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
818 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
819 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
821 /* Generate a xfx-form instruction in BUF and return the number of bytes
825 | OPCD | RST | RI | XO |/| */
828 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
831 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
833 gdb_assert ((opcd
& ~0x3f) == 0);
834 gdb_assert ((rst
& ~0x1f) == 0);
835 gdb_assert ((xo
& ~0x3ff) == 0);
837 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
838 *buf
= (opcd
<< 26) | insn
;
842 /* Followings are frequently used xfx-form instructions. */
844 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
845 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
846 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
847 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
848 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
850 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
853 /* Generate a x-form instruction in BUF and return the number of bytes written.
856 | OPCD | RST | RA | RB | XO |RC| */
859 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
863 gdb_assert ((opcd
& ~0x3f) == 0);
864 gdb_assert ((rst
& ~0x1f) == 0);
865 gdb_assert ((ra
& ~0x1f) == 0);
866 gdb_assert ((rb
& ~0x1f) == 0);
867 gdb_assert ((xo
& ~0x3ff) == 0);
868 gdb_assert ((rc
& ~1) == 0);
870 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
871 *buf
= (opcd
<< 26) | insn
;
875 /* Followings are frequently used x-form instructions. */
877 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
878 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
879 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
880 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
881 /* Assume bf = cr7. */
882 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
885 /* Generate a md-form instruction in BUF and return the number of bytes written.
887 0 6 11 16 21 27 30 31 32
888 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
891 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
895 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
896 unsigned int sh0_4
= sh
& 0x1f;
897 unsigned int sh5
= (sh
>> 5) & 1;
899 gdb_assert ((opcd
& ~0x3f) == 0);
900 gdb_assert ((rs
& ~0x1f) == 0);
901 gdb_assert ((ra
& ~0x1f) == 0);
902 gdb_assert ((sh
& ~0x3f) == 0);
903 gdb_assert ((mb
& ~0x3f) == 0);
904 gdb_assert ((xo
& ~0x7) == 0);
905 gdb_assert ((rc
& ~0x1) == 0);
907 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
908 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
909 *buf
= (opcd
<< 26) | insn
;
913 /* The following are frequently used md-form instructions. */
915 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
916 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
917 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
918 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
920 /* Generate a i-form instruction in BUF and return the number of bytes written.
923 | OPCD | LI |AA|LK| */
926 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
930 gdb_assert ((opcd
& ~0x3f) == 0);
932 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
933 *buf
= (opcd
<< 26) | insn
;
937 /* The following are frequently used i-form instructions. */
939 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
940 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
942 /* Generate a b-form instruction in BUF and return the number of bytes written.
945 | OPCD | BO | BI | BD |AA|LK| */
948 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
953 gdb_assert ((opcd
& ~0x3f) == 0);
954 gdb_assert ((bo
& ~0x1f) == 0);
955 gdb_assert ((bi
& ~0x1f) == 0);
957 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
958 *buf
= (opcd
<< 26) | insn
;
962 /* The following are frequently used b-form instructions. */
963 /* Assume bi = cr7. */
964 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
966 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
967 respectively. They are primary used for save/restore GPRs in jump-pad,
968 not used for bytecode compiling. */
971 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
972 GEN_LD (buf, rt, ra, si) : \
973 GEN_LWZ (buf, rt, ra, si))
974 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
975 GEN_STD (buf, rt, ra, si) : \
976 GEN_STW (buf, rt, ra, si))
978 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
979 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
982 /* Generate a sequence of instructions to load IMM in the register REG.
983 Write the instructions in BUF and return the number of bytes written. */
986 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
990 if ((imm
+ 32768) < 65536)
992 /* li reg, imm[15:0] */
993 p
+= GEN_LI (p
, reg
, imm
);
995 else if ((imm
>> 32) == 0)
997 /* lis reg, imm[31:16]
998 ori reg, reg, imm[15:0]
999 rldicl reg, reg, 0, 32 */
1000 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1001 if ((imm
& 0xffff) != 0)
1002 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1003 /* Clear upper 32-bit if sign-bit is set. */
1004 if (imm
& (1u << 31) && is_64
)
1005 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1010 /* lis reg, <imm[63:48]>
1011 ori reg, reg, <imm[48:32]>
1012 rldicr reg, reg, 32, 31
1013 oris reg, reg, <imm[31:16]>
1014 ori reg, reg, <imm[15:0]> */
1015 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1016 if (((imm
>> 32) & 0xffff) != 0)
1017 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1018 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1019 if (((imm
>> 16) & 0xffff) != 0)
1020 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1021 if ((imm
& 0xffff) != 0)
1022 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1028 /* Generate a sequence for atomically exchange at location LOCK.
1029 This code sequence clobbers r6, r7, r8. LOCK is the location for
1030 the atomic-xchg, OLD_VALUE is expected old value stored in the
1031 location, and R_NEW is a register for the new value. */
1034 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1037 const int r_lock
= 6;
1038 const int r_old
= 7;
1039 const int r_tmp
= 8;
1043 1: lwarx TMP, 0, LOCK
1049 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1050 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1052 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1053 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1054 p
+= GEN_BNE (p
, -8);
1055 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1056 p
+= GEN_BNE (p
, -16);
1061 /* Generate a sequence of instructions for calling a function
1062 at address of FN. Return the number of bytes are written in BUF. */
1065 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1069 /* Must be called by r12 for caller to calculate TOC address. */
1070 p
+= gen_limm (p
, 12, fn
, is_64
);
1073 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1074 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1075 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1077 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1078 *p
++ = 0x4e800421; /* bctrl */
1083 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1084 of instruction. This function is used to adjust pc-relative instructions
1088 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1093 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1094 op6
= PPC_OP6 (insn
);
1096 if (op6
== 18 && (insn
& 2) == 0)
1098 /* branch && AA = 0 */
1099 rel
= PPC_LI (insn
);
1100 newrel
= (oldloc
- *to
) + rel
;
1102 /* Out of range. Cannot relocate instruction. */
1103 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1106 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1108 else if (op6
== 16 && (insn
& 2) == 0)
1110 /* conditional branch && AA = 0 */
1112 /* If the new relocation is too big for even a 26-bit unconditional
1113 branch, there is nothing we can do. Just abort.
1115 Otherwise, if it can be fit in 16-bit conditional branch, just
1116 copy the instruction and relocate the address.
1118 If the it's big for conditional-branch (16-bit), try to invert the
1119 condition and jump with 26-bit branch. For example,
1130 After this transform, we are actually jump from *TO+4 instead of *TO,
1131 so check the relocation again because it will be 1-insn farther then
1132 before if *TO is after OLDLOC.
1135 For BDNZT (or so) is transformed from
1147 See also "BO field encodings". */
1149 rel
= PPC_BD (insn
);
1150 newrel
= (oldloc
- *to
) + rel
;
1152 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1153 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1154 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1158 /* Out of range. Cannot relocate instruction. */
1159 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1162 if ((PPC_BO (insn
) & 0x14) == 0x4)
1164 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1167 /* Jump over the unconditional branch. */
1168 insn
= (insn
& ~0xfffc) | 0x8;
1169 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1172 /* Build a unconditional branch and copy LK bit. */
1173 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1174 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1179 else if ((PPC_BO (insn
) & 0x14) == 0)
1181 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1182 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1186 /* Out of range. Cannot relocate instruction. */
1187 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1190 /* Copy BI field. */
1191 bf_insn
|= (insn
& 0x1f0000);
1193 /* Invert condition. */
1194 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1195 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1197 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1199 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1202 /* Build a unconditional branch and copy LK bit. */
1203 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1204 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1209 else /* (BO & 0x14) == 0x14, branch always. */
1211 /* Out of range. Cannot relocate instruction. */
1212 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1215 /* Build a unconditional branch and copy LK bit. */
1216 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1217 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1224 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1228 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1229 See target.h for details. */
1232 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1233 CORE_ADDR collector
,
1236 CORE_ADDR
*jump_entry
,
1237 CORE_ADDR
*trampoline
,
1238 ULONGEST
*trampoline_size
,
1239 unsigned char *jjump_pad_insn
,
1240 ULONGEST
*jjump_pad_insn_size
,
1241 CORE_ADDR
*adjusted_insn_addr
,
1242 CORE_ADDR
*adjusted_insn_addr_end
,
1248 CORE_ADDR buildaddr
= *jump_entry
;
1249 const CORE_ADDR entryaddr
= *jump_entry
;
1250 int rsz
, min_frame
, frame_size
, tp_reg
;
1251 #ifdef __powerpc64__
1252 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1253 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1254 int is_opd
= is_64
&& !is_elfv2_inferior ();
1256 int is_64
= 0, is_opd
= 0;
1259 #ifdef __powerpc64__
1262 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1265 frame_size
= (40 * rsz
) + min_frame
;
1273 frame_size
= (40 * rsz
) + min_frame
;
1275 #ifdef __powerpc64__
1279 /* Stack frame layout for this jump pad,
1281 High thread_area (r13/r2) |
1282 tpoint - collecting_t obj
1292 R0 - collected registers
1298 The code flow of this jump pad,
1303 4. Call gdb_collector
1304 5. Restore GPR and SPR
1306 7. Build a jump for back to the program
1307 8. Copy/relocate original instruction
1308 9. Build a jump for replacing orignal instruction. */
1310 /* Adjust stack pointer. */
1312 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1314 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1316 /* Store GPRs. Save R1 later, because it had just been modified, but
1317 we want the original value. */
1318 for (j
= 2; j
< 32; j
++)
1319 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1320 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1321 /* Set r0 to the original value of r1 before adjusting stack frame,
1322 and then save it. */
1323 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1324 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1326 /* Save CR, XER, LR, and CTR. */
1327 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1328 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1329 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1330 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1331 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1332 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1333 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1334 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1336 /* Save PC<tpaddr> */
1337 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1338 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1341 /* Setup arguments to collector. */
1342 /* Set r4 to collected registers. */
1343 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1344 /* Set r3 to TPOINT. */
1345 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1347 /* Prepare collecting_t object for lock. */
1348 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1349 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1350 /* Set R5 to collecting object. */
1351 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1353 p
+= GEN_LWSYNC (p
);
1354 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1355 p
+= GEN_LWSYNC (p
);
1357 /* Call to collector. */
1358 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1360 /* Simply write 0 to release the lock. */
1361 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1362 p
+= gen_limm (p
, 4, 0, is_64
);
1363 p
+= GEN_LWSYNC (p
);
1364 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1366 /* Restore stack and registers. */
1367 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1368 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1369 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1370 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1371 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1372 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1373 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1374 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1377 for (j
= 2; j
< 32; j
++)
1378 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1379 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1381 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1383 /* Flush instructions to inferior memory. */
1384 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1386 /* Now, insert the original instruction to execute in the jump pad. */
1387 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1388 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1389 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1391 /* Verify the relocation size. If should be 4 for normal copy,
1392 8 or 12 for some conditional branch. */
1393 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1394 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1396 sprintf (err
, "E.Unexpected instruction length = %d"
1397 "when relocate instruction.",
1398 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1402 buildaddr
= *adjusted_insn_addr_end
;
1404 /* Finally, write a jump back to the program. */
1405 offset
= (tpaddr
+ 4) - buildaddr
;
1406 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1408 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1409 "(offset 0x%x > 26-bit).", offset
);
1413 p
+= GEN_B (p
, offset
);
1414 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1415 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1417 /* The jump pad is now built. Wire in a jump to our jump pad. This
1418 is always done last (by our caller actually), so that we can
1419 install fast tracepoints with threads running. This relies on
1420 the agent's atomic write support. */
1421 offset
= entryaddr
- tpaddr
;
1422 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1424 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1425 "(offset 0x%x > 26-bit).", offset
);
1429 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1430 *jjump_pad_insn_size
= 4;
1435 /* Returns the minimum instruction length for installing a tracepoint. */
1438 ppc_get_min_fast_tracepoint_insn_len (void)
1443 /* Emits a given buffer into the target at current_insn_ptr. Length
1444 is in units of 32-bit words. */
1447 emit_insns (uint32_t *buf
, int n
)
1449 n
= n
* sizeof (uint32_t);
1450 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1451 current_insn_ptr
+= n
;
1454 #define __EMIT_ASM(NAME, INSNS) \
1457 extern uint32_t start_bcax_ ## NAME []; \
1458 extern uint32_t end_bcax_ ## NAME []; \
1459 emit_insns (start_bcax_ ## NAME, \
1460 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1461 __asm__ (".section .text.__ppcbcax\n\t" \
1462 "start_bcax_" #NAME ":\n\t" \
1464 "end_bcax_" #NAME ":\n\t" \
1468 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1469 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1473 Bytecode execution stack frame - 32-bit
1475 | LR save area (SP + 4)
1476 SP' -> +- Back chain (SP + 0)
1477 | Save r31 for access saved arguments
1478 | Save r30 for bytecode stack pointer
1479 | Save r4 for incoming argument *value
1480 | Save r3 for incoming argument regs
1481 r30 -> +- Bytecode execution stack
1483 | 64-byte (8 doublewords) at initial.
1484 | Expand stack as needed.
1487 | Some padding for minimum stack frame and 16-byte alignment.
1489 SP +- Back-chain (SP')
1495 r30 is the stack-pointer for bytecode machine.
1496 It should point to next-empty, so we can use LDU for pop.
1497 r3 is used for cache of the high part of TOP value.
1498 It was the first argument, pointer to regs.
1499 r4 is used for cache of the low part of TOP value.
1500 It was the second argument, pointer to the result.
1501 We should set *result = TOP after leaving this function.
1504 * To restore stack at epilogue
1506 * To check stack is big enough for bytecode execution.
1508 * To return execution result.
1513 /* Regardless of endian, register 3 is always high part, 4 is low part.
1514 These defines are used when the register pair is stored/loaded.
1515 Likewise, to simplify code, have a similiar define for 5:6. */
1517 #if __BYTE_ORDER == __LITTLE_ENDIAN
1518 #define TOP_FIRST "4"
1519 #define TOP_SECOND "3"
1520 #define TMP_FIRST "6"
1521 #define TMP_SECOND "5"
1523 #define TOP_FIRST "3"
1524 #define TOP_SECOND "4"
1525 #define TMP_FIRST "5"
1526 #define TMP_SECOND "6"
1529 /* Emit prologue in inferior memory. See above comments. */
1532 ppc_emit_prologue (void)
1534 EMIT_ASM (/* Save return address. */
1537 /* Adjust SP. 96 is the initial frame size. */
1539 /* Save r30 and incoming arguments. */
1540 "stw 31, 96-4(1) \n"
1541 "stw 30, 96-8(1) \n"
1542 "stw 4, 96-12(1) \n"
1543 "stw 3, 96-16(1) \n"
1544 /* Point r31 to original r1 for access arguments. */
1546 /* Set r30 to pointing stack-top. */
1548 /* Initial r3/TOP to 0. */
1553 /* Emit epilogue in inferior memory. See above comments. */
1556 ppc_emit_epilogue (void)
1558 EMIT_ASM (/* *result = TOP */
1560 "stw " TOP_FIRST
", 0(5) \n"
1561 "stw " TOP_SECOND
", 4(5) \n"
1562 /* Restore registers. */
1569 /* Return 0 for no-error. */
1575 /* TOP = stack[--sp] + TOP */
1580 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1581 "lwz " TMP_SECOND
", 4(30)\n"
1586 /* TOP = stack[--sp] - TOP */
1591 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1592 "lwz " TMP_SECOND
", 4(30) \n"
1594 "subfe 3, 3, 5 \n");
1597 /* TOP = stack[--sp] * TOP */
1602 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1603 "lwz " TMP_SECOND
", 4(30) \n"
1612 /* TOP = stack[--sp] << TOP */
1617 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1618 "lwz " TMP_SECOND
", 4(30) \n"
1619 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1620 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1621 "slw 5, 5, 4\n" /* Shift high part left */
1622 "slw 4, 6, 4\n" /* Shift low part left */
1623 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1624 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1626 "or 3, 7, 3\n"); /* Assemble high part */
1629 /* Top = stack[--sp] >> TOP
1630 (Arithmetic shift right) */
1633 ppc_emit_rsh_signed (void)
1635 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1636 "lwz " TMP_SECOND
", 4(30) \n"
1637 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1638 "sraw 3, 5, 4\n" /* Shift high part right */
1640 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1641 "sraw 4, 5, 7\n" /* Shift high to low */
1644 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1645 "srw 4, 6, 4\n" /* Shift low part right */
1646 "slw 5, 5, 7\n" /* Shift high to low */
1647 "or 4, 4, 5\n" /* Assemble low part */
1651 /* Top = stack[--sp] >> TOP
1652 (Logical shift right) */
1655 ppc_emit_rsh_unsigned (void)
1657 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1658 "lwz " TMP_SECOND
", 4(30) \n"
1659 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1660 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1661 "srw 6, 6, 4\n" /* Shift low part right */
1662 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1663 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1665 "srw 3, 5, 4\n" /* Shift high part right */
1666 "or 4, 6, 7\n"); /* Assemble low part */
1669 /* Emit code for signed-extension specified by ARG. */
1672 ppc_emit_ext (int arg
)
1677 EMIT_ASM ("extsb 4, 4\n"
1681 EMIT_ASM ("extsh 4, 4\n"
1685 EMIT_ASM ("srawi 3, 4, 31");
1692 /* Emit code for zero-extension specified by ARG. */
1695 ppc_emit_zero_ext (int arg
)
1700 EMIT_ASM ("clrlwi 4,4,24\n"
1704 EMIT_ASM ("clrlwi 4,4,16\n"
1708 EMIT_ASM ("li 3, 0");
1716 i.e., TOP = (TOP == 0) ? 1 : 0; */
1719 ppc_emit_log_not (void)
1721 EMIT_ASM ("or 4, 3, 4 \n"
1727 /* TOP = stack[--sp] & TOP */
1730 ppc_emit_bit_and (void)
1732 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1733 "lwz " TMP_SECOND
", 4(30) \n"
1738 /* TOP = stack[--sp] | TOP */
1741 ppc_emit_bit_or (void)
1743 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1744 "lwz " TMP_SECOND
", 4(30) \n"
1749 /* TOP = stack[--sp] ^ TOP */
1752 ppc_emit_bit_xor (void)
1754 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1755 "lwz " TMP_SECOND
", 4(30) \n"
1761 i.e., TOP = ~(TOP | TOP) */
1764 ppc_emit_bit_not (void)
1766 EMIT_ASM ("nor 3, 3, 3 \n"
1770 /* TOP = stack[--sp] == TOP */
1773 ppc_emit_equal (void)
1775 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1776 "lwz " TMP_SECOND
", 4(30) \n"
1785 /* TOP = stack[--sp] < TOP
1786 (Signed comparison) */
1789 ppc_emit_less_signed (void)
1791 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1792 "lwz " TMP_SECOND
", 4(30) \n"
1795 /* CR6 bit 0 = low less and high equal */
1796 "crand 6*4+0, 6*4+0, 7*4+2\n"
1797 /* CR7 bit 0 = (low less and high equal) or high less */
1798 "cror 7*4+0, 7*4+0, 6*4+0\n"
1800 "rlwinm 4, 4, 29, 31, 31 \n"
1804 /* TOP = stack[--sp] < TOP
1805 (Unsigned comparison) */
1808 ppc_emit_less_unsigned (void)
1810 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1811 "lwz " TMP_SECOND
", 4(30) \n"
1814 /* CR6 bit 0 = low less and high equal */
1815 "crand 6*4+0, 6*4+0, 7*4+2\n"
1816 /* CR7 bit 0 = (low less and high equal) or high less */
1817 "cror 7*4+0, 7*4+0, 6*4+0\n"
1819 "rlwinm 4, 4, 29, 31, 31 \n"
1823 /* Access the memory address in TOP in size of SIZE.
1824 Zero-extend the read value. */
1827 ppc_emit_ref (int size
)
1832 EMIT_ASM ("lbz 4, 0(4)\n"
1836 EMIT_ASM ("lhz 4, 0(4)\n"
1840 EMIT_ASM ("lwz 4, 0(4)\n"
1844 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1845 EMIT_ASM ("lwz 3, 4(4)\n"
1848 EMIT_ASM ("lwz 3, 0(4)\n"
1857 ppc_emit_const (LONGEST num
)
1862 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
1863 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
1865 emit_insns (buf
, p
- buf
);
1866 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1869 /* Set TOP to the value of register REG by calling get_raw_reg function
1870 with two argument, collected buffer and register number. */
1873 ppc_emit_reg (int reg
)
1878 /* fctx->regs is passed in r3 and then saved in -16(31). */
1879 p
+= GEN_LWZ (p
, 3, 31, -16);
1880 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
1881 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
1883 emit_insns (buf
, p
- buf
);
1884 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1886 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1888 EMIT_ASM ("mr 5, 4\n"
1894 /* TOP = stack[--sp] */
1899 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
1900 "lwz " TOP_SECOND
", 4(30) \n");
1903 /* stack[sp++] = TOP
1905 Because we may use up bytecode stack, expand 8 doublewords more
1909 ppc_emit_stack_flush (void)
1911 /* Make sure bytecode stack is big enough before push.
1912 Otherwise, expand 64-byte more. */
1914 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
1915 " stw " TOP_SECOND
", 4(30)\n"
1916 " addi 5, 30, -(8 + 8) \n"
1919 " stwu 31, -64(1) \n"
1920 "1:addi 30, 30, -8 \n");
1923 /* Swap TOP and stack[sp-1] */
1926 ppc_emit_swap (void)
1928 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
1929 "lwz " TMP_SECOND
", 12(30) \n"
1930 "stw " TOP_FIRST
", 8(30) \n"
1931 "stw " TOP_SECOND
", 12(30) \n"
1936 /* Discard N elements in the stack. Also used for ppc64. */
1939 ppc_emit_stack_adjust (int n
)
1951 p
+= GEN_ADDI (p
, 30, 30, n
);
1953 emit_insns (buf
, p
- buf
);
1954 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1957 /* Call function FN. */
1960 ppc_emit_call (CORE_ADDR fn
)
1965 p
+= gen_call (p
, fn
, 0, 0);
1967 emit_insns (buf
, p
- buf
);
1968 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1971 /* FN's prototype is `LONGEST(*fn)(int)'.
1976 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
1981 /* Setup argument. arg1 is a 16-bit value. */
1982 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
1983 p
+= gen_call (p
, fn
, 0, 0);
1985 emit_insns (buf
, p
- buf
);
1986 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1988 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1990 EMIT_ASM ("mr 5, 4\n"
1996 /* FN's prototype is `void(*fn)(int,LONGEST)'.
1999 TOP should be preserved/restored before/after the call. */
2002 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2007 /* Save TOP. 0(30) is next-empty. */
2008 p
+= GEN_STW (p
, 3, 30, 0);
2009 p
+= GEN_STW (p
, 4, 30, 4);
2011 /* Setup argument. arg1 is a 16-bit value. */
2012 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2014 p
+= GEN_MR (p
, 5, 4);
2015 p
+= GEN_MR (p
, 6, 3);
2019 p
+= GEN_MR (p
, 5, 3);
2020 p
+= GEN_MR (p
, 6, 4);
2022 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2023 p
+= gen_call (p
, fn
, 0, 0);
2026 p
+= GEN_LWZ (p
, 3, 30, 0);
2027 p
+= GEN_LWZ (p
, 4, 30, 4);
2029 emit_insns (buf
, p
- buf
);
2030 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2033 /* Note in the following goto ops:
2035 When emitting goto, the target address is later relocated by
2036 write_goto_address. OFFSET_P is the offset of the branch instruction
2037 in the code sequence, and SIZE_P is how to relocate the instruction,
2038 recognized by ppc_write_goto_address. In current implementation,
2039 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2042 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2045 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2047 EMIT_ASM ("or. 3, 3, 4 \n"
2048 "lwzu " TOP_FIRST
", 8(30) \n"
2049 "lwz " TOP_SECOND
", 4(30) \n"
2058 /* Unconditional goto. Also used for ppc64. */
2061 ppc_emit_goto (int *offset_p
, int *size_p
)
2063 EMIT_ASM ("1:b 1b");
2071 /* Goto if stack[--sp] == TOP */
2074 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2076 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2077 "lwz " TMP_SECOND
", 4(30) \n"
2081 "lwzu " TOP_FIRST
", 8(30) \n"
2082 "lwz " TOP_SECOND
", 4(30) \n"
2091 /* Goto if stack[--sp] != TOP */
2094 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2096 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2097 "lwz " TMP_SECOND
", 4(30) \n"
2101 "lwzu " TOP_FIRST
", 8(30) \n"
2102 "lwz " TOP_SECOND
", 4(30) \n"
2111 /* Goto if stack[--sp] < TOP */
2114 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2116 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2117 "lwz " TMP_SECOND
", 4(30) \n"
2120 /* CR6 bit 0 = low less and high equal */
2121 "crand 6*4+0, 6*4+0, 7*4+2\n"
2122 /* CR7 bit 0 = (low less and high equal) or high less */
2123 "cror 7*4+0, 7*4+0, 6*4+0\n"
2124 "lwzu " TOP_FIRST
", 8(30) \n"
2125 "lwz " TOP_SECOND
", 4(30)\n"
2134 /* Goto if stack[--sp] <= TOP */
2137 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2139 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2140 "lwz " TMP_SECOND
", 4(30) \n"
2143 /* CR6 bit 0 = low less/equal and high equal */
2144 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2145 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2146 "cror 7*4+0, 7*4+0, 6*4+0\n"
2147 "lwzu " TOP_FIRST
", 8(30) \n"
2148 "lwz " TOP_SECOND
", 4(30)\n"
2157 /* Goto if stack[--sp] > TOP */
2160 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2162 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2163 "lwz " TMP_SECOND
", 4(30) \n"
2166 /* CR6 bit 0 = low greater and high equal */
2167 "crand 6*4+0, 6*4+1, 7*4+2\n"
2168 /* CR7 bit 0 = (low greater and high equal) or high greater */
2169 "cror 7*4+0, 7*4+1, 6*4+0\n"
2170 "lwzu " TOP_FIRST
", 8(30) \n"
2171 "lwz " TOP_SECOND
", 4(30)\n"
2180 /* Goto if stack[--sp] >= TOP */
2183 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2185 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2186 "lwz " TMP_SECOND
", 4(30) \n"
2189 /* CR6 bit 0 = low ge and high equal */
2190 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2191 /* CR7 bit 0 = (low ge and high equal) or high greater */
2192 "cror 7*4+0, 7*4+1, 6*4+0\n"
2193 "lwzu " TOP_FIRST
", 8(30)\n"
2194 "lwz " TOP_SECOND
", 4(30)\n"
2203 /* Relocate previous emitted branch instruction. FROM is the address
2204 of the branch instruction, TO is the goto target address, and SIZE
2205 if the value we set by *SIZE_P before. Currently, it is either
2206 24 or 14 of branch and conditional-branch instruction.
2207 Also used for ppc64. */
2210 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2212 long rel
= to
- from
;
2216 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2217 opcd
= (insn
>> 26) & 0x3f;
2223 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2225 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2229 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2231 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2238 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2241 /* Table of emit ops for 32-bit. */
2243 static struct emit_ops ppc_emit_ops_impl
=
2251 ppc_emit_rsh_signed
,
2252 ppc_emit_rsh_unsigned
,
2260 ppc_emit_less_signed
,
2261 ppc_emit_less_unsigned
,
2265 ppc_write_goto_address
,
2270 ppc_emit_stack_flush
,
2273 ppc_emit_stack_adjust
,
2274 ppc_emit_int_call_1
,
2275 ppc_emit_void_call_2
,
2284 #ifdef __powerpc64__
2288 Bytecode execution stack frame - 64-bit
2290 | LR save area (SP + 16)
2291 | CR save area (SP + 8)
2292 SP' -> +- Back chain (SP + 0)
2293 | Save r31 for access saved arguments
2294 | Save r30 for bytecode stack pointer
2295 | Save r4 for incoming argument *value
2296 | Save r3 for incoming argument regs
2297 r30 -> +- Bytecode execution stack
2299 | 64-byte (8 doublewords) at initial.
2300 | Expand stack as needed.
2303 | Some padding for minimum stack frame.
2305 SP +- Back-chain (SP')
2308 = 112 + (4 * 8) + 64
2311 r30 is the stack-pointer for bytecode machine.
2312 It should point to next-empty, so we can use LDU for pop.
2313 r3 is used for cache of TOP value.
2314 It was the first argument, pointer to regs.
2315 r4 is the second argument, pointer to the result.
2316 We should set *result = TOP after leaving this function.
2319 * To restore stack at epilogue
2321 * To check stack is big enough for bytecode execution.
2322 => r30 - 8 > SP + 112
2323 * To return execution result.
2328 /* Emit prologue in inferior memory. See above comments. */
2331 ppc64v1_emit_prologue (void)
2333 /* On ELFv1, function pointers really point to function descriptor,
2334 so emit one here. We don't care about contents of words 1 and 2,
2335 so let them just overlap out code. */
2336 uint64_t opd
= current_insn_ptr
+ 8;
2339 /* Mind the strict aliasing rules. */
2340 memcpy (buf
, &opd
, sizeof buf
);
2342 EMIT_ASM (/* Save return address. */
2345 /* Save r30 and incoming arguments. */
2350 /* Point r31 to current r1 for access arguments. */
2352 /* Adjust SP. 208 is the initial frame size. */
2353 "stdu 1, -208(1) \n"
2354 /* Set r30 to pointing stack-top. */
2355 "addi 30, 1, 168 \n"
2356 /* Initial r3/TOP to 0. */
2360 /* Emit prologue in inferior memory. See above comments. */
2363 ppc64v2_emit_prologue (void)
2365 EMIT_ASM (/* Save return address. */
2368 /* Save r30 and incoming arguments. */
2373 /* Point r31 to current r1 for access arguments. */
2375 /* Adjust SP. 208 is the initial frame size. */
2376 "stdu 1, -208(1) \n"
2377 /* Set r30 to pointing stack-top. */
2378 "addi 30, 1, 168 \n"
2379 /* Initial r3/TOP to 0. */
2383 /* Emit epilogue in inferior memory. See above comments. */
2386 ppc64_emit_epilogue (void)
2388 EMIT_ASM (/* Restore SP. */
2393 /* Restore registers. */
2398 /* Return 0 for no-error. */
2404 /* TOP = stack[--sp] + TOP */
2407 ppc64_emit_add (void)
2409 EMIT_ASM ("ldu 4, 8(30) \n"
2413 /* TOP = stack[--sp] - TOP */
2416 ppc64_emit_sub (void)
2418 EMIT_ASM ("ldu 4, 8(30) \n"
2422 /* TOP = stack[--sp] * TOP */
2425 ppc64_emit_mul (void)
2427 EMIT_ASM ("ldu 4, 8(30) \n"
2428 "mulld 3, 4, 3 \n");
2431 /* TOP = stack[--sp] << TOP */
2434 ppc64_emit_lsh (void)
2436 EMIT_ASM ("ldu 4, 8(30) \n"
2440 /* Top = stack[--sp] >> TOP
2441 (Arithmetic shift right) */
2444 ppc64_emit_rsh_signed (void)
2446 EMIT_ASM ("ldu 4, 8(30) \n"
2450 /* Top = stack[--sp] >> TOP
2451 (Logical shift right) */
2454 ppc64_emit_rsh_unsigned (void)
2456 EMIT_ASM ("ldu 4, 8(30) \n"
2460 /* Emit code for signed-extension specified by ARG. */
2463 ppc64_emit_ext (int arg
)
2468 EMIT_ASM ("extsb 3, 3");
2471 EMIT_ASM ("extsh 3, 3");
2474 EMIT_ASM ("extsw 3, 3");
2481 /* Emit code for zero-extension specified by ARG. */
2484 ppc64_emit_zero_ext (int arg
)
2489 EMIT_ASM ("rldicl 3,3,0,56");
2492 EMIT_ASM ("rldicl 3,3,0,48");
2495 EMIT_ASM ("rldicl 3,3,0,32");
2503 i.e., TOP = (TOP == 0) ? 1 : 0; */
2506 ppc64_emit_log_not (void)
2508 EMIT_ASM ("cntlzd 3, 3 \n"
2512 /* TOP = stack[--sp] & TOP */
2515 ppc64_emit_bit_and (void)
2517 EMIT_ASM ("ldu 4, 8(30) \n"
2521 /* TOP = stack[--sp] | TOP */
2524 ppc64_emit_bit_or (void)
2526 EMIT_ASM ("ldu 4, 8(30) \n"
2530 /* TOP = stack[--sp] ^ TOP */
2533 ppc64_emit_bit_xor (void)
2535 EMIT_ASM ("ldu 4, 8(30) \n"
2540 i.e., TOP = ~(TOP | TOP) */
2543 ppc64_emit_bit_not (void)
2545 EMIT_ASM ("nor 3, 3, 3 \n");
2548 /* TOP = stack[--sp] == TOP */
2551 ppc64_emit_equal (void)
2553 EMIT_ASM ("ldu 4, 8(30) \n"
2559 /* TOP = stack[--sp] < TOP
2560 (Signed comparison) */
2563 ppc64_emit_less_signed (void)
2565 EMIT_ASM ("ldu 4, 8(30) \n"
2568 "rlwinm 3, 3, 29, 31, 31 \n");
2571 /* TOP = stack[--sp] < TOP
2572 (Unsigned comparison) */
2575 ppc64_emit_less_unsigned (void)
2577 EMIT_ASM ("ldu 4, 8(30) \n"
2580 "rlwinm 3, 3, 29, 31, 31 \n");
2583 /* Access the memory address in TOP in size of SIZE.
2584 Zero-extend the read value. */
2587 ppc64_emit_ref (int size
)
2592 EMIT_ASM ("lbz 3, 0(3)");
2595 EMIT_ASM ("lhz 3, 0(3)");
2598 EMIT_ASM ("lwz 3, 0(3)");
2601 EMIT_ASM ("ld 3, 0(3)");
2609 ppc64_emit_const (LONGEST num
)
2614 p
+= gen_limm (p
, 3, num
, 1);
2616 emit_insns (buf
, p
- buf
);
2617 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2620 /* Set TOP to the value of register REG by calling get_raw_reg function
2621 with two argument, collected buffer and register number. */
2624 ppc64v1_emit_reg (int reg
)
2629 /* fctx->regs is passed in r3 and then saved in 176(1). */
2630 p
+= GEN_LD (p
, 3, 31, -32);
2631 p
+= GEN_LI (p
, 4, reg
);
2632 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2633 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2634 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2636 emit_insns (buf
, p
- buf
);
2637 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2640 /* Likewise, for ELFv2. */
2643 ppc64v2_emit_reg (int reg
)
2648 /* fctx->regs is passed in r3 and then saved in 176(1). */
2649 p
+= GEN_LD (p
, 3, 31, -32);
2650 p
+= GEN_LI (p
, 4, reg
);
2651 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2652 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2653 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2655 emit_insns (buf
, p
- buf
);
2656 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2659 /* TOP = stack[--sp] */
2662 ppc64_emit_pop (void)
2664 EMIT_ASM ("ldu 3, 8(30)");
2667 /* stack[sp++] = TOP
2669 Because we may use up bytecode stack, expand 8 doublewords more
2673 ppc64_emit_stack_flush (void)
2675 /* Make sure bytecode stack is big enough before push.
2676 Otherwise, expand 64-byte more. */
2678 EMIT_ASM (" std 3, 0(30) \n"
2679 " addi 4, 30, -(112 + 8) \n"
2682 " stdu 31, -64(1) \n"
2683 "1:addi 30, 30, -8 \n");
2686 /* Swap TOP and stack[sp-1] */
2689 ppc64_emit_swap (void)
2691 EMIT_ASM ("ld 4, 8(30) \n"
2696 /* Call function FN - ELFv1. */
2699 ppc64v1_emit_call (CORE_ADDR fn
)
2704 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2705 p
+= gen_call (p
, fn
, 1, 1);
2706 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2708 emit_insns (buf
, p
- buf
);
2709 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2712 /* Call function FN - ELFv2. */
2715 ppc64v2_emit_call (CORE_ADDR fn
)
2720 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2721 p
+= gen_call (p
, fn
, 1, 0);
2722 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2724 emit_insns (buf
, p
- buf
);
2725 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2728 /* FN's prototype is `LONGEST(*fn)(int)'.
2733 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2738 /* Setup argument. arg1 is a 16-bit value. */
2739 p
+= gen_limm (p
, 3, arg1
, 1);
2740 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2741 p
+= gen_call (p
, fn
, 1, 1);
2742 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2744 emit_insns (buf
, p
- buf
);
2745 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2748 /* Likewise for ELFv2. */
2751 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2756 /* Setup argument. arg1 is a 16-bit value. */
2757 p
+= gen_limm (p
, 3, arg1
, 1);
2758 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2759 p
+= gen_call (p
, fn
, 1, 0);
2760 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2762 emit_insns (buf
, p
- buf
);
2763 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2766 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2769 TOP should be preserved/restored before/after the call. */
2772 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2777 /* Save TOP. 0(30) is next-empty. */
2778 p
+= GEN_STD (p
, 3, 30, 0);
2780 /* Setup argument. arg1 is a 16-bit value. */
2781 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2782 p
+= gen_limm (p
, 3, arg1
, 1);
2783 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2784 p
+= gen_call (p
, fn
, 1, 1);
2785 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2788 p
+= GEN_LD (p
, 3, 30, 0);
2790 emit_insns (buf
, p
- buf
);
2791 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2794 /* Likewise for ELFv2. */
2797 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2802 /* Save TOP. 0(30) is next-empty. */
2803 p
+= GEN_STD (p
, 3, 30, 0);
2805 /* Setup argument. arg1 is a 16-bit value. */
2806 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2807 p
+= gen_limm (p
, 3, arg1
, 1);
2808 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2809 p
+= gen_call (p
, fn
, 1, 0);
2810 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2813 p
+= GEN_LD (p
, 3, 30, 0);
2815 emit_insns (buf
, p
- buf
);
2816 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2819 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2822 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
2824 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2834 /* Goto if stack[--sp] == TOP */
2837 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
2839 EMIT_ASM ("ldu 4, 8(30) \n"
2850 /* Goto if stack[--sp] != TOP */
2853 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
2855 EMIT_ASM ("ldu 4, 8(30) \n"
2866 /* Goto if stack[--sp] < TOP */
2869 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
2871 EMIT_ASM ("ldu 4, 8(30) \n"
2882 /* Goto if stack[--sp] <= TOP */
2885 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
2887 EMIT_ASM ("ldu 4, 8(30) \n"
2898 /* Goto if stack[--sp] > TOP */
2901 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
2903 EMIT_ASM ("ldu 4, 8(30) \n"
2914 /* Goto if stack[--sp] >= TOP */
2917 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
2919 EMIT_ASM ("ldu 4, 8(30) \n"
2930 /* Table of emit ops for 64-bit ELFv1. */
2932 static struct emit_ops ppc64v1_emit_ops_impl
=
2934 ppc64v1_emit_prologue
,
2935 ppc64_emit_epilogue
,
2940 ppc64_emit_rsh_signed
,
2941 ppc64_emit_rsh_unsigned
,
2949 ppc64_emit_less_signed
,
2950 ppc64_emit_less_unsigned
,
2954 ppc_write_goto_address
,
2959 ppc64_emit_stack_flush
,
2960 ppc64_emit_zero_ext
,
2962 ppc_emit_stack_adjust
,
2963 ppc64v1_emit_int_call_1
,
2964 ppc64v1_emit_void_call_2
,
2973 /* Table of emit ops for 64-bit ELFv2. */
2975 static struct emit_ops ppc64v2_emit_ops_impl
=
2977 ppc64v2_emit_prologue
,
2978 ppc64_emit_epilogue
,
2983 ppc64_emit_rsh_signed
,
2984 ppc64_emit_rsh_unsigned
,
2992 ppc64_emit_less_signed
,
2993 ppc64_emit_less_unsigned
,
2997 ppc_write_goto_address
,
3002 ppc64_emit_stack_flush
,
3003 ppc64_emit_zero_ext
,
3005 ppc_emit_stack_adjust
,
3006 ppc64v2_emit_int_call_1
,
3007 ppc64v2_emit_void_call_2
,
3018 /* Implementation of linux_target_ops method "emit_ops". */
3020 static struct emit_ops
*
3023 #ifdef __powerpc64__
3024 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3026 if (register_size (regcache
->tdesc
, 0) == 8)
3028 if (is_elfv2_inferior ())
3029 return &ppc64v2_emit_ops_impl
;
3031 return &ppc64v1_emit_ops_impl
;
3034 return &ppc_emit_ops_impl
;
3037 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3040 ppc_get_ipa_tdesc_idx (void)
3042 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3043 const struct target_desc
*tdesc
= regcache
->tdesc
;
3045 #ifdef __powerpc64__
3046 if (tdesc
== tdesc_powerpc_64l
)
3047 return PPC_TDESC_BASE
;
3048 if (tdesc
== tdesc_powerpc_altivec64l
)
3049 return PPC_TDESC_ALTIVEC
;
3050 if (tdesc
== tdesc_powerpc_cell64l
)
3051 return PPC_TDESC_CELL
;
3052 if (tdesc
== tdesc_powerpc_vsx64l
)
3053 return PPC_TDESC_VSX
;
3054 if (tdesc
== tdesc_powerpc_isa205_64l
)
3055 return PPC_TDESC_ISA205
;
3056 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3057 return PPC_TDESC_ISA205_ALTIVEC
;
3058 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3059 return PPC_TDESC_ISA205_VSX
;
3062 if (tdesc
== tdesc_powerpc_32l
)
3063 return PPC_TDESC_BASE
;
3064 if (tdesc
== tdesc_powerpc_altivec32l
)
3065 return PPC_TDESC_ALTIVEC
;
3066 if (tdesc
== tdesc_powerpc_cell32l
)
3067 return PPC_TDESC_CELL
;
3068 if (tdesc
== tdesc_powerpc_vsx32l
)
3069 return PPC_TDESC_VSX
;
3070 if (tdesc
== tdesc_powerpc_isa205_32l
)
3071 return PPC_TDESC_ISA205
;
3072 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3073 return PPC_TDESC_ISA205_ALTIVEC
;
3074 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3075 return PPC_TDESC_ISA205_VSX
;
3076 if (tdesc
== tdesc_powerpc_e500l
)
3077 return PPC_TDESC_E500
;
3082 struct linux_target_ops the_low_target
= {
3085 ppc_cannot_fetch_register
,
3086 ppc_cannot_store_register
,
3087 NULL
, /* fetch_register */
3090 NULL
, /* breakpoint_kind_from_pc */
3091 ppc_sw_breakpoint_from_kind
,
3095 ppc_supports_z_point_type
,
3100 ppc_collect_ptrace_register
,
3101 ppc_supply_ptrace_register
,
3102 NULL
, /* siginfo_fixup */
3103 NULL
, /* new_process */
3104 NULL
, /* delete_process */
3105 NULL
, /* new_thread */
3106 NULL
, /* delete_thread */
3107 NULL
, /* new_fork */
3108 NULL
, /* prepare_to_resume */
3109 NULL
, /* process_qsupported */
3110 ppc_supports_tracepoints
,
3111 ppc_get_thread_area
,
3112 ppc_install_fast_tracepoint_jump_pad
,
3114 ppc_get_min_fast_tracepoint_insn_len
,
3115 NULL
, /* supports_range_stepping */
3116 NULL
, /* breakpoint_kind_from_current_state */
3117 ppc_supports_hardware_single_step
,
3118 NULL
, /* get_syscall_trapinfo */
3119 ppc_get_ipa_tdesc_idx
,
3123 initialize_low_arch (void)
3125 /* Initialize the Linux target descriptions. */
3127 init_registers_powerpc_32l ();
3128 init_registers_powerpc_altivec32l ();
3129 init_registers_powerpc_cell32l ();
3130 init_registers_powerpc_vsx32l ();
3131 init_registers_powerpc_isa205_32l ();
3132 init_registers_powerpc_isa205_altivec32l ();
3133 init_registers_powerpc_isa205_vsx32l ();
3134 init_registers_powerpc_e500l ();
3136 init_registers_powerpc_64l ();
3137 init_registers_powerpc_altivec64l ();
3138 init_registers_powerpc_cell64l ();
3139 init_registers_powerpc_vsx64l ();
3140 init_registers_powerpc_isa205_64l ();
3141 init_registers_powerpc_isa205_altivec64l ();
3142 init_registers_powerpc_isa205_vsx64l ();
3145 initialize_regsets_info (&ppc_regsets_info
);