1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "linux-ppc-tdesc-init.h"
33 #include "tracepoint.h"
35 #define PPC_FIELD(value, from, len) \
36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
37 #define PPC_SEXT(v, bs) \
38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
40 - ((CORE_ADDR) 1 << ((bs) - 1)))
41 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
42 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
43 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
44 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
46 /* Holds the AT_HWCAP auxv entry. */
48 static unsigned long ppc_hwcap
;
50 /* Holds the AT_HWCAP2 auxv entry. */
52 static unsigned long ppc_hwcap2
;
55 #define ppc_num_regs 73
58 /* We use a constant for FPSCR instead of PT_FPSCR, because
59 many shipped PPC64 kernels had the wrong value in ptrace.h. */
60 static int ppc_regmap
[] =
61 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
62 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
63 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
64 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
65 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
66 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
67 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
68 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
69 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
70 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
71 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
72 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
73 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
74 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
75 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
76 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
77 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
78 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
79 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
81 /* Currently, don't check/send MQ. */
82 static int ppc_regmap
[] =
83 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
84 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
85 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
86 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
87 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
88 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
89 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
90 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
91 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
92 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
93 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
94 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
95 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
96 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
97 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
98 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
99 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
100 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
101 PT_ORIG_R3
* 4, PT_TRAP
* 4
104 static int ppc_regmap_e500
[] =
105 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
106 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
107 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
108 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
109 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
110 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
111 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
112 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
121 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
122 PT_CTR
* 4, PT_XER
* 4, -1,
123 PT_ORIG_R3
* 4, PT_TRAP
* 4
127 /* Check whether the kernel provides a register set with number
128 REGSET_ID of size REGSETSIZE for process/thread TID. */
131 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
133 void *buf
= alloca (regsetsize
);
137 iov
.iov_len
= regsetsize
;
139 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
146 ppc_cannot_store_register (int regno
)
148 const struct target_desc
*tdesc
= current_process ()->tdesc
;
150 #ifndef __powerpc64__
151 /* Some kernels do not allow us to store fpscr. */
152 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
153 && regno
== find_regno (tdesc
, "fpscr"))
157 /* Some kernels do not allow us to store orig_r3 or trap. */
158 if (regno
== find_regno (tdesc
, "orig_r3")
159 || regno
== find_regno (tdesc
, "trap"))
166 ppc_cannot_fetch_register (int regno
)
172 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
174 memset (buf
, 0, sizeof (long));
176 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
178 /* Little-endian values always sit at the left end of the buffer. */
179 collect_register (regcache
, regno
, buf
);
181 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
183 /* Big-endian values sit at the right end of the buffer. In case of
184 registers whose sizes are smaller than sizeof (long), we must use a
185 padding to access them correctly. */
186 int size
= register_size (regcache
->tdesc
, regno
);
188 if (size
< sizeof (long))
189 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
191 collect_register (regcache
, regno
, buf
);
194 perror_with_name ("Unexpected byte order");
198 ppc_supply_ptrace_register (struct regcache
*regcache
,
199 int regno
, const char *buf
)
201 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
203 /* Little-endian values always sit at the left end of the buffer. */
204 supply_register (regcache
, regno
, buf
);
206 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
208 /* Big-endian values sit at the right end of the buffer. In case of
209 registers whose sizes are smaller than sizeof (long), we must use a
210 padding to access them correctly. */
211 int size
= register_size (regcache
->tdesc
, regno
);
213 if (size
< sizeof (long))
214 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
216 supply_register (regcache
, regno
, buf
);
219 perror_with_name ("Unexpected byte order");
223 #define INSTR_SC 0x44000002
224 #define NR_spu_run 0x0116
226 /* If the PPU thread is currently stopped on a spu_run system call,
227 return to FD and ADDR the file handle and NPC parameter address
228 used with the system call. Return non-zero if successful. */
230 parse_spufs_run (struct regcache
*regcache
, int *fd
, CORE_ADDR
*addr
)
236 if (register_size (regcache
->tdesc
, 0) == 4)
238 unsigned int pc
, r0
, r3
, r4
;
239 collect_register_by_name (regcache
, "pc", &pc
);
240 collect_register_by_name (regcache
, "r0", &r0
);
241 collect_register_by_name (regcache
, "orig_r3", &r3
);
242 collect_register_by_name (regcache
, "r4", &r4
);
243 curr_pc
= (CORE_ADDR
) pc
;
246 *addr
= (CORE_ADDR
) r4
;
250 unsigned long pc
, r0
, r3
, r4
;
251 collect_register_by_name (regcache
, "pc", &pc
);
252 collect_register_by_name (regcache
, "r0", &r0
);
253 collect_register_by_name (regcache
, "orig_r3", &r3
);
254 collect_register_by_name (regcache
, "r4", &r4
);
255 curr_pc
= (CORE_ADDR
) pc
;
258 *addr
= (CORE_ADDR
) r4
;
261 /* Fetch instruction preceding current NIP. */
262 if ((*the_target
->read_memory
) (curr_pc
- 4,
263 (unsigned char *) &curr_insn
, 4) != 0)
265 /* It should be a "sc" instruction. */
266 if (curr_insn
!= INSTR_SC
)
268 /* System call number should be NR_spu_run. */
269 if (curr_r0
!= NR_spu_run
)
276 ppc_get_pc (struct regcache
*regcache
)
281 if (parse_spufs_run (regcache
, &fd
, &addr
))
284 (*the_target
->read_memory
) (addr
, (unsigned char *) &pc
, 4);
285 return ((CORE_ADDR
)1 << 63)
286 | ((CORE_ADDR
)fd
<< 32) | (CORE_ADDR
) (pc
- 4);
288 else if (register_size (regcache
->tdesc
, 0) == 4)
291 collect_register_by_name (regcache
, "pc", &pc
);
292 return (CORE_ADDR
) pc
;
297 collect_register_by_name (regcache
, "pc", &pc
);
298 return (CORE_ADDR
) pc
;
303 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
308 if (parse_spufs_run (regcache
, &fd
, &addr
))
310 unsigned int newpc
= pc
;
311 (*the_target
->write_memory
) (addr
, (unsigned char *) &newpc
, 4);
313 else if (register_size (regcache
->tdesc
, 0) == 4)
315 unsigned int newpc
= pc
;
316 supply_register_by_name (regcache
, "pc", &newpc
);
320 unsigned long newpc
= pc
;
321 supply_register_by_name (regcache
, "pc", &newpc
);
327 ppc_get_auxv (unsigned long type
, unsigned long *valp
)
329 const struct target_desc
*tdesc
= current_process ()->tdesc
;
330 int wordsize
= register_size (tdesc
, 0);
331 unsigned char *data
= (unsigned char *) alloca (2 * wordsize
);
334 while ((*the_target
->read_auxv
) (offset
, data
, 2 * wordsize
) == 2 * wordsize
)
338 unsigned int *data_p
= (unsigned int *)data
;
339 if (data_p
[0] == type
)
347 unsigned long *data_p
= (unsigned long *)data
;
348 if (data_p
[0] == type
)
355 offset
+= 2 * wordsize
;
362 #ifndef __powerpc64__
363 static int ppc_regmap_adjusted
;
367 /* Correct in either endianness.
368 This instruction is "twge r2, r2", which GDB uses as a software
370 static const unsigned int ppc_breakpoint
= 0x7d821008;
371 #define ppc_breakpoint_len 4
373 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
375 static const gdb_byte
*
376 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
378 *size
= ppc_breakpoint_len
;
379 return (const gdb_byte
*) &ppc_breakpoint
;
383 ppc_breakpoint_at (CORE_ADDR where
)
387 if (where
& ((CORE_ADDR
)1 << 63))
390 sprintf (mem_annex
, "%d/mem", (int)((where
>> 32) & 0x7fffffff));
391 (*the_target
->qxfer_spu
) (mem_annex
, (unsigned char *) &insn
,
392 NULL
, where
& 0xffffffff, 4);
398 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
, 4);
399 if (insn
== ppc_breakpoint
)
401 /* If necessary, recognize more trap instructions here. GDB only uses
408 /* Implement supports_z_point_type target-ops.
409 Returns true if type Z_TYPE breakpoint is supported.
411 Handling software breakpoint at server side, so tracepoints
412 and breakpoints can be inserted at the same location. */
415 ppc_supports_z_point_type (char z_type
)
422 case Z_PACKET_WRITE_WP
:
423 case Z_PACKET_ACCESS_WP
:
429 /* Implement insert_point target-ops.
430 Returns 0 on success, -1 on failure and 1 on unsupported. */
433 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
434 int size
, struct raw_breakpoint
*bp
)
438 case raw_bkpt_type_sw
:
439 return insert_memory_breakpoint (bp
);
441 case raw_bkpt_type_hw
:
442 case raw_bkpt_type_write_wp
:
443 case raw_bkpt_type_access_wp
:
450 /* Implement remove_point target-ops.
451 Returns 0 on success, -1 on failure and 1 on unsupported. */
454 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
455 int size
, struct raw_breakpoint
*bp
)
459 case raw_bkpt_type_sw
:
460 return remove_memory_breakpoint (bp
);
462 case raw_bkpt_type_hw
:
463 case raw_bkpt_type_write_wp
:
464 case raw_bkpt_type_access_wp
:
471 /* Provide only a fill function for the general register set. ps_lgetregs
472 will use this for NPTL support. */
474 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
478 for (i
= 0; i
< 32; i
++)
479 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
481 for (i
= 64; i
< 70; i
++)
482 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
484 for (i
= 71; i
< 73; i
++)
485 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
488 /* Program Priority Register regset fill function. */
491 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
493 char *ppr
= (char *) buf
;
495 collect_register_by_name (regcache
, "ppr", ppr
);
498 /* Program Priority Register regset store function. */
501 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
503 const char *ppr
= (const char *) buf
;
505 supply_register_by_name (regcache
, "ppr", ppr
);
508 /* Data Stream Control Register regset fill function. */
511 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
513 char *dscr
= (char *) buf
;
515 collect_register_by_name (regcache
, "dscr", dscr
);
518 /* Data Stream Control Register regset store function. */
521 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
523 const char *dscr
= (const char *) buf
;
525 supply_register_by_name (regcache
, "dscr", dscr
);
529 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
532 char *regset
= (char *) buf
;
534 base
= find_regno (regcache
->tdesc
, "vs0h");
535 for (i
= 0; i
< 32; i
++)
536 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
540 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
543 const char *regset
= (const char *) buf
;
545 base
= find_regno (regcache
->tdesc
, "vs0h");
546 for (i
= 0; i
< 32; i
++)
547 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
551 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
554 char *regset
= (char *) buf
;
557 base
= find_regno (regcache
->tdesc
, "vr0");
558 for (i
= 0; i
< 32; i
++)
559 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
561 if (__BYTE_ORDER
== __BIG_ENDIAN
)
564 collect_register_by_name (regcache
, "vscr",
565 ®set
[32 * 16 + vscr_offset
]);
567 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
571 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
574 const char *regset
= (const char *) buf
;
577 base
= find_regno (regcache
->tdesc
, "vr0");
578 for (i
= 0; i
< 32; i
++)
579 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
581 if (__BYTE_ORDER
== __BIG_ENDIAN
)
584 supply_register_by_name (regcache
, "vscr",
585 ®set
[32 * 16 + vscr_offset
]);
586 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
589 struct gdb_evrregset_t
591 unsigned long evr
[32];
592 unsigned long long acc
;
593 unsigned long spefscr
;
597 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
600 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
602 ev0
= find_regno (regcache
->tdesc
, "ev0h");
603 for (i
= 0; i
< 32; i
++)
604 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
606 collect_register_by_name (regcache
, "acc", ®set
->acc
);
607 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
611 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
614 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
616 ev0
= find_regno (regcache
->tdesc
, "ev0h");
617 for (i
= 0; i
< 32; i
++)
618 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
620 supply_register_by_name (regcache
, "acc", ®set
->acc
);
621 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
624 /* Support for hardware single step. */
627 ppc_supports_hardware_single_step (void)
632 static struct regset_info ppc_regsets
[] = {
633 /* List the extra register sets before GENERAL_REGS. That way we will
634 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
635 general registers. Some kernels support these, but not the newer
636 PPC_PTRACE_GETREGS. */
637 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
638 ppc_fill_pprregset
, ppc_store_pprregset
},
639 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
640 ppc_fill_dscrregset
, ppc_store_dscrregset
},
641 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
642 ppc_fill_vsxregset
, ppc_store_vsxregset
},
643 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
644 ppc_fill_vrregset
, ppc_store_vrregset
},
645 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
646 ppc_fill_evrregset
, ppc_store_evrregset
},
647 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
651 static struct usrregs_info ppc_usrregs_info
=
657 static struct regsets_info ppc_regsets_info
=
659 ppc_regsets
, /* regsets */
661 NULL
, /* disabled_regsets */
664 static struct regs_info regs_info
=
666 NULL
, /* regset_bitmap */
671 static const struct regs_info
*
678 ppc_arch_setup (void)
680 const struct target_desc
*tdesc
;
681 struct regset_info
*regset
;
682 struct ppc_linux_features features
= ppc_linux_no_features
;
684 int tid
= lwpid_of (current_thread
);
686 features
.wordsize
= ppc_linux_target_wordsize (tid
);
688 if (features
.wordsize
== 4)
689 tdesc
= tdesc_powerpc_32l
;
691 tdesc
= tdesc_powerpc_64l
;
693 current_process ()->tdesc
= tdesc
;
695 /* The value of current_process ()->tdesc needs to be set for this
697 ppc_get_auxv (AT_HWCAP
, &ppc_hwcap
);
698 ppc_get_auxv (AT_HWCAP2
, &ppc_hwcap2
);
700 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
702 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
705 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
706 features
.altivec
= true;
708 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
709 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
710 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
711 features
.ppr_dscr
= true;
713 if (ppc_hwcap
& PPC_FEATURE_CELL
)
714 features
.cell
= true;
716 tdesc
= ppc_linux_match_description (features
);
718 /* On 32-bit machines, check for SPE registers.
719 Set the low target's regmap field as appropriately. */
720 #ifndef __powerpc64__
721 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
722 tdesc
= tdesc_powerpc_e500l
;
724 if (!ppc_regmap_adjusted
)
726 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
727 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
729 /* If the FPSCR is 64-bit wide, we need to fetch the whole
730 64-bit slot and not just its second word. The PT_FPSCR
731 supplied in a 32-bit GDB compilation doesn't reflect
733 if (register_size (tdesc
, 70) == 8)
734 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
736 ppc_regmap_adjusted
= 1;
740 current_process ()->tdesc
= tdesc
;
742 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
743 switch (regset
->get_request
)
745 case PTRACE_GETVRREGS
:
746 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
748 case PTRACE_GETVSXREGS
:
749 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
751 case PTRACE_GETEVRREGS
:
752 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
753 regset
->size
= 32 * 4 + 8 + 4;
757 case PTRACE_GETREGSET
:
758 switch (regset
->nt_type
)
761 regset
->size
= (features
.ppr_dscr
?
762 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
765 regset
->size
= (features
.ppr_dscr
?
766 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
777 /* Implementation of linux_target_ops method "supports_tracepoints". */
780 ppc_supports_tracepoints (void)
785 /* Get the thread area address. This is used to recognize which
786 thread is which when tracing with the in-process agent library. We
787 don't read anything from the address, and treat it as opaque; it's
788 the address itself that we assume is unique per-thread. */
791 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
793 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
794 struct thread_info
*thr
= get_lwp_thread (lwp
);
795 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
799 if (register_size (regcache
->tdesc
, 0) == 8)
800 collect_register_by_name (regcache
, "r13", &tp
);
803 collect_register_by_name (regcache
, "r2", &tp
);
812 /* Older glibc doesn't provide this. */
815 #define EF_PPC64_ABI 3
818 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
822 is_elfv2_inferior (void)
824 /* To be used as fallback if we're unable to determine the right result -
825 assume inferior uses the same ABI as gdbserver. */
827 const int def_res
= 1;
829 const int def_res
= 0;
834 if (!ppc_get_auxv (AT_PHDR
, &phdr
))
837 /* Assume ELF header is at the beginning of the page where program headers
838 are located. If it doesn't look like one, bail. */
840 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
841 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
844 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
849 /* Generate a ds-form instruction in BUF and return the number of bytes written
852 | OPCD | RST | RA | DS |XO| */
854 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
856 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
860 gdb_assert ((opcd
& ~0x3f) == 0);
861 gdb_assert ((rst
& ~0x1f) == 0);
862 gdb_assert ((ra
& ~0x1f) == 0);
863 gdb_assert ((xo
& ~0x3) == 0);
865 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
866 *buf
= (opcd
<< 26) | insn
;
870 /* Followings are frequently used ds-form instructions. */
872 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
873 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
874 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
875 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
877 /* Generate a d-form instruction in BUF.
880 | OPCD | RST | RA | D | */
883 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
887 gdb_assert ((opcd
& ~0x3f) == 0);
888 gdb_assert ((rst
& ~0x1f) == 0);
889 gdb_assert ((ra
& ~0x1f) == 0);
891 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
892 *buf
= (opcd
<< 26) | insn
;
896 /* Followings are frequently used d-form instructions. */
898 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
899 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
900 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
901 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
902 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
903 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
904 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
905 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
906 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
908 /* Generate a xfx-form instruction in BUF and return the number of bytes
912 | OPCD | RST | RI | XO |/| */
915 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
918 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
920 gdb_assert ((opcd
& ~0x3f) == 0);
921 gdb_assert ((rst
& ~0x1f) == 0);
922 gdb_assert ((xo
& ~0x3ff) == 0);
924 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
925 *buf
= (opcd
<< 26) | insn
;
929 /* Followings are frequently used xfx-form instructions. */
931 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
932 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
933 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
934 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
935 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
937 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
940 /* Generate a x-form instruction in BUF and return the number of bytes written.
943 | OPCD | RST | RA | RB | XO |RC| */
946 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
950 gdb_assert ((opcd
& ~0x3f) == 0);
951 gdb_assert ((rst
& ~0x1f) == 0);
952 gdb_assert ((ra
& ~0x1f) == 0);
953 gdb_assert ((rb
& ~0x1f) == 0);
954 gdb_assert ((xo
& ~0x3ff) == 0);
955 gdb_assert ((rc
& ~1) == 0);
957 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
958 *buf
= (opcd
<< 26) | insn
;
962 /* Followings are frequently used x-form instructions. */
964 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
965 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
966 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
967 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
968 /* Assume bf = cr7. */
969 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
972 /* Generate a md-form instruction in BUF and return the number of bytes written.
974 0 6 11 16 21 27 30 31 32
975 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
978 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
982 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
983 unsigned int sh0_4
= sh
& 0x1f;
984 unsigned int sh5
= (sh
>> 5) & 1;
986 gdb_assert ((opcd
& ~0x3f) == 0);
987 gdb_assert ((rs
& ~0x1f) == 0);
988 gdb_assert ((ra
& ~0x1f) == 0);
989 gdb_assert ((sh
& ~0x3f) == 0);
990 gdb_assert ((mb
& ~0x3f) == 0);
991 gdb_assert ((xo
& ~0x7) == 0);
992 gdb_assert ((rc
& ~0x1) == 0);
994 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
995 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
996 *buf
= (opcd
<< 26) | insn
;
1000 /* The following are frequently used md-form instructions. */
1002 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1003 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1004 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1005 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1007 /* Generate a i-form instruction in BUF and return the number of bytes written.
1010 | OPCD | LI |AA|LK| */
1013 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1017 gdb_assert ((opcd
& ~0x3f) == 0);
1019 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1020 *buf
= (opcd
<< 26) | insn
;
1024 /* The following are frequently used i-form instructions. */
1026 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1027 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1029 /* Generate a b-form instruction in BUF and return the number of bytes written.
1032 | OPCD | BO | BI | BD |AA|LK| */
1035 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1040 gdb_assert ((opcd
& ~0x3f) == 0);
1041 gdb_assert ((bo
& ~0x1f) == 0);
1042 gdb_assert ((bi
& ~0x1f) == 0);
1044 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1045 *buf
= (opcd
<< 26) | insn
;
1049 /* The following are frequently used b-form instructions. */
1050 /* Assume bi = cr7. */
1051 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1053 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1054 respectively. They are primary used for save/restore GPRs in jump-pad,
1055 not used for bytecode compiling. */
1057 #ifdef __powerpc64__
1058 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1059 GEN_LD (buf, rt, ra, si) : \
1060 GEN_LWZ (buf, rt, ra, si))
1061 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1062 GEN_STD (buf, rt, ra, si) : \
1063 GEN_STW (buf, rt, ra, si))
1065 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1066 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1069 /* Generate a sequence of instructions to load IMM in the register REG.
1070 Write the instructions in BUF and return the number of bytes written. */
1073 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1077 if ((imm
+ 32768) < 65536)
1079 /* li reg, imm[15:0] */
1080 p
+= GEN_LI (p
, reg
, imm
);
1082 else if ((imm
>> 32) == 0)
1084 /* lis reg, imm[31:16]
1085 ori reg, reg, imm[15:0]
1086 rldicl reg, reg, 0, 32 */
1087 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1088 if ((imm
& 0xffff) != 0)
1089 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1090 /* Clear upper 32-bit if sign-bit is set. */
1091 if (imm
& (1u << 31) && is_64
)
1092 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1097 /* lis reg, <imm[63:48]>
1098 ori reg, reg, <imm[48:32]>
1099 rldicr reg, reg, 32, 31
1100 oris reg, reg, <imm[31:16]>
1101 ori reg, reg, <imm[15:0]> */
1102 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1103 if (((imm
>> 32) & 0xffff) != 0)
1104 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1105 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1106 if (((imm
>> 16) & 0xffff) != 0)
1107 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1108 if ((imm
& 0xffff) != 0)
1109 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1115 /* Generate a sequence for atomically exchange at location LOCK.
1116 This code sequence clobbers r6, r7, r8. LOCK is the location for
1117 the atomic-xchg, OLD_VALUE is expected old value stored in the
1118 location, and R_NEW is a register for the new value. */
1121 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1124 const int r_lock
= 6;
1125 const int r_old
= 7;
1126 const int r_tmp
= 8;
1130 1: lwarx TMP, 0, LOCK
1136 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1137 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1139 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1140 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1141 p
+= GEN_BNE (p
, -8);
1142 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1143 p
+= GEN_BNE (p
, -16);
1148 /* Generate a sequence of instructions for calling a function
1149 at address of FN. Return the number of bytes are written in BUF. */
1152 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1156 /* Must be called by r12 for caller to calculate TOC address. */
1157 p
+= gen_limm (p
, 12, fn
, is_64
);
1160 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1161 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1162 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1164 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1165 *p
++ = 0x4e800421; /* bctrl */
1170 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1171 of instruction. This function is used to adjust pc-relative instructions
1175 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1180 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1181 op6
= PPC_OP6 (insn
);
1183 if (op6
== 18 && (insn
& 2) == 0)
1185 /* branch && AA = 0 */
1186 rel
= PPC_LI (insn
);
1187 newrel
= (oldloc
- *to
) + rel
;
1189 /* Out of range. Cannot relocate instruction. */
1190 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1193 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1195 else if (op6
== 16 && (insn
& 2) == 0)
1197 /* conditional branch && AA = 0 */
1199 /* If the new relocation is too big for even a 26-bit unconditional
1200 branch, there is nothing we can do. Just abort.
1202 Otherwise, if it can be fit in 16-bit conditional branch, just
1203 copy the instruction and relocate the address.
1205 If the it's big for conditional-branch (16-bit), try to invert the
1206 condition and jump with 26-bit branch. For example,
1217 After this transform, we are actually jump from *TO+4 instead of *TO,
1218 so check the relocation again because it will be 1-insn farther then
1219 before if *TO is after OLDLOC.
1222 For BDNZT (or so) is transformed from
1234 See also "BO field encodings". */
1236 rel
= PPC_BD (insn
);
1237 newrel
= (oldloc
- *to
) + rel
;
1239 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1240 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1241 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1245 /* Out of range. Cannot relocate instruction. */
1246 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1249 if ((PPC_BO (insn
) & 0x14) == 0x4)
1251 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1254 /* Jump over the unconditional branch. */
1255 insn
= (insn
& ~0xfffc) | 0x8;
1256 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1259 /* Build a unconditional branch and copy LK bit. */
1260 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1261 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1266 else if ((PPC_BO (insn
) & 0x14) == 0)
1268 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1269 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1273 /* Out of range. Cannot relocate instruction. */
1274 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1277 /* Copy BI field. */
1278 bf_insn
|= (insn
& 0x1f0000);
1280 /* Invert condition. */
1281 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1282 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1284 write_inferior_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1286 write_inferior_memory (*to
, (unsigned char *) &bf_insn
, 4);
1289 /* Build a unconditional branch and copy LK bit. */
1290 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1291 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1296 else /* (BO & 0x14) == 0x14, branch always. */
1298 /* Out of range. Cannot relocate instruction. */
1299 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1302 /* Build a unconditional branch and copy LK bit. */
1303 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1304 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1311 write_inferior_memory (*to
, (unsigned char *) &insn
, 4);
1315 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1316 See target.h for details. */
1319 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1320 CORE_ADDR collector
,
1323 CORE_ADDR
*jump_entry
,
1324 CORE_ADDR
*trampoline
,
1325 ULONGEST
*trampoline_size
,
1326 unsigned char *jjump_pad_insn
,
1327 ULONGEST
*jjump_pad_insn_size
,
1328 CORE_ADDR
*adjusted_insn_addr
,
1329 CORE_ADDR
*adjusted_insn_addr_end
,
1335 CORE_ADDR buildaddr
= *jump_entry
;
1336 const CORE_ADDR entryaddr
= *jump_entry
;
1337 int rsz
, min_frame
, frame_size
, tp_reg
;
1338 #ifdef __powerpc64__
1339 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1340 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1341 int is_opd
= is_64
&& !is_elfv2_inferior ();
1343 int is_64
= 0, is_opd
= 0;
1346 #ifdef __powerpc64__
1349 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1352 frame_size
= (40 * rsz
) + min_frame
;
1360 frame_size
= (40 * rsz
) + min_frame
;
1362 #ifdef __powerpc64__
1366 /* Stack frame layout for this jump pad,
1368 High thread_area (r13/r2) |
1369 tpoint - collecting_t obj
1379 R0 - collected registers
1385 The code flow of this jump pad,
1390 4. Call gdb_collector
1391 5. Restore GPR and SPR
1393 7. Build a jump for back to the program
1394 8. Copy/relocate original instruction
1395 9. Build a jump for replacing orignal instruction. */
1397 /* Adjust stack pointer. */
1399 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1401 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1403 /* Store GPRs. Save R1 later, because it had just been modified, but
1404 we want the original value. */
1405 for (j
= 2; j
< 32; j
++)
1406 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1407 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1408 /* Set r0 to the original value of r1 before adjusting stack frame,
1409 and then save it. */
1410 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1411 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1413 /* Save CR, XER, LR, and CTR. */
1414 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1415 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1416 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1417 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1418 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1419 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1420 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1421 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1423 /* Save PC<tpaddr> */
1424 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1425 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1428 /* Setup arguments to collector. */
1429 /* Set r4 to collected registers. */
1430 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1431 /* Set r3 to TPOINT. */
1432 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1434 /* Prepare collecting_t object for lock. */
1435 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1436 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1437 /* Set R5 to collecting object. */
1438 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1440 p
+= GEN_LWSYNC (p
);
1441 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1442 p
+= GEN_LWSYNC (p
);
1444 /* Call to collector. */
1445 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1447 /* Simply write 0 to release the lock. */
1448 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1449 p
+= gen_limm (p
, 4, 0, is_64
);
1450 p
+= GEN_LWSYNC (p
);
1451 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1453 /* Restore stack and registers. */
1454 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1455 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1456 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1457 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1458 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1459 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1460 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1461 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1464 for (j
= 2; j
< 32; j
++)
1465 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1466 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1468 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1470 /* Flush instructions to inferior memory. */
1471 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1473 /* Now, insert the original instruction to execute in the jump pad. */
1474 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1475 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1476 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1478 /* Verify the relocation size. If should be 4 for normal copy,
1479 8 or 12 for some conditional branch. */
1480 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1481 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1483 sprintf (err
, "E.Unexpected instruction length = %d"
1484 "when relocate instruction.",
1485 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1489 buildaddr
= *adjusted_insn_addr_end
;
1491 /* Finally, write a jump back to the program. */
1492 offset
= (tpaddr
+ 4) - buildaddr
;
1493 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1495 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1496 "(offset 0x%x > 26-bit).", offset
);
1500 p
+= GEN_B (p
, offset
);
1501 write_inferior_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1502 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1504 /* The jump pad is now built. Wire in a jump to our jump pad. This
1505 is always done last (by our caller actually), so that we can
1506 install fast tracepoints with threads running. This relies on
1507 the agent's atomic write support. */
1508 offset
= entryaddr
- tpaddr
;
1509 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1511 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1512 "(offset 0x%x > 26-bit).", offset
);
1516 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1517 *jjump_pad_insn_size
= 4;
1522 /* Returns the minimum instruction length for installing a tracepoint. */
1525 ppc_get_min_fast_tracepoint_insn_len (void)
1530 /* Emits a given buffer into the target at current_insn_ptr. Length
1531 is in units of 32-bit words. */
1534 emit_insns (uint32_t *buf
, int n
)
1536 n
= n
* sizeof (uint32_t);
1537 write_inferior_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1538 current_insn_ptr
+= n
;
1541 #define __EMIT_ASM(NAME, INSNS) \
1544 extern uint32_t start_bcax_ ## NAME []; \
1545 extern uint32_t end_bcax_ ## NAME []; \
1546 emit_insns (start_bcax_ ## NAME, \
1547 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1548 __asm__ (".section .text.__ppcbcax\n\t" \
1549 "start_bcax_" #NAME ":\n\t" \
1551 "end_bcax_" #NAME ":\n\t" \
1555 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1556 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1560 Bytecode execution stack frame - 32-bit
1562 | LR save area (SP + 4)
1563 SP' -> +- Back chain (SP + 0)
1564 | Save r31 for access saved arguments
1565 | Save r30 for bytecode stack pointer
1566 | Save r4 for incoming argument *value
1567 | Save r3 for incoming argument regs
1568 r30 -> +- Bytecode execution stack
1570 | 64-byte (8 doublewords) at initial.
1571 | Expand stack as needed.
1574 | Some padding for minimum stack frame and 16-byte alignment.
1576 SP +- Back-chain (SP')
1582 r30 is the stack-pointer for bytecode machine.
1583 It should point to next-empty, so we can use LDU for pop.
1584 r3 is used for cache of the high part of TOP value.
1585 It was the first argument, pointer to regs.
1586 r4 is used for cache of the low part of TOP value.
1587 It was the second argument, pointer to the result.
1588 We should set *result = TOP after leaving this function.
1591 * To restore stack at epilogue
1593 * To check stack is big enough for bytecode execution.
1595 * To return execution result.
1600 /* Regardless of endian, register 3 is always high part, 4 is low part.
1601 These defines are used when the register pair is stored/loaded.
1602 Likewise, to simplify code, have a similiar define for 5:6. */
1604 #if __BYTE_ORDER == __LITTLE_ENDIAN
1605 #define TOP_FIRST "4"
1606 #define TOP_SECOND "3"
1607 #define TMP_FIRST "6"
1608 #define TMP_SECOND "5"
1610 #define TOP_FIRST "3"
1611 #define TOP_SECOND "4"
1612 #define TMP_FIRST "5"
1613 #define TMP_SECOND "6"
1616 /* Emit prologue in inferior memory. See above comments. */
1619 ppc_emit_prologue (void)
1621 EMIT_ASM (/* Save return address. */
1624 /* Adjust SP. 96 is the initial frame size. */
1626 /* Save r30 and incoming arguments. */
1627 "stw 31, 96-4(1) \n"
1628 "stw 30, 96-8(1) \n"
1629 "stw 4, 96-12(1) \n"
1630 "stw 3, 96-16(1) \n"
1631 /* Point r31 to original r1 for access arguments. */
1633 /* Set r30 to pointing stack-top. */
1635 /* Initial r3/TOP to 0. */
1640 /* Emit epilogue in inferior memory. See above comments. */
1643 ppc_emit_epilogue (void)
1645 EMIT_ASM (/* *result = TOP */
1647 "stw " TOP_FIRST
", 0(5) \n"
1648 "stw " TOP_SECOND
", 4(5) \n"
1649 /* Restore registers. */
1656 /* Return 0 for no-error. */
1662 /* TOP = stack[--sp] + TOP */
1667 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1668 "lwz " TMP_SECOND
", 4(30)\n"
1673 /* TOP = stack[--sp] - TOP */
1678 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1679 "lwz " TMP_SECOND
", 4(30) \n"
1681 "subfe 3, 3, 5 \n");
1684 /* TOP = stack[--sp] * TOP */
1689 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1690 "lwz " TMP_SECOND
", 4(30) \n"
1699 /* TOP = stack[--sp] << TOP */
1704 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1705 "lwz " TMP_SECOND
", 4(30) \n"
1706 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1707 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1708 "slw 5, 5, 4\n" /* Shift high part left */
1709 "slw 4, 6, 4\n" /* Shift low part left */
1710 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1711 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1713 "or 3, 7, 3\n"); /* Assemble high part */
1716 /* Top = stack[--sp] >> TOP
1717 (Arithmetic shift right) */
1720 ppc_emit_rsh_signed (void)
1722 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1723 "lwz " TMP_SECOND
", 4(30) \n"
1724 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1725 "sraw 3, 5, 4\n" /* Shift high part right */
1727 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1728 "sraw 4, 5, 7\n" /* Shift high to low */
1731 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1732 "srw 4, 6, 4\n" /* Shift low part right */
1733 "slw 5, 5, 7\n" /* Shift high to low */
1734 "or 4, 4, 5\n" /* Assemble low part */
1738 /* Top = stack[--sp] >> TOP
1739 (Logical shift right) */
1742 ppc_emit_rsh_unsigned (void)
1744 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1745 "lwz " TMP_SECOND
", 4(30) \n"
1746 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1747 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1748 "srw 6, 6, 4\n" /* Shift low part right */
1749 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1750 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1752 "srw 3, 5, 4\n" /* Shift high part right */
1753 "or 4, 6, 7\n"); /* Assemble low part */
1756 /* Emit code for signed-extension specified by ARG. */
1759 ppc_emit_ext (int arg
)
1764 EMIT_ASM ("extsb 4, 4\n"
1768 EMIT_ASM ("extsh 4, 4\n"
1772 EMIT_ASM ("srawi 3, 4, 31");
1779 /* Emit code for zero-extension specified by ARG. */
1782 ppc_emit_zero_ext (int arg
)
1787 EMIT_ASM ("clrlwi 4,4,24\n"
1791 EMIT_ASM ("clrlwi 4,4,16\n"
1795 EMIT_ASM ("li 3, 0");
1803 i.e., TOP = (TOP == 0) ? 1 : 0; */
1806 ppc_emit_log_not (void)
1808 EMIT_ASM ("or 4, 3, 4 \n"
1814 /* TOP = stack[--sp] & TOP */
1817 ppc_emit_bit_and (void)
1819 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1820 "lwz " TMP_SECOND
", 4(30) \n"
1825 /* TOP = stack[--sp] | TOP */
1828 ppc_emit_bit_or (void)
1830 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1831 "lwz " TMP_SECOND
", 4(30) \n"
1836 /* TOP = stack[--sp] ^ TOP */
1839 ppc_emit_bit_xor (void)
1841 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1842 "lwz " TMP_SECOND
", 4(30) \n"
1848 i.e., TOP = ~(TOP | TOP) */
1851 ppc_emit_bit_not (void)
1853 EMIT_ASM ("nor 3, 3, 3 \n"
1857 /* TOP = stack[--sp] == TOP */
1860 ppc_emit_equal (void)
1862 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1863 "lwz " TMP_SECOND
", 4(30) \n"
1872 /* TOP = stack[--sp] < TOP
1873 (Signed comparison) */
1876 ppc_emit_less_signed (void)
1878 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1879 "lwz " TMP_SECOND
", 4(30) \n"
1882 /* CR6 bit 0 = low less and high equal */
1883 "crand 6*4+0, 6*4+0, 7*4+2\n"
1884 /* CR7 bit 0 = (low less and high equal) or high less */
1885 "cror 7*4+0, 7*4+0, 6*4+0\n"
1887 "rlwinm 4, 4, 29, 31, 31 \n"
1891 /* TOP = stack[--sp] < TOP
1892 (Unsigned comparison) */
1895 ppc_emit_less_unsigned (void)
1897 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1898 "lwz " TMP_SECOND
", 4(30) \n"
1901 /* CR6 bit 0 = low less and high equal */
1902 "crand 6*4+0, 6*4+0, 7*4+2\n"
1903 /* CR7 bit 0 = (low less and high equal) or high less */
1904 "cror 7*4+0, 7*4+0, 6*4+0\n"
1906 "rlwinm 4, 4, 29, 31, 31 \n"
1910 /* Access the memory address in TOP in size of SIZE.
1911 Zero-extend the read value. */
1914 ppc_emit_ref (int size
)
1919 EMIT_ASM ("lbz 4, 0(4)\n"
1923 EMIT_ASM ("lhz 4, 0(4)\n"
1927 EMIT_ASM ("lwz 4, 0(4)\n"
1931 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1932 EMIT_ASM ("lwz 3, 4(4)\n"
1935 EMIT_ASM ("lwz 3, 0(4)\n"
1944 ppc_emit_const (LONGEST num
)
1949 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
1950 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
1952 emit_insns (buf
, p
- buf
);
1953 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1956 /* Set TOP to the value of register REG by calling get_raw_reg function
1957 with two argument, collected buffer and register number. */
1960 ppc_emit_reg (int reg
)
1965 /* fctx->regs is passed in r3 and then saved in -16(31). */
1966 p
+= GEN_LWZ (p
, 3, 31, -16);
1967 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
1968 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
1970 emit_insns (buf
, p
- buf
);
1971 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
1973 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
1975 EMIT_ASM ("mr 5, 4\n"
1981 /* TOP = stack[--sp] */
1986 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
1987 "lwz " TOP_SECOND
", 4(30) \n");
1990 /* stack[sp++] = TOP
1992 Because we may use up bytecode stack, expand 8 doublewords more
1996 ppc_emit_stack_flush (void)
1998 /* Make sure bytecode stack is big enough before push.
1999 Otherwise, expand 64-byte more. */
2001 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2002 " stw " TOP_SECOND
", 4(30)\n"
2003 " addi 5, 30, -(8 + 8) \n"
2006 " stwu 31, -64(1) \n"
2007 "1:addi 30, 30, -8 \n");
2010 /* Swap TOP and stack[sp-1] */
2013 ppc_emit_swap (void)
2015 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2016 "lwz " TMP_SECOND
", 12(30) \n"
2017 "stw " TOP_FIRST
", 8(30) \n"
2018 "stw " TOP_SECOND
", 12(30) \n"
2023 /* Discard N elements in the stack. Also used for ppc64. */
2026 ppc_emit_stack_adjust (int n
)
2038 p
+= GEN_ADDI (p
, 30, 30, n
);
2040 emit_insns (buf
, p
- buf
);
2041 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2044 /* Call function FN. */
2047 ppc_emit_call (CORE_ADDR fn
)
2052 p
+= gen_call (p
, fn
, 0, 0);
2054 emit_insns (buf
, p
- buf
);
2055 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2058 /* FN's prototype is `LONGEST(*fn)(int)'.
2063 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2068 /* Setup argument. arg1 is a 16-bit value. */
2069 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2070 p
+= gen_call (p
, fn
, 0, 0);
2072 emit_insns (buf
, p
- buf
);
2073 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2075 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2077 EMIT_ASM ("mr 5, 4\n"
2083 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2086 TOP should be preserved/restored before/after the call. */
2089 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2094 /* Save TOP. 0(30) is next-empty. */
2095 p
+= GEN_STW (p
, 3, 30, 0);
2096 p
+= GEN_STW (p
, 4, 30, 4);
2098 /* Setup argument. arg1 is a 16-bit value. */
2099 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2101 p
+= GEN_MR (p
, 5, 4);
2102 p
+= GEN_MR (p
, 6, 3);
2106 p
+= GEN_MR (p
, 5, 3);
2107 p
+= GEN_MR (p
, 6, 4);
2109 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2110 p
+= gen_call (p
, fn
, 0, 0);
2113 p
+= GEN_LWZ (p
, 3, 30, 0);
2114 p
+= GEN_LWZ (p
, 4, 30, 4);
2116 emit_insns (buf
, p
- buf
);
2117 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2120 /* Note in the following goto ops:
2122 When emitting goto, the target address is later relocated by
2123 write_goto_address. OFFSET_P is the offset of the branch instruction
2124 in the code sequence, and SIZE_P is how to relocate the instruction,
2125 recognized by ppc_write_goto_address. In current implementation,
2126 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2129 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2132 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2134 EMIT_ASM ("or. 3, 3, 4 \n"
2135 "lwzu " TOP_FIRST
", 8(30) \n"
2136 "lwz " TOP_SECOND
", 4(30) \n"
2145 /* Unconditional goto. Also used for ppc64. */
2148 ppc_emit_goto (int *offset_p
, int *size_p
)
2150 EMIT_ASM ("1:b 1b");
2158 /* Goto if stack[--sp] == TOP */
2161 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2163 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2164 "lwz " TMP_SECOND
", 4(30) \n"
2168 "lwzu " TOP_FIRST
", 8(30) \n"
2169 "lwz " TOP_SECOND
", 4(30) \n"
2178 /* Goto if stack[--sp] != TOP */
2181 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2183 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2184 "lwz " TMP_SECOND
", 4(30) \n"
2188 "lwzu " TOP_FIRST
", 8(30) \n"
2189 "lwz " TOP_SECOND
", 4(30) \n"
2198 /* Goto if stack[--sp] < TOP */
2201 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2203 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2204 "lwz " TMP_SECOND
", 4(30) \n"
2207 /* CR6 bit 0 = low less and high equal */
2208 "crand 6*4+0, 6*4+0, 7*4+2\n"
2209 /* CR7 bit 0 = (low less and high equal) or high less */
2210 "cror 7*4+0, 7*4+0, 6*4+0\n"
2211 "lwzu " TOP_FIRST
", 8(30) \n"
2212 "lwz " TOP_SECOND
", 4(30)\n"
2221 /* Goto if stack[--sp] <= TOP */
2224 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2226 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2227 "lwz " TMP_SECOND
", 4(30) \n"
2230 /* CR6 bit 0 = low less/equal and high equal */
2231 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2232 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2233 "cror 7*4+0, 7*4+0, 6*4+0\n"
2234 "lwzu " TOP_FIRST
", 8(30) \n"
2235 "lwz " TOP_SECOND
", 4(30)\n"
2244 /* Goto if stack[--sp] > TOP */
2247 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2249 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2250 "lwz " TMP_SECOND
", 4(30) \n"
2253 /* CR6 bit 0 = low greater and high equal */
2254 "crand 6*4+0, 6*4+1, 7*4+2\n"
2255 /* CR7 bit 0 = (low greater and high equal) or high greater */
2256 "cror 7*4+0, 7*4+1, 6*4+0\n"
2257 "lwzu " TOP_FIRST
", 8(30) \n"
2258 "lwz " TOP_SECOND
", 4(30)\n"
2267 /* Goto if stack[--sp] >= TOP */
2270 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2272 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2273 "lwz " TMP_SECOND
", 4(30) \n"
2276 /* CR6 bit 0 = low ge and high equal */
2277 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2278 /* CR7 bit 0 = (low ge and high equal) or high greater */
2279 "cror 7*4+0, 7*4+1, 6*4+0\n"
2280 "lwzu " TOP_FIRST
", 8(30)\n"
2281 "lwz " TOP_SECOND
", 4(30)\n"
2290 /* Relocate previous emitted branch instruction. FROM is the address
2291 of the branch instruction, TO is the goto target address, and SIZE
2292 if the value we set by *SIZE_P before. Currently, it is either
2293 24 or 14 of branch and conditional-branch instruction.
2294 Also used for ppc64. */
2297 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2299 long rel
= to
- from
;
2303 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2304 opcd
= (insn
>> 26) & 0x3f;
2310 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2312 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2316 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2318 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2325 write_inferior_memory (from
, (unsigned char *) &insn
, 4);
2328 /* Table of emit ops for 32-bit. */
2330 static struct emit_ops ppc_emit_ops_impl
=
2338 ppc_emit_rsh_signed
,
2339 ppc_emit_rsh_unsigned
,
2347 ppc_emit_less_signed
,
2348 ppc_emit_less_unsigned
,
2352 ppc_write_goto_address
,
2357 ppc_emit_stack_flush
,
2360 ppc_emit_stack_adjust
,
2361 ppc_emit_int_call_1
,
2362 ppc_emit_void_call_2
,
2371 #ifdef __powerpc64__
2375 Bytecode execution stack frame - 64-bit
2377 | LR save area (SP + 16)
2378 | CR save area (SP + 8)
2379 SP' -> +- Back chain (SP + 0)
2380 | Save r31 for access saved arguments
2381 | Save r30 for bytecode stack pointer
2382 | Save r4 for incoming argument *value
2383 | Save r3 for incoming argument regs
2384 r30 -> +- Bytecode execution stack
2386 | 64-byte (8 doublewords) at initial.
2387 | Expand stack as needed.
2390 | Some padding for minimum stack frame.
2392 SP +- Back-chain (SP')
2395 = 112 + (4 * 8) + 64
2398 r30 is the stack-pointer for bytecode machine.
2399 It should point to next-empty, so we can use LDU for pop.
2400 r3 is used for cache of TOP value.
2401 It was the first argument, pointer to regs.
2402 r4 is the second argument, pointer to the result.
2403 We should set *result = TOP after leaving this function.
2406 * To restore stack at epilogue
2408 * To check stack is big enough for bytecode execution.
2409 => r30 - 8 > SP + 112
2410 * To return execution result.
2415 /* Emit prologue in inferior memory. See above comments. */
2418 ppc64v1_emit_prologue (void)
2420 /* On ELFv1, function pointers really point to function descriptor,
2421 so emit one here. We don't care about contents of words 1 and 2,
2422 so let them just overlap out code. */
2423 uint64_t opd
= current_insn_ptr
+ 8;
2426 /* Mind the strict aliasing rules. */
2427 memcpy (buf
, &opd
, sizeof buf
);
2429 EMIT_ASM (/* Save return address. */
2432 /* Save r30 and incoming arguments. */
2437 /* Point r31 to current r1 for access arguments. */
2439 /* Adjust SP. 208 is the initial frame size. */
2440 "stdu 1, -208(1) \n"
2441 /* Set r30 to pointing stack-top. */
2442 "addi 30, 1, 168 \n"
2443 /* Initial r3/TOP to 0. */
2447 /* Emit prologue in inferior memory. See above comments. */
2450 ppc64v2_emit_prologue (void)
2452 EMIT_ASM (/* Save return address. */
2455 /* Save r30 and incoming arguments. */
2460 /* Point r31 to current r1 for access arguments. */
2462 /* Adjust SP. 208 is the initial frame size. */
2463 "stdu 1, -208(1) \n"
2464 /* Set r30 to pointing stack-top. */
2465 "addi 30, 1, 168 \n"
2466 /* Initial r3/TOP to 0. */
2470 /* Emit epilogue in inferior memory. See above comments. */
2473 ppc64_emit_epilogue (void)
2475 EMIT_ASM (/* Restore SP. */
2480 /* Restore registers. */
2485 /* Return 0 for no-error. */
2491 /* TOP = stack[--sp] + TOP */
2494 ppc64_emit_add (void)
2496 EMIT_ASM ("ldu 4, 8(30) \n"
2500 /* TOP = stack[--sp] - TOP */
2503 ppc64_emit_sub (void)
2505 EMIT_ASM ("ldu 4, 8(30) \n"
2509 /* TOP = stack[--sp] * TOP */
2512 ppc64_emit_mul (void)
2514 EMIT_ASM ("ldu 4, 8(30) \n"
2515 "mulld 3, 4, 3 \n");
2518 /* TOP = stack[--sp] << TOP */
2521 ppc64_emit_lsh (void)
2523 EMIT_ASM ("ldu 4, 8(30) \n"
2527 /* Top = stack[--sp] >> TOP
2528 (Arithmetic shift right) */
2531 ppc64_emit_rsh_signed (void)
2533 EMIT_ASM ("ldu 4, 8(30) \n"
2537 /* Top = stack[--sp] >> TOP
2538 (Logical shift right) */
2541 ppc64_emit_rsh_unsigned (void)
2543 EMIT_ASM ("ldu 4, 8(30) \n"
2547 /* Emit code for signed-extension specified by ARG. */
2550 ppc64_emit_ext (int arg
)
2555 EMIT_ASM ("extsb 3, 3");
2558 EMIT_ASM ("extsh 3, 3");
2561 EMIT_ASM ("extsw 3, 3");
2568 /* Emit code for zero-extension specified by ARG. */
2571 ppc64_emit_zero_ext (int arg
)
2576 EMIT_ASM ("rldicl 3,3,0,56");
2579 EMIT_ASM ("rldicl 3,3,0,48");
2582 EMIT_ASM ("rldicl 3,3,0,32");
2590 i.e., TOP = (TOP == 0) ? 1 : 0; */
2593 ppc64_emit_log_not (void)
2595 EMIT_ASM ("cntlzd 3, 3 \n"
2599 /* TOP = stack[--sp] & TOP */
2602 ppc64_emit_bit_and (void)
2604 EMIT_ASM ("ldu 4, 8(30) \n"
2608 /* TOP = stack[--sp] | TOP */
2611 ppc64_emit_bit_or (void)
2613 EMIT_ASM ("ldu 4, 8(30) \n"
2617 /* TOP = stack[--sp] ^ TOP */
2620 ppc64_emit_bit_xor (void)
2622 EMIT_ASM ("ldu 4, 8(30) \n"
2627 i.e., TOP = ~(TOP | TOP) */
2630 ppc64_emit_bit_not (void)
2632 EMIT_ASM ("nor 3, 3, 3 \n");
2635 /* TOP = stack[--sp] == TOP */
2638 ppc64_emit_equal (void)
2640 EMIT_ASM ("ldu 4, 8(30) \n"
2646 /* TOP = stack[--sp] < TOP
2647 (Signed comparison) */
2650 ppc64_emit_less_signed (void)
2652 EMIT_ASM ("ldu 4, 8(30) \n"
2655 "rlwinm 3, 3, 29, 31, 31 \n");
2658 /* TOP = stack[--sp] < TOP
2659 (Unsigned comparison) */
2662 ppc64_emit_less_unsigned (void)
2664 EMIT_ASM ("ldu 4, 8(30) \n"
2667 "rlwinm 3, 3, 29, 31, 31 \n");
2670 /* Access the memory address in TOP in size of SIZE.
2671 Zero-extend the read value. */
2674 ppc64_emit_ref (int size
)
2679 EMIT_ASM ("lbz 3, 0(3)");
2682 EMIT_ASM ("lhz 3, 0(3)");
2685 EMIT_ASM ("lwz 3, 0(3)");
2688 EMIT_ASM ("ld 3, 0(3)");
2696 ppc64_emit_const (LONGEST num
)
2701 p
+= gen_limm (p
, 3, num
, 1);
2703 emit_insns (buf
, p
- buf
);
2704 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2707 /* Set TOP to the value of register REG by calling get_raw_reg function
2708 with two argument, collected buffer and register number. */
2711 ppc64v1_emit_reg (int reg
)
2716 /* fctx->regs is passed in r3 and then saved in 176(1). */
2717 p
+= GEN_LD (p
, 3, 31, -32);
2718 p
+= GEN_LI (p
, 4, reg
);
2719 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2720 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2721 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2723 emit_insns (buf
, p
- buf
);
2724 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2727 /* Likewise, for ELFv2. */
2730 ppc64v2_emit_reg (int reg
)
2735 /* fctx->regs is passed in r3 and then saved in 176(1). */
2736 p
+= GEN_LD (p
, 3, 31, -32);
2737 p
+= GEN_LI (p
, 4, reg
);
2738 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2739 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2740 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2742 emit_insns (buf
, p
- buf
);
2743 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2746 /* TOP = stack[--sp] */
2749 ppc64_emit_pop (void)
2751 EMIT_ASM ("ldu 3, 8(30)");
2754 /* stack[sp++] = TOP
2756 Because we may use up bytecode stack, expand 8 doublewords more
2760 ppc64_emit_stack_flush (void)
2762 /* Make sure bytecode stack is big enough before push.
2763 Otherwise, expand 64-byte more. */
2765 EMIT_ASM (" std 3, 0(30) \n"
2766 " addi 4, 30, -(112 + 8) \n"
2769 " stdu 31, -64(1) \n"
2770 "1:addi 30, 30, -8 \n");
2773 /* Swap TOP and stack[sp-1] */
2776 ppc64_emit_swap (void)
2778 EMIT_ASM ("ld 4, 8(30) \n"
2783 /* Call function FN - ELFv1. */
2786 ppc64v1_emit_call (CORE_ADDR fn
)
2791 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2792 p
+= gen_call (p
, fn
, 1, 1);
2793 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2795 emit_insns (buf
, p
- buf
);
2796 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2799 /* Call function FN - ELFv2. */
2802 ppc64v2_emit_call (CORE_ADDR fn
)
2807 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2808 p
+= gen_call (p
, fn
, 1, 0);
2809 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2811 emit_insns (buf
, p
- buf
);
2812 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2815 /* FN's prototype is `LONGEST(*fn)(int)'.
2820 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2825 /* Setup argument. arg1 is a 16-bit value. */
2826 p
+= gen_limm (p
, 3, arg1
, 1);
2827 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2828 p
+= gen_call (p
, fn
, 1, 1);
2829 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2831 emit_insns (buf
, p
- buf
);
2832 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2835 /* Likewise for ELFv2. */
2838 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2843 /* Setup argument. arg1 is a 16-bit value. */
2844 p
+= gen_limm (p
, 3, arg1
, 1);
2845 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2846 p
+= gen_call (p
, fn
, 1, 0);
2847 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2849 emit_insns (buf
, p
- buf
);
2850 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2853 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2856 TOP should be preserved/restored before/after the call. */
2859 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2864 /* Save TOP. 0(30) is next-empty. */
2865 p
+= GEN_STD (p
, 3, 30, 0);
2867 /* Setup argument. arg1 is a 16-bit value. */
2868 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2869 p
+= gen_limm (p
, 3, arg1
, 1);
2870 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2871 p
+= gen_call (p
, fn
, 1, 1);
2872 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2875 p
+= GEN_LD (p
, 3, 30, 0);
2877 emit_insns (buf
, p
- buf
);
2878 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2881 /* Likewise for ELFv2. */
2884 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2889 /* Save TOP. 0(30) is next-empty. */
2890 p
+= GEN_STD (p
, 3, 30, 0);
2892 /* Setup argument. arg1 is a 16-bit value. */
2893 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
2894 p
+= gen_limm (p
, 3, arg1
, 1);
2895 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2896 p
+= gen_call (p
, fn
, 1, 0);
2897 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2900 p
+= GEN_LD (p
, 3, 30, 0);
2902 emit_insns (buf
, p
- buf
);
2903 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2906 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2909 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
2911 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2921 /* Goto if stack[--sp] == TOP */
2924 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
2926 EMIT_ASM ("ldu 4, 8(30) \n"
2937 /* Goto if stack[--sp] != TOP */
2940 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
2942 EMIT_ASM ("ldu 4, 8(30) \n"
2953 /* Goto if stack[--sp] < TOP */
2956 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
2958 EMIT_ASM ("ldu 4, 8(30) \n"
2969 /* Goto if stack[--sp] <= TOP */
2972 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
2974 EMIT_ASM ("ldu 4, 8(30) \n"
2985 /* Goto if stack[--sp] > TOP */
2988 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
2990 EMIT_ASM ("ldu 4, 8(30) \n"
3001 /* Goto if stack[--sp] >= TOP */
3004 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3006 EMIT_ASM ("ldu 4, 8(30) \n"
3017 /* Table of emit ops for 64-bit ELFv1. */
3019 static struct emit_ops ppc64v1_emit_ops_impl
=
3021 ppc64v1_emit_prologue
,
3022 ppc64_emit_epilogue
,
3027 ppc64_emit_rsh_signed
,
3028 ppc64_emit_rsh_unsigned
,
3036 ppc64_emit_less_signed
,
3037 ppc64_emit_less_unsigned
,
3041 ppc_write_goto_address
,
3046 ppc64_emit_stack_flush
,
3047 ppc64_emit_zero_ext
,
3049 ppc_emit_stack_adjust
,
3050 ppc64v1_emit_int_call_1
,
3051 ppc64v1_emit_void_call_2
,
3060 /* Table of emit ops for 64-bit ELFv2. */
3062 static struct emit_ops ppc64v2_emit_ops_impl
=
3064 ppc64v2_emit_prologue
,
3065 ppc64_emit_epilogue
,
3070 ppc64_emit_rsh_signed
,
3071 ppc64_emit_rsh_unsigned
,
3079 ppc64_emit_less_signed
,
3080 ppc64_emit_less_unsigned
,
3084 ppc_write_goto_address
,
3089 ppc64_emit_stack_flush
,
3090 ppc64_emit_zero_ext
,
3092 ppc_emit_stack_adjust
,
3093 ppc64v2_emit_int_call_1
,
3094 ppc64v2_emit_void_call_2
,
3105 /* Implementation of linux_target_ops method "emit_ops". */
3107 static struct emit_ops
*
3110 #ifdef __powerpc64__
3111 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3113 if (register_size (regcache
->tdesc
, 0) == 8)
3115 if (is_elfv2_inferior ())
3116 return &ppc64v2_emit_ops_impl
;
3118 return &ppc64v1_emit_ops_impl
;
3121 return &ppc_emit_ops_impl
;
3124 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3127 ppc_get_ipa_tdesc_idx (void)
3129 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3130 const struct target_desc
*tdesc
= regcache
->tdesc
;
3132 #ifdef __powerpc64__
3133 if (tdesc
== tdesc_powerpc_64l
)
3134 return PPC_TDESC_BASE
;
3135 if (tdesc
== tdesc_powerpc_altivec64l
)
3136 return PPC_TDESC_ALTIVEC
;
3137 if (tdesc
== tdesc_powerpc_cell64l
)
3138 return PPC_TDESC_CELL
;
3139 if (tdesc
== tdesc_powerpc_vsx64l
)
3140 return PPC_TDESC_VSX
;
3141 if (tdesc
== tdesc_powerpc_isa205_64l
)
3142 return PPC_TDESC_ISA205
;
3143 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3144 return PPC_TDESC_ISA205_ALTIVEC
;
3145 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3146 return PPC_TDESC_ISA205_VSX
;
3147 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3148 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3151 if (tdesc
== tdesc_powerpc_32l
)
3152 return PPC_TDESC_BASE
;
3153 if (tdesc
== tdesc_powerpc_altivec32l
)
3154 return PPC_TDESC_ALTIVEC
;
3155 if (tdesc
== tdesc_powerpc_cell32l
)
3156 return PPC_TDESC_CELL
;
3157 if (tdesc
== tdesc_powerpc_vsx32l
)
3158 return PPC_TDESC_VSX
;
3159 if (tdesc
== tdesc_powerpc_isa205_32l
)
3160 return PPC_TDESC_ISA205
;
3161 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3162 return PPC_TDESC_ISA205_ALTIVEC
;
3163 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3164 return PPC_TDESC_ISA205_VSX
;
3165 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3166 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3167 if (tdesc
== tdesc_powerpc_e500l
)
3168 return PPC_TDESC_E500
;
3173 struct linux_target_ops the_low_target
= {
3176 ppc_cannot_fetch_register
,
3177 ppc_cannot_store_register
,
3178 NULL
, /* fetch_register */
3181 NULL
, /* breakpoint_kind_from_pc */
3182 ppc_sw_breakpoint_from_kind
,
3186 ppc_supports_z_point_type
,
3191 ppc_collect_ptrace_register
,
3192 ppc_supply_ptrace_register
,
3193 NULL
, /* siginfo_fixup */
3194 NULL
, /* new_process */
3195 NULL
, /* delete_process */
3196 NULL
, /* new_thread */
3197 NULL
, /* delete_thread */
3198 NULL
, /* new_fork */
3199 NULL
, /* prepare_to_resume */
3200 NULL
, /* process_qsupported */
3201 ppc_supports_tracepoints
,
3202 ppc_get_thread_area
,
3203 ppc_install_fast_tracepoint_jump_pad
,
3205 ppc_get_min_fast_tracepoint_insn_len
,
3206 NULL
, /* supports_range_stepping */
3207 NULL
, /* breakpoint_kind_from_current_state */
3208 ppc_supports_hardware_single_step
,
3209 NULL
, /* get_syscall_trapinfo */
3210 ppc_get_ipa_tdesc_idx
,
3214 initialize_low_arch (void)
3216 /* Initialize the Linux target descriptions. */
3218 init_registers_powerpc_32l ();
3219 init_registers_powerpc_altivec32l ();
3220 init_registers_powerpc_cell32l ();
3221 init_registers_powerpc_vsx32l ();
3222 init_registers_powerpc_isa205_32l ();
3223 init_registers_powerpc_isa205_altivec32l ();
3224 init_registers_powerpc_isa205_vsx32l ();
3225 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3226 init_registers_powerpc_e500l ();
3228 init_registers_powerpc_64l ();
3229 init_registers_powerpc_altivec64l ();
3230 init_registers_powerpc_cell64l ();
3231 init_registers_powerpc_vsx64l ();
3232 init_registers_powerpc_isa205_64l ();
3233 init_registers_powerpc_isa205_altivec64l ();
3234 init_registers_powerpc_isa205_vsx64l ();
3235 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3238 initialize_regsets_info (&ppc_regsets_info
);