gdb/gdbserver/linux-ppc-low.c

   1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
   2    GDB.
   3    Copyright (C) 1995-2014 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "server.h"
  21 #include "linux-low.h"
  22
  23 #include <elf.h>
  24 #include <asm/ptrace.h>
  25
  26 /* These are in <asm/cputable.h> in current kernels.  */
  27 #define PPC_FEATURE_HAS_VSX             0x00000080
  28 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
  29 #define PPC_FEATURE_HAS_SPE             0x00800000
  30 #define PPC_FEATURE_CELL                0x00010000
  31 #define PPC_FEATURE_HAS_DFP             0x00000400
  32
  33 static unsigned long ppc_hwcap;
  34
  35
  36 /* Defined in auto-generated file powerpc-32l.c.  */
  37 void init_registers_powerpc_32l (void);
  38 extern const struct target_desc *tdesc_powerpc_32l;
  39
  40 /* Defined in auto-generated file powerpc-altivec32l.c.  */
  41 void init_registers_powerpc_altivec32l (void);
  42 extern const struct target_desc *tdesc_powerpc_altivec32l;
  43
  44 /* Defined in auto-generated file powerpc-cell32l.c.  */
  45 void init_registers_powerpc_cell32l (void);
  46 extern const struct target_desc *tdesc_powerpc_cell32l;
  47
  48 /* Defined in auto-generated file powerpc-vsx32l.c.  */
  49 void init_registers_powerpc_vsx32l (void);
  50 extern const struct target_desc *tdesc_powerpc_vsx32l;
  51
  52 /* Defined in auto-generated file powerpc-isa205-32l.c.  */
  53 void init_registers_powerpc_isa205_32l (void);
  54 extern const struct target_desc *tdesc_powerpc_isa205_32l;
  55
  56 /* Defined in auto-generated file powerpc-isa205-altivec32l.c.  */
  57 void init_registers_powerpc_isa205_altivec32l (void);
  58 extern const struct target_desc *tdesc_powerpc_isa205_altivec32l;
  59
  60 /* Defined in auto-generated file powerpc-isa205-vsx32l.c.  */
  61 void init_registers_powerpc_isa205_vsx32l (void);
  62 extern const struct target_desc *tdesc_powerpc_isa205_vsx32l;
  63
  64 /* Defined in auto-generated file powerpc-e500l.c.  */
  65 void init_registers_powerpc_e500l (void);
  66 extern const struct target_desc *tdesc_powerpc_e500l;
  67
  68 /* Defined in auto-generated file powerpc-64l.c.  */
  69 void init_registers_powerpc_64l (void);
  70 extern const struct target_desc *tdesc_powerpc_64l;
  71
  72 /* Defined in auto-generated file powerpc-altivec64l.c.  */
  73 void init_registers_powerpc_altivec64l (void);
  74 extern const struct target_desc *tdesc_powerpc_altivec64l;
  75
  76 /* Defined in auto-generated file powerpc-cell64l.c.  */
  77 void init_registers_powerpc_cell64l (void);
  78 extern const struct target_desc *tdesc_powerpc_cell64l;
  79
  80 /* Defined in auto-generated file powerpc-vsx64l.c.  */
  81 void init_registers_powerpc_vsx64l (void);
  82 extern const struct target_desc *tdesc_powerpc_vsx64l;
  83
  84 /* Defined in auto-generated file powerpc-isa205-64l.c.  */
  85 void init_registers_powerpc_isa205_64l (void);
  86 extern const struct target_desc *tdesc_powerpc_isa205_64l;
  87
  88 /* Defined in auto-generated file powerpc-isa205-altivec64l.c.  */
  89 void init_registers_powerpc_isa205_altivec64l (void);
  90 extern const struct target_desc *tdesc_powerpc_isa205_altivec64l;
  91
  92 /* Defined in auto-generated file powerpc-isa205-vsx64l.c.  */
  93 void init_registers_powerpc_isa205_vsx64l (void);
  94 extern const struct target_desc *tdesc_powerpc_isa205_vsx64l;
  95
  96 #define ppc_num_regs 73
  97
  98 /* This sometimes isn't defined.  */
  99 #ifndef PT_ORIG_R3
 100 #define PT_ORIG_R3 34
 101 #endif
 102 #ifndef PT_TRAP
 103 #define PT_TRAP 40
 104 #endif
 105
 106 #ifdef __powerpc64__
 107 /* We use a constant for FPSCR instead of PT_FPSCR, because
 108    many shipped PPC64 kernels had the wrong value in ptrace.h.  */
 109 static int ppc_regmap[] =
 110  {PT_R0 * 8,     PT_R1 * 8,     PT_R2 * 8,     PT_R3 * 8,
 111   PT_R4 * 8,     PT_R5 * 8,     PT_R6 * 8,     PT_R7 * 8,
 112   PT_R8 * 8,     PT_R9 * 8,     PT_R10 * 8,    PT_R11 * 8,
 113   PT_R12 * 8,    PT_R13 * 8,    PT_R14 * 8,    PT_R15 * 8,
 114   PT_R16 * 8,    PT_R17 * 8,    PT_R18 * 8,    PT_R19 * 8,
 115   PT_R20 * 8,    PT_R21 * 8,    PT_R22 * 8,    PT_R23 * 8,
 116   PT_R24 * 8,    PT_R25 * 8,    PT_R26 * 8,    PT_R27 * 8,
 117   PT_R28 * 8,    PT_R29 * 8,    PT_R30 * 8,    PT_R31 * 8,
 118   PT_FPR0*8,     PT_FPR0*8 + 8, PT_FPR0*8+16,  PT_FPR0*8+24,
 119   PT_FPR0*8+32,  PT_FPR0*8+40,  PT_FPR0*8+48,  PT_FPR0*8+56,
 120   PT_FPR0*8+64,  PT_FPR0*8+72,  PT_FPR0*8+80,  PT_FPR0*8+88,
 121   PT_FPR0*8+96,  PT_FPR0*8+104,  PT_FPR0*8+112,  PT_FPR0*8+120,
 122   PT_FPR0*8+128, PT_FPR0*8+136,  PT_FPR0*8+144,  PT_FPR0*8+152,
 123   PT_FPR0*8+160,  PT_FPR0*8+168,  PT_FPR0*8+176,  PT_FPR0*8+184,
 124   PT_FPR0*8+192,  PT_FPR0*8+200,  PT_FPR0*8+208,  PT_FPR0*8+216,
 125   PT_FPR0*8+224,  PT_FPR0*8+232,  PT_FPR0*8+240,  PT_FPR0*8+248,
 126   PT_NIP * 8,    PT_MSR * 8,    PT_CCR * 8,    PT_LNK * 8,
 127   PT_CTR * 8,    PT_XER * 8,    PT_FPR0*8 + 256,
 128   PT_ORIG_R3 * 8, PT_TRAP * 8 };
 129 #else
 130 /* Currently, don't check/send MQ.  */
 131 static int ppc_regmap[] =
 132  {PT_R0 * 4,     PT_R1 * 4,     PT_R2 * 4,     PT_R3 * 4,
 133   PT_R4 * 4,     PT_R5 * 4,     PT_R6 * 4,     PT_R7 * 4,
 134   PT_R8 * 4,     PT_R9 * 4,     PT_R10 * 4,    PT_R11 * 4,
 135   PT_R12 * 4,    PT_R13 * 4,    PT_R14 * 4,    PT_R15 * 4,
 136   PT_R16 * 4,    PT_R17 * 4,    PT_R18 * 4,    PT_R19 * 4,
 137   PT_R20 * 4,    PT_R21 * 4,    PT_R22 * 4,    PT_R23 * 4,
 138   PT_R24 * 4,    PT_R25 * 4,    PT_R26 * 4,    PT_R27 * 4,
 139   PT_R28 * 4,    PT_R29 * 4,    PT_R30 * 4,    PT_R31 * 4,
 140   PT_FPR0*4,     PT_FPR0*4 + 8, PT_FPR0*4+16,  PT_FPR0*4+24,
 141   PT_FPR0*4+32,  PT_FPR0*4+40,  PT_FPR0*4+48,  PT_FPR0*4+56,
 142   PT_FPR0*4+64,  PT_FPR0*4+72,  PT_FPR0*4+80,  PT_FPR0*4+88,
 143   PT_FPR0*4+96,  PT_FPR0*4+104,  PT_FPR0*4+112,  PT_FPR0*4+120,
 144   PT_FPR0*4+128, PT_FPR0*4+136,  PT_FPR0*4+144,  PT_FPR0*4+152,
 145   PT_FPR0*4+160,  PT_FPR0*4+168,  PT_FPR0*4+176,  PT_FPR0*4+184,
 146   PT_FPR0*4+192,  PT_FPR0*4+200,  PT_FPR0*4+208,  PT_FPR0*4+216,
 147   PT_FPR0*4+224,  PT_FPR0*4+232,  PT_FPR0*4+240,  PT_FPR0*4+248,
 148   PT_NIP * 4,    PT_MSR * 4,    PT_CCR * 4,    PT_LNK * 4,
 149   PT_CTR * 4,    PT_XER * 4,    PT_FPSCR * 4,
 150   PT_ORIG_R3 * 4, PT_TRAP * 4
 151  };
 152
 153 static int ppc_regmap_e500[] =
 154  {PT_R0 * 4,     PT_R1 * 4,     PT_R2 * 4,     PT_R3 * 4,
 155   PT_R4 * 4,     PT_R5 * 4,     PT_R6 * 4,     PT_R7 * 4,
 156   PT_R8 * 4,     PT_R9 * 4,     PT_R10 * 4,    PT_R11 * 4,
 157   PT_R12 * 4,    PT_R13 * 4,    PT_R14 * 4,    PT_R15 * 4,
 158   PT_R16 * 4,    PT_R17 * 4,    PT_R18 * 4,    PT_R19 * 4,
 159   PT_R20 * 4,    PT_R21 * 4,    PT_R22 * 4,    PT_R23 * 4,
 160   PT_R24 * 4,    PT_R25 * 4,    PT_R26 * 4,    PT_R27 * 4,
 161   PT_R28 * 4,    PT_R29 * 4,    PT_R30 * 4,    PT_R31 * 4,
 162   -1,            -1,            -1,            -1,
 163   -1,            -1,            -1,            -1,
 164   -1,            -1,            -1,            -1,
 165   -1,            -1,            -1,            -1,
 166   -1,            -1,            -1,            -1,
 167   -1,            -1,            -1,            -1,
 168   -1,            -1,            -1,            -1,
 169   -1,            -1,            -1,            -1,
 170   PT_NIP * 4,    PT_MSR * 4,    PT_CCR * 4,    PT_LNK * 4,
 171   PT_CTR * 4,    PT_XER * 4,    -1,
 172   PT_ORIG_R3 * 4, PT_TRAP * 4
 173  };
 174 #endif
 175
 176 static int
 177 ppc_cannot_store_register (int regno)
 178 {
 179   const struct target_desc *tdesc = current_process ()->tdesc;
 180
 181 #ifndef __powerpc64__
 182   /* Some kernels do not allow us to store fpscr.  */
 183   if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
 184       && regno == find_regno (tdesc, "fpscr"))
 185     return 2;
 186 #endif
 187
 188   /* Some kernels do not allow us to store orig_r3 or trap.  */
 189   if (regno == find_regno (tdesc, "orig_r3")
 190       || regno == find_regno (tdesc, "trap"))
 191     return 2;
 192
 193   return 0;
 194 }
 195
 196 static int
 197 ppc_cannot_fetch_register (int regno)
 198 {
 199   return 0;
 200 }
 201
 202 static void
 203 ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
 204 {
 205   memset (buf, 0, sizeof (long));
 206
 207   if (__BYTE_ORDER == __LITTLE_ENDIAN)
 208     {
 209       /* Little-endian values always sit at the left end of the buffer.  */
 210       collect_register (regcache, regno, buf);
 211     }
 212   else if (__BYTE_ORDER == __BIG_ENDIAN)
 213     {
 214       /* Big-endian values sit at the right end of the buffer.  In case of
 215          registers whose sizes are smaller than sizeof (long), we must use a
 216          padding to access them correctly.  */
 217       int size = register_size (regcache->tdesc, regno);
 218
 219       if (size < sizeof (long))
 220         collect_register (regcache, regno, buf + sizeof (long) - size);
 221       else
 222         collect_register (regcache, regno, buf);
 223     }
 224   else
 225     perror_with_name ("Unexpected byte order");
 226 }
 227
 228 static void
 229 ppc_supply_ptrace_register (struct regcache *regcache,
 230                             int regno, const char *buf)
 231 {
 232   if (__BYTE_ORDER == __LITTLE_ENDIAN)
 233     {
 234       /* Little-endian values always sit at the left end of the buffer.  */
 235       supply_register (regcache, regno, buf);
 236     }
 237   else if (__BYTE_ORDER == __BIG_ENDIAN)
 238     {
 239       /* Big-endian values sit at the right end of the buffer.  In case of
 240          registers whose sizes are smaller than sizeof (long), we must use a
 241          padding to access them correctly.  */
 242       int size = register_size (regcache->tdesc, regno);
 243
 244       if (size < sizeof (long))
 245         supply_register (regcache, regno, buf + sizeof (long) - size);
 246       else
 247         supply_register (regcache, regno, buf);
 248     }
 249   else
 250     perror_with_name ("Unexpected byte order");
 251 }
 252
 253
 254 #define INSTR_SC        0x44000002
 255 #define NR_spu_run      0x0116
 256
 257 /* If the PPU thread is currently stopped on a spu_run system call,
 258    return to FD and ADDR the file handle and NPC parameter address
 259    used with the system call.  Return non-zero if successful.  */
 260 static int
 261 parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
 262 {
 263   CORE_ADDR curr_pc;
 264   int curr_insn;
 265   int curr_r0;
 266
 267   if (register_size (regcache->tdesc, 0) == 4)
 268     {
 269       unsigned int pc, r0, r3, r4;
 270       collect_register_by_name (regcache, "pc", &pc);
 271       collect_register_by_name (regcache, "r0", &r0);
 272       collect_register_by_name (regcache, "orig_r3", &r3);
 273       collect_register_by_name (regcache, "r4", &r4);
 274       curr_pc = (CORE_ADDR) pc;
 275       curr_r0 = (int) r0;
 276       *fd = (int) r3;
 277       *addr = (CORE_ADDR) r4;
 278     }
 279   else
 280     {
 281       unsigned long pc, r0, r3, r4;
 282       collect_register_by_name (regcache, "pc", &pc);
 283       collect_register_by_name (regcache, "r0", &r0);
 284       collect_register_by_name (regcache, "orig_r3", &r3);
 285       collect_register_by_name (regcache, "r4", &r4);
 286       curr_pc = (CORE_ADDR) pc;
 287       curr_r0 = (int) r0;
 288       *fd = (int) r3;
 289       *addr = (CORE_ADDR) r4;
 290     }
 291
 292   /* Fetch instruction preceding current NIP.  */
 293   if ((*the_target->read_memory) (curr_pc - 4,
 294                                   (unsigned char *) &curr_insn, 4) != 0)
 295     return 0;
 296   /* It should be a "sc" instruction.  */
 297   if (curr_insn != INSTR_SC)
 298     return 0;
 299   /* System call number should be NR_spu_run.  */
 300   if (curr_r0 != NR_spu_run)
 301     return 0;
 302
 303   return 1;
 304 }
 305
 306 static CORE_ADDR
 307 ppc_get_pc (struct regcache *regcache)
 308 {
 309   CORE_ADDR addr;
 310   int fd;
 311
 312   if (parse_spufs_run (regcache, &fd, &addr))
 313     {
 314       unsigned int pc;
 315       (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
 316       return ((CORE_ADDR)1 << 63)
 317         | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
 318     }
 319   else if (register_size (regcache->tdesc, 0) == 4)
 320     {
 321       unsigned int pc;
 322       collect_register_by_name (regcache, "pc", &pc);
 323       return (CORE_ADDR) pc;
 324     }
 325   else
 326     {
 327       unsigned long pc;
 328       collect_register_by_name (regcache, "pc", &pc);
 329       return (CORE_ADDR) pc;
 330     }
 331 }
 332
 333 static void
 334 ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
 335 {
 336   CORE_ADDR addr;
 337   int fd;
 338
 339   if (parse_spufs_run (regcache, &fd, &addr))
 340     {
 341       unsigned int newpc = pc;
 342       (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
 343     }
 344   else if (register_size (regcache->tdesc, 0) == 4)
 345     {
 346       unsigned int newpc = pc;
 347       supply_register_by_name (regcache, "pc", &newpc);
 348     }
 349   else
 350     {
 351       unsigned long newpc = pc;
 352       supply_register_by_name (regcache, "pc", &newpc);
 353     }
 354 }
 355
 356
 357 static int
 358 ppc_get_hwcap (unsigned long *valp)
 359 {
 360   const struct target_desc *tdesc = current_process ()->tdesc;
 361   int wordsize = register_size (tdesc, 0);
 362   unsigned char *data = alloca (2 * wordsize);
 363   int offset = 0;
 364
 365   while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
 366     {
 367       if (wordsize == 4)
 368         {
 369           unsigned int *data_p = (unsigned int *)data;
 370           if (data_p[0] == AT_HWCAP)
 371             {
 372               *valp = data_p[1];
 373               return 1;
 374             }
 375         }
 376       else
 377         {
 378           unsigned long *data_p = (unsigned long *)data;
 379           if (data_p[0] == AT_HWCAP)
 380             {
 381               *valp = data_p[1];
 382               return 1;
 383             }
 384         }
 385
 386       offset += 2 * wordsize;
 387     }
 388
 389   *valp = 0;
 390   return 0;
 391 }
 392
 393 /* Forward declaration.  */
 394 static struct usrregs_info ppc_usrregs_info;
 395 #ifndef __powerpc64__
 396 static int ppc_regmap_adjusted;
 397 #endif
 398
 399 static void
 400 ppc_arch_setup (void)
 401 {
 402   const struct target_desc *tdesc;
 403 #ifdef __powerpc64__
 404   long msr;
 405   struct regcache *regcache;
 406
 407   /* On a 64-bit host, assume 64-bit inferior process with no
 408      AltiVec registers.  Reset ppc_hwcap to ensure that the
 409      collect_register call below does not fail.  */
 410   tdesc = tdesc_powerpc_64l;
 411   current_process ()->tdesc = tdesc;
 412   ppc_hwcap = 0;
 413
 414   /* Only if the high bit of the MSR is set, we actually have
 415      a 64-bit inferior.  */
 416   regcache = new_register_cache (tdesc);
 417   fetch_inferior_registers (regcache, find_regno (tdesc, "msr"));
 418   collect_register_by_name (regcache, "msr", &msr);
 419   free_register_cache (regcache);
 420   if (msr < 0)
 421     {
 422       ppc_get_hwcap (&ppc_hwcap);
 423       if (ppc_hwcap & PPC_FEATURE_CELL)
 424         tdesc = tdesc_powerpc_cell64l;
 425       else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
 426         {
 427           /* Power ISA 2.05 (implemented by Power 6 and newer processors)
 428              increases the FPSCR from 32 bits to 64 bits. Even though Power 7
 429              supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05
 430              set, only PPC_FEATURE_ARCH_2_06.  Since for now the only bits
 431              used in the higher half of the register are for Decimal Floating
 432              Point, we check if that feature is available to decide the size
 433              of the FPSCR.  */
 434           if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 435             tdesc = tdesc_powerpc_isa205_vsx64l;
 436           else
 437             tdesc = tdesc_powerpc_vsx64l;
 438         }
 439       else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
 440         {
 441           if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 442             tdesc = tdesc_powerpc_isa205_altivec64l;
 443           else
 444             tdesc = tdesc_powerpc_altivec64l;
 445         }
 446
 447       current_process ()->tdesc = tdesc;
 448       return;
 449     }
 450 #endif
 451
 452   /* OK, we have a 32-bit inferior.  */
 453   tdesc = tdesc_powerpc_32l;
 454   current_process ()->tdesc = tdesc;
 455
 456   ppc_get_hwcap (&ppc_hwcap);
 457   if (ppc_hwcap & PPC_FEATURE_CELL)
 458     tdesc = tdesc_powerpc_cell32l;
 459   else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
 460     {
 461       if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 462         tdesc = tdesc_powerpc_isa205_vsx32l;
 463       else
 464         tdesc = tdesc_powerpc_vsx32l;
 465     }
 466   else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
 467     {
 468       if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
 469         tdesc = tdesc_powerpc_isa205_altivec32l;
 470       else
 471         tdesc = tdesc_powerpc_altivec32l;
 472     }
 473
 474   /* On 32-bit machines, check for SPE registers.
 475      Set the low target's regmap field as appropriately.  */
 476 #ifndef __powerpc64__
 477   if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
 478     tdesc = tdesc_powerpc_e500l;
 479
 480   if (!ppc_regmap_adjusted)
 481     {
 482       if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
 483         ppc_usrregs_info.regmap = ppc_regmap_e500;
 484
 485       /* If the FPSCR is 64-bit wide, we need to fetch the whole
 486          64-bit slot and not just its second word.  The PT_FPSCR
 487          supplied in a 32-bit GDB compilation doesn't reflect
 488          this.  */
 489       if (register_size (tdesc, 70) == 8)
 490         ppc_regmap[70] = (48 + 2*32) * sizeof (long);
 491
 492       ppc_regmap_adjusted = 1;
 493    }
 494 #endif
 495   current_process ()->tdesc = tdesc;
 496 }
 497
 498 /* Correct in either endianness.
 499    This instruction is "twge r2, r2", which GDB uses as a software
 500    breakpoint.  */
 501 static const unsigned int ppc_breakpoint = 0x7d821008;
 502 #define ppc_breakpoint_len 4
 503
 504 static int
 505 ppc_breakpoint_at (CORE_ADDR where)
 506 {
 507   unsigned int insn;
 508
 509   if (where & ((CORE_ADDR)1 << 63))
 510     {
 511       char mem_annex[32];
 512       sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
 513       (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
 514                                 NULL, where & 0xffffffff, 4);
 515       if (insn == 0x3fff)
 516         return 1;
 517     }
 518   else
 519     {
 520       (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
 521       if (insn == ppc_breakpoint)
 522         return 1;
 523       /* If necessary, recognize more trap instructions here.  GDB only uses
 524          the one.  */
 525     }
 526
 527   return 0;
 528 }
 529
 530 /* Provide only a fill function for the general register set.  ps_lgetregs
 531    will use this for NPTL support.  */
 532
 533 static void ppc_fill_gregset (struct regcache *regcache, void *buf)
 534 {
 535   int i;
 536
 537   for (i = 0; i < 32; i++)
 538     ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
 539
 540   for (i = 64; i < 70; i++)
 541     ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
 542
 543   for (i = 71; i < 73; i++)
 544     ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
 545 }
 546
 547 #ifndef PTRACE_GETVSXREGS
 548 #define PTRACE_GETVSXREGS 27
 549 #define PTRACE_SETVSXREGS 28
 550 #endif
 551
 552 #define SIZEOF_VSXREGS 32*8
 553
 554 static void
 555 ppc_fill_vsxregset (struct regcache *regcache, void *buf)
 556 {
 557   int i, base;
 558   char *regset = buf;
 559
 560   if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
 561     return;
 562
 563   base = find_regno (regcache->tdesc, "vs0h");
 564   for (i = 0; i < 32; i++)
 565     collect_register (regcache, base + i, &regset[i * 8]);
 566 }
 567
 568 static void
 569 ppc_store_vsxregset (struct regcache *regcache, const void *buf)
 570 {
 571   int i, base;
 572   const char *regset = buf;
 573
 574   if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
 575     return;
 576
 577   base = find_regno (regcache->tdesc, "vs0h");
 578   for (i = 0; i < 32; i++)
 579     supply_register (regcache, base + i, &regset[i * 8]);
 580 }
 581
 582 #ifndef PTRACE_GETVRREGS
 583 #define PTRACE_GETVRREGS 18
 584 #define PTRACE_SETVRREGS 19
 585 #endif
 586
 587 #define SIZEOF_VRREGS 33*16+4
 588
 589 static void
 590 ppc_fill_vrregset (struct regcache *regcache, void *buf)
 591 {
 592   int i, base;
 593   char *regset = buf;
 594
 595   if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
 596     return;
 597
 598   base = find_regno (regcache->tdesc, "vr0");
 599   for (i = 0; i < 32; i++)
 600     collect_register (regcache, base + i, &regset[i * 16]);
 601
 602   collect_register_by_name (regcache, "vscr", &regset[32 * 16 + 12]);
 603   collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
 604 }
 605
 606 static void
 607 ppc_store_vrregset (struct regcache *regcache, const void *buf)
 608 {
 609   int i, base;
 610   const char *regset = buf;
 611
 612   if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
 613     return;
 614
 615   base = find_regno (regcache->tdesc, "vr0");
 616   for (i = 0; i < 32; i++)
 617     supply_register (regcache, base + i, &regset[i * 16]);
 618
 619   supply_register_by_name (regcache, "vscr", &regset[32 * 16 + 12]);
 620   supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
 621 }
 622
 623 #ifndef PTRACE_GETEVRREGS
 624 #define PTRACE_GETEVRREGS       20
 625 #define PTRACE_SETEVRREGS       21
 626 #endif
 627
 628 struct gdb_evrregset_t
 629 {
 630   unsigned long evr[32];
 631   unsigned long long acc;
 632   unsigned long spefscr;
 633 };
 634
 635 static void
 636 ppc_fill_evrregset (struct regcache *regcache, void *buf)
 637 {
 638   int i, ev0;
 639   struct gdb_evrregset_t *regset = buf;
 640
 641   if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
 642     return;
 643
 644   ev0 = find_regno (regcache->tdesc, "ev0h");
 645   for (i = 0; i < 32; i++)
 646     collect_register (regcache, ev0 + i, &regset->evr[i]);
 647
 648   collect_register_by_name (regcache, "acc", &regset->acc);
 649   collect_register_by_name (regcache, "spefscr", &regset->spefscr);
 650 }
 651
 652 static void
 653 ppc_store_evrregset (struct regcache *regcache, const void *buf)
 654 {
 655   int i, ev0;
 656   const struct gdb_evrregset_t *regset = buf;
 657
 658   if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
 659     return;
 660
 661   ev0 = find_regno (regcache->tdesc, "ev0h");
 662   for (i = 0; i < 32; i++)
 663     supply_register (regcache, ev0 + i, &regset->evr[i]);
 664
 665   supply_register_by_name (regcache, "acc", &regset->acc);
 666   supply_register_by_name (regcache, "spefscr", &regset->spefscr);
 667 }
 668
 669 static struct regset_info ppc_regsets[] = {
 670   /* List the extra register sets before GENERAL_REGS.  That way we will
 671      fetch them every time, but still fall back to PTRACE_PEEKUSER for the
 672      general registers.  Some kernels support these, but not the newer
 673      PPC_PTRACE_GETREGS.  */
 674   { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, SIZEOF_VSXREGS, EXTENDED_REGS,
 675   ppc_fill_vsxregset, ppc_store_vsxregset },
 676   { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, SIZEOF_VRREGS, EXTENDED_REGS,
 677     ppc_fill_vrregset, ppc_store_vrregset },
 678   { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 32 * 4 + 8 + 4, EXTENDED_REGS,
 679     ppc_fill_evrregset, ppc_store_evrregset },
 680   { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
 681   { 0, 0, 0, -1, -1, NULL, NULL }
 682 };
 683
 684 static struct usrregs_info ppc_usrregs_info =
 685   {
 686     ppc_num_regs,
 687     ppc_regmap,
 688   };
 689
 690 static struct regsets_info ppc_regsets_info =
 691   {
 692     ppc_regsets, /* regsets */
 693     0, /* num_regsets */
 694     NULL, /* disabled_regsets */
 695   };
 696
 697 static struct regs_info regs_info =
 698   {
 699     NULL, /* regset_bitmap */
 700     &ppc_usrregs_info,
 701     &ppc_regsets_info
 702   };
 703
 704 static const struct regs_info *
 705 ppc_regs_info (void)
 706 {
 707   return &regs_info;
 708 }
 709
 710 struct linux_target_ops the_low_target = {
 711   ppc_arch_setup,
 712   ppc_regs_info,
 713   ppc_cannot_fetch_register,
 714   ppc_cannot_store_register,
 715   NULL, /* fetch_register */
 716   ppc_get_pc,
 717   ppc_set_pc,
 718   (const unsigned char *) &ppc_breakpoint,
 719   ppc_breakpoint_len,
 720   NULL,
 721   0,
 722   ppc_breakpoint_at,
 723   NULL, /* supports_z_point_type */
 724   NULL,
 725   NULL,
 726   NULL,
 727   NULL,
 728   ppc_collect_ptrace_register,
 729   ppc_supply_ptrace_register,
 730 };
 731
 732 void
 733 initialize_low_arch (void)
 734 {
 735   /* Initialize the Linux target descriptions.  */
 736
 737   init_registers_powerpc_32l ();
 738   init_registers_powerpc_altivec32l ();
 739   init_registers_powerpc_cell32l ();
 740   init_registers_powerpc_vsx32l ();
 741   init_registers_powerpc_isa205_32l ();
 742   init_registers_powerpc_isa205_altivec32l ();
 743   init_registers_powerpc_isa205_vsx32l ();
 744   init_registers_powerpc_e500l ();
 745   init_registers_powerpc_64l ();
 746   init_registers_powerpc_altivec64l ();
 747   init_registers_powerpc_cell64l ();
 748   init_registers_powerpc_vsx64l ();
 749   init_registers_powerpc_isa205_64l ();
 750   init_registers_powerpc_isa205_altivec64l ();
 751   init_registers_powerpc_isa205_vsx64l ();
 752
 753   initialize_regsets_info (&ppc_regsets_info);
 754 }